2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
41 #include <vm/vm_param.h>
43 #include <vm/vm_kern.h>
44 #include <vm/vm_extern.h>
46 #include <vm/vm_map.h>
52 #include <sys/mplock2.h>
54 #include <machine/smp.h>
55 #include <machine_base/apic/apicreg.h>
56 #include <machine/atomic.h>
57 #include <machine/cpufunc.h>
58 #include <machine/cputypes.h>
59 #include <machine_base/apic/mpapic.h>
60 #include <machine/psl.h>
61 #include <machine/segments.h>
62 #include <machine/tss.h>
63 #include <machine/specialreg.h>
64 #include <machine/globaldata.h>
65 #include <machine/pmap_inval.h>
67 #include <machine/md_var.h> /* setidt() */
68 #include <machine_base/icu/icu.h> /* IPIs */
69 #include <machine_base/isa/intr_machdep.h> /* IPIs */
71 #define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
73 #define WARMBOOT_TARGET 0
74 #define WARMBOOT_OFF (KERNBASE + 0x0467)
75 #define WARMBOOT_SEG (KERNBASE + 0x0469)
77 #define BIOS_BASE (0xf0000)
78 #define BIOS_BASE2 (0xe0000)
79 #define BIOS_SIZE (0x10000)
80 #define BIOS_COUNT (BIOS_SIZE/4)
82 #define CMOS_REG (0x70)
83 #define CMOS_DATA (0x71)
84 #define BIOS_RESET (0x0f)
85 #define BIOS_WARM (0x0a)
87 #define PROCENTRY_FLAG_EN 0x01
88 #define PROCENTRY_FLAG_BP 0x02
89 #define IOAPICENTRY_FLAG_EN 0x01
92 /* MP Floating Pointer Structure */
93 typedef struct MPFPS {
106 /* MP Configuration Table Header */
107 typedef struct MPCTH {
109 u_short base_table_length;
113 u_char product_id[12];
114 void *oem_table_pointer;
115 u_short oem_table_size;
118 u_short extended_table_length;
119 u_char extended_table_checksum;
124 typedef struct PROCENTRY {
129 u_long cpu_signature;
130 u_long feature_flags;
135 typedef struct BUSENTRY {
141 typedef struct IOAPICENTRY {
147 } *io_apic_entry_ptr;
149 typedef struct INTENTRY {
159 /* descriptions of MP basetable entries */
160 typedef struct BASETABLE_ENTRY {
169 vm_size_t mp_cth_mapsz;
172 typedef int (*mptable_iter_func)(void *, const void *, int);
175 * this code MUST be enabled here and in mpboot.s.
176 * it follows the very early stages of AP boot by placing values in CMOS ram.
177 * it NORMALLY will never be needed and thus the primitive method for enabling.
180 #if defined(CHECK_POINTS)
181 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
182 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
184 #define CHECK_INIT(D); \
185 CHECK_WRITE(0x34, (D)); \
186 CHECK_WRITE(0x35, (D)); \
187 CHECK_WRITE(0x36, (D)); \
188 CHECK_WRITE(0x37, (D)); \
189 CHECK_WRITE(0x38, (D)); \
190 CHECK_WRITE(0x39, (D));
192 #define CHECK_PRINT(S); \
193 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
202 #else /* CHECK_POINTS */
204 #define CHECK_INIT(D)
205 #define CHECK_PRINT(S)
207 #endif /* CHECK_POINTS */
210 * Values to send to the POST hardware.
212 #define MP_BOOTADDRESS_POST 0x10
213 #define MP_PROBE_POST 0x11
214 #define MPTABLE_PASS1_POST 0x12
216 #define MP_START_POST 0x13
217 #define MP_ENABLE_POST 0x14
218 #define MPTABLE_PASS2_POST 0x15
220 #define START_ALL_APS_POST 0x16
221 #define INSTALL_AP_TRAMP_POST 0x17
222 #define START_AP_POST 0x18
224 #define MP_ANNOUNCE_POST 0x19
226 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
227 int current_postcode;
229 /** XXX FIXME: what system files declare these??? */
230 extern struct region_descriptor r_gdt, r_idt;
232 int mp_naps; /* # of Applications processors */
234 static int mp_nbusses; /* # of busses */
235 int mp_napics; /* # of IO APICs */
238 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
239 u_int32_t *io_apic_versions;
243 u_int32_t cpu_apic_versions[MAXCPU];
245 extern int64_t tsc_offsets[];
247 extern u_long ebda_addr;
250 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
254 * APIC ID logical/physical mapping structures.
255 * We oversize these to simplify boot-time config.
257 int cpu_num_to_apic_id[NAPICID];
259 int io_num_to_apic_id[NAPICID];
261 int apic_id_to_logical[NAPICID];
263 /* AP uses this during bootstrap. Do not staticize. */
267 /* Hotwire a 0->4MB V==P mapping */
268 extern pt_entry_t *KPTphys;
271 * SMP page table page. Setup by locore to point to a page table
272 * page from which we allocate per-cpu privatespace areas io_apics,
276 #define IO_MAPPING_START_INDEX \
277 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
279 extern pt_entry_t *SMPpt;
280 static int SMPpt_alloc_index = IO_MAPPING_START_INDEX;
282 struct pcb stoppcbs[MAXCPU];
284 static basetable_entry basetable_entry_types[] =
286 {0, 20, "Processor"},
294 * Local data and functions.
297 static u_int boot_address;
298 static u_int base_memory;
299 static int mp_finish;
301 static void mp_enable(u_int boot_addr);
303 static int mptable_iterate_entries(const mpcth_t,
304 mptable_iter_func, void *);
305 static int mptable_probe(void);
306 static int mptable_search(void);
307 static int mptable_check(vm_paddr_t);
308 static int mptable_search_sig(u_int32_t target, int count);
309 static int mptable_hyperthread_fixup(u_int, int);
311 static void mptable_pass1(struct mptable_pos *);
312 static void mptable_pass2(struct mptable_pos *);
313 static void mptable_default(int type);
314 static void mptable_fix(void);
316 static int mptable_map(struct mptable_pos *, vm_paddr_t);
317 static void mptable_unmap(struct mptable_pos *);
318 static void mptable_imcr(struct mptable_pos *);
320 static int mptable_lapic_probe(struct lapic_enumerator *);
321 static void mptable_lapic_enumerate(struct lapic_enumerator *);
322 static void mptable_lapic_default(void);
325 static void setup_apic_irq_mapping(void);
326 static int apic_int_is_bus_type(int intr, int bus_type);
328 static int start_all_aps(u_int boot_addr);
329 static void install_ap_tramp(u_int boot_addr);
330 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
331 static int smitest(void);
333 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
334 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
335 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
338 * Calculate usable address in base memory for AP trampoline code.
341 mp_bootaddress(u_int basemem)
343 POSTCODE(MP_BOOTADDRESS_POST);
345 base_memory = basemem;
347 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
348 if ((base_memory - boot_address) < bootMP_size)
349 boot_address -= 4096; /* not enough, lower by 4k */
360 mpfps_paddr = mptable_search();
361 if (mptable_check(mpfps_paddr))
368 * Look for an Intel MP spec table (ie, SMP capable hardware).
377 * Make sure our SMPpt[] page table is big enough to hold all the
380 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
382 POSTCODE(MP_PROBE_POST);
384 /* see if EBDA exists */
385 if (ebda_addr != 0) {
386 /* search first 1K of EBDA */
387 target = (u_int32_t)ebda_addr;
388 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
391 /* last 1K of base memory, effective 'top of base' passed in */
392 target = (u_int32_t)(base_memory - 0x400);
393 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
397 /* search the BIOS */
398 target = (u_int32_t)BIOS_BASE;
399 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
402 /* search the extended BIOS */
403 target = (u_int32_t)BIOS_BASE2;
404 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
411 struct mptable_check_cbarg {
417 mptable_check_callback(void *xarg, const void *pos, int type)
419 const struct PROCENTRY *ent;
420 struct mptable_check_cbarg *arg = xarg;
426 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
430 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
431 if (arg->found_bsp) {
432 kprintf("more than one BSP in base MP table\n");
441 mptable_check(vm_paddr_t mpfps_paddr)
443 struct mptable_pos mpt;
444 struct mptable_check_cbarg arg;
448 if (mpfps_paddr == 0)
451 error = mptable_map(&mpt, mpfps_paddr);
455 if (mpt.mp_fps->mpfb1 != 0)
463 if (cth->apic_address == 0)
466 bzero(&arg, sizeof(arg));
467 error = mptable_iterate_entries(cth, mptable_check_callback, &arg);
469 if (arg.cpu_count == 0) {
470 kprintf("MP table contains no processor entries\n");
472 } else if (!arg.found_bsp) {
473 kprintf("MP table does not contains BSP entry\n");
483 mptable_iterate_entries(const mpcth_t cth, mptable_iter_func func, void *arg)
485 int count, total_size;
486 const void *position;
488 KKASSERT(cth->base_table_length >= sizeof(struct MPCTH));
489 total_size = cth->base_table_length - sizeof(struct MPCTH);
490 position = (const uint8_t *)cth + sizeof(struct MPCTH);
491 count = cth->entry_count;
496 KKASSERT(total_size >= 0);
497 if (total_size == 0) {
498 kprintf("invalid base MP table, "
499 "entry count and length mismatch\n");
503 type = *(const uint8_t *)position;
505 case 0: /* processor_entry */
506 case 1: /* bus_entry */
507 case 2: /* io_apic_entry */
508 case 3: /* int_entry */
509 case 4: /* int_entry */
512 kprintf("unknown base MP table entry type %d\n", type);
516 if (total_size < basetable_entry_types[type].length) {
517 kprintf("invalid base MP table length, "
518 "does not contain all entries\n");
521 total_size -= basetable_entry_types[type].length;
523 error = func(arg, position, type);
527 position = (const uint8_t *)position +
528 basetable_entry_types[type].length;
535 * Startup the SMP processors.
540 POSTCODE(MP_START_POST);
541 mp_enable(boot_address);
546 * Print various information about the SMP system hardware and setup.
553 POSTCODE(MP_ANNOUNCE_POST);
555 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
556 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
557 kprintf(", version: 0x%08x\n", cpu_apic_versions[0]);
558 for (x = 1; x <= mp_naps; ++x) {
559 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
560 kprintf(", version: 0x%08x\n", cpu_apic_versions[x]);
564 for (x = 0; x < mp_napics; ++x) {
565 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
566 kprintf(", version: 0x%08x", io_apic_versions[x]);
567 kprintf(", at 0x%08lx\n", io_apic_address[x]);
570 kprintf(" Warning: APIC I/O disabled\n");
575 * AP cpu's call this to sync up protected mode.
577 * WARNING! We must ensure that the cpu is sufficiently initialized to
578 * be able to use to the FP for our optimized bzero/bcopy code before
579 * we enter more mainstream C code.
581 * WARNING! %fs is not set up on entry. This routine sets up %fs.
587 int x, myid = bootAP;
589 struct mdglobaldata *md;
590 struct privatespace *ps;
592 ps = &CPU_prvspace[myid];
594 gdt_segs[GPRIV_SEL].ssd_base = (int)ps;
595 gdt_segs[GPROC0_SEL].ssd_base =
596 (int) &ps->mdglobaldata.gd_common_tss;
597 ps->mdglobaldata.mi.gd_prvspace = ps;
599 for (x = 0; x < NGDT; x++) {
600 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
603 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
604 r_gdt.rd_base = (int) &gdt[myid * NGDT];
605 lgdt(&r_gdt); /* does magic intra-segment return */
610 mdcpu->gd_currentldt = _default_ldt;
612 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
613 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
615 md = mdcpu; /* loaded through %fs:0 (mdglobaldata.mi.gd_prvspace)*/
617 md->gd_common_tss.tss_esp0 = 0; /* not used until after switch */
618 md->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
619 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
620 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
621 md->gd_common_tssd = *md->gd_tss_gdt;
625 * Set to a known state:
626 * Set by mpboot.s: CR0_PG, CR0_PE
627 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
630 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
632 pmap_set_opt(); /* PSE/4MB pages, etc */
634 /* set up CPU registers and state */
637 /* set up FPU state on the AP */
638 npxinit(__INITIAL_NPXCW__);
640 /* set up SSE registers */
644 /*******************************************************************
645 * local functions and data
649 * start the SMP system
652 mp_enable(u_int boot_addr)
658 vm_paddr_t mpfps_paddr;
659 struct mptable_pos mpt;
661 POSTCODE(MP_ENABLE_POST);
665 mpfps_paddr = mptable_probe();
667 mptable_map(&mpt, mpfps_paddr);
674 panic("no MP table, disable APIC_IO!\n");
676 mptable_map(&mpt, mpfps_paddr);
679 * Examine the MP table for needed info
686 /* Post scan cleanup */
689 setup_apic_irq_mapping();
691 /* fill the LOGICAL io_apic_versions table */
692 for (apic = 0; apic < mp_napics; ++apic) {
693 ux = io_apic_read(apic, IOAPIC_VER);
694 io_apic_versions[apic] = ux;
695 io_apic_set_id(apic, IO_TO_ID(apic));
698 /* program each IO APIC in the system */
699 for (apic = 0; apic < mp_napics; ++apic)
700 if (io_apic_setup(apic) < 0)
701 panic("IO APIC setup failure");
706 * These are required for SMP operation
709 /* install a 'Spurious INTerrupt' vector */
710 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
711 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
713 /* install an inter-CPU IPI for TLB invalidation */
714 setidt(XINVLTLB_OFFSET, Xinvltlb,
715 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
717 /* install an inter-CPU IPI for IPIQ messaging */
718 setidt(XIPIQ_OFFSET, Xipiq,
719 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
721 /* install a timer vector */
722 setidt(XTIMER_OFFSET, Xtimer,
723 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
725 /* install an inter-CPU IPI for CPU stop/restart */
726 setidt(XCPUSTOP_OFFSET, Xcpustop,
727 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
729 /* start each Application Processor */
730 start_all_aps(boot_addr);
735 * look for the MP spec signature
738 /* string defined by the Intel MP Spec as identifying the MP table */
739 #define MP_SIG 0x5f504d5f /* _MP_ */
740 #define NEXT(X) ((X) += 4)
742 mptable_search_sig(u_int32_t target, int count)
748 KKASSERT(target != 0);
750 map_size = count * sizeof(u_int32_t);
751 addr = pmap_mapdev((vm_paddr_t)target, map_size);
754 for (x = 0; x < count; NEXT(x)) {
755 if (addr[x] == MP_SIG) {
756 /* make array index a byte index */
757 ret = target + (x * sizeof(u_int32_t));
762 pmap_unmapdev((vm_offset_t)addr, map_size);
767 typedef struct BUSDATA {
769 enum busTypes bus_type;
772 typedef struct INTDATA {
782 typedef struct BUSTYPENAME {
789 static bus_type_name bus_type_table[] =
795 {UNKNOWN_BUSTYPE, "---"},
798 {UNKNOWN_BUSTYPE, "---"},
799 {UNKNOWN_BUSTYPE, "---"},
800 {UNKNOWN_BUSTYPE, "---"},
801 {UNKNOWN_BUSTYPE, "---"},
802 {UNKNOWN_BUSTYPE, "---"},
804 {UNKNOWN_BUSTYPE, "---"},
805 {UNKNOWN_BUSTYPE, "---"},
806 {UNKNOWN_BUSTYPE, "---"},
807 {UNKNOWN_BUSTYPE, "---"},
809 {UNKNOWN_BUSTYPE, "---"}
811 /* from MP spec v1.4, table 5-1 */
812 static int default_data[7][5] =
814 /* nbus, id0, type0, id1, type1 */
815 {1, 0, ISA, 255, 255},
816 {1, 0, EISA, 255, 255},
817 {1, 0, EISA, 255, 255},
818 {1, 0, MCA, 255, 255},
820 {2, 0, EISA, 1, PCI},
826 static bus_datum *bus_data;
828 /* the IO INT data, one entry per possible APIC INTerrupt */
829 static io_int *io_apic_ints;
834 static int processor_entry (const struct PROCENTRY *entry, int cpu);
836 static int bus_entry (const struct BUSENTRY *entry, int bus);
837 static int io_apic_entry (const struct IOAPICENTRY *entry, int apic);
838 static int int_entry (const struct INTENTRY *entry, int intr);
839 static int lookup_bus_type (char *name);
845 mptable_ioapic_pass1_callback(void *xarg, const void *pos, int type)
847 const struct IOAPICENTRY *ioapic_ent;
850 case 1: /* bus_entry */
854 case 2: /* io_apic_entry */
856 if (ioapic_ent->apic_flags & IOAPICENTRY_FLAG_EN) {
857 io_apic_address[mp_napics++] =
858 (vm_offset_t)ioapic_ent->apic_address;
862 case 3: /* int_entry */
870 * 1st pass on motherboard's Intel MP specification table.
879 mptable_pass1(struct mptable_pos *mpt)
884 POSTCODE(MPTABLE_PASS1_POST);
887 KKASSERT(fps != NULL);
889 /* clear various tables */
890 for (x = 0; x < NAPICID; ++x)
891 io_apic_address[x] = ~0; /* IO APIC address table */
897 /* check for use of 'default' configuration */
898 if (fps->mpfb1 != 0) {
899 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
900 mp_nbusses = default_data[fps->mpfb1 - 1][0];
906 error = mptable_iterate_entries(mpt->mp_cth,
907 mptable_ioapic_pass1_callback, NULL);
909 panic("mptable_iterate_entries(ioapic_pass1) failed\n");
913 struct mptable_ioapic2_cbarg {
920 mptable_ioapic_pass2_callback(void *xarg, const void *pos, int type)
922 struct mptable_ioapic2_cbarg *arg = xarg;
926 if (bus_entry(pos, arg->bus))
931 if (io_apic_entry(pos, arg->apic))
936 if (int_entry(pos, arg->intr))
944 * 2nd pass on motherboard's Intel MP specification table.
947 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
948 * IO_TO_ID(N), logical IO to APIC ID table
953 mptable_pass2(struct mptable_pos *mpt)
955 struct mptable_ioapic2_cbarg arg;
959 POSTCODE(MPTABLE_PASS2_POST);
962 KKASSERT(fps != NULL);
964 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
966 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
967 M_DEVBUF, M_WAITOK | M_ZERO);
968 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
970 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
973 for (x = 0; x < mp_napics; x++)
974 ioapic[x] = permanent_io_mapping(io_apic_address[x]);
976 /* clear various tables */
977 for (x = 0; x < NAPICID; ++x) {
978 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
979 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
982 /* clear bus data table */
983 for (x = 0; x < mp_nbusses; ++x)
984 bus_data[x].bus_id = 0xff;
986 /* clear IO APIC INT table */
987 for (x = 0; x < (nintrs + 1); ++x) {
988 io_apic_ints[x].int_type = 0xff;
989 io_apic_ints[x].int_vector = 0xff;
992 /* check for use of 'default' configuration */
993 if (fps->mpfb1 != 0) {
994 mptable_default(fps->mpfb1);
998 bzero(&arg, sizeof(arg));
999 error = mptable_iterate_entries(mpt->mp_cth,
1000 mptable_ioapic_pass2_callback, &arg);
1002 panic("mptable_iterate_entries(ioapic_pass2) failed\n");
1005 #endif /* APIC_IO */
1008 * Check if we should perform a hyperthreading "fix-up" to
1009 * enumerate any logical CPU's that aren't already listed
1012 * XXX: We assume that all of the physical CPUs in the
1013 * system have the same number of logical CPUs.
1015 * XXX: We assume that APIC ID's are allocated such that
1016 * the APIC ID's for a physical processor are aligned
1017 * with the number of logical CPU's in the processor.
1020 mptable_hyperthread_fixup(u_int id_mask, int cpu_count)
1022 int i, id, lcpus_max, logical_cpus;
1024 if ((cpu_feature & CPUID_HTT) == 0)
1027 lcpus_max = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1031 if (cpu_vendor_id == CPU_VENDOR_INTEL) {
1033 * INSTRUCTION SET REFERENCE, A-M (#253666)
1034 * Page 3-181, Table 3-20
1035 * "The nearest power-of-2 integer that is not smaller
1036 * than EBX[23:16] is the number of unique initial APIC
1037 * IDs reserved for addressing different logical
1038 * processors in a physical package."
1040 for (i = 0; ; ++i) {
1041 if ((1 << i) >= lcpus_max) {
1048 KKASSERT(cpu_count != 0);
1049 if (cpu_count == lcpus_max) {
1050 /* We have nothing to fix */
1052 } else if (cpu_count == 1) {
1053 /* XXX this may be incorrect */
1054 logical_cpus = lcpus_max;
1056 int cur, prev, dist;
1059 * Calculate the distances between two nearest
1060 * APIC IDs. If all such distances are same,
1061 * then it is the number of missing cpus that
1062 * we are going to fill later.
1064 dist = cur = prev = -1;
1065 for (id = 0; id < MAXCPU; ++id) {
1066 if ((id_mask & 1 << id) == 0)
1071 int new_dist = cur - prev;
1077 * Make sure that all distances
1078 * between two nearest APIC IDs
1081 if (dist != new_dist)
1089 /* Must be power of 2 */
1090 if (dist & (dist - 1))
1093 /* Can't exceed CPU package capacity */
1094 if (dist > lcpus_max)
1095 logical_cpus = lcpus_max;
1097 logical_cpus = dist;
1101 * For each APIC ID of a CPU that is set in the mask,
1102 * scan the other candidate APIC ID's for this
1103 * physical processor. If any of those ID's are
1104 * already in the table, then kill the fixup.
1106 for (id = 0; id < MAXCPU; id++) {
1107 if ((id_mask & 1 << id) == 0)
1109 /* First, make sure we are on a logical_cpus boundary. */
1110 if (id % logical_cpus != 0)
1112 for (i = id + 1; i < id + logical_cpus; i++)
1113 if ((id_mask & 1 << i) != 0)
1116 return logical_cpus;
1120 mptable_map(struct mptable_pos *mpt, vm_paddr_t mpfps_paddr)
1124 vm_size_t cth_mapsz = 0;
1126 bzero(mpt, sizeof(*mpt));
1128 fps = pmap_mapdev(mpfps_paddr, sizeof(*fps));
1129 if (fps->pap != 0) {
1131 * Map configuration table header to get
1132 * the base table size
1134 cth = pmap_mapdev(fps->pap, sizeof(*cth));
1135 cth_mapsz = cth->base_table_length;
1136 pmap_unmapdev((vm_offset_t)cth, sizeof(*cth));
1138 if (cth_mapsz < sizeof(*cth)) {
1139 kprintf("invalid base MP table length %d\n",
1141 pmap_unmapdev((vm_offset_t)fps, sizeof(*fps));
1146 * Map the base table
1148 cth = pmap_mapdev(fps->pap, cth_mapsz);
1153 mpt->mp_cth_mapsz = cth_mapsz;
1159 mptable_unmap(struct mptable_pos *mpt)
1161 if (mpt->mp_cth != NULL) {
1162 pmap_unmapdev((vm_offset_t)mpt->mp_cth, mpt->mp_cth_mapsz);
1164 mpt->mp_cth_mapsz = 0;
1166 if (mpt->mp_fps != NULL) {
1167 pmap_unmapdev((vm_offset_t)mpt->mp_fps, sizeof(*mpt->mp_fps));
1175 assign_apic_irq(int apic, int intpin, int irq)
1179 if (int_to_apicintpin[irq].ioapic != -1)
1180 panic("assign_apic_irq: inconsistent table");
1182 int_to_apicintpin[irq].ioapic = apic;
1183 int_to_apicintpin[irq].int_pin = intpin;
1184 int_to_apicintpin[irq].apic_address = ioapic[apic];
1185 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1187 for (x = 0; x < nintrs; x++) {
1188 if ((io_apic_ints[x].int_type == 0 ||
1189 io_apic_ints[x].int_type == 3) &&
1190 io_apic_ints[x].int_vector == 0xff &&
1191 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1192 io_apic_ints[x].dst_apic_int == intpin)
1193 io_apic_ints[x].int_vector = irq;
1198 revoke_apic_irq(int irq)
1204 if (int_to_apicintpin[irq].ioapic == -1)
1205 panic("revoke_apic_irq: inconsistent table");
1207 oldapic = int_to_apicintpin[irq].ioapic;
1208 oldintpin = int_to_apicintpin[irq].int_pin;
1210 int_to_apicintpin[irq].ioapic = -1;
1211 int_to_apicintpin[irq].int_pin = 0;
1212 int_to_apicintpin[irq].apic_address = NULL;
1213 int_to_apicintpin[irq].redirindex = 0;
1215 for (x = 0; x < nintrs; x++) {
1216 if ((io_apic_ints[x].int_type == 0 ||
1217 io_apic_ints[x].int_type == 3) &&
1218 io_apic_ints[x].int_vector != 0xff &&
1219 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1220 io_apic_ints[x].dst_apic_int == oldintpin)
1221 io_apic_ints[x].int_vector = 0xff;
1229 allocate_apic_irq(int intr)
1235 if (io_apic_ints[intr].int_vector != 0xff)
1236 return; /* Interrupt handler already assigned */
1238 if (io_apic_ints[intr].int_type != 0 &&
1239 (io_apic_ints[intr].int_type != 3 ||
1240 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1241 io_apic_ints[intr].dst_apic_int == 0)))
1242 return; /* Not INT or ExtInt on != (0, 0) */
1245 while (irq < APIC_INTMAPSIZE &&
1246 int_to_apicintpin[irq].ioapic != -1)
1249 if (irq >= APIC_INTMAPSIZE)
1250 return; /* No free interrupt handlers */
1252 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1253 intpin = io_apic_ints[intr].dst_apic_int;
1255 assign_apic_irq(apic, intpin, irq);
1256 io_apic_setup_intpin(apic, intpin);
1261 swap_apic_id(int apic, int oldid, int newid)
1268 return; /* Nothing to do */
1270 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1271 apic, oldid, newid);
1273 /* Swap physical APIC IDs in interrupt entries */
1274 for (x = 0; x < nintrs; x++) {
1275 if (io_apic_ints[x].dst_apic_id == oldid)
1276 io_apic_ints[x].dst_apic_id = newid;
1277 else if (io_apic_ints[x].dst_apic_id == newid)
1278 io_apic_ints[x].dst_apic_id = oldid;
1281 /* Swap physical APIC IDs in IO_TO_ID mappings */
1282 for (oapic = 0; oapic < mp_napics; oapic++)
1283 if (IO_TO_ID(oapic) == newid)
1286 if (oapic < mp_napics) {
1287 kprintf("Changing APIC ID for IO APIC #%d from "
1288 "%d to %d in MP table\n",
1289 oapic, newid, oldid);
1290 IO_TO_ID(oapic) = oldid;
1292 IO_TO_ID(apic) = newid;
1297 fix_id_to_io_mapping(void)
1301 for (x = 0; x < NAPICID; x++)
1304 for (x = 0; x <= mp_naps; x++)
1305 if (CPU_TO_ID(x) < NAPICID)
1306 ID_TO_IO(CPU_TO_ID(x)) = x;
1308 for (x = 0; x < mp_napics; x++)
1309 if (IO_TO_ID(x) < NAPICID)
1310 ID_TO_IO(IO_TO_ID(x)) = x;
1315 first_free_apic_id(void)
1319 for (freeid = 0; freeid < NAPICID; freeid++) {
1320 for (x = 0; x <= mp_naps; x++)
1321 if (CPU_TO_ID(x) == freeid)
1325 for (x = 0; x < mp_napics; x++)
1326 if (IO_TO_ID(x) == freeid)
1337 io_apic_id_acceptable(int apic, int id)
1339 int cpu; /* Logical CPU number */
1340 int oapic; /* Logical IO APIC number for other IO APIC */
1343 return 0; /* Out of range */
1345 for (cpu = 0; cpu <= mp_naps; cpu++)
1346 if (CPU_TO_ID(cpu) == id)
1347 return 0; /* Conflict with CPU */
1349 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1350 if (IO_TO_ID(oapic) == id)
1351 return 0; /* Conflict with other APIC */
1353 return 1; /* ID is acceptable for IO APIC */
1358 io_apic_find_int_entry(int apic, int pin)
1362 /* search each of the possible INTerrupt sources */
1363 for (x = 0; x < nintrs; ++x) {
1364 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1365 (pin == io_apic_ints[x].dst_apic_int))
1366 return (&io_apic_ints[x]);
1372 * parse an Intel MP specification table
1379 int apic; /* IO APIC unit number */
1380 int freeid; /* Free physical APIC ID */
1381 int physid; /* Current physical IO APIC ID */
1383 int bus_0 = 0; /* Stop GCC warning */
1384 int bus_pci = 0; /* Stop GCC warning */
1388 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1389 * did it wrong. The MP spec says that when more than 1 PCI bus
1390 * exists the BIOS must begin with bus entries for the PCI bus and use
1391 * actual PCI bus numbering. This implies that when only 1 PCI bus
1392 * exists the BIOS can choose to ignore this ordering, and indeed many
1393 * MP motherboards do ignore it. This causes a problem when the PCI
1394 * sub-system makes requests of the MP sub-system based on PCI bus
1395 * numbers. So here we look for the situation and renumber the
1396 * busses and associated INTs in an effort to "make it right".
1399 /* find bus 0, PCI bus, count the number of PCI busses */
1400 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1401 if (bus_data[x].bus_id == 0) {
1404 if (bus_data[x].bus_type == PCI) {
1410 * bus_0 == slot of bus with ID of 0
1411 * bus_pci == slot of last PCI bus encountered
1414 /* check the 1 PCI bus case for sanity */
1415 /* if it is number 0 all is well */
1416 if (num_pci_bus == 1 &&
1417 bus_data[bus_pci].bus_id != 0) {
1419 /* mis-numbered, swap with whichever bus uses slot 0 */
1421 /* swap the bus entry types */
1422 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1423 bus_data[bus_0].bus_type = PCI;
1425 /* swap each relavant INTerrupt entry */
1426 id = bus_data[bus_pci].bus_id;
1427 for (x = 0; x < nintrs; ++x) {
1428 if (io_apic_ints[x].src_bus_id == id) {
1429 io_apic_ints[x].src_bus_id = 0;
1431 else if (io_apic_ints[x].src_bus_id == 0) {
1432 io_apic_ints[x].src_bus_id = id;
1437 /* Assign IO APIC IDs.
1439 * First try the existing ID. If a conflict is detected, try
1440 * the ID in the MP table. If a conflict is still detected, find
1443 * We cannot use the ID_TO_IO table before all conflicts has been
1444 * resolved and the table has been corrected.
1446 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1448 /* First try to use the value set by the BIOS */
1449 physid = io_apic_get_id(apic);
1450 if (io_apic_id_acceptable(apic, physid)) {
1451 if (IO_TO_ID(apic) != physid)
1452 swap_apic_id(apic, IO_TO_ID(apic), physid);
1456 /* Then check if the value in the MP table is acceptable */
1457 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1460 /* Last resort, find a free APIC ID and use it */
1461 freeid = first_free_apic_id();
1462 if (freeid >= NAPICID)
1463 panic("No free physical APIC IDs found");
1465 if (io_apic_id_acceptable(apic, freeid)) {
1466 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1469 panic("Free physical APIC ID not usable");
1471 fix_id_to_io_mapping();
1473 /* detect and fix broken Compaq MP table */
1474 if (apic_int_type(0, 0) == -1) {
1475 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1476 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1477 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1478 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1479 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1480 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1482 } else if (apic_int_type(0, 0) == 0) {
1483 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1484 for (x = 0; x < nintrs; ++x)
1485 if ((0 == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1486 (0 == io_apic_ints[x].dst_apic_int)) {
1487 io_apic_ints[x].int_type = 3;
1488 io_apic_ints[x].int_vector = 0xff;
1494 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1495 * controllers universally come in pairs. If IRQ 14 is specified
1496 * as an ISA interrupt, then IRQ 15 had better be too.
1498 * [ Shuttle XPC / AMD Athlon X2 ]
1499 * The MPTable is missing an entry for IRQ 15. Note that the
1500 * ACPI table has an entry for both 14 and 15.
1502 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
1503 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1504 io14 = io_apic_find_int_entry(0, 14);
1505 io_apic_ints[nintrs] = *io14;
1506 io_apic_ints[nintrs].src_bus_irq = 15;
1507 io_apic_ints[nintrs].dst_apic_int = 15;
1512 /* Assign low level interrupt handlers */
1514 setup_apic_irq_mapping(void)
1520 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1521 int_to_apicintpin[x].ioapic = -1;
1522 int_to_apicintpin[x].int_pin = 0;
1523 int_to_apicintpin[x].apic_address = NULL;
1524 int_to_apicintpin[x].redirindex = 0;
1526 /* Default to masked */
1527 int_to_apicintpin[x].flags = IOAPIC_IM_FLAG_MASKED;
1530 /* First assign ISA/EISA interrupts */
1531 for (x = 0; x < nintrs; x++) {
1532 int_vector = io_apic_ints[x].src_bus_irq;
1533 if (int_vector < APIC_INTMAPSIZE &&
1534 io_apic_ints[x].int_vector == 0xff &&
1535 int_to_apicintpin[int_vector].ioapic == -1 &&
1536 (apic_int_is_bus_type(x, ISA) ||
1537 apic_int_is_bus_type(x, EISA)) &&
1538 io_apic_ints[x].int_type == 0) {
1539 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1540 io_apic_ints[x].dst_apic_int,
1545 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1546 for (x = 0; x < nintrs; x++) {
1547 if (io_apic_ints[x].dst_apic_int == 0 &&
1548 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1549 io_apic_ints[x].int_vector == 0xff &&
1550 int_to_apicintpin[0].ioapic == -1 &&
1551 io_apic_ints[x].int_type == 3) {
1552 assign_apic_irq(0, 0, 0);
1556 /* PCI interrupt assignment is deferred */
1562 mp_set_cpuids(int cpu_id, int apic_id)
1564 CPU_TO_ID(cpu_id) = apic_id;
1565 ID_TO_CPU(apic_id) = cpu_id;
1569 processor_entry(const struct PROCENTRY *entry, int cpu)
1573 /* check for usability */
1574 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1577 /* check for BSP flag */
1578 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1579 mp_set_cpuids(0, entry->apic_id);
1580 return 0; /* its already been counted */
1583 /* add another AP to list, if less than max number of CPUs */
1584 else if (cpu < MAXCPU) {
1585 mp_set_cpuids(cpu, entry->apic_id);
1595 bus_entry(const struct BUSENTRY *entry, int bus)
1600 /* encode the name into an index */
1601 for (x = 0; x < 6; ++x) {
1602 if ((c = entry->bus_type[x]) == ' ')
1608 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1609 panic("unknown bus type: '%s'", name);
1611 bus_data[bus].bus_id = entry->bus_id;
1612 bus_data[bus].bus_type = x;
1618 io_apic_entry(const struct IOAPICENTRY *entry, int apic)
1620 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1623 IO_TO_ID(apic) = entry->apic_id;
1624 ID_TO_IO(entry->apic_id) = apic;
1630 lookup_bus_type(char *name)
1634 for (x = 0; x < MAX_BUSTYPE; ++x)
1635 if (strcmp(bus_type_table[x].name, name) == 0)
1636 return bus_type_table[x].type;
1638 return UNKNOWN_BUSTYPE;
1642 int_entry(const struct INTENTRY *entry, int intr)
1646 io_apic_ints[intr].int_type = entry->int_type;
1647 io_apic_ints[intr].int_flags = entry->int_flags;
1648 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1649 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1650 if (entry->dst_apic_id == 255) {
1651 /* This signal goes to all IO APICS. Select an IO APIC
1652 with sufficient number of interrupt pins */
1653 for (apic = 0; apic < mp_napics; apic++)
1654 if (((io_apic_read(apic, IOAPIC_VER) &
1655 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1656 entry->dst_apic_int)
1658 if (apic < mp_napics)
1659 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1661 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1663 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1664 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1670 apic_int_is_bus_type(int intr, int bus_type)
1674 for (bus = 0; bus < mp_nbusses; ++bus)
1675 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1676 && ((int) bus_data[bus].bus_type == bus_type))
1683 * Given a traditional ISA INT mask, return an APIC mask.
1686 isa_apic_mask(u_int isa_mask)
1691 #if defined(SKIP_IRQ15_REDIRECT)
1692 if (isa_mask == (1 << 15)) {
1693 kprintf("skipping ISA IRQ15 redirect\n");
1696 #endif /* SKIP_IRQ15_REDIRECT */
1698 isa_irq = ffs(isa_mask); /* find its bit position */
1699 if (isa_irq == 0) /* doesn't exist */
1701 --isa_irq; /* make it zero based */
1703 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1707 return (1 << apic_pin); /* convert pin# to a mask */
1711 * Determine which APIC pin an ISA/EISA INT is attached to.
1713 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1714 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1715 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1716 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1718 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1720 isa_apic_irq(int isa_irq)
1724 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1725 if (INTTYPE(intr) == 0) { /* standard INT */
1726 if (SRCBUSIRQ(intr) == isa_irq) {
1727 if (apic_int_is_bus_type(intr, ISA) ||
1728 apic_int_is_bus_type(intr, EISA)) {
1729 if (INTIRQ(intr) == 0xff)
1730 return -1; /* unassigned */
1731 return INTIRQ(intr); /* found */
1736 return -1; /* NOT found */
1741 * Determine which APIC pin a PCI INT is attached to.
1743 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1744 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1745 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1747 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1751 --pciInt; /* zero based */
1753 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1754 if ((INTTYPE(intr) == 0) /* standard INT */
1755 && (SRCBUSID(intr) == pciBus)
1756 && (SRCBUSDEVICE(intr) == pciDevice)
1757 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
1758 if (apic_int_is_bus_type(intr, PCI)) {
1759 if (INTIRQ(intr) == 0xff)
1760 allocate_apic_irq(intr);
1761 if (INTIRQ(intr) == 0xff)
1762 return -1; /* unassigned */
1763 return INTIRQ(intr); /* exact match */
1768 return -1; /* NOT found */
1772 next_apic_irq(int irq)
1779 for (intr = 0; intr < nintrs; intr++) {
1780 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1782 bus = SRCBUSID(intr);
1783 bustype = apic_bus_type(bus);
1784 if (bustype != ISA &&
1790 if (intr >= nintrs) {
1793 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1794 if (INTTYPE(ointr) != 0)
1796 if (bus != SRCBUSID(ointr))
1798 if (bustype == PCI) {
1799 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1801 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1804 if (bustype == ISA || bustype == EISA) {
1805 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1808 if (INTPIN(intr) == INTPIN(ointr))
1812 if (ointr >= nintrs) {
1815 return INTIRQ(ointr);
1830 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1833 * Exactly what this means is unclear at this point. It is a solution
1834 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1835 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1836 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1840 undirect_isa_irq(int rirq)
1844 kprintf("Freeing redirected ISA irq %d.\n", rirq);
1845 /** FIXME: tickle the MB redirector chip */
1849 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1856 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1859 undirect_pci_irq(int rirq)
1863 kprintf("Freeing redirected PCI irq %d.\n", rirq);
1865 /** FIXME: tickle the MB redirector chip */
1869 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1879 * given a bus ID, return:
1880 * the bus type if found
1884 apic_bus_type(int id)
1888 for (x = 0; x < mp_nbusses; ++x)
1889 if (bus_data[x].bus_id == id)
1890 return bus_data[x].bus_type;
1896 * given a LOGICAL APIC# and pin#, return:
1897 * the associated src bus ID if found
1901 apic_src_bus_id(int apic, int pin)
1905 /* search each of the possible INTerrupt sources */
1906 for (x = 0; x < nintrs; ++x)
1907 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1908 (pin == io_apic_ints[x].dst_apic_int))
1909 return (io_apic_ints[x].src_bus_id);
1911 return -1; /* NOT found */
1915 * given a LOGICAL APIC# and pin#, return:
1916 * the associated src bus IRQ if found
1920 apic_src_bus_irq(int apic, int pin)
1924 for (x = 0; x < nintrs; x++)
1925 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1926 (pin == io_apic_ints[x].dst_apic_int))
1927 return (io_apic_ints[x].src_bus_irq);
1929 return -1; /* NOT found */
1934 * given a LOGICAL APIC# and pin#, return:
1935 * the associated INTerrupt type if found
1939 apic_int_type(int apic, int pin)
1943 /* search each of the possible INTerrupt sources */
1944 for (x = 0; x < nintrs; ++x) {
1945 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1946 (pin == io_apic_ints[x].dst_apic_int))
1947 return (io_apic_ints[x].int_type);
1949 return -1; /* NOT found */
1953 * Return the IRQ associated with an APIC pin
1956 apic_irq(int apic, int pin)
1961 for (x = 0; x < nintrs; ++x) {
1962 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1963 (pin == io_apic_ints[x].dst_apic_int)) {
1964 res = io_apic_ints[x].int_vector;
1967 if (apic != int_to_apicintpin[res].ioapic)
1968 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
1969 if (pin != int_to_apicintpin[res].int_pin)
1970 panic("apic_irq inconsistent table (2)");
1979 * given a LOGICAL APIC# and pin#, return:
1980 * the associated trigger mode if found
1984 apic_trigger(int apic, int pin)
1988 /* search each of the possible INTerrupt sources */
1989 for (x = 0; x < nintrs; ++x)
1990 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1991 (pin == io_apic_ints[x].dst_apic_int))
1992 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1994 return -1; /* NOT found */
1999 * given a LOGICAL APIC# and pin#, return:
2000 * the associated 'active' level if found
2004 apic_polarity(int apic, int pin)
2008 /* search each of the possible INTerrupt sources */
2009 for (x = 0; x < nintrs; ++x)
2010 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
2011 (pin == io_apic_ints[x].dst_apic_int))
2012 return (io_apic_ints[x].int_flags & 0x03);
2014 return -1; /* NOT found */
2018 * set data according to MP defaults
2019 * FIXME: probably not complete yet...
2022 mptable_default(int type)
2028 kprintf(" MP default config type: %d\n", type);
2031 kprintf(" bus: ISA, APIC: 82489DX\n");
2034 kprintf(" bus: EISA, APIC: 82489DX\n");
2037 kprintf(" bus: EISA, APIC: 82489DX\n");
2040 kprintf(" bus: MCA, APIC: 82489DX\n");
2043 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
2046 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
2049 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
2052 kprintf(" future type\n");
2058 /* one and only IO APIC */
2059 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
2062 * sanity check, refer to MP spec section 3.6.6, last paragraph
2063 * necessary as some hardware isn't properly setting up the IO APIC
2065 #if defined(REALLY_ANAL_IOAPICID_VALUE)
2066 if (io_apic_id != 2) {
2068 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
2069 #endif /* REALLY_ANAL_IOAPICID_VALUE */
2070 io_apic_set_id(0, 2);
2073 IO_TO_ID(0) = io_apic_id;
2074 ID_TO_IO(io_apic_id) = 0;
2076 /* fill out bus entries */
2085 bus_data[0].bus_id = default_data[type - 1][1];
2086 bus_data[0].bus_type = default_data[type - 1][2];
2087 bus_data[1].bus_id = default_data[type - 1][3];
2088 bus_data[1].bus_type = default_data[type - 1][4];
2091 /* case 4: case 7: MCA NOT supported */
2092 default: /* illegal/reserved */
2093 panic("BAD default MP config: %d", type);
2097 /* general cases from MP v1.4, table 5-2 */
2098 for (pin = 0; pin < 16; ++pin) {
2099 io_apic_ints[pin].int_type = 0;
2100 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2101 io_apic_ints[pin].src_bus_id = 0;
2102 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2103 io_apic_ints[pin].dst_apic_id = io_apic_id;
2104 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2107 /* special cases from MP v1.4, table 5-2 */
2109 io_apic_ints[2].int_type = 0xff; /* N/C */
2110 io_apic_ints[13].int_type = 0xff; /* N/C */
2111 #if !defined(APIC_MIXED_MODE)
2113 panic("sorry, can't support type 2 default yet");
2114 #endif /* APIC_MIXED_MODE */
2117 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2120 io_apic_ints[0].int_type = 0xff; /* N/C */
2122 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2125 #endif /* APIC_IO */
2128 * Map a physical memory address representing I/O into KVA. The I/O
2129 * block is assumed not to cross a page boundary.
2132 permanent_io_mapping(vm_paddr_t pa)
2138 KKASSERT(pa < 0x100000000LL);
2140 pgeflag = 0; /* not used for SMP yet */
2143 * If the requested physical address has already been incidently
2144 * mapped, just use the existing mapping. Otherwise create a new
2147 for (i = IO_MAPPING_START_INDEX; i < SMPpt_alloc_index; ++i) {
2148 if (((vm_offset_t)SMPpt[i] & PG_FRAME) ==
2149 ((vm_offset_t)pa & PG_FRAME)) {
2153 if (i == SMPpt_alloc_index) {
2154 if (i == NPTEPG - 2) {
2155 panic("permanent_io_mapping: We ran out of space"
2158 SMPpt[i] = (pt_entry_t)(PG_V | PG_RW | PG_N | pgeflag |
2159 ((vm_offset_t)pa & PG_FRAME));
2160 ++SMPpt_alloc_index;
2162 vaddr = (vm_offset_t)CPU_prvspace + (i * PAGE_SIZE) +
2163 ((vm_offset_t)pa & PAGE_MASK);
2164 return ((void *)vaddr);
2168 * start each AP in our list
2171 start_all_aps(u_int boot_addr)
2178 u_char mpbiosreason;
2179 u_long mpbioswarmvec;
2180 struct mdglobaldata *gd;
2181 struct privatespace *ps;
2185 POSTCODE(START_ALL_APS_POST);
2187 /* Initialize BSP's local APIC */
2188 apic_initialize(TRUE);
2190 /* install the AP 1st level boot code */
2191 install_ap_tramp(boot_addr);
2194 /* save the current value of the warm-start vector */
2195 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
2196 outb(CMOS_REG, BIOS_RESET);
2197 mpbiosreason = inb(CMOS_DATA);
2199 /* setup a vector to our boot code */
2200 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2201 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2202 outb(CMOS_REG, BIOS_RESET);
2203 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2206 * If we have a TSC we can figure out the SMI interrupt rate.
2207 * The SMI does not necessarily use a constant rate. Spend
2208 * up to 250ms trying to figure it out.
2211 if (cpu_feature & CPUID_TSC) {
2212 set_apic_timer(275000);
2213 smilast = read_apic_timer();
2214 for (x = 0; x < 20 && read_apic_timer(); ++x) {
2215 smicount = smitest();
2216 if (smibest == 0 || smilast - smicount < smibest)
2217 smibest = smilast - smicount;
2220 if (smibest > 250000)
2223 smibest = smibest * (int64_t)1000000 /
2224 get_apic_timer_frequency();
2228 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
2229 1000000 / smibest, smibest);
2232 /* set up temporary P==V mapping for AP boot */
2233 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
2234 kptbase = (uintptr_t)(void *)KPTphys;
2235 for (x = 0; x < NKPT; x++) {
2236 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
2237 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
2242 for (x = 1; x <= mp_naps; ++x) {
2244 /* This is a bit verbose, it will go away soon. */
2246 /* first page of AP's private space */
2247 pg = x * i386_btop(sizeof(struct privatespace));
2249 /* allocate new private data page(s) */
2250 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
2251 MDGLOBALDATA_BASEALLOC_SIZE);
2252 /* wire it into the private page table page */
2253 for (i = 0; i < MDGLOBALDATA_BASEALLOC_SIZE; i += PAGE_SIZE) {
2254 SMPpt[pg + i / PAGE_SIZE] = (pt_entry_t)
2255 (PG_V | PG_RW | vtophys_pte((char *)gd + i));
2257 pg += MDGLOBALDATA_BASEALLOC_PAGES;
2259 SMPpt[pg + 0] = 0; /* *gd_CMAP1 */
2260 SMPpt[pg + 1] = 0; /* *gd_CMAP2 */
2261 SMPpt[pg + 2] = 0; /* *gd_CMAP3 */
2262 SMPpt[pg + 3] = 0; /* *gd_PMAP1 */
2264 /* allocate and set up an idle stack data page */
2265 stack = (char *)kmem_alloc(&kernel_map, UPAGES*PAGE_SIZE);
2266 for (i = 0; i < UPAGES; i++) {
2267 SMPpt[pg + 4 + i] = (pt_entry_t)
2268 (PG_V | PG_RW | vtophys_pte(PAGE_SIZE * i + stack));
2271 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2272 bzero(gd, sizeof(*gd));
2273 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2275 /* prime data page for it to use */
2276 mi_gdinit(&gd->mi, x);
2278 gd->gd_CMAP1 = &SMPpt[pg + 0];
2279 gd->gd_CMAP2 = &SMPpt[pg + 1];
2280 gd->gd_CMAP3 = &SMPpt[pg + 2];
2281 gd->gd_PMAP1 = &SMPpt[pg + 3];
2282 gd->gd_CADDR1 = ps->CPAGE1;
2283 gd->gd_CADDR2 = ps->CPAGE2;
2284 gd->gd_CADDR3 = ps->CPAGE3;
2285 gd->gd_PADDR1 = (unsigned *)ps->PPAGE1;
2288 * Per-cpu pmap for get_ptbase().
2290 gd->gd_GDADDR1= (unsigned *)
2291 kmem_alloc_nofault(&kernel_map, SEG_SIZE, SEG_SIZE);
2292 gd->gd_GDMAP1 = &PTD[(vm_offset_t)gd->gd_GDADDR1 >> PDRSHIFT];
2294 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2295 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2298 * Setup the AP boot stack
2300 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2303 /* attempt to start the Application Processor */
2304 CHECK_INIT(99); /* setup checkpoints */
2305 if (!start_ap(gd, boot_addr, smibest)) {
2306 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2307 CHECK_PRINT("trace"); /* show checkpoints */
2308 /* better panic as the AP may be running loose */
2309 kprintf("panic y/n? [y] ");
2310 if (cngetc() != 'n')
2313 CHECK_PRINT("trace"); /* show checkpoints */
2315 /* record its version info */
2316 cpu_apic_versions[x] = cpu_apic_versions[0];
2319 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2322 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2323 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2326 ncpus2_shift = shift;
2327 ncpus2 = 1 << shift;
2328 ncpus2_mask = ncpus2 - 1;
2330 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2331 if ((1 << shift) < ncpus)
2333 ncpus_fit = 1 << shift;
2334 ncpus_fit_mask = ncpus_fit - 1;
2336 /* build our map of 'other' CPUs */
2337 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2338 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
2339 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2341 /* fill in our (BSP) APIC version */
2342 cpu_apic_versions[0] = lapic.version;
2344 /* restore the warmstart vector */
2345 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2346 outb(CMOS_REG, BIOS_RESET);
2347 outb(CMOS_DATA, mpbiosreason);
2350 * NOTE! The idlestack for the BSP was setup by locore. Finish
2351 * up, clean out the P==V mapping we did earlier.
2353 for (x = 0; x < NKPT; x++)
2357 /* number of APs actually started */
2362 * load the 1st level AP boot code into base memory.
2365 /* targets for relocation */
2366 extern void bigJump(void);
2367 extern void bootCodeSeg(void);
2368 extern void bootDataSeg(void);
2369 extern void MPentry(void);
2370 extern u_int MP_GDT;
2371 extern u_int mp_gdtbase;
2374 install_ap_tramp(u_int boot_addr)
2377 int size = *(int *) ((u_long) & bootMP_size);
2378 u_char *src = (u_char *) ((u_long) bootMP);
2379 u_char *dst = (u_char *) boot_addr + KERNBASE;
2380 u_int boot_base = (u_int) bootMP;
2385 POSTCODE(INSTALL_AP_TRAMP_POST);
2387 for (x = 0; x < size; ++x)
2391 * modify addresses in code we just moved to basemem. unfortunately we
2392 * need fairly detailed info about mpboot.s for this to work. changes
2393 * to mpboot.s might require changes here.
2396 /* boot code is located in KERNEL space */
2397 dst = (u_char *) boot_addr + KERNBASE;
2399 /* modify the lgdt arg */
2400 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2401 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2403 /* modify the ljmp target for MPentry() */
2404 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2405 *dst32 = ((u_int) MPentry - KERNBASE);
2407 /* modify the target for boot code segment */
2408 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2409 dst8 = (u_int8_t *) (dst16 + 1);
2410 *dst16 = (u_int) boot_addr & 0xffff;
2411 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2413 /* modify the target for boot data segment */
2414 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2415 dst8 = (u_int8_t *) (dst16 + 1);
2416 *dst16 = (u_int) boot_addr & 0xffff;
2417 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2422 * This function starts the AP (application processor) identified
2423 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2424 * to accomplish this. This is necessary because of the nuances
2425 * of the different hardware we might encounter. It ain't pretty,
2426 * but it seems to work.
2428 * NOTE: eventually an AP gets to ap_init(), which is called just
2429 * before the AP goes into the LWKT scheduler's idle loop.
2432 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
2436 u_long icr_lo, icr_hi;
2438 POSTCODE(START_AP_POST);
2440 /* get the PHYSICAL APIC ID# */
2441 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2443 /* calculate the vector */
2444 vector = (boot_addr >> 12) & 0xff;
2446 /* We don't want anything interfering */
2449 /* Make sure the target cpu sees everything */
2453 * Try to detect when a SMI has occurred, wait up to 200ms.
2455 * If a SMI occurs during an AP reset but before we issue
2456 * the STARTUP command, the AP may brick. To work around
2457 * this problem we hold off doing the AP startup until
2458 * after we have detected the SMI. Hopefully another SMI
2459 * will not occur before we finish the AP startup.
2461 * Retries don't seem to help. SMIs have a window of opportunity
2462 * and if USB->legacy keyboard emulation is enabled in the BIOS
2463 * the interrupt rate can be quite high.
2465 * NOTE: Don't worry about the L1 cache load, it might bloat
2466 * ldelta a little but ndelta will be so huge when the SMI
2467 * occurs the detection logic will still work fine.
2470 set_apic_timer(200000);
2475 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2476 * and running the target CPU. OR this INIT IPI might be latched (P5
2477 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2480 * see apic/apicreg.h for icr bit definitions.
2482 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
2486 * Setup the address for the target AP. We can setup
2487 * icr_hi once and then just trigger operations with
2490 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
2491 icr_hi |= (physical_cpu << 24);
2492 icr_lo = lapic.icr_lo & 0xfff00000;
2493 lapic.icr_hi = icr_hi;
2496 * Do an INIT IPI: assert RESET
2498 * Use edge triggered mode to assert INIT
2500 lapic.icr_lo = icr_lo | 0x0000c500;
2501 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2505 * The spec calls for a 10ms delay but we may have to use a
2506 * MUCH lower delay to avoid bricking an AP due to a fast SMI
2507 * interrupt. We have other loops here too and dividing by 2
2508 * doesn't seem to be enough even after subtracting 350us,
2509 * so we divide by 4.
2511 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
2512 * interrupt was detected we use the full 10ms.
2516 else if (smibest < 150 * 4 + 350)
2518 else if ((smibest - 350) / 4 < 10000)
2519 u_sleep((smibest - 350) / 4);
2524 * Do an INIT IPI: deassert RESET
2526 * Use level triggered mode to deassert. It is unclear
2527 * why we need to do this.
2529 lapic.icr_lo = icr_lo | 0x00008500;
2530 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2532 u_sleep(150); /* wait 150us */
2535 * Next we do a STARTUP IPI: the previous INIT IPI might still be
2536 * latched, (P5 bug) this 1st STARTUP would then terminate
2537 * immediately, and the previously started INIT IPI would continue. OR
2538 * the previous INIT IPI has already run. and this STARTUP IPI will
2539 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2542 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2543 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2545 u_sleep(200); /* wait ~200uS */
2548 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2549 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2550 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2551 * recognized after hardware RESET or INIT IPI.
2553 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2554 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2557 /* Resume normal operation */
2560 /* wait for it to start, see ap_init() */
2561 set_apic_timer(5000000);/* == 5 seconds */
2562 while (read_apic_timer()) {
2563 if (smp_startup_mask & (1 << gd->mi.gd_cpuid))
2564 return 1; /* return SUCCESS */
2567 return 0; /* return FAILURE */
2582 while (read_apic_timer()) {
2584 for (count = 0; count < 100; ++count)
2585 ntsc = rdtsc(); /* force loop to occur */
2587 ndelta = ntsc - ltsc;
2588 if (ldelta > ndelta)
2590 if (ndelta > ldelta * 2)
2593 ldelta = ntsc - ltsc;
2596 return(read_apic_timer());
2600 * Lazy flush the TLB on all other CPU's. DEPRECATED.
2602 * If for some reason we were unable to start all cpus we cannot safely
2603 * use broadcast IPIs.
2609 pmap_inval_info info;
2611 pmap_inval_init(&info);
2612 pmap_inval_interlock(&info, &kernel_pmap, -1);
2613 pmap_inval_deinterlock(&info, &kernel_pmap);
2614 pmap_inval_done(&info);
2616 if (smp_startup_mask == smp_active_mask) {
2617 all_but_self_ipi(XINVLTLB_OFFSET);
2619 selected_apic_ipi(smp_active_mask, XINVLTLB_OFFSET,
2620 APIC_DELMODE_FIXED);
2627 * When called the executing CPU will send an IPI to all other CPUs
2628 * requesting that they halt execution.
2630 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2632 * - Signals all CPUs in map to stop.
2633 * - Waits for each to stop.
2640 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2641 * from executing at same time.
2644 stop_cpus(u_int map)
2646 map &= smp_active_mask;
2648 /* send the Xcpustop IPI to all CPUs in map */
2649 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2651 while ((stopped_cpus & map) != map)
2659 * Called by a CPU to restart stopped CPUs.
2661 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2663 * - Signals all CPUs in map to restart.
2664 * - Waits for each to restart.
2672 restart_cpus(u_int map)
2674 /* signal other cpus to restart */
2675 started_cpus = map & smp_active_mask;
2677 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2684 * This is called once the mpboot code has gotten us properly relocated
2685 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2686 * and when it returns the scheduler will call the real cpu_idle() main
2687 * loop for the idlethread. Interrupts are disabled on entry and should
2688 * remain disabled at return.
2696 * Adjust smp_startup_mask to signal the BSP that we have started
2697 * up successfully. Note that we do not yet hold the BGL. The BSP
2698 * is waiting for our signal.
2700 * We can't set our bit in smp_active_mask yet because we are holding
2701 * interrupts physically disabled and remote cpus could deadlock
2702 * trying to send us an IPI.
2704 smp_startup_mask |= 1 << mycpu->gd_cpuid;
2708 * Interlock for finalization. Wait until mp_finish is non-zero,
2709 * then get the MP lock.
2711 * Note: We are in a critical section.
2713 * Note: We have to synchronize td_mpcount to our desired MP state
2714 * before calling cpu_try_mplock().
2716 * Note: we are the idle thread, we can only spin.
2718 * Note: The load fence is memory volatile and prevents the compiler
2719 * from improperly caching mp_finish, and the cpu from improperly
2722 while (mp_finish == 0)
2724 ++curthread->td_mpcount;
2725 while (cpu_try_mplock() == 0)
2728 if (cpu_feature & CPUID_TSC) {
2730 * The BSP is constantly updating tsc0_offset, figure out the
2731 * relative difference to synchronize ktrdump.
2733 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2736 /* BSP may have changed PTD while we're waiting for the lock */
2739 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2743 /* Build our map of 'other' CPUs. */
2744 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2746 kprintf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
2748 /* A quick check from sanity claus */
2749 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]);
2750 if (mycpu->gd_cpuid != apic_id) {
2751 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2752 kprintf("SMP: apic_id = %d\n", apic_id);
2753 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2754 panic("cpuid mismatch! boom!!");
2757 /* Initialize AP's local APIC for irq's */
2758 apic_initialize(FALSE);
2760 /* Set memory range attributes for this CPU to match the BSP */
2761 mem_range_AP_init();
2764 * Once we go active we must process any IPIQ messages that may
2765 * have been queued, because no actual IPI will occur until we
2766 * set our bit in the smp_active_mask. If we don't the IPI
2767 * message interlock could be left set which would also prevent
2770 * The idle loop doesn't expect the BGL to be held and while
2771 * lwkt_switch() normally cleans things up this is a special case
2772 * because we returning almost directly into the idle loop.
2774 * The idle thread is never placed on the runq, make sure
2775 * nothing we've done put it there.
2777 KKASSERT(curthread->td_mpcount == 1);
2778 smp_active_mask |= 1 << mycpu->gd_cpuid;
2781 * Enable interrupts here. idle_restore will also do it, but
2782 * doing it here lets us clean up any strays that got posted to
2783 * the CPU during the AP boot while we are still in a critical
2786 __asm __volatile("sti; pause; pause"::);
2787 mdcpu->gd_fpending = 0;
2789 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2790 lwkt_process_ipiq();
2793 * Releasing the mp lock lets the BSP finish up the SMP init
2796 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
2800 * Get SMP fully working before we start initializing devices.
2808 kprintf("Finish MP startup\n");
2809 if (cpu_feature & CPUID_TSC)
2810 tsc0_offset = rdtsc();
2813 while (smp_active_mask != smp_startup_mask) {
2815 if (cpu_feature & CPUID_TSC)
2816 tsc0_offset = rdtsc();
2818 while (try_mplock() == 0)
2821 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
2824 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
2827 cpu_send_ipiq(int dcpu)
2829 if ((1 << dcpu) & smp_active_mask)
2830 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2833 #if 0 /* single_apic_ipi_passive() not working yet */
2835 * Returns 0 on failure, 1 on success
2838 cpu_send_ipiq_passive(int dcpu)
2841 if ((1 << dcpu) & smp_active_mask) {
2842 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2843 APIC_DELMODE_FIXED);
2849 struct mptable_lapic_cbarg1 {
2852 u_int ht_apicid_mask;
2856 mptable_lapic_pass1_callback(void *xarg, const void *pos, int type)
2858 const struct PROCENTRY *ent;
2859 struct mptable_lapic_cbarg1 *arg = xarg;
2865 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
2869 if (ent->apic_id < 32) {
2870 arg->ht_apicid_mask |= 1 << ent->apic_id;
2871 } else if (arg->ht_fixup) {
2872 kprintf("MPTABLE: lapic id > 32, disable HTT fixup\n");
2878 struct mptable_lapic_cbarg2 {
2885 mptable_lapic_pass2_callback(void *xarg, const void *pos, int type)
2887 const struct PROCENTRY *ent;
2888 struct mptable_lapic_cbarg2 *arg = xarg;
2894 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
2895 KKASSERT(!arg->found_bsp);
2899 if (processor_entry(ent, arg->cpu))
2902 if (arg->logical_cpus) {
2903 struct PROCENTRY proc;
2907 * Create fake mptable processor entries
2908 * and feed them to processor_entry() to
2909 * enumerate the logical CPUs.
2911 bzero(&proc, sizeof(proc));
2913 proc.cpu_flags = PROCENTRY_FLAG_EN;
2914 proc.apic_id = ent->apic_id;
2916 for (i = 1; i < arg->logical_cpus; i++) {
2918 processor_entry(&proc, arg->cpu);
2926 mptable_imcr(struct mptable_pos *mpt)
2928 /* record whether PIC or virtual-wire mode */
2929 machintr_setvar_simple(MACHINTR_VAR_IMCR_PRESENT,
2930 mpt->mp_fps->mpfb2 & 0x80);
2933 struct mptable_lapic_enumerator {
2934 struct lapic_enumerator enumerator;
2935 vm_paddr_t mpfps_paddr;
2939 mptable_lapic_default(void)
2941 int ap_apicid, bsp_apicid;
2943 mp_naps = 1; /* exclude BSP */
2945 /* Map local apic before the id field is accessed */
2946 lapic_map(DEFAULT_APIC_BASE);
2948 bsp_apicid = APIC_ID(lapic.id);
2949 ap_apicid = (bsp_apicid == 0) ? 1 : 0;
2952 mp_set_cpuids(0, bsp_apicid);
2953 /* one and only AP */
2954 mp_set_cpuids(1, ap_apicid);
2960 * ID_TO_CPU(N), APIC ID to logical CPU table
2961 * CPU_TO_ID(N), logical CPU to APIC ID table
2964 mptable_lapic_enumerate(struct lapic_enumerator *e)
2966 struct mptable_pos mpt;
2967 struct mptable_lapic_cbarg1 arg1;
2968 struct mptable_lapic_cbarg2 arg2;
2970 int error, logical_cpus = 0;
2971 vm_offset_t lapic_addr;
2972 vm_paddr_t mpfps_paddr;
2974 mpfps_paddr = ((struct mptable_lapic_enumerator *)e)->mpfps_paddr;
2975 KKASSERT(mpfps_paddr != 0);
2977 error = mptable_map(&mpt, mpfps_paddr);
2979 panic("mptable_lapic_enumerate mptable_map failed\n");
2981 KKASSERT(mpt.mp_fps != NULL);
2984 * Check for use of 'default' configuration
2986 if (mpt.mp_fps->mpfb1 != 0) {
2987 mptable_lapic_default();
2988 mptable_unmap(&mpt);
2993 KKASSERT(cth != NULL);
2995 /* Save local apic address */
2996 lapic_addr = (vm_offset_t)cth->apic_address;
2997 KKASSERT(lapic_addr != 0);
3000 * Find out how many CPUs do we have
3002 bzero(&arg1, sizeof(arg1));
3003 arg1.ht_fixup = 1; /* Apply ht fixup by default */
3005 error = mptable_iterate_entries(cth,
3006 mptable_lapic_pass1_callback, &arg1);
3008 panic("mptable_iterate_entries(lapic_pass1) failed\n");
3009 KKASSERT(arg1.cpu_count != 0);
3011 /* See if we need to fixup HT logical CPUs. */
3012 if (arg1.ht_fixup) {
3013 logical_cpus = mptable_hyperthread_fixup(arg1.ht_apicid_mask,
3015 if (logical_cpus != 0)
3016 arg1.cpu_count *= logical_cpus;
3018 mp_naps = arg1.cpu_count;
3020 /* Qualify the numbers again, after possible HT fixup */
3021 if (mp_naps > MAXCPU) {
3022 kprintf("Warning: only using %d of %d available CPUs!\n",
3027 --mp_naps; /* subtract the BSP */
3030 * Link logical CPU id to local apic id
3032 bzero(&arg2, sizeof(arg2));
3034 arg2.logical_cpus = logical_cpus;
3036 error = mptable_iterate_entries(cth,
3037 mptable_lapic_pass2_callback, &arg2);
3039 panic("mptable_iterate_entries(lapic_pass2) failed\n");
3040 KKASSERT(arg2.found_bsp);
3042 /* Map local apic */
3043 lapic_map(lapic_addr);
3045 mptable_unmap(&mpt);
3049 mptable_lapic_probe(struct lapic_enumerator *e)
3051 vm_paddr_t mpfps_paddr;
3053 mpfps_paddr = mptable_probe();
3054 if (mpfps_paddr == 0)
3057 ((struct mptable_lapic_enumerator *)e)->mpfps_paddr = mpfps_paddr;
3061 static struct mptable_lapic_enumerator mptable_lapic_enumerator = {
3063 .lapic_prio = LAPIC_ENUM_PRIO_MPTABLE,
3064 .lapic_probe = mptable_lapic_probe,
3065 .lapic_enumerate = mptable_lapic_enumerate
3070 mptable_apic_register(void)
3072 lapic_enumerator_register(&mptable_lapic_enumerator.enumerator);
3074 SYSINIT(madt, SI_BOOT2_PRESMP, SI_ORDER_ANY, mptable_apic_register, 0);