sys/dev/netif/re/if_re.c

   1 /*
   2  * Copyright (c) 2004
   3  *      Joerg Sonnenberger <joerg@bec.de>.  All rights reserved.
   4  *
   5  * Copyright (c) 1997, 1998-2003
   6  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   7  *
   8  * Redistribution and use in source and binary forms, with or without
   9  * modification, are permitted provided that the following conditions
  10  * are met:
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in the
  15  *    documentation and/or other materials provided with the distribution.
  16  * 3. All advertising materials mentioning features or use of this software
  17  *    must display the following acknowledgement:
  18  *      This product includes software developed by Bill Paul.
  19  * 4. Neither the name of the author nor the names of any co-contributors
  20  *    may be used to endorse or promote products derived from this software
  21  *    without specific prior written permission.
  22  *
  23  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  24  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  25  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  26  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  27  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  28  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  29  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  30  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  31  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  32  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  33  * THE POSSIBILITY OF SUCH DAMAGE.
  34  *
  35  * $FreeBSD: src/sys/dev/re/if_re.c,v 1.25 2004/06/09 14:34:01 naddy Exp $
  36  * $DragonFly: src/sys/dev/netif/re/if_re.c,v 1.99 2008/10/30 11:27:40 sephe Exp $
  37  */
  38
  39 /*
  40  * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver
  41  *
  42  * Written by Bill Paul <wpaul@windriver.com>
  43  * Senior Networking Software Engineer
  44  * Wind River Systems
  45  */
  46
  47 /*
  48  * This driver is designed to support RealTek's next generation of
  49  * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently
  50  * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S,
  51  * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E.
  52  *
  53  * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible
  54  * with the older 8139 family, however it also supports a special
  55  * C+ mode of operation that provides several new performance enhancing
  56  * features. These include:
  57  *
  58  *      o Descriptor based DMA mechanism. Each descriptor represents
  59  *        a single packet fragment. Data buffers may be aligned on
  60  *        any byte boundary.
  61  *
  62  *      o 64-bit DMA
  63  *
  64  *      o TCP/IP checksum offload for both RX and TX
  65  *
  66  *      o High and normal priority transmit DMA rings
  67  *
  68  *      o VLAN tag insertion and extraction
  69  *
  70  *      o TCP large send (segmentation offload)
  71  *
  72  * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+
  73  * programming API is fairly straightforward. The RX filtering, EEPROM
  74  * access and PHY access is the same as it is on the older 8139 series
  75  * chips.
  76  *
  77  * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the
  78  * same programming API and feature set as the 8139C+ with the following
  79  * differences and additions:
  80  *
  81  *      o 1000Mbps mode
  82  *
  83  *      o Jumbo frames
  84  *
  85  *      o GMII and TBI ports/registers for interfacing with copper
  86  *        or fiber PHYs
  87  *
  88  *      o RX and TX DMA rings can have up to 1024 descriptors
  89  *        (the 8139C+ allows a maximum of 64)
  90  *
  91  *      o Slight differences in register layout from the 8139C+
  92  *
  93  * The TX start and timer interrupt registers are at different locations
  94  * on the 8169 than they are on the 8139C+. Also, the status word in the
  95  * RX descriptor has a slightly different bit layout. The 8169 does not
  96  * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska'
  97  * copper gigE PHY.
  98  *
  99  * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs
 100  * (the 'S' stands for 'single-chip'). These devices have the same
 101  * programming API as the older 8169, but also have some vendor-specific
 102  * registers for the on-board PHY. The 8110S is a LAN-on-motherboard
 103  * part designed to be pin-compatible with the RealTek 8100 10/100 chip.
 104  *
 105  * This driver takes advantage of the RX and TX checksum offload and
 106  * VLAN tag insertion/extraction features. It also implements TX
 107  * interrupt moderation using the timer interrupt registers, which
 108  * significantly reduces TX interrupt load. There is also support
 109  * for jumbo frames, however the 8169/8169S/8110S can not transmit
 110  * jumbo frames larger than 7440, so the max MTU possible with this
 111  * driver is 7422 bytes.
 112  */
 113
 114 #define _IP_VHL
 115
 116 #include "opt_polling.h"
 117
 118 #include <sys/param.h>
 119 #include <sys/bus.h>
 120 #include <sys/endian.h>
 121 #include <sys/kernel.h>
 122 #include <sys/in_cksum.h>
 123 #include <sys/interrupt.h>
 124 #include <sys/malloc.h>
 125 #include <sys/mbuf.h>
 126 #include <sys/rman.h>
 127 #include <sys/serialize.h>
 128 #include <sys/socket.h>
 129 #include <sys/sockio.h>
 130 #include <sys/sysctl.h>
 131
 132 #include <net/bpf.h>
 133 #include <net/ethernet.h>
 134 #include <net/if.h>
 135 #include <net/ifq_var.h>
 136 #include <net/if_arp.h>
 137 #include <net/if_dl.h>
 138 #include <net/if_media.h>
 139 #include <net/if_types.h>
 140 #include <net/vlan/if_vlan_var.h>
 141 #include <net/vlan/if_vlan_ether.h>
 142
 143 #include <netinet/ip.h>
 144
 145 #include <dev/netif/mii_layer/mii.h>
 146 #include <dev/netif/mii_layer/miivar.h>
 147
 148 #include <bus/pci/pcidevs.h>
 149 #include <bus/pci/pcireg.h>
 150 #include <bus/pci/pcivar.h>
 151
 152 /* "device miibus" required.  See GENERIC if you get errors here. */
 153 #include "miibus_if.h"
 154
 155 #include <dev/netif/re/if_rereg.h>
 156 #include <dev/netif/re/if_revar.h>
 157
 158 #define RE_CSUM_FEATURES    (CSUM_IP | CSUM_TCP | CSUM_UDP)
 159
 160 /*
 161  * Various supported device vendors/types and their names.
 162  */
 163 static const struct re_type {
 164         uint16_t        re_vid;
 165         uint16_t        re_did;
 166         const char      *re_name;
 167 } re_devs[] = {
 168         { PCI_VENDOR_DLINK, PCI_PRODUCT_DLINK_DGE528T,
 169           "D-Link DGE-528(T) Gigabit Ethernet Adapter" },
 170
 171         { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8139,
 172           "RealTek 8139C+ 10/100BaseTX" },
 173
 174         { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8101E,
 175           "RealTek 810x PCIe 10/100baseTX" },
 176
 177         { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8168,
 178           "RealTek 8111/8168 PCIe Gigabit Ethernet" },
 179
 180         { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169,
 181           "RealTek 8110/8169 Gigabit Ethernet" },
 182
 183         { PCI_VENDOR_REALTEK, PCI_PRODUCT_REALTEK_RT8169SC,
 184           "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" },
 185
 186         { PCI_VENDOR_COREGA, PCI_PRODUCT_COREGA_CG_LAPCIGT,
 187           "Corega CG-LAPCIGT Gigabit Ethernet" },
 188
 189         { PCI_VENDOR_LINKSYS, PCI_PRODUCT_LINKSYS_EG1032,
 190           "Linksys EG1032 Gigabit Ethernet" },
 191
 192         { PCI_VENDOR_USR2, PCI_PRODUCT_USR2_997902,
 193           "US Robotics 997902 Gigabit Ethernet" },
 194
 195         { 0, 0, NULL }
 196 };
 197
 198 static const struct re_hwrev re_hwrevs[] = {
 199         { RE_HWREV_8139CPLUS,   RE_MACVER_UNKN,         ETHERMTU,
 200           RE_C_HWCSUM | RE_C_8139CP },
 201
 202         { RE_HWREV_8169,        RE_MACVER_UNKN,         ETHERMTU,
 203           RE_C_HWCSUM | RE_C_8169 },
 204
 205         { RE_HWREV_8110S,       RE_MACVER_03,           RE_MTU_6K,
 206           RE_C_HWCSUM | RE_C_8169 },
 207
 208         { RE_HWREV_8169S,       RE_MACVER_03,           RE_MTU_6K,
 209           RE_C_HWCSUM | RE_C_8169 },
 210
 211         { RE_HWREV_8169SB,      RE_MACVER_04,           RE_MTU_6K,
 212           RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_8169 },
 213
 214         { RE_HWREV_8169SC1,     RE_MACVER_05,           RE_MTU_6K,
 215           RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_8169 },
 216
 217         { RE_HWREV_8169SC2,     RE_MACVER_06,           RE_MTU_6K,
 218           RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_8169 },
 219
 220         { RE_HWREV_8168B1,      RE_MACVER_21,           RE_MTU_6K,
 221           RE_C_HWIM | RE_C_HWCSUM | RE_C_PHYPMGT },
 222
 223         { RE_HWREV_8168B2,      RE_MACVER_23,           RE_MTU_6K,
 224           RE_C_HWIM | RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_AUTOPAD },
 225
 226         { RE_HWREV_8168B3,      RE_MACVER_23,           RE_MTU_6K,
 227           RE_C_HWIM | RE_C_HWCSUM | RE_C_PHYPMGT | RE_C_AUTOPAD },
 228
 229         { RE_HWREV_8168C,       RE_MACVER_29,           RE_MTU_6K,
 230           RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT |
 231           RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX },
 232
 233         { RE_HWREV_8168CP,      RE_MACVER_2B,           RE_MTU_6K,
 234           RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT |
 235           RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX },
 236
 237         { RE_HWREV_8168D,       RE_MACVER_2A,           RE_MTU_9K,
 238           RE_C_HWIM | RE_C_HWCSUM | RE_C_MAC2 | RE_C_PHYPMGT |
 239           RE_C_AUTOPAD | RE_C_CONTIGRX | RE_C_STOP_RXTX },
 240
 241         { RE_HWREV_8100E,       RE_MACVER_UNKN,         ETHERMTU,
 242           RE_C_HWCSUM },
 243
 244         { RE_HWREV_8101E1,      RE_MACVER_16,           ETHERMTU,
 245           RE_C_HWCSUM },
 246
 247         { RE_HWREV_8101E2,      RE_MACVER_16,           ETHERMTU,
 248           RE_C_HWCSUM },
 249
 250         { RE_HWREV_8102E,       RE_MACVER_15,           ETHERMTU,
 251           RE_C_HWCSUM | RE_C_MAC2 | RE_C_AUTOPAD | RE_C_STOP_RXTX },
 252
 253         { RE_HWREV_8102EL,      RE_MACVER_15,           ETHERMTU,
 254           RE_C_HWCSUM | RE_C_MAC2 | RE_C_AUTOPAD | RE_C_STOP_RXTX },
 255
 256         { RE_HWREV_NULL, 0, 0, 0 }
 257 };
 258
 259 static int      re_probe(device_t);
 260 static int      re_attach(device_t);
 261 static int      re_detach(device_t);
 262 static int      re_suspend(device_t);
 263 static int      re_resume(device_t);
 264 static void     re_shutdown(device_t);
 265
 266 static void     re_dma_map_addr(void *, bus_dma_segment_t *, int, int);
 267 static void     re_dma_map_desc(void *, bus_dma_segment_t *, int,
 268                                 bus_size_t, int);
 269 static int      re_allocmem(device_t);
 270 static void     re_freemem(device_t);
 271 static void     re_freebufmem(struct re_softc *, int, int);
 272 static int      re_encap(struct re_softc *, struct mbuf **, int *);
 273 static int      re_newbuf_std(struct re_softc *, int, int);
 274 static int      re_newbuf_jumbo(struct re_softc *, int, int);
 275 static void     re_setup_rxdesc(struct re_softc *, int);
 276 static int      re_rx_list_init(struct re_softc *);
 277 static int      re_tx_list_init(struct re_softc *);
 278 static int      re_rxeof(struct re_softc *);
 279 static int      re_txeof(struct re_softc *);
 280 static int      re_tx_collect(struct re_softc *);
 281 static void     re_intr(void *);
 282 static void     re_tick(void *);
 283 static void     re_tick_serialized(void *);
 284
 285 static void     re_start(struct ifnet *);
 286 static int      re_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 287 static void     re_init(void *);
 288 static void     re_stop(struct re_softc *);
 289 static void     re_watchdog(struct ifnet *);
 290 static int      re_ifmedia_upd(struct ifnet *);
 291 static void     re_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 292
 293 static void     re_eeprom_putbyte(struct re_softc *, int);
 294 static void     re_eeprom_getword(struct re_softc *, int, u_int16_t *);
 295 static void     re_read_eeprom(struct re_softc *, caddr_t, int, int);
 296 static void     re_get_eewidth(struct re_softc *);
 297
 298 static int      re_gmii_readreg(device_t, int, int);
 299 static int      re_gmii_writereg(device_t, int, int, int);
 300
 301 static int      re_miibus_readreg(device_t, int, int);
 302 static int      re_miibus_writereg(device_t, int, int, int);
 303 static void     re_miibus_statchg(device_t);
 304
 305 static void     re_setmulti(struct re_softc *);
 306 static void     re_reset(struct re_softc *, int);
 307 static void     re_get_eaddr(struct re_softc *, uint8_t *);
 308
 309 static void     re_setup_hw_im(struct re_softc *);
 310 static void     re_setup_sim_im(struct re_softc *);
 311 static void     re_disable_hw_im(struct re_softc *);
 312 static void     re_disable_sim_im(struct re_softc *);
 313 static void     re_config_imtype(struct re_softc *, int);
 314 static void     re_setup_intr(struct re_softc *, int, int);
 315
 316 static int      re_sysctl_hwtime(SYSCTL_HANDLER_ARGS, int *);
 317 static int      re_sysctl_rxtime(SYSCTL_HANDLER_ARGS);
 318 static int      re_sysctl_txtime(SYSCTL_HANDLER_ARGS);
 319 static int      re_sysctl_simtime(SYSCTL_HANDLER_ARGS);
 320 static int      re_sysctl_imtype(SYSCTL_HANDLER_ARGS);
 321
 322 static int      re_jpool_alloc(struct re_softc *);
 323 static void     re_jpool_free(struct re_softc *);
 324 static struct re_jbuf *re_jbuf_alloc(struct re_softc *);
 325 static void     re_jbuf_free(void *);
 326 static void     re_jbuf_ref(void *);
 327
 328 #ifdef RE_DIAG
 329 static int      re_diag(struct re_softc *);
 330 #endif
 331
 332 #ifdef DEVICE_POLLING
 333 static void     re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count);
 334 #endif
 335
 336 static device_method_t re_methods[] = {
 337         /* Device interface */
 338         DEVMETHOD(device_probe,         re_probe),
 339         DEVMETHOD(device_attach,        re_attach),
 340         DEVMETHOD(device_detach,        re_detach),
 341         DEVMETHOD(device_suspend,       re_suspend),
 342         DEVMETHOD(device_resume,        re_resume),
 343         DEVMETHOD(device_shutdown,      re_shutdown),
 344
 345         /* bus interface */
 346         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 347         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 348
 349         /* MII interface */
 350         DEVMETHOD(miibus_readreg,       re_miibus_readreg),
 351         DEVMETHOD(miibus_writereg,      re_miibus_writereg),
 352         DEVMETHOD(miibus_statchg,       re_miibus_statchg),
 353
 354         { 0, 0 }
 355 };
 356
 357 static driver_t re_driver = {
 358         "re",
 359         re_methods,
 360         sizeof(struct re_softc)
 361 };
 362
 363 static devclass_t re_devclass;
 364
 365 DECLARE_DUMMY_MODULE(if_re);
 366 DRIVER_MODULE(if_re, pci, re_driver, re_devclass, 0, 0);
 367 DRIVER_MODULE(if_re, cardbus, re_driver, re_devclass, 0, 0);
 368 DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0);
 369
 370 static int      re_rx_desc_count = RE_RX_DESC_CNT_DEF;
 371 static int      re_tx_desc_count = RE_TX_DESC_CNT_DEF;
 372
 373 TUNABLE_INT("hw.re.rx_desc_count", &re_rx_desc_count);
 374 TUNABLE_INT("hw.re.tx_desc_count", &re_tx_desc_count);
 375
 376 #define EE_SET(x)       \
 377         CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) | (x))
 378
 379 #define EE_CLR(x)       \
 380         CSR_WRITE_1(sc, RE_EECMD, CSR_READ_1(sc, RE_EECMD) & ~(x))
 381
 382 static __inline void
 383 re_free_rxchain(struct re_softc *sc)
 384 {
 385         if (sc->re_head != NULL) {
 386                 m_freem(sc->re_head);
 387                 sc->re_head = sc->re_tail = NULL;
 388         }
 389 }
 390
 391 /*
 392  * Send a read command and address to the EEPROM, check for ACK.
 393  */
 394 static void
 395 re_eeprom_putbyte(struct re_softc *sc, int addr)
 396 {
 397         int d, i;
 398
 399         d = addr | (RE_9346_READ << sc->re_eewidth);
 400
 401         /*
 402          * Feed in each bit and strobe the clock.
 403          */
 404         for (i = 1 << (sc->re_eewidth + 3); i; i >>= 1) {
 405                 if (d & i)
 406                         EE_SET(RE_EE_DATAIN);
 407                 else
 408                         EE_CLR(RE_EE_DATAIN);
 409                 DELAY(100);
 410                 EE_SET(RE_EE_CLK);
 411                 DELAY(150);
 412                 EE_CLR(RE_EE_CLK);
 413                 DELAY(100);
 414         }
 415 }
 416
 417 /*
 418  * Read a word of data stored in the EEPROM at address 'addr.'
 419  */
 420 static void
 421 re_eeprom_getword(struct re_softc *sc, int addr, uint16_t *dest)
 422 {
 423         int i;
 424         uint16_t word = 0;
 425
 426         /*
 427          * Send address of word we want to read.
 428          */
 429         re_eeprom_putbyte(sc, addr);
 430
 431         /*
 432          * Start reading bits from EEPROM.
 433          */
 434         for (i = 0x8000; i != 0; i >>= 1) {
 435                 EE_SET(RE_EE_CLK);
 436                 DELAY(100);
 437                 if (CSR_READ_1(sc, RE_EECMD) & RE_EE_DATAOUT)
 438                         word |= i;
 439                 EE_CLR(RE_EE_CLK);
 440                 DELAY(100);
 441         }
 442
 443         *dest = word;
 444 }
 445
 446 /*
 447  * Read a sequence of words from the EEPROM.
 448  */
 449 static void
 450 re_read_eeprom(struct re_softc *sc, caddr_t dest, int off, int cnt)
 451 {
 452         int i;
 453         uint16_t word = 0, *ptr;
 454
 455         CSR_SETBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM);
 456         DELAY(100);
 457
 458         for (i = 0; i < cnt; i++) {
 459                 CSR_SETBIT_1(sc, RE_EECMD, RE_EE_SEL);
 460                 re_eeprom_getword(sc, off + i, &word);
 461                 CSR_CLRBIT_1(sc, RE_EECMD, RE_EE_SEL);
 462                 ptr = (uint16_t *)(dest + (i * 2));
 463                 *ptr = word;
 464         }
 465
 466         CSR_CLRBIT_1(sc, RE_EECMD, RE_EEMODE_PROGRAM);
 467 }
 468
 469 static void
 470 re_get_eewidth(struct re_softc *sc)
 471 {
 472         uint16_t re_did = 0;
 473
 474         sc->re_eewidth = 6;
 475         re_read_eeprom(sc, (caddr_t)&re_did, 0, 1);
 476         if (re_did != 0x8129)
 477                 sc->re_eewidth = 8;
 478 }
 479
 480 static int
 481 re_gmii_readreg(device_t dev, int phy, int reg)
 482 {
 483         struct re_softc *sc = device_get_softc(dev);
 484         u_int32_t rval;
 485         int i;
 486
 487         if (phy != 1)
 488                 return(0);
 489
 490         /* Let the rgephy driver read the GMEDIASTAT register */
 491
 492         if (reg == RE_GMEDIASTAT)
 493                 return(CSR_READ_1(sc, RE_GMEDIASTAT));
 494
 495         CSR_WRITE_4(sc, RE_PHYAR, reg << 16);
 496         DELAY(1000);
 497
 498         for (i = 0; i < RE_TIMEOUT; i++) {
 499                 rval = CSR_READ_4(sc, RE_PHYAR);
 500                 if (rval & RE_PHYAR_BUSY)
 501                         break;
 502                 DELAY(100);
 503         }
 504
 505         if (i == RE_TIMEOUT) {
 506                 device_printf(dev, "PHY read failed\n");
 507                 return(0);
 508         }
 509
 510         return(rval & RE_PHYAR_PHYDATA);
 511 }
 512
 513 static int
 514 re_gmii_writereg(device_t dev, int phy, int reg, int data)
 515 {
 516         struct re_softc *sc = device_get_softc(dev);
 517         uint32_t rval;
 518         int i;
 519
 520         CSR_WRITE_4(sc, RE_PHYAR,
 521                     (reg << 16) | (data & RE_PHYAR_PHYDATA) | RE_PHYAR_BUSY);
 522         DELAY(1000);
 523
 524         for (i = 0; i < RE_TIMEOUT; i++) {
 525                 rval = CSR_READ_4(sc, RE_PHYAR);
 526                 if ((rval & RE_PHYAR_BUSY) == 0)
 527                         break;
 528                 DELAY(100);
 529         }
 530
 531         if (i == RE_TIMEOUT)
 532                 device_printf(dev, "PHY write failed\n");
 533
 534         return(0);
 535 }
 536
 537 static int
 538 re_miibus_readreg(device_t dev, int phy, int reg)
 539 {
 540         struct re_softc *sc = device_get_softc(dev);
 541         uint16_t rval = 0;
 542         uint16_t re8139_reg = 0;
 543
 544         if (!RE_IS_8139CP(sc)) {
 545                 rval = re_gmii_readreg(dev, phy, reg);
 546                 return(rval);
 547         }
 548
 549         /* Pretend the internal PHY is only at address 0 */
 550         if (phy)
 551                 return(0);
 552
 553         switch(reg) {
 554         case MII_BMCR:
 555                 re8139_reg = RE_BMCR;
 556                 break;
 557         case MII_BMSR:
 558                 re8139_reg = RE_BMSR;
 559                 break;
 560         case MII_ANAR:
 561                 re8139_reg = RE_ANAR;
 562                 break;
 563         case MII_ANER:
 564                 re8139_reg = RE_ANER;
 565                 break;
 566         case MII_ANLPAR:
 567                 re8139_reg = RE_LPAR;
 568                 break;
 569         case MII_PHYIDR1:
 570         case MII_PHYIDR2:
 571                 return(0);
 572         /*
 573          * Allow the rlphy driver to read the media status
 574          * register. If we have a link partner which does not
 575          * support NWAY, this is the register which will tell
 576          * us the results of parallel detection.
 577          */
 578         case RE_MEDIASTAT:
 579                 return(CSR_READ_1(sc, RE_MEDIASTAT));
 580         default:
 581                 device_printf(dev, "bad phy register\n");
 582                 return(0);
 583         }
 584         rval = CSR_READ_2(sc, re8139_reg);
 585         if (re8139_reg == RE_BMCR) {
 586                 /* 8139C+ has different bit layout. */
 587                 rval &= ~(BMCR_LOOP | BMCR_ISO);
 588         }
 589         return(rval);
 590 }
 591
 592 static int
 593 re_miibus_writereg(device_t dev, int phy, int reg, int data)
 594 {
 595         struct re_softc *sc= device_get_softc(dev);
 596         u_int16_t re8139_reg = 0;
 597
 598         if (!RE_IS_8139CP(sc))
 599                 return(re_gmii_writereg(dev, phy, reg, data));
 600
 601         /* Pretend the internal PHY is only at address 0 */
 602         if (phy)
 603                 return(0);
 604
 605         switch(reg) {
 606         case MII_BMCR:
 607                 re8139_reg = RE_BMCR;
 608                 /* 8139C+ has different bit layout. */
 609                 data &= ~(BMCR_LOOP | BMCR_ISO);
 610                 break;
 611         case MII_BMSR:
 612                 re8139_reg = RE_BMSR;
 613                 break;
 614         case MII_ANAR:
 615                 re8139_reg = RE_ANAR;
 616                 break;
 617         case MII_ANER:
 618                 re8139_reg = RE_ANER;
 619                 break;
 620         case MII_ANLPAR:
 621                 re8139_reg = RE_LPAR;
 622                 break;
 623         case MII_PHYIDR1:
 624         case MII_PHYIDR2:
 625                 return(0);
 626         default:
 627                 device_printf(dev, "bad phy register\n");
 628                 return(0);
 629         }
 630         CSR_WRITE_2(sc, re8139_reg, data);
 631         return(0);
 632 }
 633
 634 static void
 635 re_miibus_statchg(device_t dev)
 636 {
 637 }
 638
 639 /*
 640  * Program the 64-bit multicast hash filter.
 641  */
 642 static void
 643 re_setmulti(struct re_softc *sc)
 644 {
 645         struct ifnet *ifp = &sc->arpcom.ac_if;
 646         int h = 0;
 647         uint32_t hashes[2] = { 0, 0 };
 648         struct ifmultiaddr *ifma;
 649         uint32_t rxfilt;
 650         int mcnt = 0;
 651
 652         rxfilt = CSR_READ_4(sc, RE_RXCFG);
 653
 654         /* Set the individual bit to receive frames for this host only. */
 655         rxfilt |= RE_RXCFG_RX_INDIV;
 656         /* Set capture broadcast bit to capture broadcast frames. */
 657         rxfilt |= RE_RXCFG_RX_BROAD;
 658
 659         rxfilt &= ~(RE_RXCFG_RX_ALLPHYS | RE_RXCFG_RX_MULTI);
 660         if ((ifp->if_flags & IFF_ALLMULTI) || (ifp->if_flags & IFF_PROMISC)) {
 661                 rxfilt |= RE_RXCFG_RX_MULTI;
 662
 663                 /* If we want promiscuous mode, set the allframes bit. */
 664                 if (ifp->if_flags & IFF_PROMISC)
 665                         rxfilt |= RE_RXCFG_RX_ALLPHYS;
 666
 667                 CSR_WRITE_4(sc, RE_RXCFG, rxfilt);
 668                 CSR_WRITE_4(sc, RE_MAR0, 0xFFFFFFFF);
 669                 CSR_WRITE_4(sc, RE_MAR4, 0xFFFFFFFF);
 670                 return;
 671         }
 672
 673         /* first, zot all the existing hash bits */
 674         CSR_WRITE_4(sc, RE_MAR0, 0);
 675         CSR_WRITE_4(sc, RE_MAR4, 0);
 676
 677         /* now program new ones */
 678         LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
 679                 if (ifma->ifma_addr->sa_family != AF_LINK)
 680                         continue;
 681                 h = ether_crc32_be(LLADDR((struct sockaddr_dl *)
 682                     ifma->ifma_addr), ETHER_ADDR_LEN) >> 26;
 683                 if (h < 32)
 684                         hashes[0] |= (1 << h);
 685                 else
 686                         hashes[1] |= (1 << (h - 32));
 687                 mcnt++;
 688         }
 689
 690         if (mcnt)
 691                 rxfilt |= RE_RXCFG_RX_MULTI;
 692         else
 693                 rxfilt &= ~RE_RXCFG_RX_MULTI;
 694
 695         CSR_WRITE_4(sc, RE_RXCFG, rxfilt);
 696
 697         /*
 698          * For some unfathomable reason, RealTek decided to reverse
 699          * the order of the multicast hash registers in the PCI Express
 700          * parts. This means we have to write the hash pattern in reverse
 701          * order for those devices.
 702          */
 703         if (sc->re_caps & RE_C_PCIE) {
 704                 CSR_WRITE_4(sc, RE_MAR0, bswap32(hashes[0]));
 705                 CSR_WRITE_4(sc, RE_MAR4, bswap32(hashes[1]));
 706         } else {
 707                 CSR_WRITE_4(sc, RE_MAR0, hashes[0]);
 708                 CSR_WRITE_4(sc, RE_MAR4, hashes[1]);
 709         }
 710 }
 711
 712 static void
 713 re_reset(struct re_softc *sc, int running)
 714 {
 715         int i;
 716
 717         if ((sc->re_caps & RE_C_STOP_RXTX) && running) {
 718                 CSR_WRITE_1(sc, RE_COMMAND,
 719                             RE_CMD_STOPREQ | RE_CMD_TX_ENB | RE_CMD_RX_ENB);
 720                 DELAY(100);
 721         }
 722
 723         CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_RESET);
 724
 725         for (i = 0; i < RE_TIMEOUT; i++) {
 726                 DELAY(10);
 727                 if ((CSR_READ_1(sc, RE_COMMAND) & RE_CMD_RESET) == 0)
 728                         break;
 729         }
 730         if (i == RE_TIMEOUT)
 731                 if_printf(&sc->arpcom.ac_if, "reset never completed!\n");
 732 }
 733
 734 #ifdef RE_DIAG
 735 /*
 736  * The following routine is designed to test for a defect on some
 737  * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64#
 738  * lines connected to the bus, however for a 32-bit only card, they
 739  * should be pulled high. The result of this defect is that the
 740  * NIC will not work right if you plug it into a 64-bit slot: DMA
 741  * operations will be done with 64-bit transfers, which will fail
 742  * because the 64-bit data lines aren't connected.
 743  *
 744  * There's no way to work around this (short of talking a soldering
 745  * iron to the board), however we can detect it. The method we use
 746  * here is to put the NIC into digital loopback mode, set the receiver
 747  * to promiscuous mode, and then try to send a frame. We then compare
 748  * the frame data we sent to what was received. If the data matches,
 749  * then the NIC is working correctly, otherwise we know the user has
 750  * a defective NIC which has been mistakenly plugged into a 64-bit PCI
 751  * slot. In the latter case, there's no way the NIC can work correctly,
 752  * so we print out a message on the console and abort the device attach.
 753  */
 754
 755 static int
 756 re_diag(struct re_softc *sc)
 757 {
 758         struct ifnet *ifp = &sc->arpcom.ac_if;
 759         struct mbuf *m0;
 760         struct ether_header *eh;
 761         struct re_desc *cur_rx;
 762         uint16_t status;
 763         uint32_t rxstat;
 764         int total_len, i, error = 0, phyaddr;
 765         uint8_t dst[ETHER_ADDR_LEN] = { 0x00, 'h', 'e', 'l', 'l', 'o' };
 766         uint8_t src[ETHER_ADDR_LEN] = { 0x00, 'w', 'o', 'r', 'l', 'd' };
 767
 768         /* Allocate a single mbuf */
 769
 770         MGETHDR(m0, MB_DONTWAIT, MT_DATA);
 771         if (m0 == NULL)
 772                 return(ENOBUFS);
 773
 774         /*
 775          * Initialize the NIC in test mode. This sets the chip up
 776          * so that it can send and receive frames, but performs the
 777          * following special functions:
 778          * - Puts receiver in promiscuous mode
 779          * - Enables digital loopback mode
 780          * - Leaves interrupts turned off
 781          */
 782
 783         ifp->if_flags |= IFF_PROMISC;
 784         sc->re_flags |= RE_F_TESTMODE;
 785         re_init(sc);
 786         sc->re_flags |= RE_F_LINKED;
 787         if (!RE_IS_8139CP(sc))
 788                 phyaddr = 1;
 789         else
 790                 phyaddr = 0;
 791
 792         re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_RESET);
 793         for (i = 0; i < RE_TIMEOUT; i++) {
 794                 status = re_miibus_readreg(sc->re_dev, phyaddr, MII_BMCR);
 795                 if (!(status & BMCR_RESET))
 796                         break;
 797         }
 798
 799         re_miibus_writereg(sc->re_dev, phyaddr, MII_BMCR, BMCR_LOOP);
 800         CSR_WRITE_2(sc, RE_ISR, RE_INTRS_DIAG);
 801
 802         DELAY(100000);
 803
 804         /* Put some data in the mbuf */
 805
 806         eh = mtod(m0, struct ether_header *);
 807         bcopy (dst, eh->ether_dhost, ETHER_ADDR_LEN);
 808         bcopy (src, eh->ether_shost, ETHER_ADDR_LEN);
 809         eh->ether_type = htons(ETHERTYPE_IP);
 810         m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN;
 811
 812         /*
 813          * Queue the packet, start transmission.
 814          * Note: ifq_handoff() ultimately calls re_start() for us.
 815          */
 816
 817         CSR_WRITE_2(sc, RE_ISR, 0xFFFF);
 818         error = ifq_handoff(ifp, m0, NULL);
 819         if (error) {
 820                 m0 = NULL;
 821                 goto done;
 822         }
 823         m0 = NULL;
 824
 825         /* Wait for it to propagate through the chip */
 826
 827         DELAY(100000);
 828         for (i = 0; i < RE_TIMEOUT; i++) {
 829                 status = CSR_READ_2(sc, RE_ISR);
 830                 CSR_WRITE_2(sc, RE_ISR, status);
 831                 if ((status & (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK)) ==
 832                     (RE_ISR_TIMEOUT_EXPIRED|RE_ISR_RX_OK))
 833                         break;
 834                 DELAY(10);
 835         }
 836
 837         if (i == RE_TIMEOUT) {
 838                 if_printf(ifp, "diagnostic failed to receive packet "
 839                           "in loopback mode\n");
 840                 error = EIO;
 841                 goto done;
 842         }
 843
 844         /*
 845          * The packet should have been dumped into the first
 846          * entry in the RX DMA ring. Grab it from there.
 847          */
 848
 849         bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
 850                         sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD);
 851         bus_dmamap_sync(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0],
 852                         BUS_DMASYNC_POSTWRITE);
 853         bus_dmamap_unload(sc->re_ldata.re_mtag, sc->re_ldata.re_rx_dmamap[0]);
 854
 855         m0 = sc->re_ldata.re_rx_mbuf[0];
 856         sc->re_ldata.re_rx_mbuf[0] = NULL;
 857         eh = mtod(m0, struct ether_header *);
 858
 859         cur_rx = &sc->re_ldata.re_rx_list[0];
 860         total_len = RE_RXBYTES(cur_rx);
 861         rxstat = le32toh(cur_rx->re_cmdstat);
 862
 863         if (total_len != ETHER_MIN_LEN) {
 864                 if_printf(ifp, "diagnostic failed, received short packet\n");
 865                 error = EIO;
 866                 goto done;
 867         }
 868
 869         /* Test that the received packet data matches what we sent. */
 870
 871         if (bcmp(eh->ether_dhost, dst, ETHER_ADDR_LEN) ||
 872             bcmp(eh->ether_shost, &src, ETHER_ADDR_LEN) ||
 873             be16toh(eh->ether_type) != ETHERTYPE_IP) {
 874                 if_printf(ifp, "WARNING, DMA FAILURE!\n");
 875                 if_printf(ifp, "expected TX data: %6D/%6D/0x%x\n",
 876                     dst, ":", src, ":", ETHERTYPE_IP);
 877                 if_printf(ifp, "received RX data: %6D/%6D/0x%x\n",
 878                     eh->ether_dhost, ":",  eh->ether_shost, ":",
 879                     ntohs(eh->ether_type));
 880                 if_printf(ifp, "You may have a defective 32-bit NIC plugged "
 881                     "into a 64-bit PCI slot.\n");
 882                 if_printf(ifp, "Please re-install the NIC in a 32-bit slot "
 883                     "for proper operation.\n");
 884                 if_printf(ifp, "Read the re(4) man page for more details.\n");
 885                 error = EIO;
 886         }
 887
 888 done:
 889         /* Turn interface off, release resources */
 890
 891         sc->re_flags &= ~(RE_F_LINKED | RE_F_TESTMODE);
 892         ifp->if_flags &= ~IFF_PROMISC;
 893         re_stop(sc);
 894         if (m0 != NULL)
 895                 m_freem(m0);
 896
 897         return (error);
 898 }
 899 #endif  /* RE_DIAG */
 900
 901 /*
 902  * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device
 903  * IDs against our list and return a device name if we find a match.
 904  */
 905 static int
 906 re_probe(device_t dev)
 907 {
 908         const struct re_type *t;
 909         const struct re_hwrev *hw_rev;
 910         struct re_softc *sc;
 911         int rid;
 912         uint32_t hwrev, macmode, txcfg;
 913         uint16_t vendor, product;
 914
 915         vendor = pci_get_vendor(dev);
 916         product = pci_get_device(dev);
 917
 918         /*
 919          * Only attach to rev.3 of the Linksys EG1032 adapter.
 920          * Rev.2 is supported by sk(4).
 921          */
 922         if (vendor == PCI_VENDOR_LINKSYS &&
 923             product == PCI_PRODUCT_LINKSYS_EG1032 &&
 924             pci_get_subdevice(dev) != PCI_SUBDEVICE_LINKSYS_EG1032_REV3)
 925                 return ENXIO;
 926
 927         for (t = re_devs; t->re_name != NULL; t++) {
 928                 if (product == t->re_did && vendor == t->re_vid)
 929                         break;
 930         }
 931
 932         /*
 933          * Check if we found a RealTek device.
 934          */
 935         if (t->re_name == NULL)
 936                 return ENXIO;
 937
 938         /*
 939          * Temporarily map the I/O space so we can read the chip ID register.
 940          */
 941         sc = kmalloc(sizeof(*sc), M_TEMP, M_WAITOK | M_ZERO);
 942         rid = RE_PCI_LOIO;
 943         sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
 944                                             RF_ACTIVE);
 945         if (sc->re_res == NULL) {
 946                 device_printf(dev, "couldn't map ports/memory\n");
 947                 kfree(sc, M_TEMP);
 948                 return ENXIO;
 949         }
 950
 951         sc->re_btag = rman_get_bustag(sc->re_res);
 952         sc->re_bhandle = rman_get_bushandle(sc->re_res);
 953
 954         txcfg = CSR_READ_4(sc, RE_TXCFG);
 955         hwrev = txcfg & RE_TXCFG_HWREV;
 956         macmode = txcfg & RE_TXCFG_MACMODE;
 957         bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO, sc->re_res);
 958         kfree(sc, M_TEMP);
 959
 960         /*
 961          * and continue matching for the specific chip...
 962          */
 963         for (hw_rev = re_hwrevs; hw_rev->re_hwrev != RE_HWREV_NULL; hw_rev++) {
 964                 if (hw_rev->re_hwrev == hwrev) {
 965                         sc = device_get_softc(dev);
 966
 967                         sc->re_hwrev = hw_rev->re_hwrev;
 968                         sc->re_macver = hw_rev->re_macver;
 969                         sc->re_caps = hw_rev->re_caps;
 970                         sc->re_maxmtu = hw_rev->re_maxmtu;
 971
 972                         /*
 973                          * Apply chip property fixup
 974                          */
 975                         switch (sc->re_hwrev) {
 976                         case RE_HWREV_8101E1:
 977                         case RE_HWREV_8101E2:
 978                                 if (macmode == 0)
 979                                         sc->re_macver = RE_MACVER_11;
 980                                 else if (macmode == 0x200000)
 981                                         sc->re_macver = RE_MACVER_12;
 982                                 break;
 983                         case RE_HWREV_8102E:
 984                         case RE_HWREV_8102EL:
 985                                 if (macmode == 0)
 986                                         sc->re_macver = RE_MACVER_13;
 987                                 else if (macmode == 0x100000)
 988                                         sc->re_macver = RE_MACVER_14;
 989                                 break;
 990                         case RE_HWREV_8168B2:
 991                         case RE_HWREV_8168B3:
 992                                 if (macmode == 0)
 993                                         sc->re_macver = RE_MACVER_22;
 994                                 break;
 995                         case RE_HWREV_8168C:
 996                                 if (macmode == 0)
 997                                         sc->re_macver = RE_MACVER_24;
 998                                 else if (macmode == 0x200000)
 999                                         sc->re_macver = RE_MACVER_25;
1000                                 else if (macmode == 0x300000)
1001                                         sc->re_macver = RE_MACVER_27;
1002                                 break;
1003                         case RE_HWREV_8168CP:
1004                                 if (macmode == 0)
1005                                         sc->re_macver = RE_MACVER_26;
1006                                 else if (macmode == 0x100000)
1007                                         sc->re_macver = RE_MACVER_28;
1008                                 break;
1009                         }
1010                         if (pci_get_pciecap_ptr(dev) != 0)
1011                                 sc->re_caps |= RE_C_PCIE;
1012
1013                         device_set_desc(dev, t->re_name);
1014                         return 0;
1015                 }
1016         }
1017
1018         if (bootverbose) {
1019                 device_printf(dev, "unknown hwrev 0x%08x, macmode 0x%08x\n",
1020                               hwrev, macmode);
1021         }
1022         return ENXIO;
1023 }
1024
1025 static void
1026 re_dma_map_desc(void *xarg, bus_dma_segment_t *segs, int nsegs,
1027                 bus_size_t mapsize, int error)
1028 {
1029         struct re_dmaload_arg *arg = xarg;
1030         int i;
1031
1032         if (error)
1033                 return;
1034
1035         if (nsegs > arg->re_nsegs) {
1036                 arg->re_nsegs = 0;
1037                 return;
1038         }
1039
1040         arg->re_nsegs = nsegs;
1041         for (i = 0; i < nsegs; ++i)
1042                 arg->re_segs[i] = segs[i];
1043 }
1044
1045 /*
1046  * Map a single buffer address.
1047  */
1048
1049 static void
1050 re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1051 {
1052         uint32_t *addr;
1053
1054         if (error)
1055                 return;
1056
1057         KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg));
1058         addr = arg;
1059         *addr = segs->ds_addr;
1060 }
1061
1062 static int
1063 re_allocmem(device_t dev)
1064 {
1065         struct re_softc *sc = device_get_softc(dev);
1066         int error, i;
1067
1068         /*
1069          * Allocate list data
1070          */
1071         sc->re_ldata.re_tx_mbuf =
1072         kmalloc(sc->re_tx_desc_cnt * sizeof(struct mbuf *),
1073                 M_DEVBUF, M_ZERO | M_WAITOK);
1074
1075         sc->re_ldata.re_rx_mbuf =
1076         kmalloc(sc->re_rx_desc_cnt * sizeof(struct mbuf *),
1077                 M_DEVBUF, M_ZERO | M_WAITOK);
1078
1079         sc->re_ldata.re_rx_paddr =
1080         kmalloc(sc->re_rx_desc_cnt * sizeof(bus_addr_t),
1081                 M_DEVBUF, M_ZERO | M_WAITOK);
1082
1083         sc->re_ldata.re_tx_dmamap =
1084         kmalloc(sc->re_tx_desc_cnt * sizeof(bus_dmamap_t),
1085                 M_DEVBUF, M_ZERO | M_WAITOK);
1086
1087         sc->re_ldata.re_rx_dmamap =
1088         kmalloc(sc->re_rx_desc_cnt * sizeof(bus_dmamap_t),
1089                 M_DEVBUF, M_ZERO | M_WAITOK);
1090
1091         /*
1092          * Allocate the parent bus DMA tag appropriate for PCI.
1093          */
1094         error = bus_dma_tag_create(NULL,        /* parent */
1095                         1, 0,                   /* alignment, boundary */
1096                         BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
1097                         BUS_SPACE_MAXADDR,      /* highaddr */
1098                         NULL, NULL,             /* filter, filterarg */
1099                         MAXBSIZE, RE_MAXSEGS,   /* maxsize, nsegments */
1100                         BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
1101                         BUS_DMA_ALLOCNOW,       /* flags */
1102                         &sc->re_parent_tag);
1103         if (error) {
1104                 device_printf(dev, "could not allocate parent dma tag\n");
1105                 return error;
1106         }
1107
1108         /* Allocate tag for TX descriptor list. */
1109         error = bus_dma_tag_create(sc->re_parent_tag,
1110                         RE_RING_ALIGN, 0,
1111                         BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1112                         NULL, NULL,
1113                         RE_TX_LIST_SZ(sc), 1, RE_TX_LIST_SZ(sc),
1114                         BUS_DMA_ALLOCNOW,
1115                         &sc->re_ldata.re_tx_list_tag);
1116         if (error) {
1117                 device_printf(dev, "could not allocate TX ring dma tag\n");
1118                 return(error);
1119         }
1120
1121         /* Allocate DMA'able memory for the TX ring */
1122         error = bus_dmamem_alloc(sc->re_ldata.re_tx_list_tag,
1123                         (void **)&sc->re_ldata.re_tx_list,
1124                         BUS_DMA_WAITOK | BUS_DMA_ZERO,
1125                         &sc->re_ldata.re_tx_list_map);
1126         if (error) {
1127                 device_printf(dev, "could not allocate TX ring\n");
1128                 bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag);
1129                 sc->re_ldata.re_tx_list_tag = NULL;
1130                 return(error);
1131         }
1132
1133         /* Load the map for the TX ring. */
1134         error = bus_dmamap_load(sc->re_ldata.re_tx_list_tag,
1135                         sc->re_ldata.re_tx_list_map,
1136                         sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc),
1137                         re_dma_map_addr, &sc->re_ldata.re_tx_list_addr,
1138                         BUS_DMA_NOWAIT);
1139         if (error) {
1140                 device_printf(dev, "could not get address of TX ring\n");
1141                 bus_dmamem_free(sc->re_ldata.re_tx_list_tag,
1142                                 sc->re_ldata.re_tx_list,
1143                                 sc->re_ldata.re_tx_list_map);
1144                 bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag);
1145                 sc->re_ldata.re_tx_list_tag = NULL;
1146                 return(error);
1147         }
1148
1149         /* Allocate tag for RX descriptor list. */
1150         error = bus_dma_tag_create(sc->re_parent_tag,
1151                         RE_RING_ALIGN, 0,
1152                         BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1153                         NULL, NULL,
1154                         RE_RX_LIST_SZ(sc), 1, RE_RX_LIST_SZ(sc),
1155                         BUS_DMA_ALLOCNOW,
1156                         &sc->re_ldata.re_rx_list_tag);
1157         if (error) {
1158                 device_printf(dev, "could not allocate RX ring dma tag\n");
1159                 return(error);
1160         }
1161
1162         /* Allocate DMA'able memory for the RX ring */
1163         error = bus_dmamem_alloc(sc->re_ldata.re_rx_list_tag,
1164                         (void **)&sc->re_ldata.re_rx_list,
1165                         BUS_DMA_WAITOK | BUS_DMA_ZERO,
1166                         &sc->re_ldata.re_rx_list_map);
1167         if (error) {
1168                 device_printf(dev, "could not allocate RX ring\n");
1169                 bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag);
1170                 sc->re_ldata.re_rx_list_tag = NULL;
1171                 return(error);
1172         }
1173
1174         /* Load the map for the RX ring. */
1175         error = bus_dmamap_load(sc->re_ldata.re_rx_list_tag,
1176                         sc->re_ldata.re_rx_list_map,
1177                         sc->re_ldata.re_rx_list, RE_RX_LIST_SZ(sc),
1178                         re_dma_map_addr, &sc->re_ldata.re_rx_list_addr,
1179                         BUS_DMA_NOWAIT);
1180         if (error) {
1181                 device_printf(dev, "could not get address of RX ring\n");
1182                 bus_dmamem_free(sc->re_ldata.re_rx_list_tag,
1183                                 sc->re_ldata.re_rx_list,
1184                                 sc->re_ldata.re_rx_list_map);
1185                 bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag);
1186                 sc->re_ldata.re_rx_list_tag = NULL;
1187                 return(error);
1188         }
1189
1190         /* Allocate map for RX/TX mbufs. */
1191         error = bus_dma_tag_create(sc->re_parent_tag,
1192                         ETHER_ALIGN, 0,
1193                         BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR,
1194                         NULL, NULL,
1195                         RE_FRAMELEN_MAX, RE_MAXSEGS, MCLBYTES,
1196                         BUS_DMA_ALLOCNOW,
1197                         &sc->re_ldata.re_mtag);
1198         if (error) {
1199                 device_printf(dev, "could not allocate buf dma tag\n");
1200                 return(error);
1201         }
1202
1203         /* Create spare DMA map for RX */
1204         error = bus_dmamap_create(sc->re_ldata.re_mtag, 0,
1205                         &sc->re_ldata.re_rx_spare);
1206         if (error) {
1207                 device_printf(dev, "can't create spare DMA map for RX\n");
1208                 bus_dma_tag_destroy(sc->re_ldata.re_mtag);
1209                 sc->re_ldata.re_mtag = NULL;
1210                 return error;
1211         }
1212
1213         /* Create DMA maps for TX buffers */
1214         for (i = 0; i < sc->re_tx_desc_cnt; i++) {
1215                 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0,
1216                                 &sc->re_ldata.re_tx_dmamap[i]);
1217                 if (error) {
1218                         device_printf(dev, "can't create DMA map for TX buf\n");
1219                         re_freebufmem(sc, i, 0);
1220                         return(error);
1221                 }
1222         }
1223
1224         /* Create DMA maps for RX buffers */
1225         for (i = 0; i < sc->re_rx_desc_cnt; i++) {
1226                 error = bus_dmamap_create(sc->re_ldata.re_mtag, 0,
1227                                 &sc->re_ldata.re_rx_dmamap[i]);
1228                 if (error) {
1229                         device_printf(dev, "can't create DMA map for RX buf\n");
1230                         re_freebufmem(sc, sc->re_tx_desc_cnt, i);
1231                         return(error);
1232                 }
1233         }
1234
1235         /* Create jumbo buffer pool for RX if required */
1236         if (sc->re_caps & RE_C_CONTIGRX) {
1237                 error = re_jpool_alloc(sc);
1238                 if (error) {
1239                         re_jpool_free(sc);
1240                         /* Disable jumbo frame support */
1241                         sc->re_maxmtu = ETHERMTU;
1242                 }
1243         }
1244         return(0);
1245 }
1246
1247 static void
1248 re_freebufmem(struct re_softc *sc, int tx_cnt, int rx_cnt)
1249 {
1250         int i;
1251
1252         /* Destroy all the RX and TX buffer maps */
1253         if (sc->re_ldata.re_mtag) {
1254                 for (i = 0; i < tx_cnt; i++) {
1255                         bus_dmamap_destroy(sc->re_ldata.re_mtag,
1256                                            sc->re_ldata.re_tx_dmamap[i]);
1257                 }
1258                 for (i = 0; i < rx_cnt; i++) {
1259                         bus_dmamap_destroy(sc->re_ldata.re_mtag,
1260                                            sc->re_ldata.re_rx_dmamap[i]);
1261                 }
1262                 bus_dmamap_destroy(sc->re_ldata.re_mtag,
1263                                    sc->re_ldata.re_rx_spare);
1264                 bus_dma_tag_destroy(sc->re_ldata.re_mtag);
1265                 sc->re_ldata.re_mtag = NULL;
1266         }
1267 }
1268
1269 static void
1270 re_freemem(device_t dev)
1271 {
1272         struct re_softc *sc = device_get_softc(dev);
1273
1274         /* Unload and free the RX DMA ring memory and map */
1275         if (sc->re_ldata.re_rx_list_tag) {
1276                 bus_dmamap_unload(sc->re_ldata.re_rx_list_tag,
1277                                   sc->re_ldata.re_rx_list_map);
1278                 bus_dmamem_free(sc->re_ldata.re_rx_list_tag,
1279                                 sc->re_ldata.re_rx_list,
1280                                 sc->re_ldata.re_rx_list_map);
1281                 bus_dma_tag_destroy(sc->re_ldata.re_rx_list_tag);
1282         }
1283
1284         /* Unload and free the TX DMA ring memory and map */
1285         if (sc->re_ldata.re_tx_list_tag) {
1286                 bus_dmamap_unload(sc->re_ldata.re_tx_list_tag,
1287                                   sc->re_ldata.re_tx_list_map);
1288                 bus_dmamem_free(sc->re_ldata.re_tx_list_tag,
1289                                 sc->re_ldata.re_tx_list,
1290                                 sc->re_ldata.re_tx_list_map);
1291                 bus_dma_tag_destroy(sc->re_ldata.re_tx_list_tag);
1292         }
1293
1294         /* Free RX/TX buf DMA stuffs */
1295         re_freebufmem(sc, sc->re_tx_desc_cnt, sc->re_rx_desc_cnt);
1296
1297         /* Unload and free the stats buffer and map */
1298         if (sc->re_ldata.re_stag) {
1299                 bus_dmamap_unload(sc->re_ldata.re_stag,
1300                                   sc->re_ldata.re_rx_list_map);
1301                 bus_dmamem_free(sc->re_ldata.re_stag,
1302                                 sc->re_ldata.re_stats,
1303                                 sc->re_ldata.re_smap);
1304                 bus_dma_tag_destroy(sc->re_ldata.re_stag);
1305         }
1306
1307         if (sc->re_caps & RE_C_CONTIGRX)
1308                 re_jpool_free(sc);
1309
1310         if (sc->re_parent_tag)
1311                 bus_dma_tag_destroy(sc->re_parent_tag);
1312
1313         if (sc->re_ldata.re_tx_mbuf != NULL)
1314                 kfree(sc->re_ldata.re_tx_mbuf, M_DEVBUF);
1315         if (sc->re_ldata.re_rx_mbuf != NULL)
1316                 kfree(sc->re_ldata.re_rx_mbuf, M_DEVBUF);
1317         if (sc->re_ldata.re_rx_paddr != NULL)
1318                 kfree(sc->re_ldata.re_rx_paddr, M_DEVBUF);
1319         if (sc->re_ldata.re_tx_dmamap != NULL)
1320                 kfree(sc->re_ldata.re_tx_dmamap, M_DEVBUF);
1321         if (sc->re_ldata.re_rx_dmamap != NULL)
1322                 kfree(sc->re_ldata.re_rx_dmamap, M_DEVBUF);
1323 }
1324
1325 /*
1326  * Attach the interface. Allocate softc structures, do ifmedia
1327  * setup and ethernet/BPF attach.
1328  */
1329 static int
1330 re_attach(device_t dev)
1331 {
1332         struct re_softc *sc = device_get_softc(dev);
1333         struct ifnet *ifp;
1334         uint8_t eaddr[ETHER_ADDR_LEN];
1335         int error = 0, rid, qlen;
1336
1337         callout_init(&sc->re_timer);
1338         sc->re_dev = dev;
1339
1340         if (RE_IS_8139CP(sc)) {
1341                 sc->re_rx_desc_cnt = RE_RX_DESC_CNT_8139CP;
1342                 sc->re_tx_desc_cnt = RE_TX_DESC_CNT_8139CP;
1343         } else {
1344                 sc->re_rx_desc_cnt = re_rx_desc_count;
1345                 if (sc->re_rx_desc_cnt > RE_RX_DESC_CNT_MAX)
1346                         sc->re_rx_desc_cnt = RE_RX_DESC_CNT_MAX;
1347
1348                 sc->re_tx_desc_cnt = re_tx_desc_count;
1349                 if (sc->re_tx_desc_cnt > RE_TX_DESC_CNT_MAX)
1350                         sc->re_tx_desc_cnt = RE_TX_DESC_CNT_MAX;
1351         }
1352
1353         qlen = RE_IFQ_MAXLEN;
1354         if (sc->re_tx_desc_cnt > qlen)
1355                 qlen = sc->re_tx_desc_cnt;
1356
1357         sc->re_rxbuf_size = MCLBYTES;
1358         sc->re_newbuf = re_newbuf_std;
1359
1360         sc->re_tx_time = 5;             /* 125us */
1361         sc->re_rx_time = 2;             /* 50us */
1362         if (sc->re_caps & RE_C_PCIE)
1363                 sc->re_sim_time = 75;   /* 75us */
1364         else
1365                 sc->re_sim_time = 125;  /* 125us */
1366         sc->re_imtype = RE_IMTYPE_SIM;  /* simulated interrupt moderation */
1367         re_config_imtype(sc, sc->re_imtype);
1368
1369         sysctl_ctx_init(&sc->re_sysctl_ctx);
1370         sc->re_sysctl_tree = SYSCTL_ADD_NODE(&sc->re_sysctl_ctx,
1371                                              SYSCTL_STATIC_CHILDREN(_hw),
1372                                              OID_AUTO,
1373                                              device_get_nameunit(dev),
1374                                              CTLFLAG_RD, 0, "");
1375         if (sc->re_sysctl_tree == NULL) {
1376                 device_printf(dev, "can't add sysctl node\n");
1377                 error = ENXIO;
1378                 goto fail;
1379         }
1380         SYSCTL_ADD_INT(&sc->re_sysctl_ctx,
1381                        SYSCTL_CHILDREN(sc->re_sysctl_tree), OID_AUTO,
1382                        "rx_desc_count", CTLFLAG_RD, &sc->re_rx_desc_cnt,
1383                        0, "RX desc count");
1384         SYSCTL_ADD_INT(&sc->re_sysctl_ctx,
1385                        SYSCTL_CHILDREN(sc->re_sysctl_tree), OID_AUTO,
1386                        "tx_desc_count", CTLFLAG_RD, &sc->re_tx_desc_cnt,
1387                        0, "TX desc count");
1388         SYSCTL_ADD_PROC(&sc->re_sysctl_ctx,
1389                         SYSCTL_CHILDREN(sc->re_sysctl_tree),
1390                         OID_AUTO, "sim_time",
1391                         CTLTYPE_INT | CTLFLAG_RW,
1392                         sc, 0, re_sysctl_simtime, "I",
1393                         "Simulated interrupt moderation time (usec).");
1394         SYSCTL_ADD_PROC(&sc->re_sysctl_ctx,
1395                         SYSCTL_CHILDREN(sc->re_sysctl_tree),
1396                         OID_AUTO, "imtype",
1397                         CTLTYPE_INT | CTLFLAG_RW,
1398                         sc, 0, re_sysctl_imtype, "I",
1399                         "Interrupt moderation type -- "
1400                         "0:disable, 1:simulated, "
1401                         "2:hardware(if supported)");
1402         if (sc->re_caps & RE_C_HWIM) {
1403                 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx,
1404                                 SYSCTL_CHILDREN(sc->re_sysctl_tree),
1405                                 OID_AUTO, "hw_rxtime",
1406                                 CTLTYPE_INT | CTLFLAG_RW,
1407                                 sc, 0, re_sysctl_rxtime, "I",
1408                                 "Hardware interrupt moderation time "
1409                                 "(unit: 25usec).");
1410                 SYSCTL_ADD_PROC(&sc->re_sysctl_ctx,
1411                                 SYSCTL_CHILDREN(sc->re_sysctl_tree),
1412                                 OID_AUTO, "hw_txtime",
1413                                 CTLTYPE_INT | CTLFLAG_RW,
1414                                 sc, 0, re_sysctl_txtime, "I",
1415                                 "Hardware interrupt moderation time "
1416                                 "(unit: 25usec).");
1417         }
1418
1419 #ifndef BURN_BRIDGES
1420         /*
1421          * Handle power management nonsense.
1422          */
1423
1424         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
1425                 uint32_t membase, irq;
1426
1427                 /* Save important PCI config data. */
1428                 membase = pci_read_config(dev, RE_PCI_LOMEM, 4);
1429                 irq = pci_read_config(dev, PCIR_INTLINE, 4);
1430
1431                 /* Reset the power state. */
1432                 device_printf(dev, "chip is in D%d power mode "
1433                     "-- setting to D0\n", pci_get_powerstate(dev));
1434
1435                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
1436
1437                 /* Restore PCI config data. */
1438                 pci_write_config(dev, RE_PCI_LOMEM, membase, 4);
1439                 pci_write_config(dev, PCIR_INTLINE, irq, 4);
1440         }
1441 #endif
1442         /*
1443          * Map control/status registers.
1444          */
1445         pci_enable_busmaster(dev);
1446
1447         rid = RE_PCI_LOIO;
1448         sc->re_res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid,
1449                                             RF_ACTIVE);
1450
1451         if (sc->re_res == NULL) {
1452                 device_printf(dev, "couldn't map ports\n");
1453                 error = ENXIO;
1454                 goto fail;
1455         }
1456
1457         sc->re_btag = rman_get_bustag(sc->re_res);
1458         sc->re_bhandle = rman_get_bushandle(sc->re_res);
1459
1460         /* Allocate interrupt */
1461         rid = 0;
1462         sc->re_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1463                                             RF_SHAREABLE | RF_ACTIVE);
1464
1465         if (sc->re_irq == NULL) {
1466                 device_printf(dev, "couldn't map interrupt\n");
1467                 error = ENXIO;
1468                 goto fail;
1469         }
1470
1471         /* Reset the adapter. */
1472         re_reset(sc, 0);
1473
1474         if (RE_IS_8139CP(sc)) {
1475                 sc->re_bus_speed = 33; /* XXX */
1476         } else if (sc->re_caps & RE_C_PCIE) {
1477                 sc->re_bus_speed = 125;
1478         } else {
1479                 uint8_t cfg2;
1480
1481                 cfg2 = CSR_READ_1(sc, RE_CFG2);
1482                 switch (cfg2 & RE_CFG2_PCICLK_MASK) {
1483                 case RE_CFG2_PCICLK_33MHZ:
1484                         sc->re_bus_speed = 33;
1485                         break;
1486                 case RE_CFG2_PCICLK_66MHZ:
1487                         sc->re_bus_speed = 66;
1488                         break;
1489                 default:
1490                         device_printf(dev, "unknown bus speed, assume 33MHz\n");
1491                         sc->re_bus_speed = 33;
1492                         break;
1493                 }
1494                 if (cfg2 & RE_CFG2_PCI64)
1495                         sc->re_caps |= RE_C_PCI64;
1496         }
1497         device_printf(dev, "Hardware rev. 0x%08x; MAC ver. 0x%02x; "
1498                       "PCI%s %dMHz\n",
1499                       sc->re_hwrev, sc->re_macver,
1500                       (sc->re_caps & RE_C_PCIE) ?
1501                       "-E" : ((sc->re_caps & RE_C_PCI64) ? "64" : "32"),
1502                       sc->re_bus_speed);
1503
1504         /*
1505          * NOTE:
1506          * DO NOT try to adjust config1 and config5 which was spotted in
1507          * Realtek's Linux drivers.  It will _permanently_ damage certain
1508          * cards EEPROM, e.g. one of my 8168B (0x38000000) card ...
1509          */
1510
1511         re_get_eaddr(sc, eaddr);
1512
1513         if (!RE_IS_8139CP(sc)) {
1514                 /* Set RX length mask */
1515                 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN;
1516                 sc->re_txstart = RE_GTXSTART;
1517         } else {
1518                 /* Set RX length mask */
1519                 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN;
1520                 sc->re_txstart = RE_TXSTART;
1521         }
1522
1523         /* Allocate DMA stuffs */
1524         error = re_allocmem(dev);
1525         if (error)
1526                 goto fail;
1527
1528         /*
1529          * Apply some magic PCI settings from Realtek ...
1530          */
1531         if (RE_IS_8169(sc)) {
1532                 CSR_WRITE_1(sc, 0x82, 1);
1533                 pci_write_config(dev, PCIR_CACHELNSZ, 0x8, 1);
1534         }
1535         pci_write_config(dev, PCIR_LATTIMER, 0x40, 1);
1536
1537         if (sc->re_caps & RE_C_MAC2) {
1538                 /*
1539                  * Following part is extracted from Realtek BSD driver v176.
1540                  * However, this does _not_ make much/any sense:
1541                  * 8168C's PCI Express device control is located at 0x78,
1542                  * so the reading from 0x79 (higher part of 0x78) and setting
1543                  * the 4~6bits intend to enlarge the "max read request size"
1544                  * (we will do it).  The content of the rest part of this
1545                  * register is not meaningful to other PCI registers, so
1546                  * writing the value to 0x54 could be completely wrong.
1547                  * 0x80 is the lower part of PCI Express device status, non-
1548                  * reserved bits are RW1C, writing 0 to them will not have
1549                  * any effect at all.
1550                  */
1551 #ifdef foo
1552                 uint8_t val;
1553
1554                 val = pci_read_config(dev, 0x79, 1);
1555                 val = (val & ~0x70) | 0x50;
1556                 pci_write_config(dev, 0x54, val, 1);
1557                 pci_write_config(dev, 0x80, 0, 1);
1558 #endif
1559         }
1560
1561         /*
1562          * Apply some PHY fixup from Realtek ...
1563          */
1564         if (sc->re_hwrev == RE_HWREV_8110S) {
1565                 CSR_WRITE_1(sc, 0x82, 1);
1566                 re_miibus_writereg(dev, 1, 0xb, 0);
1567         }
1568         if (sc->re_caps & RE_C_PHYPMGT) {
1569                 /* Power up PHY */
1570                 re_miibus_writereg(dev, 1, 0x1f, 0);
1571                 re_miibus_writereg(dev, 1, 0xe, 0);
1572         }
1573
1574         /* Do MII setup */
1575         if (mii_phy_probe(dev, &sc->re_miibus,
1576             re_ifmedia_upd, re_ifmedia_sts)) {
1577                 device_printf(dev, "MII without any phy!\n");
1578                 error = ENXIO;
1579                 goto fail;
1580         }
1581
1582         ifp = &sc->arpcom.ac_if;
1583         ifp->if_softc = sc;
1584         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1585         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1586         ifp->if_ioctl = re_ioctl;
1587         ifp->if_start = re_start;
1588 #ifdef DEVICE_POLLING
1589         ifp->if_poll = re_poll;
1590 #endif
1591         ifp->if_watchdog = re_watchdog;
1592         ifp->if_init = re_init;
1593         if (!RE_IS_8139CP(sc)) /* XXX */
1594                 ifp->if_baudrate = 1000000000;
1595         else
1596                 ifp->if_baudrate = 100000000;
1597         ifq_set_maxlen(&ifp->if_snd, qlen);
1598         ifq_set_ready(&ifp->if_snd);
1599
1600         ifp->if_capabilities = IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING;
1601         if (sc->re_caps & RE_C_HWCSUM)
1602                 ifp->if_capabilities |= IFCAP_HWCSUM;
1603
1604         ifp->if_capenable = ifp->if_capabilities;
1605         if (ifp->if_capabilities & IFCAP_HWCSUM)
1606                 ifp->if_hwassist = RE_CSUM_FEATURES;
1607         else
1608                 ifp->if_hwassist = 0;
1609
1610         /*
1611          * Call MI attach routine.
1612          */
1613         ether_ifattach(ifp, eaddr, NULL);
1614
1615 #ifdef RE_DIAG
1616         /*
1617          * Perform hardware diagnostic on the original RTL8169.
1618          * Some 32-bit cards were incorrectly wired and would
1619          * malfunction if plugged into a 64-bit slot.
1620          */
1621         if (sc->re_hwrev == RE_HWREV_8169) {
1622                 lwkt_serialize_enter(ifp->if_serializer);
1623                 error = re_diag(sc);
1624                 lwkt_serialize_exit(ifp->if_serializer);
1625
1626                 if (error) {
1627                         device_printf(dev, "hardware diagnostic failure\n");
1628                         ether_ifdetach(ifp);
1629                         goto fail;
1630                 }
1631         }
1632 #endif  /* RE_DIAG */
1633
1634         /* Hook interrupt last to avoid having to lock softc */
1635         error = bus_setup_intr(dev, sc->re_irq, INTR_MPSAFE, re_intr, sc,
1636                                &sc->re_intrhand, ifp->if_serializer);
1637
1638         if (error) {
1639                 device_printf(dev, "couldn't set up irq\n");
1640                 ether_ifdetach(ifp);
1641                 goto fail;
1642         }
1643
1644         ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->re_irq));
1645         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
1646
1647 fail:
1648         if (error)
1649                 re_detach(dev);
1650
1651         return (error);
1652 }
1653
1654 /*
1655  * Shutdown hardware and free up resources. This can be called any
1656  * time after the mutex has been initialized. It is called in both
1657  * the error case in attach and the normal detach case so it needs
1658  * to be careful about only freeing resources that have actually been
1659  * allocated.
1660  */
1661 static int
1662 re_detach(device_t dev)
1663 {
1664         struct re_softc *sc = device_get_softc(dev);
1665         struct ifnet *ifp = &sc->arpcom.ac_if;
1666
1667         /* These should only be active if attach succeeded */
1668         if (device_is_attached(dev)) {
1669                 lwkt_serialize_enter(ifp->if_serializer);
1670                 re_stop(sc);
1671                 bus_teardown_intr(dev, sc->re_irq, sc->re_intrhand);
1672                 lwkt_serialize_exit(ifp->if_serializer);
1673
1674                 ether_ifdetach(ifp);
1675         }
1676         if (sc->re_miibus)
1677                 device_delete_child(dev, sc->re_miibus);
1678         bus_generic_detach(dev);
1679
1680         if (sc->re_sysctl_tree != NULL)
1681                 sysctl_ctx_free(&sc->re_sysctl_ctx);
1682
1683         if (sc->re_irq)
1684                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->re_irq);
1685         if (sc->re_res) {
1686                 bus_release_resource(dev, SYS_RES_IOPORT, RE_PCI_LOIO,
1687                                      sc->re_res);
1688         }
1689
1690         /* Free DMA stuffs */
1691         re_freemem(dev);
1692
1693         return(0);
1694 }
1695
1696 static void
1697 re_setup_rxdesc(struct re_softc *sc, int idx)
1698 {
1699         bus_addr_t paddr;
1700         uint32_t cmdstat;
1701         struct re_desc *d;
1702
1703         paddr = sc->re_ldata.re_rx_paddr[idx];
1704         d = &sc->re_ldata.re_rx_list[idx];
1705
1706         d->re_bufaddr_lo = htole32(RE_ADDR_LO(paddr));
1707         d->re_bufaddr_hi = htole32(RE_ADDR_HI(paddr));
1708
1709         cmdstat = sc->re_rxbuf_size | RE_RDESC_CMD_OWN;
1710         if (idx == (sc->re_rx_desc_cnt - 1))
1711                 cmdstat |= RE_RDESC_CMD_EOR;
1712         d->re_cmdstat = htole32(cmdstat);
1713 }
1714
1715 static int
1716 re_newbuf_std(struct re_softc *sc, int idx, int init)
1717 {
1718         struct re_dmaload_arg arg;
1719         bus_dma_segment_t seg;
1720         bus_dmamap_t map;
1721         struct mbuf *m;
1722         int error;
1723
1724         m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
1725         if (m == NULL) {
1726                 error = ENOBUFS;
1727
1728                 if (init) {
1729                         if_printf(&sc->arpcom.ac_if, "m_getcl failed\n");
1730                         return error;
1731                 } else {
1732                         goto back;
1733                 }
1734         }
1735         m->m_len = m->m_pkthdr.len = MCLBYTES;
1736
1737         /*
1738          * NOTE:
1739          * Some re(4) chips(e.g. RTL8101E) need address of the receive buffer
1740          * to be 8-byte aligned, so don't call m_adj(m, ETHER_ALIGN) here.
1741          */
1742
1743         arg.re_nsegs = 1;
1744         arg.re_segs = &seg;
1745         error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag,
1746                                      sc->re_ldata.re_rx_spare, m,
1747                                      re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
1748         if (error || arg.re_nsegs == 0) {
1749                 if (!error) {
1750                         if_printf(&sc->arpcom.ac_if, "too many segments?!\n");
1751                         bus_dmamap_unload(sc->re_ldata.re_mtag,
1752                                           sc->re_ldata.re_rx_spare);
1753                         error = EFBIG;
1754                 }
1755                 m_freem(m);
1756
1757                 if (init) {
1758                         if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n");
1759                         return error;
1760                 } else {
1761                         goto back;
1762                 }
1763         }
1764
1765         if (!init) {
1766                 bus_dmamap_sync(sc->re_ldata.re_mtag,
1767                                 sc->re_ldata.re_rx_dmamap[idx],
1768                                 BUS_DMASYNC_POSTREAD);
1769                 bus_dmamap_unload(sc->re_ldata.re_mtag,
1770                                   sc->re_ldata.re_rx_dmamap[idx]);
1771         }
1772         sc->re_ldata.re_rx_mbuf[idx] = m;
1773         sc->re_ldata.re_rx_paddr[idx] = seg.ds_addr;
1774
1775         map = sc->re_ldata.re_rx_dmamap[idx];
1776         sc->re_ldata.re_rx_dmamap[idx] = sc->re_ldata.re_rx_spare;
1777         sc->re_ldata.re_rx_spare = map;
1778 back:
1779         re_setup_rxdesc(sc, idx);
1780         return error;
1781 }
1782
1783 static int
1784 re_newbuf_jumbo(struct re_softc *sc, int idx, int init)
1785 {
1786         struct mbuf *m;
1787         struct re_jbuf *jbuf;
1788         int error = 0;
1789
1790         MGETHDR(m, init ? MB_WAIT : MB_DONTWAIT, MT_DATA);
1791         if (m == NULL) {
1792                 error = ENOBUFS;
1793                 if (init) {
1794                         if_printf(&sc->arpcom.ac_if, "MGETHDR failed\n");
1795                         return error;
1796                 } else {
1797                         goto back;
1798                 }
1799         }
1800
1801         jbuf = re_jbuf_alloc(sc);
1802         if (jbuf == NULL) {
1803                 m_freem(m);
1804
1805                 error = ENOBUFS;
1806                 if (init) {
1807                         if_printf(&sc->arpcom.ac_if, "jpool is empty\n");
1808                         return error;
1809                 } else {
1810                         goto back;
1811                 }
1812         }
1813
1814         m->m_ext.ext_arg = jbuf;
1815         m->m_ext.ext_buf = jbuf->re_buf;
1816         m->m_ext.ext_free = re_jbuf_free;
1817         m->m_ext.ext_ref = re_jbuf_ref;
1818         m->m_ext.ext_size = sc->re_rxbuf_size;
1819
1820         m->m_data = m->m_ext.ext_buf;
1821         m->m_flags |= M_EXT;
1822         m->m_len = m->m_pkthdr.len = m->m_ext.ext_size;
1823
1824         /*
1825          * NOTE:
1826          * Some re(4) chips(e.g. RTL8101E) need address of the receive buffer
1827          * to be 8-byte aligned, so don't call m_adj(m, ETHER_ALIGN) here.
1828          */
1829
1830         sc->re_ldata.re_rx_mbuf[idx] = m;
1831         sc->re_ldata.re_rx_paddr[idx] = jbuf->re_paddr;
1832 back:
1833         re_setup_rxdesc(sc, idx);
1834         return error;
1835 }
1836
1837 static int
1838 re_tx_list_init(struct re_softc *sc)
1839 {
1840         bzero(sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc));
1841
1842         /* Flush the TX descriptors */
1843         bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
1844                         sc->re_ldata.re_tx_list_map, BUS_DMASYNC_PREWRITE);
1845
1846         sc->re_ldata.re_tx_prodidx = 0;
1847         sc->re_ldata.re_tx_considx = 0;
1848         sc->re_ldata.re_tx_free = sc->re_tx_desc_cnt;
1849
1850         return(0);
1851 }
1852
1853 static int
1854 re_rx_list_init(struct re_softc *sc)
1855 {
1856         int i, error;
1857
1858         bzero(sc->re_ldata.re_rx_list, RE_RX_LIST_SZ(sc));
1859
1860         for (i = 0; i < sc->re_rx_desc_cnt; i++) {
1861                 error = sc->re_newbuf(sc, i, 1);
1862                 if (error)
1863                         return(error);
1864         }
1865
1866         /* Flush the RX descriptors */
1867         bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
1868                         sc->re_ldata.re_rx_list_map, BUS_DMASYNC_PREWRITE);
1869
1870         sc->re_ldata.re_rx_prodidx = 0;
1871         sc->re_head = sc->re_tail = NULL;
1872
1873         return(0);
1874 }
1875
1876 #define RE_IP4_PACKET   0x1
1877 #define RE_TCP_PACKET   0x2
1878 #define RE_UDP_PACKET   0x4
1879
1880 static __inline uint8_t
1881 re_packet_type(struct re_softc *sc, uint32_t rxstat, uint32_t rxctrl)
1882 {
1883         uint8_t packet_type = 0;
1884
1885         if (sc->re_caps & RE_C_MAC2) {
1886                 if (rxctrl & RE_RDESC_CTL_PROTOIP4)
1887                         packet_type |= RE_IP4_PACKET;
1888         } else {
1889                 if (rxstat & RE_RDESC_STAT_PROTOID)
1890                         packet_type |= RE_IP4_PACKET;
1891         }
1892         if (RE_TCPPKT(rxstat))
1893                 packet_type |= RE_TCP_PACKET;
1894         else if (RE_UDPPKT(rxstat))
1895                 packet_type |= RE_UDP_PACKET;
1896         return packet_type;
1897 }
1898
1899 /*
1900  * RX handler for C+ and 8169. For the gigE chips, we support
1901  * the reception of jumbo frames that have been fragmented
1902  * across multiple 2K mbuf cluster buffers.
1903  */
1904 static int
1905 re_rxeof(struct re_softc *sc)
1906 {
1907         struct ifnet *ifp = &sc->arpcom.ac_if;
1908         struct mbuf *m;
1909         struct re_desc  *cur_rx;
1910         uint32_t rxstat, rxctrl;
1911         int i, total_len, rx = 0;
1912         struct mbuf_chain chain[MAXCPU];
1913
1914         /* Invalidate the descriptor memory */
1915
1916         bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
1917                         sc->re_ldata.re_rx_list_map, BUS_DMASYNC_POSTREAD);
1918
1919         ether_input_chain_init(chain);
1920
1921         for (i = sc->re_ldata.re_rx_prodidx;
1922              RE_OWN(&sc->re_ldata.re_rx_list[i]) == 0; RE_RXDESC_INC(sc, i)) {
1923                 cur_rx = &sc->re_ldata.re_rx_list[i];
1924                 m = sc->re_ldata.re_rx_mbuf[i];
1925                 total_len = RE_RXBYTES(cur_rx);
1926                 rxstat = le32toh(cur_rx->re_cmdstat);
1927                 rxctrl = le32toh(cur_rx->re_control);
1928
1929                 rx = 1;
1930
1931 #ifdef INVARIANTS
1932                 if (sc->re_flags & RE_F_USE_JPOOL)
1933                         KKASSERT(rxstat & RE_RDESC_STAT_EOF);
1934 #endif
1935
1936                 if ((rxstat & RE_RDESC_STAT_EOF) == 0) {
1937                         if (sc->re_flags & RE_F_DROP_RXFRAG) {
1938                                 re_setup_rxdesc(sc, i);
1939                                 continue;
1940                         }
1941
1942                         if (sc->re_newbuf(sc, i, 0)) {
1943                                 /* Drop upcoming fragments */
1944                                 sc->re_flags |= RE_F_DROP_RXFRAG;
1945                                 continue;
1946                         }
1947
1948                         m->m_len = MCLBYTES;
1949                         if (sc->re_head == NULL) {
1950                                 sc->re_head = sc->re_tail = m;
1951                         } else {
1952                                 sc->re_tail->m_next = m;
1953                                 sc->re_tail = m;
1954                         }
1955                         continue;
1956                 } else if (sc->re_flags & RE_F_DROP_RXFRAG) {
1957                         /*
1958                          * Last fragment of a multi-fragment packet.
1959                          *
1960                          * Since error already happened, this fragment
1961                          * must be dropped as well as the fragment chain.
1962                          */
1963                         re_setup_rxdesc(sc, i);
1964                         re_free_rxchain(sc);
1965                         sc->re_flags &= ~RE_F_DROP_RXFRAG;
1966                         continue;
1967                 }
1968
1969                 /*
1970                  * NOTE: for the 8139C+, the frame length field
1971                  * is always 12 bits in size, but for the gigE chips,
1972                  * it is 13 bits (since the max RX frame length is 16K).
1973                  * Unfortunately, all 32 bits in the status word
1974                  * were already used, so to make room for the extra
1975                  * length bit, RealTek took out the 'frame alignment
1976                  * error' bit and shifted the other status bits
1977                  * over one slot. The OWN, EOR, FS and LS bits are
1978                  * still in the same places. We have already extracted
1979                  * the frame length and checked the OWN bit, so rather
1980                  * than using an alternate bit mapping, we shift the
1981                  * status bits one space to the right so we can evaluate
1982                  * them using the 8169 status as though it was in the
1983                  * same format as that of the 8139C+.
1984                  */
1985                 if (!RE_IS_8139CP(sc))
1986                         rxstat >>= 1;
1987
1988                 if (rxstat & RE_RDESC_STAT_RXERRSUM) {
1989                         ifp->if_ierrors++;
1990                         /*
1991                          * If this is part of a multi-fragment packet,
1992                          * discard all the pieces.
1993                          */
1994                         re_free_rxchain(sc);
1995                         re_setup_rxdesc(sc, i);
1996                         continue;
1997                 }
1998
1999                 /*
2000                  * If allocating a replacement mbuf fails,
2001                  * reload the current one.
2002                  */
2003
2004                 if (sc->re_newbuf(sc, i, 0)) {
2005                         ifp->if_ierrors++;
2006                         continue;
2007                 }
2008
2009                 if (sc->re_head != NULL) {
2010                         m->m_len = total_len % MCLBYTES;
2011                         /*
2012                          * Special case: if there's 4 bytes or less
2013                          * in this buffer, the mbuf can be discarded:
2014                          * the last 4 bytes is the CRC, which we don't
2015                          * care about anyway.
2016                          */
2017                         if (m->m_len <= ETHER_CRC_LEN) {
2018                                 sc->re_tail->m_len -=
2019                                     (ETHER_CRC_LEN - m->m_len);
2020                                 m_freem(m);
2021                         } else {
2022                                 m->m_len -= ETHER_CRC_LEN;
2023                                 sc->re_tail->m_next = m;
2024                         }
2025                         m = sc->re_head;
2026                         sc->re_head = sc->re_tail = NULL;
2027                         m->m_pkthdr.len = total_len - ETHER_CRC_LEN;
2028                 } else {
2029                         m->m_pkthdr.len = m->m_len =
2030                             (total_len - ETHER_CRC_LEN);
2031                 }
2032
2033                 ifp->if_ipackets++;
2034                 m->m_pkthdr.rcvif = ifp;
2035
2036                 /* Do RX checksumming if enabled */
2037
2038                 if (ifp->if_capenable & IFCAP_RXCSUM) {
2039                         uint8_t packet_type;
2040
2041                         packet_type = re_packet_type(sc, rxstat, rxctrl);
2042
2043                         /* Check IP header checksum */
2044                         if (packet_type & RE_IP4_PACKET) {
2045                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2046                                 if ((rxstat & RE_RDESC_STAT_IPSUMBAD) == 0)
2047                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2048                         }
2049
2050                         /* Check TCP/UDP checksum */
2051                         if (((packet_type & RE_TCP_PACKET) &&
2052                              (rxstat & RE_RDESC_STAT_TCPSUMBAD) == 0) ||
2053                             ((packet_type & RE_UDP_PACKET) &&
2054                              (rxstat & RE_RDESC_STAT_UDPSUMBAD) == 0)) {
2055                                 m->m_pkthdr.csum_flags |=
2056                                     CSUM_DATA_VALID|CSUM_PSEUDO_HDR|
2057                                     CSUM_FRAG_NOT_CHECKED;
2058                                 m->m_pkthdr.csum_data = 0xffff;
2059                         }
2060                 }
2061
2062                 if (rxctrl & RE_RDESC_CTL_HASTAG) {
2063                         m->m_flags |= M_VLANTAG;
2064                         m->m_pkthdr.ether_vlantag =
2065                                 be16toh((rxctrl & RE_RDESC_CTL_TAGDATA));
2066                 }
2067                 ether_input_chain(ifp, m, chain);
2068         }
2069
2070         ether_input_dispatch(chain);
2071
2072         /* Flush the RX DMA ring */
2073
2074         bus_dmamap_sync(sc->re_ldata.re_rx_list_tag,
2075                         sc->re_ldata.re_rx_list_map, BUS_DMASYNC_PREWRITE);
2076
2077         sc->re_ldata.re_rx_prodidx = i;
2078
2079         return rx;
2080 }
2081
2082 #undef RE_IP4_PACKET
2083 #undef RE_TCP_PACKET
2084 #undef RE_UDP_PACKET
2085
2086 static int
2087 re_tx_collect(struct re_softc *sc)
2088 {
2089         struct ifnet *ifp = &sc->arpcom.ac_if;
2090         uint32_t txstat;
2091         int idx, tx = 0;
2092
2093         /* Invalidate the TX descriptor list */
2094         bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
2095                         sc->re_ldata.re_tx_list_map, BUS_DMASYNC_POSTREAD);
2096
2097         for (idx = sc->re_ldata.re_tx_considx;
2098              sc->re_ldata.re_tx_free < sc->re_tx_desc_cnt;
2099              RE_TXDESC_INC(sc, idx)) {
2100                 txstat = le32toh(sc->re_ldata.re_tx_list[idx].re_cmdstat);
2101                 if (txstat & RE_TDESC_CMD_OWN)
2102                         break;
2103
2104                 tx = 1;
2105
2106                 sc->re_ldata.re_tx_list[idx].re_bufaddr_lo = 0;
2107
2108                 /*
2109                  * We only stash mbufs in the last descriptor
2110                  * in a fragment chain, which also happens to
2111                  * be the only place where the TX status bits
2112                  * are valid.
2113                  */
2114                 if (txstat & RE_TDESC_CMD_EOF) {
2115                         m_freem(sc->re_ldata.re_tx_mbuf[idx]);
2116                         sc->re_ldata.re_tx_mbuf[idx] = NULL;
2117                         bus_dmamap_unload(sc->re_ldata.re_mtag,
2118                             sc->re_ldata.re_tx_dmamap[idx]);
2119                         if (txstat & (RE_TDESC_STAT_EXCESSCOL|
2120                             RE_TDESC_STAT_COLCNT))
2121                                 ifp->if_collisions++;
2122                         if (txstat & RE_TDESC_STAT_TXERRSUM)
2123                                 ifp->if_oerrors++;
2124                         else
2125                                 ifp->if_opackets++;
2126                 }
2127                 sc->re_ldata.re_tx_free++;
2128         }
2129         sc->re_ldata.re_tx_considx = idx;
2130
2131         return tx;
2132 }
2133
2134 static int
2135 re_txeof(struct re_softc *sc)
2136 {
2137         struct ifnet *ifp = &sc->arpcom.ac_if;
2138         int tx;
2139
2140         tx = re_tx_collect(sc);
2141
2142         /* There is enough free TX descs */
2143         if (sc->re_ldata.re_tx_free > RE_TXDESC_SPARE)
2144                 ifp->if_flags &= ~IFF_OACTIVE;
2145
2146         /*
2147          * Some chips will ignore a second TX request issued while an
2148          * existing transmission is in progress. If the transmitter goes
2149          * idle but there are still packets waiting to be sent, we need
2150          * to restart the channel here to flush them out. This only seems
2151          * to be required with the PCIe devices.
2152          */
2153         if (sc->re_ldata.re_tx_free < sc->re_tx_desc_cnt)
2154                 CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START);
2155         else
2156                 ifp->if_timer = 0;
2157
2158         return tx;
2159 }
2160
2161 static void
2162 re_tick(void *xsc)
2163 {
2164         struct re_softc *sc = xsc;
2165
2166         lwkt_serialize_enter(sc->arpcom.ac_if.if_serializer);
2167         re_tick_serialized(xsc);
2168         lwkt_serialize_exit(sc->arpcom.ac_if.if_serializer);
2169 }
2170
2171 static void
2172 re_tick_serialized(void *xsc)
2173 {
2174         struct re_softc *sc = xsc;
2175         struct ifnet *ifp = &sc->arpcom.ac_if;
2176         struct mii_data *mii;
2177
2178         ASSERT_SERIALIZED(ifp->if_serializer);
2179
2180         mii = device_get_softc(sc->re_miibus);
2181         mii_tick(mii);
2182         if (sc->re_flags & RE_F_LINKED) {
2183                 if (!(mii->mii_media_status & IFM_ACTIVE))
2184                         sc->re_flags &= ~RE_F_LINKED;
2185         } else {
2186                 if (mii->mii_media_status & IFM_ACTIVE &&
2187                     IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
2188                         sc->re_flags |= RE_F_LINKED;
2189                         if (!ifq_is_empty(&ifp->if_snd))
2190                                 if_devstart(ifp);
2191                 }
2192         }
2193
2194         callout_reset(&sc->re_timer, hz, re_tick, sc);
2195 }
2196
2197 #ifdef DEVICE_POLLING
2198
2199 static void
2200 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2201 {
2202         struct re_softc *sc = ifp->if_softc;
2203
2204         ASSERT_SERIALIZED(ifp->if_serializer);
2205
2206         switch(cmd) {
2207         case POLL_REGISTER:
2208                 /* disable interrupts */
2209                 re_setup_intr(sc, 0, RE_IMTYPE_NONE);
2210                 break;
2211
2212         case POLL_DEREGISTER:
2213                 /* enable interrupts */
2214                 re_setup_intr(sc, 1, sc->re_imtype);
2215                 break;
2216
2217         default:
2218                 sc->rxcycles = count;
2219                 re_rxeof(sc);
2220                 re_txeof(sc);
2221
2222                 if (!ifq_is_empty(&ifp->if_snd))
2223                         if_devstart(ifp);
2224
2225                 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */
2226                         uint16_t       status;
2227
2228                         status = CSR_READ_2(sc, RE_ISR);
2229                         if (status == 0xffff)
2230                                 return;
2231                         if (status)
2232                                 CSR_WRITE_2(sc, RE_ISR, status);
2233
2234                         /*
2235                          * XXX check behaviour on receiver stalls.
2236                          */
2237
2238                         if (status & RE_ISR_SYSTEM_ERR)
2239                                 re_init(sc);
2240                 }
2241                 break;
2242         }
2243 }
2244 #endif /* DEVICE_POLLING */
2245
2246 static void
2247 re_intr(void *arg)
2248 {
2249         struct re_softc *sc = arg;
2250         struct ifnet *ifp = &sc->arpcom.ac_if;
2251         uint16_t status;
2252         int rx, tx;
2253
2254         ASSERT_SERIALIZED(ifp->if_serializer);
2255
2256         if ((sc->re_flags & RE_F_SUSPENDED) ||
2257             (ifp->if_flags & IFF_RUNNING) == 0)
2258                 return;
2259
2260         rx = tx = 0;
2261         for (;;) {
2262                 status = CSR_READ_2(sc, RE_ISR);
2263                 /* If the card has gone away the read returns 0xffff. */
2264                 if (status == 0xffff)
2265                         break;
2266                 if (status)
2267                         CSR_WRITE_2(sc, RE_ISR, status);
2268
2269                 if ((status & sc->re_intrs) == 0)
2270                         break;
2271
2272                 if (status & (sc->re_rx_ack | RE_ISR_RX_ERR))
2273                         rx |= re_rxeof(sc);
2274
2275                 if (status & (sc->re_tx_ack | RE_ISR_TX_ERR))
2276                         tx |= re_txeof(sc);
2277
2278                 if (status & RE_ISR_SYSTEM_ERR)
2279                         re_init(sc);
2280
2281                 if (status & RE_ISR_LINKCHG) {
2282                         callout_stop(&sc->re_timer);
2283                         re_tick_serialized(sc);
2284                 }
2285         }
2286
2287         if (sc->re_imtype == RE_IMTYPE_SIM) {
2288                 if ((sc->re_flags & RE_F_TIMER_INTR)) {
2289                         if ((tx | rx) == 0) {
2290                                 /*
2291                                  * Nothing needs to be processed, fallback
2292                                  * to use TX/RX interrupts.
2293                                  */
2294                                 re_setup_intr(sc, 1, RE_IMTYPE_NONE);
2295
2296                                 /*
2297                                  * Recollect, mainly to avoid the possible
2298                                  * race introduced by changing interrupt
2299                                  * masks.
2300                                  */
2301                                 re_rxeof(sc);
2302                                 tx = re_txeof(sc);
2303                         } else {
2304                                 CSR_WRITE_4(sc, RE_TIMERCNT, 1); /* reload */
2305                         }
2306                 } else if (tx | rx) {
2307                         /*
2308                          * Assume that using simulated interrupt moderation
2309                          * (hardware timer based) could reduce the interript
2310                          * rate.
2311                          */
2312                         re_setup_intr(sc, 1, RE_IMTYPE_SIM);
2313                 }
2314         }
2315
2316         if (tx && !ifq_is_empty(&ifp->if_snd))
2317                 if_devstart(ifp);
2318 }
2319
2320 static int
2321 re_encap(struct re_softc *sc, struct mbuf **m_head, int *idx0)
2322 {
2323         struct ifnet *ifp = &sc->arpcom.ac_if;
2324         struct mbuf *m;
2325         struct re_dmaload_arg arg;
2326         bus_dma_segment_t segs[RE_MAXSEGS];
2327         bus_dmamap_t map;
2328         int error, maxsegs, idx, i;
2329         struct re_desc *d, *tx_ring;
2330         uint32_t cmd_csum, ctl_csum, vlantag;
2331
2332         KASSERT(sc->re_ldata.re_tx_free > RE_TXDESC_SPARE,
2333                 ("not enough free TX desc\n"));
2334
2335         m = *m_head;
2336         map = sc->re_ldata.re_tx_dmamap[*idx0];
2337
2338         /*
2339          * Set up checksum offload. Note: checksum offload bits must
2340          * appear in all descriptors of a multi-descriptor transmit
2341          * attempt. (This is according to testing done with an 8169
2342          * chip. I'm not sure if this is a requirement or a bug.)
2343          */
2344         cmd_csum = ctl_csum = 0;
2345         if (m->m_pkthdr.csum_flags & CSUM_IP) {
2346                 cmd_csum |= RE_TDESC_CMD_IPCSUM;
2347                 ctl_csum |= RE_TDESC_CTL_IPCSUM;
2348         }
2349         if (m->m_pkthdr.csum_flags & CSUM_TCP) {
2350                 cmd_csum |= RE_TDESC_CMD_TCPCSUM;
2351                 ctl_csum |= RE_TDESC_CTL_TCPCSUM;
2352         }
2353         if (m->m_pkthdr.csum_flags & CSUM_UDP) {
2354                 cmd_csum |= RE_TDESC_CMD_UDPCSUM;
2355                 ctl_csum |= RE_TDESC_CTL_UDPCSUM;
2356         }
2357
2358         /* For MAC2 chips, csum flags are set on re_control */
2359         if (sc->re_caps & RE_C_MAC2)
2360                 cmd_csum = 0;
2361         else
2362                 ctl_csum = 0;
2363
2364         if ((sc->re_caps & RE_C_AUTOPAD) == 0) {
2365                 /*
2366                  * With some of the RealTek chips, using the checksum offload
2367                  * support in conjunction with the autopadding feature results
2368                  * in the transmission of corrupt frames. For example, if we
2369                  * need to send a really small IP fragment that's less than 60
2370                  * bytes in size, and IP header checksumming is enabled, the
2371                  * resulting ethernet frame that appears on the wire will
2372                  * have garbled payload. To work around this, if TX checksum
2373                  * offload is enabled, we always manually pad short frames out
2374                  * to the minimum ethernet frame size.
2375                  *
2376                  * Note: this appears unnecessary for TCP, and doing it for TCP
2377                  * with PCIe adapters seems to result in bad checksums.
2378                  */
2379                 if ((m->m_pkthdr.csum_flags &
2380                      (CSUM_DELAY_IP | CSUM_DELAY_DATA)) &&
2381                     (m->m_pkthdr.csum_flags & CSUM_TCP) == 0 &&
2382                     m->m_pkthdr.len < RE_MIN_FRAMELEN) {
2383                         error = m_devpad(m, RE_MIN_FRAMELEN);
2384                         if (error)
2385                                 goto back;
2386                 }
2387         }
2388
2389         vlantag = 0;
2390         if (m->m_flags & M_VLANTAG) {
2391                 vlantag = htobe16(m->m_pkthdr.ether_vlantag) |
2392                           RE_TDESC_CTL_INSTAG;
2393         }
2394
2395         maxsegs = sc->re_ldata.re_tx_free;
2396         if (maxsegs > RE_MAXSEGS)
2397                 maxsegs = RE_MAXSEGS;
2398
2399         arg.re_nsegs = maxsegs;
2400         arg.re_segs = segs;
2401         error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map, m,
2402                                      re_dma_map_desc, &arg, BUS_DMA_NOWAIT);
2403         if (error && error != EFBIG) {
2404                 if_printf(ifp, "can't map mbuf (error %d)\n", error);
2405                 goto back;
2406         }
2407
2408         /*
2409          * Too many segments to map, coalesce into a single mbuf
2410          */
2411         if (!error && arg.re_nsegs == 0) {
2412                 bus_dmamap_unload(sc->re_ldata.re_mtag, map);
2413                 error = EFBIG;
2414         }
2415         if (error) {
2416                 struct mbuf *m_new;
2417
2418                 m_new = m_defrag(m, MB_DONTWAIT);
2419                 if (m_new == NULL) {
2420                         if_printf(ifp, "can't defrag TX mbuf\n");
2421                         error = ENOBUFS;
2422                         goto back;
2423                 } else {
2424                         *m_head = m = m_new;
2425                 }
2426
2427                 arg.re_nsegs = maxsegs;
2428                 arg.re_segs = segs;
2429                 error = bus_dmamap_load_mbuf(sc->re_ldata.re_mtag, map, m,
2430                                              re_dma_map_desc, &arg,
2431                                              BUS_DMA_NOWAIT);
2432                 if (error || arg.re_nsegs == 0) {
2433                         if (!error) {
2434                                 bus_dmamap_unload(sc->re_ldata.re_mtag, map);
2435                                 error = EFBIG;
2436                         }
2437                         if_printf(ifp, "can't map mbuf (error %d)\n", error);
2438                         goto back;
2439                 }
2440         }
2441         bus_dmamap_sync(sc->re_ldata.re_mtag, map, BUS_DMASYNC_PREWRITE);
2442
2443         /*
2444          * Map the segment array into descriptors.  We also keep track
2445          * of the end of the ring and set the end-of-ring bits as needed,
2446          * and we set the ownership bits in all except the very first
2447          * descriptor, whose ownership bits will be turned on later.
2448          */
2449         tx_ring = sc->re_ldata.re_tx_list;
2450         idx = *idx0;
2451         i = 0;
2452         for (;;) {
2453                 uint32_t cmdstat;
2454
2455                 d = &tx_ring[idx];
2456
2457                 cmdstat = segs[i].ds_len;
2458                 d->re_bufaddr_lo = htole32(RE_ADDR_LO(segs[i].ds_addr));
2459                 d->re_bufaddr_hi = htole32(RE_ADDR_HI(segs[i].ds_addr));
2460                 if (i == 0)
2461                         cmdstat |= RE_TDESC_CMD_SOF;
2462                 else
2463                         cmdstat |= RE_TDESC_CMD_OWN;
2464                 if (idx == (sc->re_tx_desc_cnt - 1))
2465                         cmdstat |= RE_TDESC_CMD_EOR;
2466                 d->re_cmdstat = htole32(cmdstat | cmd_csum);
2467                 d->re_control = htole32(ctl_csum | vlantag);
2468
2469                 i++;
2470                 if (i == arg.re_nsegs)
2471                         break;
2472                 RE_TXDESC_INC(sc, idx);
2473         }
2474         d->re_cmdstat |= htole32(RE_TDESC_CMD_EOF);
2475
2476         /* Transfer ownership of packet to the chip. */
2477         d->re_cmdstat |= htole32(RE_TDESC_CMD_OWN);
2478         if (*idx0 != idx)
2479                 tx_ring[*idx0].re_cmdstat |= htole32(RE_TDESC_CMD_OWN);
2480
2481         /*
2482          * Insure that the map for this transmission
2483          * is placed at the array index of the last descriptor
2484          * in this chain.
2485          */
2486         sc->re_ldata.re_tx_dmamap[*idx0] = sc->re_ldata.re_tx_dmamap[idx];
2487         sc->re_ldata.re_tx_dmamap[idx] = map;
2488
2489         sc->re_ldata.re_tx_mbuf[idx] = m;
2490         sc->re_ldata.re_tx_free -= arg.re_nsegs;
2491
2492         RE_TXDESC_INC(sc, idx);
2493         *idx0 = idx;
2494 back:
2495         if (error) {
2496                 m_freem(m);
2497                 *m_head = NULL;
2498         }
2499         return error;
2500 }
2501
2502 /*
2503  * Main transmit routine for C+ and gigE NICs.
2504  */
2505
2506 static void
2507 re_start(struct ifnet *ifp)
2508 {
2509         struct re_softc *sc = ifp->if_softc;
2510         struct mbuf *m_head;
2511         int idx, need_trans, oactive, error;
2512
2513         ASSERT_SERIALIZED(ifp->if_serializer);
2514
2515         if ((sc->re_flags & RE_F_LINKED) == 0) {
2516                 ifq_purge(&ifp->if_snd);
2517                 return;
2518         }
2519
2520         if ((ifp->if_flags & (IFF_OACTIVE | IFF_RUNNING)) != IFF_RUNNING)
2521                 return;
2522
2523         idx = sc->re_ldata.re_tx_prodidx;
2524
2525         need_trans = 0;
2526         oactive = 0;
2527         while (sc->re_ldata.re_tx_mbuf[idx] == NULL) {
2528                 if (sc->re_ldata.re_tx_free <= RE_TXDESC_SPARE) {
2529                         if (!oactive) {
2530                                 if (re_tx_collect(sc)) {
2531                                         oactive = 1;
2532                                         continue;
2533                                 }
2534                         }
2535                         ifp->if_flags |= IFF_OACTIVE;
2536                         break;
2537                 }
2538
2539                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
2540                 if (m_head == NULL)
2541                         break;
2542
2543                 error = re_encap(sc, &m_head, &idx);
2544                 if (error) {
2545                         /* m_head is freed by re_encap(), if we reach here */
2546                         ifp->if_oerrors++;
2547
2548                         if (error == EFBIG && !oactive) {
2549                                 if (re_tx_collect(sc)) {
2550                                         oactive = 1;
2551                                         continue;
2552                                 }
2553                         }
2554                         ifp->if_flags |= IFF_OACTIVE;
2555                         break;
2556                 }
2557
2558                 oactive = 0;
2559                 need_trans = 1;
2560
2561                 /*
2562                  * If there's a BPF listener, bounce a copy of this frame
2563                  * to him.
2564                  */
2565                 ETHER_BPF_MTAP(ifp, m_head);
2566         }
2567
2568         if (!need_trans)
2569                 return;
2570
2571         /* Flush the TX descriptors */
2572         bus_dmamap_sync(sc->re_ldata.re_tx_list_tag,
2573                         sc->re_ldata.re_tx_list_map, BUS_DMASYNC_PREWRITE);
2574
2575         sc->re_ldata.re_tx_prodidx = idx;
2576
2577         /*
2578          * RealTek put the TX poll request register in a different
2579          * location on the 8169 gigE chip. I don't know why.
2580          */
2581         CSR_WRITE_1(sc, sc->re_txstart, RE_TXSTART_START);
2582
2583         /*
2584          * Set a timeout in case the chip goes out to lunch.
2585          */
2586         ifp->if_timer = 5;
2587 }
2588
2589 static void
2590 re_init(void *xsc)
2591 {
2592         struct re_softc *sc = xsc;
2593         struct ifnet *ifp = &sc->arpcom.ac_if;
2594         struct mii_data *mii;
2595         int error, framelen;
2596
2597         ASSERT_SERIALIZED(ifp->if_serializer);
2598
2599         mii = device_get_softc(sc->re_miibus);
2600
2601         /*
2602          * Cancel pending I/O and free all RX/TX buffers.
2603          */
2604         re_stop(sc);
2605
2606         if (sc->re_caps & RE_C_CONTIGRX) {
2607                 if (ifp->if_mtu > ETHERMTU) {
2608                         KKASSERT(sc->re_ldata.re_jbuf != NULL);
2609                         sc->re_flags |= RE_F_USE_JPOOL;
2610                         sc->re_rxbuf_size = RE_FRAMELEN_MAX;
2611                         sc->re_newbuf = re_newbuf_jumbo;
2612                 } else {
2613                         sc->re_flags &= ~RE_F_USE_JPOOL;
2614                         sc->re_rxbuf_size = MCLBYTES;
2615                         sc->re_newbuf = re_newbuf_std;
2616                 }
2617         }
2618
2619         /*
2620          * Adjust max read request size according to MTU.
2621          * Mainly to improve TX performance for common case (ETHERMTU).
2622          */
2623         if (sc->re_caps & RE_C_PCIE) {
2624                 if (ifp->if_mtu > ETHERMTU) {
2625                         /*
2626                          * 512 seems to be the only value that works
2627                          * reliably with jumbo frame
2628                          */
2629                         pcie_set_max_readrq(sc->re_dev,
2630                                 PCIEM_DEVCTL_MAX_READRQ_512);
2631                 } else {
2632                         pcie_set_max_readrq(sc->re_dev,
2633                                 PCIEM_DEVCTL_MAX_READRQ_4096);
2634                 }
2635         }
2636
2637         /*
2638          * Enable C+ RX and TX mode, as well as VLAN stripping and
2639          * RX checksum offload. We must configure the C+ register
2640          * before all others.
2641          */
2642         CSR_WRITE_2(sc, RE_CPLUS_CMD, RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB |
2643                     RE_CPLUSCMD_PCI_MRW |
2644                     (ifp->if_capenable & IFCAP_VLAN_HWTAGGING ?
2645                      RE_CPLUSCMD_VLANSTRIP : 0) |
2646                     (ifp->if_capenable & IFCAP_RXCSUM ?
2647                      RE_CPLUSCMD_RXCSUM_ENB : 0));
2648
2649         /*
2650          * Init our MAC address.  Even though the chipset
2651          * documentation doesn't mention it, we need to enter "Config
2652          * register write enable" mode to modify the ID registers.
2653          */
2654         CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_WRITECFG);
2655         CSR_WRITE_4(sc, RE_IDR0,
2656             htole32(*(uint32_t *)(&sc->arpcom.ac_enaddr[0])));
2657         CSR_WRITE_2(sc, RE_IDR4,
2658             htole16(*(uint16_t *)(&sc->arpcom.ac_enaddr[4])));
2659         CSR_WRITE_1(sc, RE_EECMD, RE_EEMODE_OFF);
2660
2661         /*
2662          * For C+ mode, initialize the RX descriptors and mbufs.
2663          */
2664         error = re_rx_list_init(sc);
2665         if (error) {
2666                 re_stop(sc);
2667                 return;
2668         }
2669         error = re_tx_list_init(sc);
2670         if (error) {
2671                 re_stop(sc);
2672                 return;
2673         }
2674
2675         /*
2676          * Load the addresses of the RX and TX lists into the chip.
2677          */
2678         CSR_WRITE_4(sc, RE_RXLIST_ADDR_HI,
2679             RE_ADDR_HI(sc->re_ldata.re_rx_list_addr));
2680         CSR_WRITE_4(sc, RE_RXLIST_ADDR_LO,
2681             RE_ADDR_LO(sc->re_ldata.re_rx_list_addr));
2682
2683         CSR_WRITE_4(sc, RE_TXLIST_ADDR_HI,
2684             RE_ADDR_HI(sc->re_ldata.re_tx_list_addr));
2685         CSR_WRITE_4(sc, RE_TXLIST_ADDR_LO,
2686             RE_ADDR_LO(sc->re_ldata.re_tx_list_addr));
2687
2688         /*
2689          * Enable transmit and receive.
2690          */
2691         CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB);
2692
2693         /*
2694          * Set the initial TX and RX configuration.
2695          */
2696         if (sc->re_flags & RE_F_TESTMODE) {
2697                 if (!RE_IS_8139CP(sc))
2698                         CSR_WRITE_4(sc, RE_TXCFG,
2699                                     RE_TXCFG_CONFIG | RE_LOOPTEST_ON);
2700                 else
2701                         CSR_WRITE_4(sc, RE_TXCFG,
2702                                     RE_TXCFG_CONFIG | RE_LOOPTEST_ON_CPLUS);
2703         } else
2704                 CSR_WRITE_4(sc, RE_TXCFG, RE_TXCFG_CONFIG);
2705
2706         framelen = RE_FRAMELEN(ifp->if_mtu);
2707         if (framelen < MCLBYTES)
2708                 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, howmany(MCLBYTES, 128));
2709         else
2710                 CSR_WRITE_1(sc, RE_EARLY_TX_THRESH, howmany(framelen, 128));
2711
2712         CSR_WRITE_4(sc, RE_RXCFG, RE_RXCFG_CONFIG);
2713
2714         /*
2715          * Program the multicast filter, if necessary.
2716          */
2717         re_setmulti(sc);
2718
2719 #ifdef DEVICE_POLLING
2720         /*
2721          * Disable interrupts if we are polling.
2722          */
2723         if (ifp->if_flags & IFF_POLLING)
2724                 re_setup_intr(sc, 0, RE_IMTYPE_NONE);
2725         else    /* otherwise ... */
2726 #endif /* DEVICE_POLLING */
2727         /*
2728          * Enable interrupts.
2729          */
2730         if (sc->re_flags & RE_F_TESTMODE)
2731                 CSR_WRITE_2(sc, RE_IMR, 0);
2732         else
2733                 re_setup_intr(sc, 1, sc->re_imtype);
2734         CSR_WRITE_2(sc, RE_ISR, sc->re_intrs);
2735
2736         /* Start RX/TX process. */
2737         CSR_WRITE_4(sc, RE_MISSEDPKT, 0);
2738
2739 #ifdef notdef
2740         /* Enable receiver and transmitter. */
2741         CSR_WRITE_1(sc, RE_COMMAND, RE_CMD_TX_ENB|RE_CMD_RX_ENB);
2742 #endif
2743
2744         /*
2745          * For 8169 gigE NICs, set the max allowed RX packet
2746          * size so we can receive jumbo frames.
2747          */
2748         if (!RE_IS_8139CP(sc)) {
2749                 if (sc->re_caps & RE_C_CONTIGRX)
2750                         CSR_WRITE_2(sc, RE_MAXRXPKTLEN, sc->re_rxbuf_size);
2751                 else
2752                         CSR_WRITE_2(sc, RE_MAXRXPKTLEN, 16383);
2753         }
2754
2755         if (sc->re_flags & RE_F_TESTMODE)
2756                 return;
2757
2758         mii_mediachg(mii);
2759
2760         CSR_WRITE_1(sc, RE_CFG1, RE_CFG1_DRVLOAD|RE_CFG1_FULLDUPLEX);
2761
2762         ifp->if_flags |= IFF_RUNNING;
2763         ifp->if_flags &= ~IFF_OACTIVE;
2764
2765         callout_reset(&sc->re_timer, hz, re_tick, sc);
2766 }
2767
2768 /*
2769  * Set media options.
2770  */
2771 static int
2772 re_ifmedia_upd(struct ifnet *ifp)
2773 {
2774         struct re_softc *sc = ifp->if_softc;
2775         struct mii_data *mii;
2776
2777         ASSERT_SERIALIZED(ifp->if_serializer);
2778
2779         mii = device_get_softc(sc->re_miibus);
2780         mii_mediachg(mii);
2781
2782         return(0);
2783 }
2784
2785 /*
2786  * Report current media status.
2787  */
2788 static void
2789 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2790 {
2791         struct re_softc *sc = ifp->if_softc;
2792         struct mii_data *mii;
2793
2794         ASSERT_SERIALIZED(ifp->if_serializer);
2795
2796         mii = device_get_softc(sc->re_miibus);
2797
2798         mii_pollstat(mii);
2799         ifmr->ifm_active = mii->mii_media_active;
2800         ifmr->ifm_status = mii->mii_media_status;
2801 }
2802
2803 static int
2804 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2805 {
2806         struct re_softc *sc = ifp->if_softc;
2807         struct ifreq *ifr = (struct ifreq *) data;
2808         struct mii_data *mii;
2809         int error = 0, mask;
2810
2811         ASSERT_SERIALIZED(ifp->if_serializer);
2812
2813         switch(command) {
2814         case SIOCSIFMTU:
2815                 if (ifr->ifr_mtu > sc->re_maxmtu) {
2816                         error = EINVAL;
2817                 } else if (ifp->if_mtu != ifr->ifr_mtu) {
2818                         ifp->if_mtu = ifr->ifr_mtu;
2819                         if (ifp->if_flags & IFF_RUNNING)
2820                                 ifp->if_init(sc);
2821                 }
2822                 break;
2823
2824         case SIOCSIFFLAGS:
2825                 if (ifp->if_flags & IFF_UP) {
2826                         if (ifp->if_flags & IFF_RUNNING) {
2827                                 if ((ifp->if_flags ^ sc->re_if_flags) &
2828                                     (IFF_PROMISC | IFF_ALLMULTI))
2829                                         re_setmulti(sc);
2830                         } else {
2831                                 re_init(sc);
2832                         }
2833                 } else if (ifp->if_flags & IFF_RUNNING) {
2834                         re_stop(sc);
2835                 }
2836                 sc->re_if_flags = ifp->if_flags;
2837                 break;
2838
2839         case SIOCADDMULTI:
2840         case SIOCDELMULTI:
2841                 re_setmulti(sc);
2842                 break;
2843
2844         case SIOCGIFMEDIA:
2845         case SIOCSIFMEDIA:
2846                 mii = device_get_softc(sc->re_miibus);
2847                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2848                 break;
2849
2850         case SIOCSIFCAP:
2851                 mask = (ifr->ifr_reqcap ^ ifp->if_capenable) &
2852                        ifp->if_capabilities;
2853                 ifp->if_capenable ^= mask;
2854
2855                 if (mask & IFCAP_HWCSUM) {
2856                         if (ifp->if_capenable & IFCAP_TXCSUM)
2857                                 ifp->if_hwassist = RE_CSUM_FEATURES;
2858                         else
2859                                 ifp->if_hwassist = 0;
2860                 }
2861                 if (mask && (ifp->if_flags & IFF_RUNNING))
2862                         re_init(sc);
2863                 break;
2864
2865         default:
2866                 error = ether_ioctl(ifp, command, data);
2867                 break;
2868         }
2869         return(error);
2870 }
2871
2872 static void
2873 re_watchdog(struct ifnet *ifp)
2874 {
2875         struct re_softc *sc = ifp->if_softc;
2876
2877         ASSERT_SERIALIZED(ifp->if_serializer);
2878
2879         if_printf(ifp, "watchdog timeout\n");
2880
2881         ifp->if_oerrors++;
2882
2883         re_txeof(sc);
2884         re_rxeof(sc);
2885
2886         re_init(sc);
2887
2888         if (!ifq_is_empty(&ifp->if_snd))
2889                 if_devstart(ifp);
2890 }
2891
2892 /*
2893  * Stop the adapter and free any mbufs allocated to the
2894  * RX and TX lists.
2895  */
2896 static void
2897 re_stop(struct re_softc *sc)
2898 {
2899         struct ifnet *ifp = &sc->arpcom.ac_if;
2900         int i;
2901
2902         ASSERT_SERIALIZED(ifp->if_serializer);
2903
2904         /* Reset the adapter. */
2905         re_reset(sc, ifp->if_flags & IFF_RUNNING);
2906
2907         ifp->if_timer = 0;
2908         callout_stop(&sc->re_timer);
2909
2910         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2911         sc->re_flags &= ~(RE_F_TIMER_INTR | RE_F_DROP_RXFRAG | RE_F_LINKED);
2912
2913         CSR_WRITE_1(sc, RE_COMMAND, 0x00);
2914         CSR_WRITE_2(sc, RE_IMR, 0x0000);
2915         CSR_WRITE_2(sc, RE_ISR, 0xFFFF);
2916
2917         re_free_rxchain(sc);
2918
2919         /* Free the TX list buffers. */
2920         for (i = 0; i < sc->re_tx_desc_cnt; i++) {
2921                 if (sc->re_ldata.re_tx_mbuf[i] != NULL) {
2922                         bus_dmamap_unload(sc->re_ldata.re_mtag,
2923                                           sc->re_ldata.re_tx_dmamap[i]);
2924                         m_freem(sc->re_ldata.re_tx_mbuf[i]);
2925                         sc->re_ldata.re_tx_mbuf[i] = NULL;
2926                 }
2927         }
2928
2929         /* Free the RX list buffers. */
2930         for (i = 0; i < sc->re_rx_desc_cnt; i++) {
2931                 if (sc->re_ldata.re_rx_mbuf[i] != NULL) {
2932                         if ((sc->re_flags & RE_F_USE_JPOOL) == 0) {
2933                                 bus_dmamap_unload(sc->re_ldata.re_mtag,
2934                                                   sc->re_ldata.re_rx_dmamap[i]);
2935                         }
2936                         m_freem(sc->re_ldata.re_rx_mbuf[i]);
2937                         sc->re_ldata.re_rx_mbuf[i] = NULL;
2938                 }
2939         }
2940 }
2941
2942 /*
2943  * Device suspend routine.  Stop the interface and save some PCI
2944  * settings in case the BIOS doesn't restore them properly on
2945  * resume.
2946  */
2947 static int
2948 re_suspend(device_t dev)
2949 {
2950 #ifndef BURN_BRIDGES
2951         int i;
2952 #endif
2953         struct re_softc *sc = device_get_softc(dev);
2954         struct ifnet *ifp = &sc->arpcom.ac_if;
2955
2956         lwkt_serialize_enter(ifp->if_serializer);
2957
2958         re_stop(sc);
2959
2960 #ifndef BURN_BRIDGES
2961         for (i = 0; i < 5; i++)
2962                 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
2963         sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
2964         sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
2965         sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
2966         sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
2967 #endif
2968
2969         sc->re_flags |= RE_F_SUSPENDED;
2970
2971         lwkt_serialize_exit(ifp->if_serializer);
2972
2973         return (0);
2974 }
2975
2976 /*
2977  * Device resume routine.  Restore some PCI settings in case the BIOS
2978  * doesn't, re-enable busmastering, and restart the interface if
2979  * appropriate.
2980  */
2981 static int
2982 re_resume(device_t dev)
2983 {
2984         struct re_softc *sc = device_get_softc(dev);
2985         struct ifnet *ifp = &sc->arpcom.ac_if;
2986 #ifndef BURN_BRIDGES
2987         int i;
2988 #endif
2989
2990         lwkt_serialize_enter(ifp->if_serializer);
2991
2992 #ifndef BURN_BRIDGES
2993         /* better way to do this? */
2994         for (i = 0; i < 5; i++)
2995                 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
2996         pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
2997         pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
2998         pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
2999         pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
3000
3001         /* reenable busmastering */
3002         pci_enable_busmaster(dev);
3003         pci_enable_io(dev, SYS_RES_IOPORT);
3004 #endif
3005
3006         /* reinitialize interface if necessary */
3007         if (ifp->if_flags & IFF_UP)
3008                 re_init(sc);
3009
3010         sc->re_flags &= ~RE_F_SUSPENDED;
3011
3012         lwkt_serialize_exit(ifp->if_serializer);
3013
3014         return (0);
3015 }
3016
3017 /*
3018  * Stop all chip I/O so that the kernel's probe routines don't
3019  * get confused by errant DMAs when rebooting.
3020  */
3021 static void
3022 re_shutdown(device_t dev)
3023 {
3024         struct re_softc *sc = device_get_softc(dev);
3025         struct ifnet *ifp = &sc->arpcom.ac_if;
3026
3027         lwkt_serialize_enter(ifp->if_serializer);
3028         re_stop(sc);
3029         lwkt_serialize_exit(ifp->if_serializer);
3030 }
3031
3032 static int
3033 re_sysctl_rxtime(SYSCTL_HANDLER_ARGS)
3034 {
3035         struct re_softc *sc = arg1;
3036
3037         return re_sysctl_hwtime(oidp, arg1, arg2, req, &sc->re_rx_time);
3038 }
3039
3040 static int
3041 re_sysctl_txtime(SYSCTL_HANDLER_ARGS)
3042 {
3043         struct re_softc *sc = arg1;
3044
3045         return re_sysctl_hwtime(oidp, arg1, arg2, req, &sc->re_tx_time);
3046 }
3047
3048 static int
3049 re_sysctl_hwtime(SYSCTL_HANDLER_ARGS, int *hwtime)
3050 {
3051         struct re_softc *sc = arg1;
3052         struct ifnet *ifp = &sc->arpcom.ac_if;
3053         int error, v;
3054
3055         lwkt_serialize_enter(ifp->if_serializer);
3056
3057         v = *hwtime;
3058         error = sysctl_handle_int(oidp, &v, 0, req);
3059         if (error || req->newptr == NULL)
3060                 goto back;
3061
3062         if (v <= 0) {
3063                 error = EINVAL;
3064                 goto back;
3065         }
3066
3067         if (v != *hwtime) {
3068                 *hwtime = v;
3069
3070                 if ((ifp->if_flags & (IFF_RUNNING | IFF_POLLING)) ==
3071                     IFF_RUNNING && sc->re_imtype == RE_IMTYPE_HW)
3072                         re_setup_hw_im(sc);
3073         }
3074 back:
3075         lwkt_serialize_exit(ifp->if_serializer);
3076         return error;
3077 }
3078
3079 static int
3080 re_sysctl_simtime(SYSCTL_HANDLER_ARGS)
3081 {
3082         struct re_softc *sc = arg1;
3083         struct ifnet *ifp = &sc->arpcom.ac_if;
3084         int error, v;
3085
3086         lwkt_serialize_enter(ifp->if_serializer);
3087
3088         v = sc->re_sim_time;
3089         error = sysctl_handle_int(oidp, &v, 0, req);
3090         if (error || req->newptr == NULL)
3091                 goto back;
3092
3093         if (v <= 0) {
3094                 error = EINVAL;
3095                 goto back;
3096         }
3097
3098         if (v != sc->re_sim_time) {
3099                 sc->re_sim_time = v;
3100
3101                 if ((ifp->if_flags & (IFF_RUNNING | IFF_POLLING)) ==
3102                     IFF_RUNNING && sc->re_imtype == RE_IMTYPE_SIM) {
3103 #ifdef foo
3104                         int reg;
3105
3106                         /*
3107                          * Following code causes various strange
3108                          * performance problems.  Hmm ...
3109                          */
3110                         CSR_WRITE_2(sc, RE_IMR, 0);
3111                         if (!RE_IS_8139CP(sc))
3112                                 reg = RE_TIMERINT_8169;
3113                         else
3114                                 reg = RE_TIMERINT;
3115                         CSR_WRITE_4(sc, reg, 0);
3116                         CSR_READ_4(sc, reg); /* flush */
3117
3118                         CSR_WRITE_2(sc, RE_IMR, sc->re_intrs);
3119                         re_setup_sim_im(sc);
3120 #else
3121                         re_setup_intr(sc, 0, RE_IMTYPE_NONE);
3122                         DELAY(10);
3123                         re_setup_intr(sc, 1, RE_IMTYPE_SIM);
3124 #endif
3125                 }
3126         }
3127 back:
3128         lwkt_serialize_exit(ifp->if_serializer);
3129         return error;
3130 }
3131
3132 static int
3133 re_sysctl_imtype(SYSCTL_HANDLER_ARGS)
3134 {
3135         struct re_softc *sc = arg1;
3136         struct ifnet *ifp = &sc->arpcom.ac_if;
3137         int error, v;
3138
3139         lwkt_serialize_enter(ifp->if_serializer);
3140
3141         v = sc->re_imtype;
3142         error = sysctl_handle_int(oidp, &v, 0, req);
3143         if (error || req->newptr == NULL)
3144                 goto back;
3145
3146         if (v != RE_IMTYPE_HW && v != RE_IMTYPE_SIM && v != RE_IMTYPE_NONE) {
3147                 error = EINVAL;
3148                 goto back;
3149         }
3150         if (v == RE_IMTYPE_HW && (sc->re_caps & RE_C_HWIM) == 0) {
3151                 /* Can't do hardware interrupt moderation */
3152                 error = EOPNOTSUPP;
3153                 goto back;
3154         }
3155
3156         if (v != sc->re_imtype) {
3157                 sc->re_imtype = v;
3158                 if ((ifp->if_flags & (IFF_RUNNING | IFF_POLLING)) ==
3159                     IFF_RUNNING)
3160                         re_setup_intr(sc, 1, sc->re_imtype);
3161         }
3162 back:
3163         lwkt_serialize_exit(ifp->if_serializer);
3164         return error;
3165 }
3166
3167 static void
3168 re_setup_hw_im(struct re_softc *sc)
3169 {
3170         KKASSERT(sc->re_caps & RE_C_HWIM);
3171
3172         /*
3173          * Interrupt moderation
3174          *
3175          * 0xABCD
3176          * A - unknown (maybe TX related)
3177          * B - TX timer (unit: 25us)
3178          * C - unknown (maybe RX related)
3179          * D - RX timer (unit: 25us)
3180          *
3181          *
3182          * re(4)'s interrupt moderation is actually controlled by
3183          * two variables, like most other NICs (bge, bce etc.)
3184          * o  timer
3185          * o  number of packets [P]
3186          *
3187          * The logic relationship between these two variables is
3188          * similar to other NICs too:
3189          * if (timer expire || packets > [P])
3190          *     Interrupt is delivered
3191          *
3192          * Currently we only know how to set 'timer', but not
3193          * 'number of packets', which should be ~30, as far as I
3194          * tested (sink ~900Kpps, interrupt rate is 30KHz)
3195          */
3196         CSR_WRITE_2(sc, RE_IM,
3197                     RE_IM_RXTIME(sc->re_rx_time) |
3198                     RE_IM_TXTIME(sc->re_tx_time) |
3199                     RE_IM_MAGIC);
3200 }
3201
3202 static void
3203 re_disable_hw_im(struct re_softc *sc)
3204 {
3205         if (sc->re_caps & RE_C_HWIM)
3206                 CSR_WRITE_2(sc, RE_IM, 0);
3207 }
3208
3209 static void
3210 re_setup_sim_im(struct re_softc *sc)
3211 {
3212         if (!RE_IS_8139CP(sc)) {
3213                 uint32_t ticks;
3214
3215                 /*
3216                  * Datasheet says tick decreases at bus speed,
3217                  * but it seems the clock runs a little bit
3218                  * faster, so we do some compensation here.
3219                  */
3220                 ticks = (sc->re_sim_time * sc->re_bus_speed * 8) / 5;
3221                 CSR_WRITE_4(sc, RE_TIMERINT_8169, ticks);
3222         } else {
3223                 CSR_WRITE_4(sc, RE_TIMERINT, 0x400); /* XXX */
3224         }
3225         CSR_WRITE_4(sc, RE_TIMERCNT, 1); /* reload */
3226         sc->re_flags |= RE_F_TIMER_INTR;
3227 }
3228
3229 static void
3230 re_disable_sim_im(struct re_softc *sc)
3231 {
3232         if (!RE_IS_8139CP(sc))
3233                 CSR_WRITE_4(sc, RE_TIMERINT_8169, 0);
3234         else
3235                 CSR_WRITE_4(sc, RE_TIMERINT, 0);
3236         sc->re_flags &= ~RE_F_TIMER_INTR;
3237 }
3238
3239 static void
3240 re_config_imtype(struct re_softc *sc, int imtype)
3241 {
3242         switch (imtype) {
3243         case RE_IMTYPE_HW:
3244                 KKASSERT(sc->re_caps & RE_C_HWIM);
3245                 /* FALL THROUGH */
3246         case RE_IMTYPE_NONE:
3247                 sc->re_intrs = RE_INTRS;
3248                 sc->re_rx_ack = RE_ISR_RX_OK | RE_ISR_FIFO_OFLOW |
3249                                 RE_ISR_RX_OVERRUN;
3250                 sc->re_tx_ack = RE_ISR_TX_OK;
3251                 break;
3252
3253         case RE_IMTYPE_SIM:
3254                 sc->re_intrs = RE_INTRS_TIMER;
3255                 sc->re_rx_ack = RE_ISR_TIMEOUT_EXPIRED;
3256                 sc->re_tx_ack = RE_ISR_TIMEOUT_EXPIRED;
3257                 break;
3258
3259         default:
3260                 panic("%s: unknown imtype %d\n",
3261                       sc->arpcom.ac_if.if_xname, imtype);
3262         }
3263 }
3264
3265 static void
3266 re_setup_intr(struct re_softc *sc, int enable_intrs, int imtype)
3267 {
3268         re_config_imtype(sc, imtype);
3269
3270         if (enable_intrs)
3271                 CSR_WRITE_2(sc, RE_IMR, sc->re_intrs);
3272         else
3273                 CSR_WRITE_2(sc, RE_IMR, 0);
3274
3275         switch (imtype) {
3276         case RE_IMTYPE_NONE:
3277                 re_disable_sim_im(sc);
3278                 re_disable_hw_im(sc);
3279                 break;
3280
3281         case RE_IMTYPE_HW:
3282                 KKASSERT(sc->re_caps & RE_C_HWIM);
3283                 re_disable_sim_im(sc);
3284                 re_setup_hw_im(sc);
3285                 break;
3286
3287         case RE_IMTYPE_SIM:
3288                 re_disable_hw_im(sc);
3289                 re_setup_sim_im(sc);
3290                 break;
3291
3292         default:
3293                 panic("%s: unknown imtype %d\n",
3294                       sc->arpcom.ac_if.if_xname, imtype);
3295         }
3296 }
3297
3298 static void
3299 re_get_eaddr(struct re_softc *sc, uint8_t *eaddr)
3300 {
3301         int i;
3302
3303         if (sc->re_macver == RE_MACVER_11 || sc->re_macver == RE_MACVER_12) {
3304                 uint16_t re_did;
3305
3306                 re_get_eewidth(sc);
3307                 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1);
3308                 if (re_did == 0x8128) {
3309                         uint16_t as[ETHER_ADDR_LEN / 2];
3310
3311                         /*
3312                          * Get station address from the EEPROM.
3313                          */
3314                         re_read_eeprom(sc, (caddr_t)as, RE_EE_EADDR, 3);
3315                         for (i = 0; i < ETHER_ADDR_LEN / 2; i++)
3316                                 as[i] = le16toh(as[i]);
3317                         bcopy(as, eaddr, sizeof(eaddr));
3318                         return;
3319                 }
3320         }
3321
3322         /*
3323          * Get station address from IDRx.
3324          */
3325         for (i = 0; i < ETHER_ADDR_LEN; ++i)
3326                 eaddr[i] = CSR_READ_1(sc, RE_IDR0 + i);
3327 }
3328
3329 static int
3330 re_jpool_alloc(struct re_softc *sc)
3331 {
3332         struct re_list_data *ldata = &sc->re_ldata;
3333         struct re_jbuf *jbuf;
3334         bus_addr_t paddr;
3335         bus_size_t jpool_size;
3336         caddr_t buf;
3337         int i, error;
3338
3339         lwkt_serialize_init(&ldata->re_jbuf_serializer);
3340
3341         ldata->re_jbuf = kmalloc(sizeof(struct re_jbuf) * RE_JBUF_COUNT(sc),
3342                                  M_DEVBUF, M_WAITOK | M_ZERO);
3343
3344         jpool_size = RE_JBUF_COUNT(sc) * RE_JBUF_SIZE;
3345
3346         error = bus_dma_tag_create(sc->re_parent_tag,
3347                         RE_BUF_ALIGN, 0,        /* alignment, boundary */
3348                         BUS_SPACE_MAXADDR_32BIT,/* lowaddr */
3349                         BUS_SPACE_MAXADDR,      /* highaddr */
3350                         NULL, NULL,             /* filter, filterarg */
3351                         jpool_size, 1,          /* nsegments, maxsize */
3352                         BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */
3353                         BUS_DMA_ALLOCNOW,       /* flags */
3354                         &ldata->re_jpool_tag);
3355         if (error) {
3356                 device_printf(sc->re_dev, "could not allocate jumbo dma tag\n");
3357                 return error;
3358         }
3359
3360         error = bus_dmamem_alloc(ldata->re_jpool_tag, (void **)&ldata->re_jpool,
3361                                  BUS_DMA_WAITOK, &ldata->re_jpool_map);
3362         if (error) {
3363                 device_printf(sc->re_dev,
3364                               "could not allocate jumbo dma memory\n");
3365                 bus_dma_tag_destroy(ldata->re_jpool_tag);
3366                 ldata->re_jpool_tag = NULL;
3367                 return error;
3368         }
3369
3370         error = bus_dmamap_load(ldata->re_jpool_tag, ldata->re_jpool_map,
3371                                 ldata->re_jpool, jpool_size,
3372                                 re_dma_map_addr, &paddr, BUS_DMA_WAITOK);
3373         if (error) {
3374                 device_printf(sc->re_dev, "could not load jumbo dma map\n");
3375                 bus_dmamem_free(ldata->re_jpool_tag, ldata->re_jpool,
3376                                 ldata->re_jpool_map);
3377                 bus_dma_tag_destroy(ldata->re_jpool_tag);
3378                 ldata->re_jpool_tag = NULL;
3379                 return error;
3380         }
3381
3382         /* ..and split it into 9KB chunks */
3383         SLIST_INIT(&ldata->re_jbuf_free);
3384
3385         buf = ldata->re_jpool;
3386         for (i = 0; i < RE_JBUF_COUNT(sc); i++) {
3387                 jbuf = &ldata->re_jbuf[i];
3388
3389                 jbuf->re_sc = sc;
3390                 jbuf->re_inuse = 0;
3391                 jbuf->re_slot = i;
3392                 jbuf->re_buf = buf;
3393                 jbuf->re_paddr = paddr;
3394
3395                 SLIST_INSERT_HEAD(&ldata->re_jbuf_free, jbuf, re_link);
3396
3397                 buf += RE_JBUF_SIZE;
3398                 paddr += RE_JBUF_SIZE;
3399         }
3400         return 0;
3401 }
3402
3403 static void
3404 re_jpool_free(struct re_softc *sc)
3405 {
3406         struct re_list_data *ldata = &sc->re_ldata;
3407
3408         if (ldata->re_jpool_tag != NULL) {
3409                 bus_dmamap_unload(ldata->re_jpool_tag, ldata->re_jpool_map);
3410                 bus_dmamem_free(ldata->re_jpool_tag, ldata->re_jpool,
3411                                 ldata->re_jpool_map);
3412                 bus_dma_tag_destroy(ldata->re_jpool_tag);
3413                 ldata->re_jpool_tag = NULL;
3414         }
3415
3416         if (ldata->re_jbuf != NULL) {
3417                 kfree(ldata->re_jbuf, M_DEVBUF);
3418                 ldata->re_jbuf = NULL;
3419         }
3420 }
3421
3422 static struct re_jbuf *
3423 re_jbuf_alloc(struct re_softc *sc)
3424 {
3425         struct re_list_data *ldata = &sc->re_ldata;
3426         struct re_jbuf *jbuf;
3427
3428         lwkt_serialize_enter(&ldata->re_jbuf_serializer);
3429
3430         jbuf = SLIST_FIRST(&ldata->re_jbuf_free);
3431         if (jbuf != NULL) {
3432                 SLIST_REMOVE_HEAD(&ldata->re_jbuf_free, re_link);
3433                 jbuf->re_inuse = 1;
3434         }
3435
3436         lwkt_serialize_exit(&ldata->re_jbuf_serializer);
3437
3438         return jbuf;
3439 }
3440
3441 static void
3442 re_jbuf_free(void *arg)
3443 {
3444         struct re_jbuf *jbuf = arg;
3445         struct re_softc *sc = jbuf->re_sc;
3446         struct re_list_data *ldata = &sc->re_ldata;
3447
3448         if (&ldata->re_jbuf[jbuf->re_slot] != jbuf) {
3449                 panic("%s: free wrong jumbo buffer\n",
3450                       sc->arpcom.ac_if.if_xname);
3451         } else if (jbuf->re_inuse == 0) {
3452                 panic("%s: jumbo buffer already freed\n",
3453                       sc->arpcom.ac_if.if_xname);
3454         }
3455
3456         lwkt_serialize_enter(&ldata->re_jbuf_serializer);
3457         atomic_subtract_int(&jbuf->re_inuse, 1);
3458         if (jbuf->re_inuse == 0)
3459                 SLIST_INSERT_HEAD(&ldata->re_jbuf_free, jbuf, re_link);
3460         lwkt_serialize_exit(&ldata->re_jbuf_serializer);
3461 }
3462
3463 static void
3464 re_jbuf_ref(void *arg)
3465 {
3466         struct re_jbuf *jbuf = arg;
3467         struct re_softc *sc = jbuf->re_sc;
3468         struct re_list_data *ldata = &sc->re_ldata;
3469
3470         if (&ldata->re_jbuf[jbuf->re_slot] != jbuf) {
3471                 panic("%s: ref wrong jumbo buffer\n",
3472                       sc->arpcom.ac_if.if_xname);
3473         } else if (jbuf->re_inuse == 0) {
3474                 panic("%s: jumbo buffer already freed\n",
3475                       sc->arpcom.ac_if.if_xname);
3476         }
3477         atomic_add_int(&jbuf->re_inuse, 1);
3478 }