sys/dev/netif/ig_hal/e1000_82571.c

   1 /******************************************************************************
   2
   3   Copyright (c) 2001-2008, Intel Corporation
   4   All rights reserved.
   5
   6   Redistribution and use in source and binary forms, with or without
   7   modification, are permitted provided that the following conditions are met:
   8
   9    1. Redistributions of source code must retain the above copyright notice,
  10       this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in the
  14       documentation and/or other materials provided with the distribution.
  15
  16    3. Neither the name of the Intel Corporation nor the names of its
  17       contributors may be used to endorse or promote products derived from
  18       this software without specific prior written permission.
  19
  20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30   POSSIBILITY OF SUCH DAMAGE.
  31
  32 ******************************************************************************/
  33 /*$FreeBSD$*/
  34
  35 /*
  36  * 82571EB Gigabit Ethernet Controller
  37  * 82571EB Gigabit Ethernet Controller (Copper)
  38  * 82571EB Gigabit Ethernet Controller (Fiber)
  39  * 82571EB Dual Port Gigabit Mezzanine Adapter
  40  * 82571EB Quad Port Gigabit Mezzanine Adapter
  41  * 82571PT Gigabit PT Quad Port Server ExpressModule
  42  * 82572EI Gigabit Ethernet Controller (Copper)
  43  * 82572EI Gigabit Ethernet Controller (Fiber)
  44  * 82572EI Gigabit Ethernet Controller
  45  * 82573V Gigabit Ethernet Controller (Copper)
  46  * 82573E Gigabit Ethernet Controller (Copper)
  47  * 82573L Gigabit Ethernet Controller
  48  * 82574L Gigabit Network Connection
  49  */
  50
  51 #include "e1000_api.h"
  52
  53 static s32  e1000_init_phy_params_82571(struct e1000_hw *hw);
  54 static s32  e1000_init_nvm_params_82571(struct e1000_hw *hw);
  55 static s32  e1000_init_mac_params_82571(struct e1000_hw *hw);
  56 static s32  e1000_acquire_nvm_82571(struct e1000_hw *hw);
  57 static void e1000_release_nvm_82571(struct e1000_hw *hw);
  58 static s32  e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset,
  59                                   u16 words, u16 *data);
  60 static s32  e1000_update_nvm_checksum_82571(struct e1000_hw *hw);
  61 static s32  e1000_validate_nvm_checksum_82571(struct e1000_hw *hw);
  62 static s32  e1000_get_cfg_done_82571(struct e1000_hw *hw);
  63 static s32  e1000_set_d0_lplu_state_82571(struct e1000_hw *hw,
  64                                           bool active);
  65 static s32  e1000_reset_hw_82571(struct e1000_hw *hw);
  66 static s32  e1000_init_hw_82571(struct e1000_hw *hw);
  67 static void e1000_clear_vfta_82571(struct e1000_hw *hw);
  68 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
  69 static s32 e1000_led_on_82574(struct e1000_hw *hw);
  70 static void e1000_update_mc_addr_list_82571(struct e1000_hw *hw,
  71                                            u8 *mc_addr_list, u32 mc_addr_count,
  72                                            u32 rar_used_count, u32 rar_count);
  73 static s32  e1000_setup_link_82571(struct e1000_hw *hw);
  74 static s32  e1000_setup_copper_link_82571(struct e1000_hw *hw);
  75 static s32  e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
  76 static s32  e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data);
  77 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
  78 static s32  e1000_get_hw_semaphore_82571(struct e1000_hw *hw);
  79 static s32  e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
  80 static s32  e1000_get_phy_id_82571(struct e1000_hw *hw);
  81 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
  82 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
  83 static s32  e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
  84                                        u16 words, u16 *data);
  85 static s32  e1000_read_mac_addr_82571(struct e1000_hw *hw);
  86 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
  87
  88 /**
  89  *  e1000_init_phy_params_82571 - Init PHY func ptrs.
  90  *  @hw: pointer to the HW structure
  91  **/
  92 static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
  93 {
  94         struct e1000_phy_info *phy = &hw->phy;
  95         s32 ret_val = E1000_SUCCESS;
  96
  97         DEBUGFUNC("e1000_init_phy_params_82571");
  98
  99         if (hw->phy.media_type != e1000_media_type_copper) {
 100                 phy->type = e1000_phy_none;
 101                 goto out;
 102         }
 103
 104         phy->addr                        = 1;
 105         phy->autoneg_mask                = AUTONEG_ADVERTISE_SPEED_DEFAULT;
 106         phy->reset_delay_us              = 100;
 107
 108         phy->ops.acquire                 = e1000_get_hw_semaphore_82571;
 109         phy->ops.check_polarity          = e1000_check_polarity_igp;
 110         phy->ops.check_reset_block       = e1000_check_reset_block_generic;
 111         phy->ops.release                 = e1000_put_hw_semaphore_82571;
 112         phy->ops.reset                   = e1000_phy_hw_reset_generic;
 113         phy->ops.set_d0_lplu_state       = e1000_set_d0_lplu_state_82571;
 114         phy->ops.set_d3_lplu_state       = e1000_set_d3_lplu_state_generic;
 115         phy->ops.power_up                = e1000_power_up_phy_copper;
 116         phy->ops.power_down              = e1000_power_down_phy_copper_82571;
 117
 118         switch (hw->mac.type) {
 119         case e1000_82571:
 120         case e1000_82572:
 121                 phy->type                   = e1000_phy_igp_2;
 122                 phy->ops.get_cfg_done       = e1000_get_cfg_done_82571;
 123                 phy->ops.get_info           = e1000_get_phy_info_igp;
 124                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
 125                 phy->ops.get_cable_length   = e1000_get_cable_length_igp_2;
 126                 phy->ops.read_reg           = e1000_read_phy_reg_igp;
 127                 phy->ops.write_reg          = e1000_write_phy_reg_igp;
 128
 129                 /* This uses above function pointers */
 130                 ret_val = e1000_get_phy_id_82571(hw);
 131
 132                 /* Verify PHY ID */
 133                 if (phy->id != IGP01E1000_I_PHY_ID) {
 134                         ret_val = -E1000_ERR_PHY;
 135                         goto out;
 136                 }
 137                 break;
 138         case e1000_82573:
 139                 phy->type                   = e1000_phy_m88;
 140                 phy->ops.get_cfg_done       = e1000_get_cfg_done_generic;
 141                 phy->ops.get_info           = e1000_get_phy_info_m88;
 142                 phy->ops.commit             = e1000_phy_sw_reset_generic;
 143                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 144                 phy->ops.get_cable_length   = e1000_get_cable_length_m88;
 145                 phy->ops.read_reg           = e1000_read_phy_reg_m88;
 146                 phy->ops.write_reg          = e1000_write_phy_reg_m88;
 147
 148                 /* This uses above function pointers */
 149                 ret_val = e1000_get_phy_id_82571(hw);
 150
 151                 /* Verify PHY ID */
 152                 if (phy->id != M88E1111_I_PHY_ID) {
 153                         ret_val = -E1000_ERR_PHY;
 154                         DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id);
 155                         goto out;
 156                 }
 157                 break;
 158         case e1000_82574:
 159                 phy->type                   = e1000_phy_bm;
 160                 phy->ops.get_cfg_done       = e1000_get_cfg_done_generic;
 161                 phy->ops.get_info           = e1000_get_phy_info_m88;
 162                 phy->ops.commit             = e1000_phy_sw_reset_generic;
 163                 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
 164                 phy->ops.get_cable_length   = e1000_get_cable_length_m88;
 165                 phy->ops.read_reg           = e1000_read_phy_reg_bm2;
 166                 phy->ops.write_reg          = e1000_write_phy_reg_bm2;
 167
 168                 /* This uses above function pointers */
 169                 ret_val = e1000_get_phy_id_82571(hw);
 170                 /* Verify PHY ID */
 171                 if (phy->id != BME1000_E_PHY_ID_R2) {
 172                         ret_val = -E1000_ERR_PHY;
 173                         DEBUGOUT1("PHY ID unknown: type = 0x%08x\n", phy->id);
 174                         goto out;
 175                 }
 176                 break;
 177         default:
 178                 ret_val = -E1000_ERR_PHY;
 179                 goto out;
 180                 break;
 181         }
 182
 183 out:
 184         return ret_val;
 185 }
 186
 187 /**
 188  *  e1000_init_nvm_params_82571 - Init NVM func ptrs.
 189  *  @hw: pointer to the HW structure
 190  **/
 191 static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
 192 {
 193         struct e1000_nvm_info *nvm = &hw->nvm;
 194         u32 eecd = E1000_READ_REG(hw, E1000_EECD);
 195         u16 size;
 196
 197         DEBUGFUNC("e1000_init_nvm_params_82571");
 198
 199         nvm->opcode_bits = 8;
 200         nvm->delay_usec = 1;
 201         switch (nvm->override) {
 202         case e1000_nvm_override_spi_large:
 203                 nvm->page_size = 32;
 204                 nvm->address_bits = 16;
 205                 break;
 206         case e1000_nvm_override_spi_small:
 207                 nvm->page_size = 8;
 208                 nvm->address_bits = 8;
 209                 break;
 210         default:
 211                 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
 212                 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
 213                 break;
 214         }
 215
 216         switch (hw->mac.type) {
 217         case e1000_82573:
 218         case e1000_82574:
 219                 if (((eecd >> 15) & 0x3) == 0x3) {
 220                         nvm->type = e1000_nvm_flash_hw;
 221                         nvm->word_size = 2048;
 222                         /*
 223                          * Autonomous Flash update bit must be cleared due
 224                          * to Flash update issue.
 225                          */
 226                         eecd &= ~E1000_EECD_AUPDEN;
 227                         E1000_WRITE_REG(hw, E1000_EECD, eecd);
 228                         break;
 229                 }
 230                 /* Fall Through */
 231         default:
 232                 nvm->type = e1000_nvm_eeprom_spi;
 233                 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
 234                                   E1000_EECD_SIZE_EX_SHIFT);
 235                 /*
 236                  * Added to a constant, "size" becomes the left-shift value
 237                  * for setting word_size.
 238                  */
 239                 size += NVM_WORD_SIZE_BASE_SHIFT;
 240
 241                 /* EEPROM access above 16k is unsupported */
 242                 if (size > 14)
 243                         size = 14;
 244                 nvm->word_size  = 1 << size;
 245                 break;
 246         }
 247
 248         /* Function Pointers */
 249         nvm->ops.acquire       = e1000_acquire_nvm_82571;
 250         nvm->ops.read          = e1000_read_nvm_eerd;
 251         nvm->ops.release       = e1000_release_nvm_82571;
 252         nvm->ops.update        = e1000_update_nvm_checksum_82571;
 253         nvm->ops.validate      = e1000_validate_nvm_checksum_82571;
 254         nvm->ops.valid_led_default = e1000_valid_led_default_82571;
 255         nvm->ops.write         = e1000_write_nvm_82571;
 256
 257         return E1000_SUCCESS;
 258 }
 259
 260 /**
 261  *  e1000_init_mac_params_82571 - Init MAC func ptrs.
 262  *  @hw: pointer to the HW structure
 263  **/
 264 static s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
 265 {
 266         struct e1000_mac_info *mac = &hw->mac;
 267         s32 ret_val = E1000_SUCCESS;
 268
 269         DEBUGFUNC("e1000_init_mac_params_82571");
 270
 271         /* Set media type */
 272         switch (hw->device_id) {
 273         case E1000_DEV_ID_82571EB_FIBER:
 274         case E1000_DEV_ID_82572EI_FIBER:
 275         case E1000_DEV_ID_82571EB_QUAD_FIBER:
 276                 hw->phy.media_type = e1000_media_type_fiber;
 277                 break;
 278         case E1000_DEV_ID_82571EB_SERDES:
 279         case E1000_DEV_ID_82571EB_SERDES_DUAL:
 280         case E1000_DEV_ID_82571EB_SERDES_QUAD:
 281         case E1000_DEV_ID_82572EI_SERDES:
 282                 hw->phy.media_type = e1000_media_type_internal_serdes;
 283                 break;
 284         default:
 285                 hw->phy.media_type = e1000_media_type_copper;
 286                 break;
 287         }
 288
 289         /* Set mta register count */
 290         mac->mta_reg_count = 128;
 291         /* Set rar entry count */
 292         mac->rar_entry_count = E1000_RAR_ENTRIES;
 293         /* Set if part includes ASF firmware */
 294         mac->asf_firmware_present = TRUE;
 295         /* Set if manageability features are enabled. */
 296         mac->arc_subsystem_valid =
 297                 (E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK)
 298                         ? TRUE : FALSE;
 299
 300         /* Function pointers */
 301
 302         /* bus type/speed/width */
 303         mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
 304         /* function id */
 305         switch (hw->mac.type) {
 306         case e1000_82573:
 307         case e1000_82574:
 308                 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
 309                 break;
 310         default:
 311                 break;
 312         }
 313         /* reset */
 314         mac->ops.reset_hw = e1000_reset_hw_82571;
 315         /* hw initialization */
 316         mac->ops.init_hw = e1000_init_hw_82571;
 317         /* link setup */
 318         mac->ops.setup_link = e1000_setup_link_82571;
 319         /* physical interface link setup */
 320         mac->ops.setup_physical_interface =
 321                 (hw->phy.media_type == e1000_media_type_copper)
 322                         ? e1000_setup_copper_link_82571
 323                         : e1000_setup_fiber_serdes_link_82571;
 324         /* check for link */
 325         switch (hw->phy.media_type) {
 326         case e1000_media_type_copper:
 327                 mac->ops.check_for_link = e1000_check_for_copper_link_generic;
 328                 break;
 329         case e1000_media_type_fiber:
 330                 mac->ops.check_for_link = e1000_check_for_fiber_link_generic;
 331                 break;
 332         case e1000_media_type_internal_serdes:
 333                 mac->ops.check_for_link = e1000_check_for_serdes_link_generic;
 334                 break;
 335         default:
 336                 ret_val = -E1000_ERR_CONFIG;
 337                 goto out;
 338                 break;
 339         }
 340         /* check management mode */
 341         switch (hw->mac.type) {
 342         case e1000_82574:
 343                 mac->ops.check_mng_mode = e1000_check_mng_mode_82574;
 344                 break;
 345         default:
 346                 mac->ops.check_mng_mode = e1000_check_mng_mode_generic;
 347                 break;
 348         }
 349         /* multicast address update */
 350         mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_82571;
 351         /* writing VFTA */
 352         mac->ops.write_vfta = e1000_write_vfta_generic;
 353         /* clearing VFTA */
 354         mac->ops.clear_vfta = e1000_clear_vfta_82571;
 355         /* setting MTA */
 356         mac->ops.mta_set = e1000_mta_set_generic;
 357         /* read mac address */
 358         mac->ops.read_mac_addr = e1000_read_mac_addr_82571;
 359         /* blink LED */
 360         mac->ops.blink_led = e1000_blink_led_generic;
 361         /* setup LED */
 362         mac->ops.setup_led = e1000_setup_led_generic;
 363         /* cleanup LED */
 364         mac->ops.cleanup_led = e1000_cleanup_led_generic;
 365         /* turn on/off LED */
 366         switch (hw->mac.type) {
 367         case e1000_82574:
 368                 mac->ops.led_on = e1000_led_on_82574;
 369                 break;
 370         default:
 371                 mac->ops.led_on = e1000_led_on_generic;
 372                 break;
 373         }
 374         mac->ops.led_off = e1000_led_off_generic;
 375         /* clear hardware counters */
 376         mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82571;
 377         /* link info */
 378         mac->ops.get_link_up_info =
 379                 (hw->phy.media_type == e1000_media_type_copper)
 380                         ? e1000_get_speed_and_duplex_copper_generic
 381                         : e1000_get_speed_and_duplex_fiber_serdes_generic;
 382
 383 out:
 384         return ret_val;
 385 }
 386
 387 /**
 388  *  e1000_init_function_pointers_82571 - Init func ptrs.
 389  *  @hw: pointer to the HW structure
 390  *
 391  *  Called to initialize all function pointers and parameters.
 392  **/
 393 void e1000_init_function_pointers_82571(struct e1000_hw *hw)
 394 {
 395         DEBUGFUNC("e1000_init_function_pointers_82571");
 396
 397         hw->mac.ops.init_params = e1000_init_mac_params_82571;
 398         hw->nvm.ops.init_params = e1000_init_nvm_params_82571;
 399         hw->phy.ops.init_params = e1000_init_phy_params_82571;
 400 }
 401
 402 /**
 403  *  e1000_get_phy_id_82571 - Retrieve the PHY ID and revision
 404  *  @hw: pointer to the HW structure
 405  *
 406  *  Reads the PHY registers and stores the PHY ID and possibly the PHY
 407  *  revision in the hardware structure.
 408  **/
 409 static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
 410 {
 411         struct e1000_phy_info *phy = &hw->phy;
 412         s32 ret_val = E1000_SUCCESS;
 413         u16 phy_id = 0;
 414
 415         DEBUGFUNC("e1000_get_phy_id_82571");
 416
 417         switch (hw->mac.type) {
 418         case e1000_82571:
 419         case e1000_82572:
 420                 /*
 421                  * The 82571 firmware may still be configuring the PHY.
 422                  * In this case, we cannot access the PHY until the
 423                  * configuration is done.  So we explicitly set the
 424                  * PHY ID.
 425                  */
 426                 phy->id = IGP01E1000_I_PHY_ID;
 427                 break;
 428         case e1000_82573:
 429                 ret_val = e1000_get_phy_id(hw);
 430                 break;
 431         case e1000_82574:
 432                 ret_val = phy->ops.read_reg(hw, PHY_ID1, &phy_id);
 433                 if (ret_val)
 434                         goto out;
 435
 436                 phy->id = (u32)(phy_id << 16);
 437                 usec_delay(20);
 438                 ret_val = phy->ops.read_reg(hw, PHY_ID2, &phy_id);
 439                 if (ret_val)
 440                         goto out;
 441
 442                 phy->id |= (u32)(phy_id);
 443                 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
 444                 break;
 445         default:
 446                 ret_val = -E1000_ERR_PHY;
 447                 break;
 448         }
 449
 450 out:
 451         return ret_val;
 452 }
 453
 454 /**
 455  *  e1000_get_hw_semaphore_82571 - Acquire hardware semaphore
 456  *  @hw: pointer to the HW structure
 457  *
 458  *  Acquire the HW semaphore to access the PHY or NVM
 459  **/
 460 static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
 461 {
 462         u32 swsm;
 463         s32 ret_val = E1000_SUCCESS;
 464         s32 timeout = hw->nvm.word_size + 1;
 465         s32 i = 0;
 466
 467         DEBUGFUNC("e1000_get_hw_semaphore_82571");
 468
 469         /* Get the FW semaphore. */
 470         for (i = 0; i < timeout; i++) {
 471                 swsm = E1000_READ_REG(hw, E1000_SWSM);
 472                 E1000_WRITE_REG(hw, E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
 473
 474                 /* Semaphore acquired if bit latched */
 475                 if (E1000_READ_REG(hw, E1000_SWSM) & E1000_SWSM_SWESMBI)
 476                         break;
 477
 478                 usec_delay(50);
 479         }
 480
 481         if (i == timeout) {
 482                 /* Release semaphores */
 483                 e1000_put_hw_semaphore_generic(hw);
 484                 DEBUGOUT("Driver can't access the NVM\n");
 485                 ret_val = -E1000_ERR_NVM;
 486                 goto out;
 487         }
 488
 489 out:
 490         return ret_val;
 491 }
 492
 493 /**
 494  *  e1000_put_hw_semaphore_82571 - Release hardware semaphore
 495  *  @hw: pointer to the HW structure
 496  *
 497  *  Release hardware semaphore used to access the PHY or NVM
 498  **/
 499 static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
 500 {
 501         u32 swsm;
 502
 503         DEBUGFUNC("e1000_put_hw_semaphore_82571");
 504
 505         swsm = E1000_READ_REG(hw, E1000_SWSM);
 506
 507         swsm &= ~E1000_SWSM_SWESMBI;
 508
 509         E1000_WRITE_REG(hw, E1000_SWSM, swsm);
 510 }
 511
 512 /**
 513  *  e1000_acquire_nvm_82571 - Request for access to the EEPROM
 514  *  @hw: pointer to the HW structure
 515  *
 516  *  To gain access to the EEPROM, first we must obtain a hardware semaphore.
 517  *  Then for non-82573 hardware, set the EEPROM access request bit and wait
 518  *  for EEPROM access grant bit.  If the access grant bit is not set, release
 519  *  hardware semaphore.
 520  **/
 521 static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
 522 {
 523         s32 ret_val;
 524
 525         DEBUGFUNC("e1000_acquire_nvm_82571");
 526
 527         ret_val = e1000_get_hw_semaphore_82571(hw);
 528         if (ret_val)
 529                 goto out;
 530
 531         if (hw->mac.type != e1000_82573 && hw->mac.type != e1000_82574)
 532                 ret_val = e1000_acquire_nvm_generic(hw);
 533
 534         if (ret_val)
 535                 e1000_put_hw_semaphore_82571(hw);
 536
 537 out:
 538         return ret_val;
 539 }
 540
 541 /**
 542  *  e1000_release_nvm_82571 - Release exclusive access to EEPROM
 543  *  @hw: pointer to the HW structure
 544  *
 545  *  Stop any current commands to the EEPROM and clear the EEPROM request bit.
 546  **/
 547 static void e1000_release_nvm_82571(struct e1000_hw *hw)
 548 {
 549         DEBUGFUNC("e1000_release_nvm_82571");
 550
 551         e1000_release_nvm_generic(hw);
 552         e1000_put_hw_semaphore_82571(hw);
 553 }
 554
 555 /**
 556  *  e1000_write_nvm_82571 - Write to EEPROM using appropriate interface
 557  *  @hw: pointer to the HW structure
 558  *  @offset: offset within the EEPROM to be written to
 559  *  @words: number of words to write
 560  *  @data: 16 bit word(s) to be written to the EEPROM
 561  *
 562  *  For non-82573 silicon, write data to EEPROM at offset using SPI interface.
 563  *
 564  *  If e1000_update_nvm_checksum is not called after this function, the
 565  *  EEPROM will most likely contain an invalid checksum.
 566  **/
 567 static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
 568                                  u16 *data)
 569 {
 570         s32 ret_val = E1000_SUCCESS;
 571
 572         DEBUGFUNC("e1000_write_nvm_82571");
 573
 574         switch (hw->mac.type) {
 575         case e1000_82573:
 576         case e1000_82574:
 577                 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
 578                 break;
 579         case e1000_82571:
 580         case e1000_82572:
 581                 ret_val = e1000_write_nvm_spi(hw, offset, words, data);
 582                 break;
 583         default:
 584                 ret_val = -E1000_ERR_NVM;
 585                 break;
 586         }
 587
 588         return ret_val;
 589 }
 590
 591 /**
 592  *  e1000_update_nvm_checksum_82571 - Update EEPROM checksum
 593  *  @hw: pointer to the HW structure
 594  *
 595  *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
 596  *  up to the checksum.  Then calculates the EEPROM checksum and writes the
 597  *  value to the EEPROM.
 598  **/
 599 static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
 600 {
 601         u32 eecd;
 602         s32 ret_val;
 603         u16 i;
 604
 605         DEBUGFUNC("e1000_update_nvm_checksum_82571");
 606
 607         ret_val = e1000_update_nvm_checksum_generic(hw);
 608         if (ret_val)
 609                 goto out;
 610
 611         /*
 612          * If our nvm is an EEPROM, then we're done
 613          * otherwise, commit the checksum to the flash NVM.
 614          */
 615         if (hw->nvm.type != e1000_nvm_flash_hw)
 616                 goto out;
 617
 618         /* Check for pending operations. */
 619         for (i = 0; i < E1000_FLASH_UPDATES; i++) {
 620                 msec_delay(1);
 621                 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0)
 622                         break;
 623         }
 624
 625         if (i == E1000_FLASH_UPDATES) {
 626                 ret_val = -E1000_ERR_NVM;
 627                 goto out;
 628         }
 629
 630         /* Reset the firmware if using STM opcode. */
 631         if ((E1000_READ_REG(hw, E1000_FLOP) & 0xFF00) == E1000_STM_OPCODE) {
 632                 /*
 633                  * The enabling of and the actual reset must be done
 634                  * in two write cycles.
 635                  */
 636                 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET_ENABLE);
 637                 E1000_WRITE_FLUSH(hw);
 638                 E1000_WRITE_REG(hw, E1000_HICR, E1000_HICR_FW_RESET);
 639         }
 640
 641         /* Commit the write to flash */
 642         eecd = E1000_READ_REG(hw, E1000_EECD) | E1000_EECD_FLUPD;
 643         E1000_WRITE_REG(hw, E1000_EECD, eecd);
 644
 645         for (i = 0; i < E1000_FLASH_UPDATES; i++) {
 646                 msec_delay(1);
 647                 if ((E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_FLUPD) == 0)
 648                         break;
 649         }
 650
 651         if (i == E1000_FLASH_UPDATES) {
 652                 ret_val = -E1000_ERR_NVM;
 653                 goto out;
 654         }
 655
 656 out:
 657         return ret_val;
 658 }
 659
 660 /**
 661  *  e1000_validate_nvm_checksum_82571 - Validate EEPROM checksum
 662  *  @hw: pointer to the HW structure
 663  *
 664  *  Calculates the EEPROM checksum by reading/adding each word of the EEPROM
 665  *  and then verifies that the sum of the EEPROM is equal to 0xBABA.
 666  **/
 667 static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
 668 {
 669         DEBUGFUNC("e1000_validate_nvm_checksum_82571");
 670
 671         if (hw->nvm.type == e1000_nvm_flash_hw)
 672                 e1000_fix_nvm_checksum_82571(hw);
 673
 674         return e1000_validate_nvm_checksum_generic(hw);
 675 }
 676
 677 /**
 678  *  e1000_write_nvm_eewr_82571 - Write to EEPROM for 82573 silicon
 679  *  @hw: pointer to the HW structure
 680  *  @offset: offset within the EEPROM to be written to
 681  *  @words: number of words to write
 682  *  @data: 16 bit word(s) to be written to the EEPROM
 683  *
 684  *  After checking for invalid values, poll the EEPROM to ensure the previous
 685  *  command has completed before trying to write the next word.  After write
 686  *  poll for completion.
 687  *
 688  *  If e1000_update_nvm_checksum is not called after this function, the
 689  *  EEPROM will most likely contain an invalid checksum.
 690  **/
 691 static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
 692                                       u16 words, u16 *data)
 693 {
 694         struct e1000_nvm_info *nvm = &hw->nvm;
 695         u32 i, eewr = 0;
 696         s32 ret_val = 0;
 697
 698         DEBUGFUNC("e1000_write_nvm_eewr_82571");
 699
 700         /*
 701          * A check for invalid values:  offset too large, too many words,
 702          * and not enough words.
 703          */
 704         if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
 705             (words == 0)) {
 706                 DEBUGOUT("nvm parameter(s) out of bounds\n");
 707                 ret_val = -E1000_ERR_NVM;
 708                 goto out;
 709         }
 710
 711         for (i = 0; i < words; i++) {
 712                 eewr = (data[i] << E1000_NVM_RW_REG_DATA) |
 713                        ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) |
 714                        E1000_NVM_RW_REG_START;
 715
 716                 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
 717                 if (ret_val)
 718                         break;
 719
 720                 E1000_WRITE_REG(hw, E1000_EEWR, eewr);
 721
 722                 ret_val = e1000_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
 723                 if (ret_val)
 724                         break;
 725         }
 726
 727 out:
 728         return ret_val;
 729 }
 730
 731 /**
 732  *  e1000_get_cfg_done_82571 - Poll for configuration done
 733  *  @hw: pointer to the HW structure
 734  *
 735  *  Reads the management control register for the config done bit to be set.
 736  **/
 737 static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
 738 {
 739         s32 timeout = PHY_CFG_TIMEOUT;
 740         s32 ret_val = E1000_SUCCESS;
 741
 742         DEBUGFUNC("e1000_get_cfg_done_82571");
 743
 744         while (timeout) {
 745                 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & E1000_NVM_CFG_DONE_PORT_0)
 746                         break;
 747                 msec_delay(1);
 748                 timeout--;
 749         }
 750         if (!timeout) {
 751                 DEBUGOUT("MNG configuration cycle has not completed.\n");
 752                 ret_val = -E1000_ERR_RESET;
 753                 goto out;
 754         }
 755
 756 out:
 757         return ret_val;
 758 }
 759
 760 /**
 761  *  e1000_set_d0_lplu_state_82571 - Set Low Power Linkup D0 state
 762  *  @hw: pointer to the HW structure
 763  *  @active: TRUE to enable LPLU, FALSE to disable
 764  *
 765  *  Sets the LPLU D0 state according to the active flag.  When activating LPLU
 766  *  this function also disables smart speed and vice versa.  LPLU will not be
 767  *  activated unless the device autonegotiation advertisement meets standards
 768  *  of either 10 or 10/100 or 10/100/1000 at all duplexes.  This is a function
 769  *  pointer entry point only called by PHY setup routines.
 770  **/
 771 static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
 772 {
 773         struct e1000_phy_info *phy = &hw->phy;
 774         s32 ret_val = E1000_SUCCESS;
 775         u16 data;
 776
 777         DEBUGFUNC("e1000_set_d0_lplu_state_82571");
 778
 779         if (!(phy->ops.read_reg))
 780                 goto out;
 781
 782         ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
 783         if (ret_val)
 784                 goto out;
 785
 786         if (active) {
 787                 data |= IGP02E1000_PM_D0_LPLU;
 788                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 789                                              data);
 790                 if (ret_val)
 791                         goto out;
 792
 793                 /* When LPLU is enabled, we should disable SmartSpeed */
 794                 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 795                                             &data);
 796                 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 797                 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
 798                                              data);
 799                 if (ret_val)
 800                         goto out;
 801         } else {
 802                 data &= ~IGP02E1000_PM_D0_LPLU;
 803                 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
 804                                              data);
 805                 /*
 806                  * LPLU and SmartSpeed are mutually exclusive.  LPLU is used
 807                  * during Dx states where the power conservation is most
 808                  * important.  During driver activity we should enable
 809                  * SmartSpeed, so performance is maintained.
 810                  */
 811                 if (phy->smart_speed == e1000_smart_speed_on) {
 812                         ret_val = phy->ops.read_reg(hw,
 813                                                     IGP01E1000_PHY_PORT_CONFIG,
 814                                                     &data);
 815                         if (ret_val)
 816                                 goto out;
 817
 818                         data |= IGP01E1000_PSCFR_SMART_SPEED;
 819                         ret_val = phy->ops.write_reg(hw,
 820                                                      IGP01E1000_PHY_PORT_CONFIG,
 821                                                      data);
 822                         if (ret_val)
 823                                 goto out;
 824                 } else if (phy->smart_speed == e1000_smart_speed_off) {
 825                         ret_val = phy->ops.read_reg(hw,
 826                                                     IGP01E1000_PHY_PORT_CONFIG,
 827                                                     &data);
 828                         if (ret_val)
 829                                 goto out;
 830
 831                         data &= ~IGP01E1000_PSCFR_SMART_SPEED;
 832                         ret_val = phy->ops.write_reg(hw,
 833                                                      IGP01E1000_PHY_PORT_CONFIG,
 834                                                      data);
 835                         if (ret_val)
 836                                 goto out;
 837                 }
 838         }
 839
 840 out:
 841         return ret_val;
 842 }
 843
 844 /**
 845  *  e1000_reset_hw_82571 - Reset hardware
 846  *  @hw: pointer to the HW structure
 847  *
 848  *  This resets the hardware into a known state.
 849  **/
 850 static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
 851 {
 852         u32 ctrl, extcnf_ctrl, ctrl_ext, icr;
 853         s32 ret_val;
 854         u16 i = 0;
 855
 856         DEBUGFUNC("e1000_reset_hw_82571");
 857
 858         /*
 859          * Prevent the PCI-E bus from sticking if there is no TLP connection
 860          * on the last TLP read/write transaction when MAC is reset.
 861          */
 862         ret_val = e1000_disable_pcie_master_generic(hw);
 863         if (ret_val)
 864                 DEBUGOUT("PCI-E Master disable polling has failed.\n");
 865
 866         DEBUGOUT("Masking off all interrupts\n");
 867         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
 868
 869         E1000_WRITE_REG(hw, E1000_RCTL, 0);
 870         E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
 871         E1000_WRITE_FLUSH(hw);
 872
 873         msec_delay(10);
 874
 875         /*
 876          * Must acquire the MDIO ownership before MAC reset.
 877          * Ownership defaults to firmware after a reset.
 878          */
 879         if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) {
 880                 extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
 881                 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 882
 883                 do {
 884                         E1000_WRITE_REG(hw, E1000_EXTCNF_CTRL, extcnf_ctrl);
 885                         extcnf_ctrl = E1000_READ_REG(hw, E1000_EXTCNF_CTRL);
 886
 887                         if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
 888                                 break;
 889
 890                         extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
 891
 892                         msec_delay(2);
 893                         i++;
 894                 } while (i < MDIO_OWNERSHIP_TIMEOUT);
 895         }
 896
 897         ctrl = E1000_READ_REG(hw, E1000_CTRL);
 898
 899         DEBUGOUT("Issuing a global reset to MAC\n");
 900         E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
 901
 902         if (hw->nvm.type == e1000_nvm_flash_hw) {
 903                 usec_delay(10);
 904                 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
 905                 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
 906                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
 907                 E1000_WRITE_FLUSH(hw);
 908         }
 909
 910         ret_val = e1000_get_auto_rd_done_generic(hw);
 911         if (ret_val)
 912                 /* We don't want to continue accessing MAC registers. */
 913                 goto out;
 914
 915         /*
 916          * Phy configuration from NVM just starts after EECD_AUTO_RD is set.
 917          * Need to wait for Phy configuration completion before accessing
 918          * NVM and Phy.
 919          */
 920         if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574)
 921                 msec_delay(25);
 922
 923         /* Clear any pending interrupt events. */
 924         E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
 925         icr = E1000_READ_REG(hw, E1000_ICR);
 926
 927         if (!(e1000_check_alt_mac_addr_generic(hw)))
 928                 e1000_set_laa_state_82571(hw, TRUE);
 929
 930 out:
 931         return ret_val;
 932 }
 933
 934 /**
 935  *  e1000_init_hw_82571 - Initialize hardware
 936  *  @hw: pointer to the HW structure
 937  *
 938  *  This inits the hardware readying it for operation.
 939  **/
 940 static s32 e1000_init_hw_82571(struct e1000_hw *hw)
 941 {
 942         struct e1000_mac_info *mac = &hw->mac;
 943         u32 reg_data;
 944         s32 ret_val;
 945         u16 i, rar_count = mac->rar_entry_count;
 946
 947         DEBUGFUNC("e1000_init_hw_82571");
 948
 949         e1000_initialize_hw_bits_82571(hw);
 950
 951         /* Initialize identification LED */
 952         ret_val = e1000_id_led_init_generic(hw);
 953         if (ret_val) {
 954                 DEBUGOUT("Error initializing identification LED\n");
 955                 /* This is not fatal and we should not stop init due to this */
 956         }
 957
 958         /* Disabling VLAN filtering */
 959         DEBUGOUT("Initializing the IEEE VLAN\n");
 960         mac->ops.clear_vfta(hw);
 961
 962         /* Setup the receive address. */
 963         /*
 964          * If, however, a locally administered address was assigned to the
 965          * 82571, we must reserve a RAR for it to work around an issue where
 966          * resetting one port will reload the MAC on the other port.
 967          */
 968         if (e1000_get_laa_state_82571(hw))
 969                 rar_count--;
 970         e1000_init_rx_addrs_generic(hw, rar_count);
 971
 972         /* Zero out the Multicast HASH table */
 973         DEBUGOUT("Zeroing the MTA\n");
 974         for (i = 0; i < mac->mta_reg_count; i++)
 975                 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
 976
 977         /* Setup link and flow control */
 978         ret_val = mac->ops.setup_link(hw);
 979
 980         /* Set the transmit descriptor write-back policy */
 981         reg_data = E1000_READ_REG(hw, E1000_TXDCTL(0));
 982         reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
 983                    E1000_TXDCTL_FULL_TX_DESC_WB |
 984                    E1000_TXDCTL_COUNT_DESC;
 985         E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg_data);
 986
 987         /* ...for both queues. */
 988         if (mac->type != e1000_82573 && mac->type != e1000_82574) {
 989                 reg_data = E1000_READ_REG(hw, E1000_TXDCTL(1));
 990                 reg_data = (reg_data & ~E1000_TXDCTL_WTHRESH) |
 991                            E1000_TXDCTL_FULL_TX_DESC_WB |
 992                            E1000_TXDCTL_COUNT_DESC;
 993                 E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg_data);
 994         } else {
 995                 e1000_enable_tx_pkt_filtering_generic(hw);
 996                 reg_data = E1000_READ_REG(hw, E1000_GCR);
 997                 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
 998                 E1000_WRITE_REG(hw, E1000_GCR, reg_data);
 999         }
1000
1001         /*
1002          * Clear all of the statistics registers (clear on read).  It is
1003          * important that we do this after we have tried to establish link
1004          * because the symbol error count will increment wildly if there
1005          * is no link.
1006          */
1007         e1000_clear_hw_cntrs_82571(hw);
1008
1009         return ret_val;
1010 }
1011
1012 /**
1013  *  e1000_initialize_hw_bits_82571 - Initialize hardware-dependent bits
1014  *  @hw: pointer to the HW structure
1015  *
1016  *  Initializes required hardware-dependent bits needed for normal operation.
1017  **/
1018 static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1019 {
1020         u32 reg;
1021
1022         DEBUGFUNC("e1000_initialize_hw_bits_82571");
1023
1024         /* Transmit Descriptor Control 0 */
1025         reg = E1000_READ_REG(hw, E1000_TXDCTL(0));
1026         reg |= (1 << 22);
1027         E1000_WRITE_REG(hw, E1000_TXDCTL(0), reg);
1028
1029         /* Transmit Descriptor Control 1 */
1030         reg = E1000_READ_REG(hw, E1000_TXDCTL(1));
1031         reg |= (1 << 22);
1032         E1000_WRITE_REG(hw, E1000_TXDCTL(1), reg);
1033
1034         /* Transmit Arbitration Control 0 */
1035         reg = E1000_READ_REG(hw, E1000_TARC(0));
1036         reg &= ~(0xF << 27); /* 30:27 */
1037         switch (hw->mac.type) {
1038         case e1000_82571:
1039         case e1000_82572:
1040                 reg |= (1 << 23) | (1 << 24) | (1 << 25) | (1 << 26);
1041                 break;
1042         default:
1043                 break;
1044         }
1045         E1000_WRITE_REG(hw, E1000_TARC(0), reg);
1046
1047         /* Transmit Arbitration Control 1 */
1048         reg = E1000_READ_REG(hw, E1000_TARC(1));
1049         switch (hw->mac.type) {
1050         case e1000_82571:
1051         case e1000_82572:
1052                 reg &= ~((1 << 29) | (1 << 30));
1053                 reg |= (1 << 22) | (1 << 24) | (1 << 25) | (1 << 26);
1054                 if (E1000_READ_REG(hw, E1000_TCTL) & E1000_TCTL_MULR)
1055                         reg &= ~(1 << 28);
1056                 else
1057                         reg |= (1 << 28);
1058                 E1000_WRITE_REG(hw, E1000_TARC(1), reg);
1059                 break;
1060         default:
1061                 break;
1062         }
1063
1064         /* Device Control */
1065         if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) {
1066                 reg = E1000_READ_REG(hw, E1000_CTRL);
1067                 reg &= ~(1 << 29);
1068                 E1000_WRITE_REG(hw, E1000_CTRL, reg);
1069         }
1070
1071         /* Extended Device Control */
1072         if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) {
1073                 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1074                 reg &= ~(1 << 23);
1075                 reg |= (1 << 22);
1076                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1077         }
1078
1079         /* PCI-Ex Control Register */
1080         if (hw->mac.type == e1000_82574) {
1081                 reg = E1000_READ_REG(hw, E1000_GCR);
1082                 reg |= (1 << 22);
1083                 E1000_WRITE_REG(hw, E1000_GCR, reg);
1084         }
1085
1086         return;
1087 }
1088
1089 /**
1090  *  e1000_clear_vfta_82571 - Clear VLAN filter table
1091  *  @hw: pointer to the HW structure
1092  *
1093  *  Clears the register array which contains the VLAN filter table by
1094  *  setting all the values to 0.
1095  **/
1096 static void e1000_clear_vfta_82571(struct e1000_hw *hw)
1097 {
1098         u32 offset;
1099         u32 vfta_value = 0;
1100         u32 vfta_offset = 0;
1101         u32 vfta_bit_in_reg = 0;
1102
1103         DEBUGFUNC("e1000_clear_vfta_82571");
1104
1105         if (hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) {
1106                 if (hw->mng_cookie.vlan_id != 0) {
1107                         /*
1108                          * The VFTA is a 4096b bit-field, each identifying
1109                          * a single VLAN ID.  The following operations
1110                          * determine which 32b entry (i.e. offset) into the
1111                          * array we want to set the VLAN ID (i.e. bit) of
1112                          * the manageability unit.
1113                          */
1114                         vfta_offset = (hw->mng_cookie.vlan_id >>
1115                                        E1000_VFTA_ENTRY_SHIFT) &
1116                                       E1000_VFTA_ENTRY_MASK;
1117                         vfta_bit_in_reg = 1 << (hw->mng_cookie.vlan_id &
1118                                                E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
1119                 }
1120         }
1121         for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1122                 /*
1123                  * If the offset we want to clear is the same offset of the
1124                  * manageability VLAN ID, then clear all bits except that of
1125                  * the manageability unit.
1126                  */
1127                 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
1128                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
1129                 E1000_WRITE_FLUSH(hw);
1130         }
1131 }
1132
1133 /**
1134  *  e1000_check_mng_mode_82574 - Check manageability is enabled
1135  *  @hw: pointer to the HW structure
1136  *
1137  *  Reads the NVM Initialization Control Word 2 and returns TRUE
1138  *  (>0) if any manageability is enabled, else FALSE (0).
1139  **/
1140 static bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
1141 {
1142         u16 data;
1143
1144         DEBUGFUNC("e1000_check_mng_mode_82574");
1145
1146         hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1147         return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
1148 }
1149
1150 /**
1151  *  e1000_led_on_82574 - Turn LED on
1152  *  @hw: pointer to the HW structure
1153  *
1154  *  Turn LED on.
1155  **/
1156 static s32 e1000_led_on_82574(struct e1000_hw *hw)
1157 {
1158         u32 ctrl;
1159         u32 i;
1160
1161         DEBUGFUNC("e1000_led_on_82574");
1162
1163         ctrl = hw->mac.ledctl_mode2;
1164         if (!(E1000_STATUS_LU & E1000_READ_REG(hw, E1000_STATUS))) {
1165                 /*
1166                  * If no link, then turn LED on by setting the invert bit
1167                  * for each LED that's "on" (0x0E) in ledctl_mode2.
1168                  */
1169                 for (i = 0; i < 4; i++)
1170                         if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1171                             E1000_LEDCTL_MODE_LED_ON)
1172                                 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
1173         }
1174         E1000_WRITE_REG(hw, E1000_LEDCTL, ctrl);
1175
1176         return E1000_SUCCESS;
1177 }
1178
1179 /**
1180  *  e1000_update_mc_addr_list_82571 - Update Multicast addresses
1181  *  @hw: pointer to the HW structure
1182  *  @mc_addr_list: array of multicast addresses to program
1183  *  @mc_addr_count: number of multicast addresses to program
1184  *  @rar_used_count: the first RAR register free to program
1185  *  @rar_count: total number of supported Receive Address Registers
1186  *
1187  *  Updates the Receive Address Registers and Multicast Table Array.
1188  *  The caller must have a packed mc_addr_list of multicast addresses.
1189  *  The parameter rar_count will usually be hw->mac.rar_entry_count
1190  *  unless there are workarounds that change this.
1191  **/
1192 static void e1000_update_mc_addr_list_82571(struct e1000_hw *hw,
1193                                            u8 *mc_addr_list, u32 mc_addr_count,
1194                                            u32 rar_used_count, u32 rar_count)
1195 {
1196         DEBUGFUNC("e1000_update_mc_addr_list_82571");
1197
1198         if (e1000_get_laa_state_82571(hw))
1199                 rar_count--;
1200
1201         e1000_update_mc_addr_list_generic(hw, mc_addr_list, mc_addr_count,
1202                                           rar_used_count, rar_count);
1203 }
1204
1205 /**
1206  *  e1000_setup_link_82571 - Setup flow control and link settings
1207  *  @hw: pointer to the HW structure
1208  *
1209  *  Determines which flow control settings to use, then configures flow
1210  *  control.  Calls the appropriate media-specific link configuration
1211  *  function.  Assuming the adapter has a valid link partner, a valid link
1212  *  should be established.  Assumes the hardware has previously been reset
1213  *  and the transmitter and receiver are not enabled.
1214  **/
1215 static s32 e1000_setup_link_82571(struct e1000_hw *hw)
1216 {
1217         DEBUGFUNC("e1000_setup_link_82571");
1218
1219         /*
1220          * 82573 does not have a word in the NVM to determine
1221          * the default flow control setting, so we explicitly
1222          * set it to full.
1223          */
1224         if ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) &&
1225             hw->fc.requested_mode == e1000_fc_default)
1226                 hw->fc.requested_mode = e1000_fc_full;
1227
1228         return e1000_setup_link_generic(hw);
1229 }
1230
1231 /**
1232  *  e1000_setup_copper_link_82571 - Configure copper link settings
1233  *  @hw: pointer to the HW structure
1234  *
1235  *  Configures the link for auto-neg or forced speed and duplex.  Then we check
1236  *  for link, once link is established calls to configure collision distance
1237  *  and flow control are called.
1238  **/
1239 static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
1240 {
1241         u32 ctrl, led_ctrl;
1242         s32  ret_val;
1243
1244         DEBUGFUNC("e1000_setup_copper_link_82571");
1245
1246         ctrl = E1000_READ_REG(hw, E1000_CTRL);
1247         ctrl |= E1000_CTRL_SLU;
1248         ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1249         E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1250
1251         switch (hw->phy.type) {
1252         case e1000_phy_m88:
1253         case e1000_phy_bm:
1254                 ret_val = e1000_copper_link_setup_m88(hw);
1255                 break;
1256         case e1000_phy_igp_2:
1257                 ret_val = e1000_copper_link_setup_igp(hw);
1258                 /* Setup activity LED */
1259                 led_ctrl = E1000_READ_REG(hw, E1000_LEDCTL);
1260                 led_ctrl &= IGP_ACTIVITY_LED_MASK;
1261                 led_ctrl |= (IGP_ACTIVITY_LED_ENABLE | IGP_LED3_MODE);
1262                 E1000_WRITE_REG(hw, E1000_LEDCTL, led_ctrl);
1263                 break;
1264         default:
1265                 ret_val = -E1000_ERR_PHY;
1266                 break;
1267         }
1268
1269         if (ret_val)
1270                 goto out;
1271
1272         ret_val = e1000_setup_copper_link_generic(hw);
1273
1274 out:
1275         return ret_val;
1276 }
1277
1278 /**
1279  *  e1000_setup_fiber_serdes_link_82571 - Setup link for fiber/serdes
1280  *  @hw: pointer to the HW structure
1281  *
1282  *  Configures collision distance and flow control for fiber and serdes links.
1283  *  Upon successful setup, poll for link.
1284  **/
1285 static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1286 {
1287         DEBUGFUNC("e1000_setup_fiber_serdes_link_82571");
1288
1289         switch (hw->mac.type) {
1290         case e1000_82571:
1291         case e1000_82572:
1292                 /*
1293                  * If SerDes loopback mode is entered, there is no form
1294                  * of reset to take the adapter out of that mode.  So we
1295                  * have to explicitly take the adapter out of loopback
1296                  * mode.  This prevents drivers from twiddling their thumbs
1297                  * if another tool failed to take it out of loopback mode.
1298                  */
1299                 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1300                 break;
1301         default:
1302                 break;
1303         }
1304
1305         return e1000_setup_fiber_serdes_link_generic(hw);
1306 }
1307
1308 /**
1309  *  e1000_valid_led_default_82571 - Verify a valid default LED config
1310  *  @hw: pointer to the HW structure
1311  *  @data: pointer to the NVM (EEPROM)
1312  *
1313  *  Read the EEPROM for the current default LED configuration.  If the
1314  *  LED configuration is not valid, set to a valid LED configuration.
1315  **/
1316 static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1317 {
1318         s32 ret_val;
1319
1320         DEBUGFUNC("e1000_valid_led_default_82571");
1321
1322         ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1323         if (ret_val) {
1324                 DEBUGOUT("NVM Read Error\n");
1325                 goto out;
1326         }
1327
1328         if ((hw->mac.type == e1000_82573 || hw->mac.type == e1000_82574) &&
1329             *data == ID_LED_RESERVED_F746)
1330                 *data = ID_LED_DEFAULT_82573;
1331         else if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF)
1332                 *data = ID_LED_DEFAULT;
1333 out:
1334         return ret_val;
1335 }
1336
1337 /**
1338  *  e1000_get_laa_state_82571 - Get locally administered address state
1339  *  @hw: pointer to the HW structure
1340  *
1341  *  Retrieve and return the current locally administered address state.
1342  **/
1343 bool e1000_get_laa_state_82571(struct e1000_hw *hw)
1344 {
1345         DEBUGFUNC("e1000_get_laa_state_82571");
1346
1347         if (hw->mac.type != e1000_82571)
1348                 return FALSE;
1349
1350         return hw->dev_spec._82571.laa_is_present;
1351 }
1352
1353 /**
1354  *  e1000_set_laa_state_82571 - Set locally administered address state
1355  *  @hw: pointer to the HW structure
1356  *  @state: enable/disable locally administered address
1357  *
1358  *  Enable/Disable the current locally administered address state.
1359  **/
1360 void e1000_set_laa_state_82571(struct e1000_hw *hw, bool state)
1361 {
1362         DEBUGFUNC("e1000_set_laa_state_82571");
1363
1364         if (hw->mac.type != e1000_82571)
1365                 return;
1366
1367         hw->dev_spec._82571.laa_is_present = state;
1368
1369         /* If workaround is activated... */
1370         if (state)
1371                 /*
1372                  * Hold a copy of the LAA in RAR[14] This is done so that
1373                  * between the time RAR[0] gets clobbered and the time it
1374                  * gets fixed, the actual LAA is in one of the RARs and no
1375                  * incoming packets directed to this port are dropped.
1376                  * Eventually the LAA will be in RAR[0] and RAR[14].
1377                  */
1378                 e1000_rar_set_generic(hw, hw->mac.addr,
1379                                       hw->mac.rar_entry_count - 1);
1380         return;
1381 }
1382
1383 /**
1384  *  e1000_fix_nvm_checksum_82571 - Fix EEPROM checksum
1385  *  @hw: pointer to the HW structure
1386  *
1387  *  Verifies that the EEPROM has completed the update.  After updating the
1388  *  EEPROM, we need to check bit 15 in work 0x23 for the checksum fix.  If
1389  *  the checksum fix is not implemented, we need to set the bit and update
1390  *  the checksum.  Otherwise, if bit 15 is set and the checksum is incorrect,
1391  *  we need to return bad checksum.
1392  **/
1393 static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1394 {
1395         struct e1000_nvm_info *nvm = &hw->nvm;
1396         s32 ret_val = E1000_SUCCESS;
1397         u16 data;
1398
1399         DEBUGFUNC("e1000_fix_nvm_checksum_82571");
1400
1401         if (nvm->type != e1000_nvm_flash_hw)
1402                 goto out;
1403
1404         /*
1405          * Check bit 4 of word 10h.  If it is 0, firmware is done updating
1406          * 10h-12h.  Checksum may need to be fixed.
1407          */
1408         ret_val = nvm->ops.read(hw, 0x10, 1, &data);
1409         if (ret_val)
1410                 goto out;
1411
1412         if (!(data & 0x10)) {
1413                 /*
1414                  * Read 0x23 and check bit 15.  This bit is a 1
1415                  * when the checksum has already been fixed.  If
1416                  * the checksum is still wrong and this bit is a
1417                  * 1, we need to return bad checksum.  Otherwise,
1418                  * we need to set this bit to a 1 and update the
1419                  * checksum.
1420                  */
1421                 ret_val = nvm->ops.read(hw, 0x23, 1, &data);
1422                 if (ret_val)
1423                         goto out;
1424
1425                 if (!(data & 0x8000)) {
1426                         data |= 0x8000;
1427                         ret_val = nvm->ops.write(hw, 0x23, 1, &data);
1428                         if (ret_val)
1429                                 goto out;
1430                         ret_val = nvm->ops.update(hw);
1431                 }
1432         }
1433
1434 out:
1435         return ret_val;
1436 }
1437
1438 /**
1439  *  e1000_read_mac_addr_82571 - Read device MAC address
1440  *  @hw: pointer to the HW structure
1441  **/
1442 static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw)
1443 {
1444         s32 ret_val = E1000_SUCCESS;
1445
1446         DEBUGFUNC("e1000_read_mac_addr_82571");
1447         if (e1000_check_alt_mac_addr_generic(hw))
1448                 ret_val = e1000_read_mac_addr_generic(hw);
1449
1450         return ret_val;
1451 }
1452
1453 /**
1454  * e1000_power_down_phy_copper_82571 - Remove link during PHY power down
1455  * @hw: pointer to the HW structure
1456  *
1457  * In the case of a PHY power down to save power, or to turn off link during a
1458  * driver unload, or wake on lan is not enabled, remove the link.
1459  **/
1460 static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw)
1461 {
1462         struct e1000_phy_info *phy = &hw->phy;
1463         struct e1000_mac_info *mac = &hw->mac;
1464
1465         if (!(phy->ops.check_reset_block))
1466                 return;
1467
1468         /* If the management interface is not enabled, then power down */
1469         if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
1470                 e1000_power_down_phy_copper(hw);
1471
1472         return;
1473 }
1474
1475 /**
1476  *  e1000_clear_hw_cntrs_82571 - Clear device specific hardware counters
1477  *  @hw: pointer to the HW structure
1478  *
1479  *  Clears the hardware counters by reading the counter registers.
1480  **/
1481 static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
1482 {
1483         DEBUGFUNC("e1000_clear_hw_cntrs_82571");
1484
1485         e1000_clear_hw_cntrs_base_generic(hw);
1486
1487         E1000_READ_REG(hw, E1000_PRC64);
1488         E1000_READ_REG(hw, E1000_PRC127);
1489         E1000_READ_REG(hw, E1000_PRC255);
1490         E1000_READ_REG(hw, E1000_PRC511);
1491         E1000_READ_REG(hw, E1000_PRC1023);
1492         E1000_READ_REG(hw, E1000_PRC1522);
1493         E1000_READ_REG(hw, E1000_PTC64);
1494         E1000_READ_REG(hw, E1000_PTC127);
1495         E1000_READ_REG(hw, E1000_PTC255);
1496         E1000_READ_REG(hw, E1000_PTC511);
1497         E1000_READ_REG(hw, E1000_PTC1023);
1498         E1000_READ_REG(hw, E1000_PTC1522);
1499
1500         E1000_READ_REG(hw, E1000_ALGNERRC);
1501         E1000_READ_REG(hw, E1000_RXERRC);
1502         E1000_READ_REG(hw, E1000_TNCRS);
1503         E1000_READ_REG(hw, E1000_CEXTERR);
1504         E1000_READ_REG(hw, E1000_TSCTC);
1505         E1000_READ_REG(hw, E1000_TSCTFC);
1506
1507         E1000_READ_REG(hw, E1000_MGTPRC);
1508         E1000_READ_REG(hw, E1000_MGTPDC);
1509         E1000_READ_REG(hw, E1000_MGTPTC);
1510
1511         E1000_READ_REG(hw, E1000_IAC);
1512         E1000_READ_REG(hw, E1000_ICRXOC);
1513
1514         E1000_READ_REG(hw, E1000_ICRXPTC);
1515         E1000_READ_REG(hw, E1000_ICRXATC);
1516         E1000_READ_REG(hw, E1000_ICTXPTC);
1517         E1000_READ_REG(hw, E1000_ICTXATC);
1518         E1000_READ_REG(hw, E1000_ICTXQEC);
1519         E1000_READ_REG(hw, E1000_ICTXQMTC);
1520         E1000_READ_REG(hw, E1000_ICRXDMTC);
1521 }