9d90e37621a0f9eee6db5cd51f4629266379bb52
[dragonfly.git] / sys / platform / pc32 / i386 / identcpu.c
1 /*-
2  * Copyright (c) 1992 Terrence R. Lambert.
3  * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
4  * Copyright (c) 1997 KATO Takenori.
5  * All rights reserved.
6  *
7  * This code is derived from software contributed to Berkeley by
8  * William Jolitz.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  * 3. All advertising materials mentioning features or use of this software
19  *    must display the following acknowledgement:
20  *      This product includes software developed by the University of
21  *      California, Berkeley and its contributors.
22  * 4. Neither the name of the University nor the names of its contributors
23  *    may be used to endorse or promote products derived from this software
24  *    without specific prior written permission.
25  *
26  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36  * SUCH DAMAGE.
37  *
38  *      from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
39  * $FreeBSD: src/sys/i386/i386/identcpu.c,v 1.206 2009/11/12 10:59:00 nyan
40  */
41 #include "opt_cpu.h"
42
43 #include <sys/param.h>
44 #include <sys/systm.h>
45 #include <sys/kernel.h>
46 #include <sys/sysctl.h>
47 #include <sys/lock.h>
48
49 #include <machine/asmacros.h>
50 #include <machine/clock.h>
51 #include <machine/cputypes.h>
52 #include <machine/segments.h>
53 #include <machine/specialreg.h>
54 #include <machine/md_var.h>
55
56 #include <machine_base/isa/intr_machdep.h>
57
58 #define IDENTBLUE_CYRIX486      0
59 #define IDENTBLUE_IBMCPU        1
60 #define IDENTBLUE_CYRIXM2       2
61
62 /* XXX - should be in header file: */
63 void printcpuinfo(void);
64 void finishidentcpu(void);
65 void earlysetcpuclass(void);
66 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
67 void    enable_K5_wt_alloc(void);
68 void    enable_K6_wt_alloc(void);
69 void    enable_K6_2_wt_alloc(void);
70 #endif
71 void panicifcpuunsupported(void);
72
73 static void identifycyrix(void);
74 static void init_exthigh(void);
75 static u_int find_cpu_vendor_id(void);
76 static void print_AMD_info(void);
77 static void print_INTEL_info(void);
78 static void print_INTEL_TLB(u_int data);
79 static void print_AMD_assoc(int i);
80 static void print_transmeta_info(void);
81 static void print_via_padlock_info(void);
82
83 int     cpu_class;
84 u_int   cpu_exthigh;            /* Highest arg to extended CPUID */
85 u_int   cyrix_did;              /* Device ID of Cyrix CPU */
86 char machine[] = MACHINE;
87 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD, 
88     machine, 0, "Machine class");
89
90 static char cpu_model[128];
91 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD, 
92     cpu_model, 0, "Machine model");
93
94 static int hw_clockrate;
95 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
96     &hw_clockrate, 0, "CPU instruction clock rate");
97
98 static char cpu_brand[48];
99
100 #define MAX_ADDITIONAL_INFO     16
101
102 static const char *additional_cpu_info_ary[MAX_ADDITIONAL_INFO];
103 static u_int additional_cpu_info_count;
104
105 #define MAX_BRAND_INDEX 8
106
107 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
108         NULL,                   /* No brand */
109         "Intel Celeron",
110         "Intel Pentium III",
111         "Intel Pentium III Xeon",
112         NULL,
113         NULL,
114         NULL,
115         NULL,
116         "Intel Pentium 4"
117 };
118
119 static struct {
120         char    *cpu_name;
121         int     cpu_class;
122 } i386_cpus[] = {
123         { "Intel 80286",        CPUCLASS_286 },         /* CPU_286   */
124         { "i386SX",             CPUCLASS_386 },         /* CPU_386SX */
125         { "i386DX",             CPUCLASS_386 },         /* CPU_386   */
126         { "i486SX",             CPUCLASS_486 },         /* CPU_486SX */
127         { "i486DX",             CPUCLASS_486 },         /* CPU_486   */
128         { "Pentium",            CPUCLASS_586 },         /* CPU_586   */
129         { "Cyrix 486",          CPUCLASS_486 },         /* CPU_486DLC */
130         { "Pentium Pro",        CPUCLASS_686 },         /* CPU_686 */
131         { "Cyrix 5x86",         CPUCLASS_486 },         /* CPU_M1SC */
132         { "Cyrix 6x86",         CPUCLASS_486 },         /* CPU_M1 */
133         { "Blue Lightning",     CPUCLASS_486 },         /* CPU_BLUE */
134         { "Cyrix 6x86MX",       CPUCLASS_686 },         /* CPU_M2 */
135         { "NexGen 586",         CPUCLASS_386 },         /* CPU_NX586 (XXX) */
136         { "Cyrix 486S/DX",      CPUCLASS_486 },         /* CPU_CY486DX */
137         { "Pentium II",         CPUCLASS_686 },         /* CPU_PII */
138         { "Pentium III",        CPUCLASS_686 },         /* CPU_PIII */
139         { "Pentium 4",          CPUCLASS_686 },         /* CPU_P4 */
140 };
141
142 static struct {
143         char    *vendor;
144         u_int   vendor_id;
145 } cpu_vendors[] = {
146         { INTEL_VENDOR_ID,      CPU_VENDOR_INTEL },     /* GenuineIntel */
147         { AMD_VENDOR_ID,        CPU_VENDOR_AMD },       /* AuthenticAMD */
148         { CENTAUR_VENDOR_ID,    CPU_VENDOR_CENTAUR },   /* CentaurHauls */
149         { NSC_VENDOR_ID,        CPU_VENDOR_NSC },       /* Geode by NSC */
150         { CYRIX_VENDOR_ID,      CPU_VENDOR_CYRIX },     /* CyrixInstead */
151         { TRANSMETA_VENDOR_ID,  CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */
152         { SIS_VENDOR_ID,        CPU_VENDOR_SIS },       /* SiS SiS SiS  */
153         { UMC_VENDOR_ID,        CPU_VENDOR_UMC },       /* UMC UMC UMC  */
154         { NEXGEN_VENDOR_ID,     CPU_VENDOR_NEXGEN },    /* NexGenDriven */
155         { RISE_VENDOR_ID,       CPU_VENDOR_RISE },      /* RiseRiseRise */
156 #if 0
157         /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */
158         { "TransmetaCPU",       CPU_VENDOR_TRANSMETA },
159 #endif
160 };
161
162 int cpu_cores;
163 int cpu_logical;
164
165 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
166 int has_f00f_bug = 0;           /* Initialized so that it can be patched. */
167 #endif
168
169 static void
170 init_exthigh(void)
171 {
172         static int done = 0;
173         u_int regs[4];
174
175         if (done == 0) {
176                 if (cpu_high > 0 &&
177                     (cpu_vendor_id == CPU_VENDOR_INTEL ||
178                     cpu_vendor_id == CPU_VENDOR_AMD ||
179                     cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
180                     cpu_vendor_id == CPU_VENDOR_CENTAUR ||
181                     cpu_vendor_id == CPU_VENDOR_NSC)) {
182                         do_cpuid(0x80000000, regs);
183                         if (regs[0] >= 0x80000000)
184                                 cpu_exthigh = regs[0];
185                 }
186
187                 done = 1;
188         }
189 }
190
191 void
192 printcpuinfo(void)
193 {
194         u_int regs[4], i;
195         char *brand;
196
197         cpu_class = i386_cpus[cpu].cpu_class;
198         kprintf("CPU: ");
199         strncpy(cpu_model, i386_cpus[cpu].cpu_name, sizeof (cpu_model));
200
201         /* Check for extended CPUID information and a processor name. */
202         init_exthigh();
203         if (cpu_exthigh >= 0x80000004) {
204                 brand = cpu_brand;
205                 for (i = 0x80000002; i < 0x80000005; i++) {
206                         do_cpuid(i, regs);
207                         memcpy(brand, regs, sizeof(regs));
208                         brand += sizeof(regs);
209                 }
210         }
211
212         if (cpu_vendor_id == CPU_VENDOR_INTEL) {
213                 if ((cpu_id & 0xf00) > 0x300) {
214                         u_int brand_index;
215
216                         cpu_model[0] = '\0';
217
218                         switch (cpu_id & 0x3000) {
219                         case 0x1000:
220                                 strcpy(cpu_model, "Overdrive ");
221                                 break;
222                         case 0x2000:
223                                 strcpy(cpu_model, "Dual ");
224                                 break;
225                         }
226
227                         switch (cpu_id & 0xf00) {
228                         case 0x400:
229                                 strcat(cpu_model, "i486 ");
230                                 /* Check the particular flavor of 486 */
231                                 switch (cpu_id & 0xf0) {
232                                 case 0x00:
233                                 case 0x10:
234                                         strcat(cpu_model, "DX");
235                                         break;
236                                 case 0x20:
237                                         strcat(cpu_model, "SX");
238                                         break;
239                                 case 0x30:
240                                         strcat(cpu_model, "DX2");
241                                         break;
242                                 case 0x40:
243                                         strcat(cpu_model, "SL");
244                                         break;
245                                 case 0x50:
246                                         strcat(cpu_model, "SX2");
247                                         break;
248                                 case 0x70:
249                                         strcat(cpu_model,
250                                             "DX2 Write-Back Enhanced");
251                                         break;
252                                 case 0x80:
253                                         strcat(cpu_model, "DX4");
254                                         break;
255                                 }
256                                 break;
257                         case 0x500:
258                                 /* Check the particular flavor of 586 */
259                                 strcat(cpu_model, "Pentium");
260                                 switch (cpu_id & 0xf0) {
261                                 case 0x00:
262                                         strcat(cpu_model, " A-step");
263                                         break;
264                                 case 0x10:
265                                         strcat(cpu_model, "/P5");
266                                         break;
267                                 case 0x20:
268                                         strcat(cpu_model, "/P54C");
269                                         break;
270                                 case 0x30:
271                                         strcat(cpu_model, "/P24T");
272                                         break;
273                                 case 0x40:
274                                         strcat(cpu_model, "/P55C");
275                                         break;
276                                 case 0x70:
277                                         strcat(cpu_model, "/P54C");
278                                         break;
279                                 case 0x80:
280                                         strcat(cpu_model, "/P55C (quarter-micron)");
281                                         break;
282                                 default:
283                                         /* nothing */
284                                         break;
285                                 }
286 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
287                                 /*
288                                  * XXX - If/when Intel fixes the bug, this
289                                  * should also check the version of the
290                                  * CPU, not just that it's a Pentium.
291                                  */
292                                 has_f00f_bug = 1;
293 #endif
294                                 break;
295                         case 0x600:
296                                 /* Check the particular flavor of 686 */
297                                 switch (cpu_id & 0xf0) {
298                                 case 0x00:
299                                         strcat(cpu_model, "Pentium Pro A-step");
300                                         break;
301                                 case 0x10:
302                                         strcat(cpu_model, "Pentium Pro");
303                                         break;
304                                 case 0x30:
305                                 case 0x50:
306                                 case 0x60:
307                                         strcat(cpu_model,
308                                 "Pentium II/Pentium II Xeon/Celeron");
309                                         cpu = CPU_PII;
310                                         break;
311                                 case 0x70:
312                                 case 0x80:
313                                 case 0xa0:
314                                 case 0xb0:
315                                         strcat(cpu_model,
316                                         "Pentium III/Pentium III Xeon/Celeron");
317                                         cpu = CPU_PIII;
318                                         break;
319                                 default:
320                                         strcat(cpu_model, "Unknown 80686");
321                                         break;
322                                 }
323                                 break;
324                         case 0xf00:
325                                 strcat(cpu_model, "Pentium 4");
326                                 cpu = CPU_P4;
327                                 break;
328                         default:
329                                 strcat(cpu_model, "unknown");
330                                 break;
331                         }
332
333                         /*
334                          * If we didn't get a brand name from the extended
335                          * CPUID, try to look it up in the brand table.
336                          */
337                         if (cpu_high > 0 && *cpu_brand == '\0') {
338                                 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
339                                 if (brand_index <= MAX_BRAND_INDEX &&
340                                     cpu_brandtable[brand_index] != NULL)
341                                         strcpy(cpu_brand,
342                                             cpu_brandtable[brand_index]);
343                         }
344                 }
345         } else if (cpu_vendor_id == CPU_VENDOR_AMD) {
346                 /*
347                  * Values taken from AMD Processor Recognition
348                  * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
349                  * (also describes ``Features'' encodings.
350                  */
351                 strcpy(cpu_model, "AMD ");
352                 switch (cpu_id & 0xFF0) {
353                 case 0x410:
354                         strcat(cpu_model, "Standard Am486DX");
355                         break;
356                 case 0x430:
357                         strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
358                         break;
359                 case 0x470:
360                         strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
361                         break;
362                 case 0x480:
363                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
364                         break;
365                 case 0x490:
366                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
367                         break;
368                 case 0x4E0:
369                         strcat(cpu_model, "Am5x86 Write-Through");
370                         break;
371                 case 0x4F0:
372                         strcat(cpu_model, "Am5x86 Write-Back");
373                         break;
374                 case 0x500:
375                         strcat(cpu_model, "K5 model 0");
376                         tsc_is_broken = 1;
377                         break;
378                 case 0x510:
379                         strcat(cpu_model, "K5 model 1");
380                         break;
381                 case 0x520:
382                         strcat(cpu_model, "K5 PR166 (model 2)");
383                         break;
384                 case 0x530:
385                         strcat(cpu_model, "K5 PR200 (model 3)");
386                         break;
387                 case 0x560:
388                         strcat(cpu_model, "K6");
389                         break;
390                 case 0x570:
391                         strcat(cpu_model, "K6 266 (model 1)");
392                         break;
393                 case 0x580:
394                         strcat(cpu_model, "K6-2");
395                         break;
396                 case 0x590:
397                         strcat(cpu_model, "K6-III");
398                         break;
399                 case 0x5a0:
400                         strcat(cpu_model, "Geode LX");
401                         /*
402                          * Make sure the TSC runs through suspension,
403                          * otherwise we can't use it as timecounter
404                          */
405                         wrmsr(0x1900, rdmsr(0x1900) | 0x20ULL);
406                         break;
407                 default:
408                         strcat(cpu_model, "Unknown");
409                         break;
410                 }
411 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
412                 if ((cpu_id & 0xf00) == 0x500) {
413                         if (((cpu_id & 0x0f0) > 0)
414                             && ((cpu_id & 0x0f0) < 0x60)
415                             && ((cpu_id & 0x00f) > 3))
416                                 enable_K5_wt_alloc();
417                         else if (((cpu_id & 0x0f0) > 0x80)
418                                  || (((cpu_id & 0x0f0) == 0x80)
419                                      && (cpu_id & 0x00f) > 0x07))
420                                 enable_K6_2_wt_alloc();
421                         else if ((cpu_id & 0x0f0) > 0x50)
422                                 enable_K6_wt_alloc();
423                 }
424 #endif
425         } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
426                 strcpy(cpu_model, "Cyrix ");
427                 switch (cpu_id & 0xff0) {
428                 case 0x440:
429                         strcat(cpu_model, "MediaGX");
430                         break;
431                 case 0x520:
432                         strcat(cpu_model, "6x86");
433                         break;
434                 case 0x540:
435                         cpu_class = CPUCLASS_586;
436                         strcat(cpu_model, "GXm");
437                         break;
438                 case 0x600:
439                         strcat(cpu_model, "6x86MX");
440                         break;
441                 default:
442                         /*
443                          * Even though CPU supports the cpuid
444                          * instruction, it can be disabled.
445                          * Therefore, this routine supports all Cyrix
446                          * CPUs.
447                          */
448                         switch (cyrix_did & 0xf0) {
449                         case 0x00:
450                                 switch (cyrix_did & 0x0f) {
451                                 case 0x00:
452                                         strcat(cpu_model, "486SLC");
453                                         break;
454                                 case 0x01:
455                                         strcat(cpu_model, "486DLC");
456                                         break;
457                                 case 0x02:
458                                         strcat(cpu_model, "486SLC2");
459                                         break;
460                                 case 0x03:
461                                         strcat(cpu_model, "486DLC2");
462                                         break;
463                                 case 0x04:
464                                         strcat(cpu_model, "486SRx");
465                                         break;
466                                 case 0x05:
467                                         strcat(cpu_model, "486DRx");
468                                         break;
469                                 case 0x06:
470                                         strcat(cpu_model, "486SRx2");
471                                         break;
472                                 case 0x07:
473                                         strcat(cpu_model, "486DRx2");
474                                         break;
475                                 case 0x08:
476                                         strcat(cpu_model, "486SRu");
477                                         break;
478                                 case 0x09:
479                                         strcat(cpu_model, "486DRu");
480                                         break;
481                                 case 0x0a:
482                                         strcat(cpu_model, "486SRu2");
483                                         break;
484                                 case 0x0b:
485                                         strcat(cpu_model, "486DRu2");
486                                         break;
487                                 default:
488                                         strcat(cpu_model, "Unknown");
489                                         break;
490                                 }
491                                 break;
492                         case 0x10:
493                                 switch (cyrix_did & 0x0f) {
494                                 case 0x00:
495                                         strcat(cpu_model, "486S");
496                                         break;
497                                 case 0x01:
498                                         strcat(cpu_model, "486S2");
499                                         break;
500                                 case 0x02:
501                                         strcat(cpu_model, "486Se");
502                                         break;
503                                 case 0x03:
504                                         strcat(cpu_model, "486S2e");
505                                         break;
506                                 case 0x0a:
507                                         strcat(cpu_model, "486DX");
508                                         break;
509                                 case 0x0b:
510                                         strcat(cpu_model, "486DX2");
511                                         break;
512                                 case 0x0f:
513                                         strcat(cpu_model, "486DX4");
514                                         break;
515                                 default:
516                                         strcat(cpu_model, "Unknown");
517                                         break;
518                                 }
519                                 break;
520                         case 0x20:
521                                 if ((cyrix_did & 0x0f) < 8)
522                                         strcat(cpu_model, "6x86");      /* Where did you get it? */
523                                 else
524                                         strcat(cpu_model, "5x86");
525                                 break;
526                         case 0x30:
527                                 strcat(cpu_model, "6x86");
528                                 break;
529                         case 0x40:
530                                 if ((cyrix_did & 0xf000) == 0x3000) {
531                                         cpu_class = CPUCLASS_586;
532                                         strcat(cpu_model, "GXm");
533                                 } else
534                                         strcat(cpu_model, "MediaGX");
535                                 break;
536                         case 0x50:
537                                 strcat(cpu_model, "6x86MX");
538                                 break;
539                         case 0xf0:
540                                 switch (cyrix_did & 0x0f) {
541                                 case 0x0d:
542                                         strcat(cpu_model, "Overdrive CPU");
543                                         break;
544                                 case 0x0e:
545                                         strcpy(cpu_model, "Texas Instruments 486SXL");
546                                         break;
547                                 case 0x0f:
548                                         strcat(cpu_model, "486SLC/DLC");
549                                         break;
550                                 default:
551                                         strcat(cpu_model, "Unknown");
552                                         break;
553                                 }
554                                 break;
555                         default:
556                                 strcat(cpu_model, "Unknown");
557                                 break;
558                         }
559                         break;
560                 }
561         } else if (cpu_vendor_id == CPU_VENDOR_RISE) {
562                 strcpy(cpu_model, "Rise ");
563                 switch (cpu_id & 0xff0) {
564                 case 0x500:
565                         strcat(cpu_model, "mP6");
566                         break;
567                 default:
568                         strcat(cpu_model, "Unknown");
569                 }
570         } else if (cpu_vendor_id == CPU_VENDOR_CENTAUR) {
571                 switch (cpu_id & 0xff0) {
572                 case 0x540:
573                         strcpy(cpu_model, "IDT WinChip C6");
574                         tsc_is_broken = 1;
575                         break;
576                 case 0x580:
577                         strcpy(cpu_model, "IDT WinChip 2");
578                         break;
579                 case 0x660:
580                         strcpy(cpu_model, "VIA C3 Samuel");
581                         break;
582                 case 0x670:
583                         if (cpu_id & 0x8)
584                                 strcpy(cpu_model, "VIA C3 Ezra");
585                         else
586                                 strcpy(cpu_model, "VIA C3 Samuel 2");
587                         break;
588                 case 0x680:
589                         strcpy(cpu_model, "VIA C3 Ezra-T");
590                         break;
591                 case 0x690:
592                         strcpy(cpu_model, "VIA C3 Nehemiah");
593                         break;
594                 case 0x6a0:
595                 case 0x6d0:
596                         strcpy(cpu_model, "VIA C7 Esther");
597                         break;
598                 case 0x6f0:
599                         strcpy(cpu_model, "VIA Nano");
600                         break;
601                 default:
602                         strcpy(cpu_model, "VIA/IDT Unknown");
603                 }
604         } else if (cpu_vendor_id == CPU_VENDOR_IBM) {
605                 strcpy(cpu_model, "Blue Lightning CPU");
606         } else if (cpu_vendor_id == CPU_VENDOR_NSC) {
607                 switch (cpu_id & 0xfff) {
608                 case 0x540:
609                         strcpy(cpu_model, "Geode SC1100");
610                         cpu = CPU_GEODE1100;
611                         tsc_is_broken = 1;
612                         break;
613                 default:
614                         strcpy(cpu_model, "Geode/NSC unknown");
615                         break;
616                 }
617         }
618
619         /*
620          * Replace cpu_model with cpu_brand minus leading spaces if
621          * we have one.
622          */
623         brand = cpu_brand;
624         while (*brand == ' ')
625                 ++brand;
626         if (*brand != '\0')
627                 strcpy(cpu_model, brand);
628
629         kprintf("%s (", cpu_model);
630         switch(cpu_class) {
631         case CPUCLASS_286:
632                 kprintf("286");
633                 break;
634         case CPUCLASS_386:
635                 kprintf("386");
636                 break;
637 #if defined(I486_CPU)
638         case CPUCLASS_486:
639                 kprintf("486");
640                 /* bzero_vector = i486_bzero; */
641                 break;
642 #endif
643 #if defined(I586_CPU)
644         case CPUCLASS_586:
645                 hw_clockrate = (tsc_frequency + 5000) / 1000000;
646                 kprintf("%jd.%02d-MHz ",
647                        (intmax_t)(tsc_frequency + 4999) / 1000000,
648                        (u_int)((tsc_frequency + 4999) / 10000) % 100);
649                 kprintf("586");
650                 break;
651 #endif
652 #if defined(I686_CPU)
653         case CPUCLASS_686:
654                 hw_clockrate = (tsc_frequency + 5000) / 1000000;
655                 kprintf("%jd.%02d-MHz ",
656                        (intmax_t)(tsc_frequency + 4999) / 1000000,
657                        (u_int)((tsc_frequency + 4999) / 10000) % 100);
658                 kprintf("686");
659                 break;
660 #endif
661         default:
662                 kprintf("Unknown");     /* will panic below... */
663         }
664         kprintf("-class CPU)\n");
665         if(*cpu_vendor)
666                 kprintf("  Origin = \"%s\"",cpu_vendor);
667         if(cpu_id)
668                 kprintf("  Id = 0x%x", cpu_id);
669
670         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
671             cpu_vendor_id == CPU_VENDOR_AMD ||
672             cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
673             cpu_vendor_id == CPU_VENDOR_RISE ||
674             cpu_vendor_id == CPU_VENDOR_CENTAUR ||
675             cpu_vendor_id == CPU_VENDOR_NSC ||
676                 (cpu_vendor_id == CPU_VENDOR_CYRIX &&
677                  ((cpu_id & 0xf00) > 0x500))) {
678                 kprintf("  Stepping = %u", cpu_id & 0xf);
679                 if (cpu_vendor_id == CPU_VENDOR_CYRIX)
680                         kprintf("  DIR=0x%04x", cyrix_did);
681                 if (cpu_high > 0) {
682                         u_int cmp = 1, htt = 1;
683
684                         /*
685                          * Here we should probably set up flags indicating
686                          * whether or not various features are available.
687                          * The interesting ones are probably VME, PSE, PAE,
688                          * and PGE.  The code already assumes without bothering
689                          * to check that all CPUs >= Pentium have a TSC and
690                          * MSRs.
691                          */
692                         kprintf("\n  Features=0x%b", cpu_feature,
693                         "\020"
694                         "\001FPU"       /* Integral FPU */
695                         "\002VME"       /* Extended VM86 mode support */
696                         "\003DE"        /* Debugging Extensions (CR4.DE) */
697                         "\004PSE"       /* 4MByte page tables */
698                         "\005TSC"       /* Timestamp counter */
699                         "\006MSR"       /* Machine specific registers */
700                         "\007PAE"       /* Physical address extension */
701                         "\010MCE"       /* Machine Check support */
702                         "\011CX8"       /* CMPEXCH8 instruction */
703                         "\012APIC"      /* SMP local APIC */
704                         "\013oldMTRR"   /* Previous implementation of MTRR */
705                         "\014SEP"       /* Fast System Call */
706                         "\015MTRR"      /* Memory Type Range Registers */
707                         "\016PGE"       /* PG_G (global bit) support */
708                         "\017MCA"       /* Machine Check Architecture */
709                         "\020CMOV"      /* CMOV instruction */
710                         "\021PAT"       /* Page attributes table */
711                         "\022PSE36"     /* 36 bit address space support */
712                         "\023PN"        /* Processor Serial number */
713                         "\024CLFLUSH"   /* Has the CLFLUSH instruction */
714                         "\025<b20>"
715                         "\026DTS"       /* Debug Trace Store */
716                         "\027ACPI"      /* ACPI support */
717                         "\030MMX"       /* MMX instructions */
718                         "\031FXSR"      /* FXSAVE/FXRSTOR */
719                         "\032SSE"       /* Streaming SIMD Extensions */
720                         "\033SSE2"      /* Streaming SIMD Extensions #2 */
721                         "\034SS"        /* Self snoop */
722                         "\035HTT"       /* Hyperthreading (see EBX bit 16-23) */
723                         "\036TM"        /* Thermal Monitor clock slowdown */
724                         "\037IA64"      /* CPU can execute IA64 instructions */
725                         "\040PBE"       /* Pending Break Enable */
726                         );
727
728                         if (cpu_feature2 != 0) {
729                                 kprintf("\n  Features2=0x%b", cpu_feature2,
730                                 "\020"
731                                 "\001SSE3"      /* SSE3 */
732                                 "\002PCLMULQDQ" /* Carry-Less Mul Quadword */
733                                 "\003DTES64"    /* 64-bit Debug Trace */
734                                 "\004MON"       /* MONITOR/MWAIT Instructions */
735                                 "\005DS_CPL"    /* CPL Qualified Debug Store */
736                                 "\006VMX"       /* Virtual Machine Extensions */
737                                 "\007SMX"       /* Safer Mode Extensions */
738                                 "\010EST"       /* Enhanced SpeedStep */
739                                 "\011TM2"       /* Thermal Monitor 2 */
740                                 "\012SSSE3"     /* SSSE3 */
741                                 "\013CNXT-ID"   /* L1 context ID available */
742                                 "\014<b11>"
743                                 "\015<b12>"
744                                 "\016CX16"      /* CMPXCHG16B Instruction */
745                                 "\017xTPR"      /* Send Task Priority Messages*/
746                                 "\020PDCM"      /* Perf/Debug Capability MSR */
747                                 "\021<b16>"
748                                 "\022<b17>"
749                                 "\023DCA"       /* Direct Cache Access */
750                                 "\024SSE4.1"
751                                 "\025SSE4.2"
752                                 "\026x2APIC"    /* xAPIC Extensions */
753                                 "\027MOVBE"     /* MOVBE Instruction */
754                                 "\030POPCNT"
755                                 "\031<b24>"
756                                 "\032AESNI"     /* AES Crypto*/
757                                 "\033XSAVE"
758                                 "\034OSXSAVE"
759                                 "\035<b28>"
760                                 "\036<b29>"
761                                 "\037<b30>"
762                                 "\040VMM"        /* Running on a hypervisor */
763                                 );
764                         }
765
766                         /*
767                          * AMD64 Architecture Programmer's Manual Volume 3:
768                          * General-Purpose and System Instructions
769                          * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24594.pdf
770                          *
771                          * IA-32 Intel Architecture Software Developer's Manual,
772                          * Volume 2A: Instruction Set Reference, A-M
773                          * ftp://download.intel.com/design/Pentium4/manuals/25366617.pdf
774                          */
775                         if (amd_feature != 0) {
776                                 kprintf("\n  AMD Features=0x%b", amd_feature,
777                                 "\020"          /* in hex */
778                                 "\001<s0>"      /* Same */
779                                 "\002<s1>"      /* Same */
780                                 "\003<s2>"      /* Same */
781                                 "\004<s3>"      /* Same */
782                                 "\005<s4>"      /* Same */
783                                 "\006<s5>"      /* Same */
784                                 "\007<s6>"      /* Same */
785                                 "\010<s7>"      /* Same */
786                                 "\011<s8>"      /* Same */
787                                 "\012<s9>"      /* Same */
788                                 "\013<b10>"     /* Undefined */
789                                 "\014SYSCALL"   /* Have SYSCALL/SYSRET */
790                                 "\015<s12>"     /* Same */
791                                 "\016<s13>"     /* Same */
792                                 "\017<s14>"     /* Same */
793                                 "\020<s15>"     /* Same */
794                                 "\021<s16>"     /* Same */
795                                 "\022<s17>"     /* Same */
796                                 "\023<b18>"     /* Reserved, unknown */
797                                 "\024MP"        /* Multiprocessor Capable */
798                                 "\025NX"        /* Has EFER.NXE, NX */
799                                 "\026<b21>"     /* Undefined */
800                                 "\027MMX+"      /* AMD MMX Extensions */
801                                 "\030<s23>"     /* Same */
802                                 "\031<s24>"     /* Same */
803                                 "\032FFXSR"     /* Fast FXSAVE/FXRSTOR */
804                                 "\033Page1GB"   /* 1-GB large page support */
805                                 "\034RDTSCP"    /* RDTSCP */
806                                 "\035<b28>"     /* Undefined */
807                                 "\036LM"        /* 64 bit long mode */
808                                 "\0373DNow!+"   /* AMD 3DNow! Extensions */
809                                 "\0403DNow!"    /* AMD 3DNow! */
810                                 );
811                         }
812
813                         if (amd_feature2 != 0) {
814                                 kprintf("\n  AMD Features2=0x%b", amd_feature2,
815                                 "\020"
816                                 "\001LAHF"      /* LAHF/SAHF in long mode */
817                                 "\002CMP"       /* CMP legacy */
818                                 "\003SVM"       /* Secure Virtual Mode */
819                                 "\004ExtAPIC"   /* Extended APIC register */
820                                 "\005CR8"       /* CR8 in legacy mode */
821                                 "\006ABM"       /* LZCNT instruction */
822                                 "\007SSE4A"     /* SSE4A */
823                                 "\010MAS"       /* Misaligned SSE mode */
824                                 "\011Prefetch"  /* 3DNow! Prefetch/PrefetchW */
825                                 "\012OSVW"      /* OS visible workaround */
826                                 "\013IBS"       /* Instruction based sampling */
827                                 "\014SSE5"      /* SSE5 */
828                                 "\015SKINIT"    /* SKINIT/STGI */
829                                 "\016WDT"       /* Watchdog timer */
830                                 "\017<b14>"
831                                 "\020<b15>"
832                                 "\021<b16>"
833                                 "\022<b17>"
834                                 "\023<b18>"
835                                 "\024<b19>"
836                                 "\025<b20>"
837                                 "\026<b21>"
838                                 "\027<b22>"
839                                 "\030<b23>"
840                                 "\031<b24>"
841                                 "\032<b25>"
842                                 "\033<b26>"
843                                 "\034<b27>"
844                                 "\035<b28>"
845                                 "\036<b29>"
846                                 "\037<b30>"
847                                 "\040<b31>"
848                                 );
849                         }
850
851                         if (cpu_vendor_id == CPU_VENDOR_CENTAUR)
852                                 print_via_padlock_info();
853
854                         if ((cpu_feature & CPUID_HTT) &&
855                             cpu_vendor_id == CPU_VENDOR_AMD)
856                                 cpu_feature &= ~CPUID_HTT;
857
858                         /*
859                          * If this CPU supports HTT or CMP then mention the
860                          * number of physical/logical cores it contains.
861                          */
862                         if (cpu_feature & CPUID_HTT)
863                                 htt = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
864                         if (cpu_vendor_id == CPU_VENDOR_AMD &&
865                             (amd_feature2 & AMDID2_CMP))
866                                 cmp = (cpu_procinfo2 & AMDID_CMP_CORES) + 1;
867                         else if (cpu_vendor_id == CPU_VENDOR_INTEL &&
868                             (cpu_high >= 4)) {
869                                 cpuid_count(4, 0, regs);
870                                 if ((regs[0] & 0x1f) != 0)
871                                         cmp = ((regs[0] >> 26) & 0x3f) + 1;
872                         }
873                         cpu_cores = cmp;
874                         cpu_logical = htt / cmp;
875                         if (cmp > 1)
876                                 kprintf("\n  Cores per package: %d", cmp);
877                         if ((htt / cmp) > 1)
878                                 kprintf("\n  Logical CPUs per core: %d",
879                                     cpu_logical);
880 #if 0
881                         /*
882                          * If this CPU supports P-state invariant TSC then
883                          * mention the capability.
884                          */
885                         switch (cpu_vendor_id) {
886                         case CPU_VENDOR_AMD:
887                                 if ((amd_pminfo & AMDPM_TSC_INVARIANT) ||
888                                     CPUID_TO_FAMILY(cpu_id) >= 0x10 ||
889                                     cpu_id == 0x60fb2)
890                                         tsc_is_invariant = 1;
891                                 break;
892                         case CPU_VENDOR_INTEL:
893                                 if ((amd_pminfo & AMDPM_TSC_INVARIANT) ||
894                                     (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
895                                     CPUID_TO_MODEL(cpu_id) >= 0xe) ||
896                                     (CPUID_TO_FAMILY(cpu_id) == 0xf &&
897                                     CPUID_TO_MODEL(cpu_id) >= 0x3))
898                                         tsc_is_invariant = 1;
899                                 break;
900                         case CPU_VENDOR_CENTAUR:
901                                 if (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
902                                     CPUID_TO_MODEL(cpu_id) >= 0xf &&
903                                     (rdmsr(0x1203) & 0x100000000ULL) == 0)
904                                         tsc_is_invariant = 1;
905                                 break;
906                         }
907                         if (tsc_is_invariant)
908                                 kprintf("\n  TSC: P-state invariant");
909 #endif
910
911                 }
912         } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
913                 kprintf("  DIR=0x%04x", cyrix_did);
914                 kprintf("  Stepping=%u", (cyrix_did & 0xf000) >> 12);
915                 kprintf("  Revision=%u", (cyrix_did & 0x0f00) >> 8);
916 #ifndef CYRIX_CACHE_REALLY_WORKS
917                 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
918                         kprintf("\n  CPU cache: write-through mode");
919 #endif
920         }
921
922         /* Avoid ugly blank lines: only print newline when we have to. */
923         if (*cpu_vendor || cpu_id)
924                 kprintf("\n");
925
926         for (i = 0; i < additional_cpu_info_count; ++i) {
927                 kprintf("  %s\n", additional_cpu_info_ary[i]);
928         }
929
930         if (!bootverbose)
931                 return;
932
933         if (cpu_vendor_id == CPU_VENDOR_AMD)
934                 print_AMD_info();
935         else if (cpu_vendor_id == CPU_VENDOR_INTEL)
936                 print_INTEL_info();
937         else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA)
938                 print_transmeta_info();
939
940 #ifdef CPU_HAS_SSE2
941         kprintf("Use SSE2 (lfence, mfence)\n");
942 #endif
943 #ifdef CPU_HAS_FXSR
944         kprintf("Use FXSR (sfence)\n");
945 #endif
946 }
947
948 void
949 panicifcpuunsupported(void)
950 {
951
952 #if !defined(lint)
953 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
954 #error This kernel is not configured for one of the supported CPUs
955 #endif
956 #else /* lint */
957 #endif /* lint */
958         /*
959          * Now that we have told the user what they have,
960          * let them know if that machine type isn't configured.
961          */
962         switch (cpu_class) {
963         case CPUCLASS_286:      /* a 286 should not make it this far, anyway */
964         case CPUCLASS_386:
965 #if !defined(I486_CPU)
966         case CPUCLASS_486:
967 #endif
968 #if !defined(I586_CPU)
969         case CPUCLASS_586:
970 #endif
971 #if !defined(I686_CPU)
972         case CPUCLASS_686:
973 #endif
974                 panic("CPU class not configured");
975         default:
976                 break;
977         }
978 }
979
980
981 static  volatile u_int trap_by_rdmsr;
982
983 /*
984  * Special exception 6 handler.
985  * The rdmsr instruction generates invalid opcodes fault on 486-class
986  * Cyrix CPU.  Stacked eip register points the rdmsr instruction in the
987  * function identblue() when this handler is called.  Stacked eip should
988  * be advanced.
989  */
990 inthand_t       bluetrap6;
991
992 __asm
993 ("                                                                      \n\
994         .text                                                           \n\
995         .p2align 2,0x90                                                 \n\
996         .type   " __XSTRING(CNAME(bluetrap6)) ",@function               \n\
997 " __XSTRING(CNAME(bluetrap6)) ":                                        \n\
998         ss                                                              \n\
999         movl    $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
1000         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
1001         iret                                                            \n\
1002 ");
1003
1004 /*
1005  * Special exception 13 handler.
1006  * Accessing non-existent MSR generates general protection fault.
1007  */
1008 inthand_t       bluetrap13;
1009
1010 __asm
1011 ("                                                                      \n\
1012         .text                                                           \n\
1013         .p2align 2,0x90                                                 \n\
1014         .type   " __XSTRING(CNAME(bluetrap13)) ",@function              \n\
1015 " __XSTRING(CNAME(bluetrap13)) ":                                       \n\
1016         ss                                                              \n\
1017         movl    $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
1018         popl    %eax            /* discard error code */                \n\
1019         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
1020         iret                                                            \n\
1021 ");
1022
1023 /*
1024  * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
1025  * support cpuid instruction.  This function should be called after
1026  * loading interrupt descriptor table register.
1027  *
1028  * I don't like this method that handles fault, but I couldn't get
1029  * information for any other methods.  Does blue giant know?
1030  */
1031 static int
1032 identblue(void)
1033 {
1034
1035         trap_by_rdmsr = 0;
1036
1037         /*
1038          * Cyrix 486-class CPU does not support rdmsr instruction.
1039          * The rdmsr instruction generates invalid opcode fault, and exception
1040          * will be trapped by bluetrap6() on Cyrix 486-class CPU.  The
1041          * bluetrap6() set the magic number to trap_by_rdmsr.
1042          */
1043         setidt(6, bluetrap6, SDT_SYS386TGT, SEL_KPL,
1044             GSEL(GCODE_SEL, SEL_KPL));
1045
1046         /*
1047          * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
1048          * In this case, rdmsr generates general protection fault, and
1049          * exception will be trapped by bluetrap13().
1050          */
1051         setidt(13, bluetrap13, SDT_SYS386TGT, SEL_KPL,
1052             GSEL(GCODE_SEL, SEL_KPL));
1053
1054         rdmsr(0x1002);          /* Cyrix CPU generates fault. */
1055
1056         if (trap_by_rdmsr == 0xa8c1d)
1057                 return IDENTBLUE_CYRIX486;
1058         else if (trap_by_rdmsr == 0xa89c4)
1059                 return IDENTBLUE_CYRIXM2;
1060         return IDENTBLUE_IBMCPU;
1061 }
1062
1063
1064 /*
1065  * identifycyrix() set lower 16 bits of cyrix_did as follows:
1066  *
1067  *  F E D C B A 9 8 7 6 5 4 3 2 1 0
1068  * +-------+-------+---------------+
1069  * |  SID  |  RID  |   Device ID   |
1070  * |    (DIR 1)    |    (DIR 0)    |
1071  * +-------+-------+---------------+
1072  */
1073 static void
1074 identifycyrix(void)
1075 {
1076         int     ccr2_test = 0, dir_test = 0;
1077         u_char  ccr2, ccr3;
1078
1079         mpintr_lock();
1080
1081         ccr2 = read_cyrix_reg(CCR2);
1082         write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
1083         read_cyrix_reg(CCR2);
1084         if (read_cyrix_reg(CCR2) != ccr2)
1085                 ccr2_test = 1;
1086         write_cyrix_reg(CCR2, ccr2);
1087
1088         ccr3 = read_cyrix_reg(CCR3);
1089         write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
1090         read_cyrix_reg(CCR3);
1091         if (read_cyrix_reg(CCR3) != ccr3)
1092                 dir_test = 1;                                   /* CPU supports DIRs. */
1093         write_cyrix_reg(CCR3, ccr3);
1094
1095         if (dir_test) {
1096                 /* Device ID registers are available. */
1097                 cyrix_did = read_cyrix_reg(DIR1) << 8;
1098                 cyrix_did += read_cyrix_reg(DIR0);
1099         } else if (ccr2_test)
1100                 cyrix_did = 0x0010;             /* 486S A-step */
1101         else
1102                 cyrix_did = 0x00ff;             /* Old 486SLC/DLC and TI486SXLC/SXL */
1103         mpintr_unlock();
1104 }
1105
1106 #if 0
1107 /* Update TSC freq with the value indicated by the caller. */
1108 static void
1109 tsc_frequency_changed(void *arg, const struct cf_level *level, int status)
1110 {
1111         /*
1112          * If there was an error during the transition or
1113          * TSC is P-state invariant, don't do anything.
1114          */
1115         if (status != 0 || tsc_is_invariant)
1116                 return;
1117
1118         /* Total setting for this level gives the new frequency in MHz. */
1119         hw_clockrate = level->total_set.freq;
1120 }
1121 #endif
1122
1123 /*
1124  * Final stage of CPU identification. -- Should I check TI?
1125  */
1126 void
1127 finishidentcpu(void)
1128 {
1129         int     isblue = 0;
1130         u_char  ccr3;
1131         u_int   regs[4];
1132
1133         cpu_vendor_id = find_cpu_vendor_id();
1134
1135         /*
1136          * Clear "Limit CPUID Maxval" bit and get the largest standard CPUID
1137          * function number again if it is set from BIOS.  It is necessary
1138          * for probing correct CPU topology later.
1139          * XXX This is only done on the BSP package.
1140          */
1141         if (cpu_vendor_id == CPU_VENDOR_INTEL && cpu_high > 0 && cpu_high < 4 &&
1142             ((CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x3) ||
1143             (CPUID_TO_FAMILY(cpu_id) == 0x6 && CPUID_TO_MODEL(cpu_id) >= 0xe))) {
1144                 uint64_t msr;
1145                 msr = rdmsr(MSR_IA32_MISC_ENABLE);
1146                 if ((msr & 0x400000ULL) != 0) {
1147                         wrmsr(MSR_IA32_MISC_ENABLE, msr & ~0x400000ULL);
1148                         do_cpuid(0, regs);
1149                         cpu_high = regs[0];
1150                 }
1151         }
1152
1153         /* Detect AMD features (PTE no-execute bit, 3dnow, 64 bit mode etc) */
1154         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
1155             cpu_vendor_id == CPU_VENDOR_AMD) {
1156                 init_exthigh();
1157                 if (cpu_exthigh >= 0x80000001) {
1158                         do_cpuid(0x80000001, regs);
1159                         amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
1160                         amd_feature2 = regs[2];
1161                 }
1162 #if 0
1163                 if (cpu_exthigh >= 0x80000007) {
1164                         do_cpuid(0x80000007, regs);
1165                         amd_pminfo = regs[3];
1166                 }
1167 #endif
1168                 if (cpu_exthigh >= 0x80000008) {
1169                         do_cpuid(0x80000008, regs);
1170                         cpu_procinfo2 = regs[2];
1171                 }
1172         } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1173                 if (cpu == CPU_486) {
1174                         /*
1175                          * These conditions are equivalent to:
1176                          *     - CPU does not support cpuid instruction.
1177                          *     - Cyrix/IBM CPU is detected.
1178                          */
1179                         isblue = identblue();
1180                         if (isblue == IDENTBLUE_IBMCPU) {
1181                                 strcpy(cpu_vendor, "IBM");
1182                                 cpu_vendor_id = CPU_VENDOR_IBM;
1183                                 cpu = CPU_BLUE;
1184                                 goto finish;
1185                         }
1186                 }
1187                 switch (cpu_id & 0xf00) {
1188                 case 0x600:
1189                         /*
1190                          * Cyrix's datasheet does not describe DIRs.
1191                          * Therefor, I assume it does not have them
1192                          * and use the result of the cpuid instruction.
1193                          * XXX they seem to have it for now at least. -Peter
1194                          */
1195                         identifycyrix();
1196                         cpu = CPU_M2;
1197                         break;
1198                 default:
1199                         identifycyrix();
1200                         /*
1201                          * This routine contains a trick.
1202                          * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
1203                          */
1204                         switch (cyrix_did & 0x00f0) {
1205                         case 0x00:
1206                         case 0xf0:
1207                                 cpu = CPU_486DLC;
1208                                 break;
1209                         case 0x10:
1210                                 cpu = CPU_CY486DX;
1211                                 break;
1212                         case 0x20:
1213                                 if ((cyrix_did & 0x000f) < 8)
1214                                         cpu = CPU_M1;
1215                                 else
1216                                         cpu = CPU_M1SC;
1217                                 break;
1218                         case 0x30:
1219                                 cpu = CPU_M1;
1220                                 break;
1221                         case 0x40:
1222                                 /* MediaGX CPU */
1223                                 cpu = CPU_M1SC;
1224                                 break;
1225                         default:
1226                                 /* M2 and later CPUs are treated as M2. */
1227                                 cpu = CPU_M2;
1228
1229                                 /*
1230                                  * enable cpuid instruction.
1231                                  */
1232                                 ccr3 = read_cyrix_reg(CCR3);
1233                                 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1234                                 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
1235                                 write_cyrix_reg(CCR3, ccr3);
1236
1237                                 do_cpuid(0, regs);
1238                                 cpu_high = regs[0];     /* eax */
1239                                 do_cpuid(1, regs);
1240                                 cpu_id = regs[0];       /* eax */
1241                                 cpu_feature = regs[3];  /* edx */
1242                                 break;
1243                         }
1244                 }
1245         } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
1246                 /*
1247                  * There are BlueLightning CPUs that do not change
1248                  * undefined flags by dividing 5 by 2.  In this case,
1249                  * the CPU identification routine in locore.s leaves
1250                  * cpu_vendor null string and puts CPU_486 into the
1251                  * cpu.
1252                  */
1253                 isblue = identblue();
1254                 if (isblue == IDENTBLUE_IBMCPU) {
1255                         strcpy(cpu_vendor, "IBM");
1256                         cpu_vendor_id = CPU_VENDOR_IBM;
1257                         cpu = CPU_BLUE;
1258                 }
1259         }
1260
1261         /*
1262          * Set MI flags for MI procedures implemented using machine-specific
1263          * features.
1264          */
1265 finish:
1266         if (cpu_feature & CPUID_SSE2)
1267                 cpu_mi_feature |= CPU_MI_BZERONT;
1268
1269         if (cpu_feature2 & CPUID2_MON)
1270                 cpu_mi_feature |= CPU_MI_MONITOR;
1271
1272 #ifdef CPU_HAS_SSE2
1273         if ((cpu_feature & CPUID_SSE2) == 0)
1274                 panic("CPU does not has SSE2, remove options CPU_HAS_SSE2\n");
1275 #endif
1276 #ifdef CPU_HAS_FXSR
1277         if ((cpu_feature & CPUID_FXSR) == 0)
1278                 panic("CPU does not has FXSR, remove options CPU_HAS_FXSR\n");
1279 #endif
1280 }
1281
1282 static u_int
1283 find_cpu_vendor_id(void)
1284 {
1285         int     i;
1286
1287         for (i = 0; i < NELEM(cpu_vendors); i++)
1288                 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
1289                         return (cpu_vendors[i].vendor_id);
1290         return (0);
1291 }
1292
1293 static void
1294 print_AMD_assoc(int i)
1295 {
1296         if (i == 255)
1297                 kprintf(", fully associative\n");
1298         else
1299                 kprintf(", %d-way associative\n", i);
1300 }
1301
1302 /*
1303  * #31116 Rev 3.06 section 3.9
1304  * CPUID Fn8000_0006 L2/L3 Cache and L2 TLB Identifiers
1305  */
1306 static void
1307 print_AMD_L2L3_assoc(int i)
1308 {
1309         static const char *assoc_str[] = {
1310                 [0x0] = "disabled",
1311                 [0x1] = "direct mapped",
1312                 [0x2] = "2-way associative",
1313                 [0x4] = "4-way associative",
1314                 [0x6] = "8-way associative",
1315                 [0x8] = "16-way associative",
1316                 [0xa] = "32-way associative",
1317                 [0xb] = "48-way associative",
1318                 [0xc] = "64-way associative",
1319                 [0xd] = "96-way associative",
1320                 [0xe] = "128-way associative",
1321                 [0xf] = "fully associative"
1322         };
1323
1324         i &= 0xf;
1325         if (assoc_str[i] == NULL)
1326                 kprintf(", unknown associative\n");
1327         else
1328                 kprintf(", %s\n", assoc_str[i]);
1329 }
1330
1331 static void
1332 print_AMD_info(void)
1333 {
1334         quad_t amd_whcr;
1335
1336         if (cpu_exthigh >= 0x80000005) {
1337                 u_int regs[4];
1338
1339                 do_cpuid(0x80000005, regs);
1340                 kprintf("Data TLB: %d entries", (regs[1] >> 16) & 0xff);
1341                 print_AMD_assoc(regs[1] >> 24);
1342                 kprintf("Instruction TLB: %d entries", regs[1] & 0xff);
1343                 print_AMD_assoc((regs[1] >> 8) & 0xff);
1344                 kprintf("L1 data cache: %d kbytes", regs[2] >> 24);
1345                 kprintf(", %d bytes/line", regs[2] & 0xff);
1346                 kprintf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1347                 print_AMD_assoc((regs[2] >> 16) & 0xff);
1348                 kprintf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1349                 kprintf(", %d bytes/line", regs[3] & 0xff);
1350                 kprintf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1351                 print_AMD_assoc((regs[3] >> 16) & 0xff);
1352                 if (cpu_exthigh >= 0x80000006) {        /* K6-III or later */
1353                         do_cpuid(0x80000006, regs);
1354                         /*
1355                          * Report right L2 cache size on Duron rev. A0.
1356                          */
1357                         if ((cpu_id & 0xFF0) == 0x630)
1358                                 kprintf("L2 internal cache: 64 kbytes");
1359                         else
1360                                 kprintf("L2 internal cache: %d kbytes", regs[2] >> 16);
1361
1362                         kprintf(", %d bytes/line", regs[2] & 0xff);
1363                         kprintf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1364                         print_AMD_L2L3_assoc((regs[2] >> 12) & 0x0f);
1365
1366                         /*
1367                          * #31116 Rev 3.06 section 2.16.2:
1368                          * ... If EDX[31:16] is not zero then the processor
1369                          * includes an L3. ...
1370                          */
1371                         if ((regs[3] & 0xffff0000) != 0) {
1372                                 kprintf("L3 shared cache: %d kbytes",
1373                                         (regs[3] >> 18) * 512);
1374                                 kprintf(", %d bytes/line", regs[3] & 0xff);
1375                                 kprintf(", %d lines/tag", (regs[3] >> 8) & 0x0f);
1376                                 print_AMD_L2L3_assoc((regs[3] >> 12) & 0x0f);
1377                         }
1378                 }
1379         }
1380         if (((cpu_id & 0xf00) == 0x500)
1381             && (((cpu_id & 0x0f0) > 0x80)
1382                 || (((cpu_id & 0x0f0) == 0x80)
1383                     && (cpu_id & 0x00f) > 0x07))) {
1384                 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1385                 amd_whcr = rdmsr(0xc0000082);
1386                 if (!(amd_whcr & (0x3ff << 22))) {
1387                         kprintf("Write Allocate Disable\n");
1388                 } else {
1389                         kprintf("Write Allocate Enable Limit: %dM bytes\n",
1390                             (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1391                         kprintf("Write Allocate 15-16M bytes: %s\n",
1392                             (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1393                 }
1394         } else if (((cpu_id & 0xf00) == 0x500)
1395                    && ((cpu_id & 0x0f0) > 0x50)) {
1396                 /* K6, K6-2(old core) */
1397                 amd_whcr = rdmsr(0xc0000082);
1398                 if (!(amd_whcr & (0x7f << 1))) {
1399                         kprintf("Write Allocate Disable\n");
1400                 } else {
1401                         kprintf("Write Allocate Enable Limit: %dM bytes\n",
1402                             (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1403                         kprintf("Write Allocate 15-16M bytes: %s\n",
1404                             (amd_whcr & 0x0001) ? "Enable" : "Disable");
1405                         kprintf("Hardware Write Allocate Control: %s\n",
1406                             (amd_whcr & 0x0100) ? "Enable" : "Disable");
1407                 }
1408         }
1409
1410         /*
1411          * Opteron Rev E shows a bug as in very rare occasions a read memory
1412          * barrier is not performed as expected if it is followed by a
1413          * non-atomic read-modify-write instruction.
1414          * As long as that bug pops up very rarely (intensive machine usage
1415          * on other operating systems generally generates one unexplainable
1416          * crash any 2 months) and as long as a model specific fix would be
1417          * impratical at this stage, print out a warning string if the broken
1418          * model and family are identified.
1419          */
1420         if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 &&
1421             CPUID_TO_MODEL(cpu_id) <= 0x3f)
1422                 kprintf("WARNING: This architecture revision has known SMP "
1423                     "hardware bugs which may cause random instability\n");
1424 }
1425
1426 static void
1427 print_INTEL_info(void)
1428 {
1429         u_int regs[4];
1430         u_int rounds, regnum;
1431         u_int nwaycode, nway;
1432
1433         if (cpu_high >= 2) {
1434                 rounds = 0;
1435                 do {
1436                         do_cpuid(0x2, regs);
1437                         if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0)
1438                                 break;  /* we have a buggy CPU */
1439
1440                         for (regnum = 0; regnum <= 3; ++regnum) {
1441                                 if (regs[regnum] & (1<<31))
1442                                         continue;
1443                                 if (regnum != 0)
1444                                         print_INTEL_TLB(regs[regnum] & 0xff);
1445                                 print_INTEL_TLB((regs[regnum] >> 8) & 0xff);
1446                                 print_INTEL_TLB((regs[regnum] >> 16) & 0xff);
1447                                 print_INTEL_TLB((regs[regnum] >> 24) & 0xff);
1448                         }
1449                 } while (--rounds > 0);
1450         }
1451
1452         if (cpu_exthigh >= 0x80000006) {
1453                 do_cpuid(0x80000006, regs);
1454                 nwaycode = (regs[2] >> 12) & 0x0f;
1455                 if (nwaycode >= 0x02 && nwaycode <= 0x08)
1456                         nway = 1 << (nwaycode / 2);
1457                 else
1458                         nway = 0;
1459                 kprintf("\nL2 cache: %u kbytes, %u-way associative, %u bytes/line",
1460                     (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff);
1461         }
1462
1463         kprintf("\n");
1464 }
1465
1466 static void
1467 print_INTEL_TLB(u_int data)
1468 {
1469         switch (data) {
1470         case 0x0:
1471         case 0x40:
1472         default:
1473                 break;
1474         case 0x1:
1475                 kprintf("\nInstruction TLB: 4 KB pages, 4-way set associative, 32 entries");
1476                 break;
1477         case 0x2:
1478                 kprintf("\nInstruction TLB: 4 MB pages, fully associative, 2 entries");
1479                 break;
1480         case 0x3:
1481                 kprintf("\nData TLB: 4 KB pages, 4-way set associative, 64 entries");
1482                 break;
1483         case 0x4:
1484                 kprintf("\nData TLB: 4 MB Pages, 4-way set associative, 8 entries");
1485                 break;
1486         case 0x6:
1487                 kprintf("\n1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size");
1488                 break;
1489         case 0x8:
1490                 kprintf("\n1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size");
1491                 break;
1492         case 0xa:
1493                 kprintf("\n1st-level data cache: 8 KB, 2-way set associative, 32 byte line size");
1494                 break;
1495         case 0xc:
1496                 kprintf("\n1st-level data cache: 16 KB, 4-way set associative, 32 byte line size");
1497                 break;
1498         case 0x22:
1499                 kprintf("\n3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size");
1500                 break;
1501         case 0x23:
1502                 kprintf("\n3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size");
1503                 break;
1504         case 0x25:
1505                 kprintf("\n3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size");
1506                 break;
1507         case 0x29:
1508                 kprintf("\n3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size");
1509                 break;
1510         case 0x2c:
1511                 kprintf("\n1st-level data cache: 32 KB, 8-way set associative, 64 byte line size");
1512                 break;
1513         case 0x30:
1514                 kprintf("\n1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size");
1515                 break;
1516         case 0x39:
1517                 kprintf("\n2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size");
1518                 break;
1519         case 0x3b:
1520                 kprintf("\n2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size");
1521                 break;
1522         case 0x3c:
1523                 kprintf("\n2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size");
1524                 break;
1525         case 0x41:
1526                 kprintf("\n2nd-level cache: 128 KB, 4-way set associative, 32 byte line size");
1527                 break;
1528         case 0x42:
1529                 kprintf("\n2nd-level cache: 256 KB, 4-way set associative, 32 byte line size");
1530                 break;
1531         case 0x43:
1532                 kprintf("\n2nd-level cache: 512 KB, 4-way set associative, 32 byte line size");
1533                 break;
1534         case 0x44:
1535                 kprintf("\n2nd-level cache: 1 MB, 4-way set associative, 32 byte line size");
1536                 break;
1537         case 0x45:
1538                 kprintf("\n2nd-level cache: 2 MB, 4-way set associative, 32 byte line size");
1539                 break;
1540         case 0x46:
1541                 kprintf("\n3rd-level cache: 4 MB, 4-way set associative, 64 byte line size");
1542                 break;
1543         case 0x47:
1544                 kprintf("\n3rd-level cache: 8 MB, 8-way set associative, 64 byte line size");
1545                 break;
1546         case 0x50:
1547                 kprintf("\nInstruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries");
1548                 break;
1549         case 0x51:
1550                 kprintf("\nInstruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries");
1551                 break;
1552         case 0x52:
1553                 kprintf("\nInstruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries");
1554                 break;
1555         case 0x5b:
1556                 kprintf("\nData TLB: 4 KB or 4 MB pages, fully associative, 64 entries");
1557                 break;
1558         case 0x5c:
1559                 kprintf("\nData TLB: 4 KB or 4 MB pages, fully associative, 128 entries");
1560                 break;
1561         case 0x5d:
1562                 kprintf("\nData TLB: 4 KB or 4 MB pages, fully associative, 256 entries");
1563                 break;
1564         case 0x60:
1565                 kprintf("\n1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size");
1566                 break;
1567         case 0x66:
1568                 kprintf("\n1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size");
1569                 break;
1570         case 0x67:
1571                 kprintf("\n1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size");
1572                 break;
1573         case 0x68:
1574                 kprintf("\n1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size");
1575                 break;
1576         case 0x70:
1577                 kprintf("\nTrace cache: 12K-uops, 8-way set associative");
1578                 break;
1579         case 0x71:
1580                 kprintf("\nTrace cache: 16K-uops, 8-way set associative");
1581                 break;
1582         case 0x72:
1583                 kprintf("\nTrace cache: 32K-uops, 8-way set associative");
1584                 break;
1585         case 0x78:
1586                 kprintf("\n2nd-level cache: 1 MB, 4-way set associative, 64-byte line size");
1587                 break;
1588         case 0x79:
1589                 kprintf("\n2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size");
1590                 break;
1591         case 0x7a:
1592                 kprintf("\n2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size");
1593                 break;
1594         case 0x7b:
1595                 kprintf("\n2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size");
1596                 break;
1597         case 0x7c:
1598                 kprintf("\n2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size");
1599                 break;
1600         case 0x7d:
1601                 kprintf("\n2nd-level cache: 2-MB, 8-way set associative, 64-byte line size");
1602                 break;
1603         case 0x7f:
1604                 kprintf("\n2nd-level cache: 512-KB, 2-way set associative, 64-byte line size");
1605                 break;
1606         case 0x82:
1607                 kprintf("\n2nd-level cache: 256 KB, 8-way set associative, 32 byte line size");
1608                 break;
1609         case 0x83:
1610                 kprintf("\n2nd-level cache: 512 KB, 8-way set associative, 32 byte line size");
1611                 break;
1612         case 0x84:
1613                 kprintf("\n2nd-level cache: 1 MB, 8-way set associative, 32 byte line size");
1614                 break;
1615         case 0x85:
1616                 kprintf("\n2nd-level cache: 2 MB, 8-way set associative, 32 byte line size");
1617                 break;
1618         case 0x86:
1619                 kprintf("\n2nd-level cache: 512 KB, 4-way set associative, 64 byte line size");
1620                 break;
1621         case 0x87:
1622                 kprintf("\n2nd-level cache: 1 MB, 8-way set associative, 64 byte line size");
1623                 break;
1624         case 0xb0:
1625                 kprintf("\nInstruction TLB: 4 KB Pages, 4-way set associative, 128 entries");
1626                 break;
1627         case 0xb3:
1628                 kprintf("\nData TLB: 4 KB Pages, 4-way set associative, 128 entries");
1629                 break;
1630         }
1631 }
1632
1633 static void
1634 print_transmeta_info(void)
1635 {
1636         u_int regs[4], nreg = 0;
1637
1638         do_cpuid(0x80860000, regs);
1639         nreg = regs[0];
1640         if (nreg >= 0x80860001) {
1641                 do_cpuid(0x80860001, regs);
1642                 kprintf("  Processor revision %u.%u.%u.%u\n",
1643                        (regs[1] >> 24) & 0xff,
1644                        (regs[1] >> 16) & 0xff,
1645                        (regs[1] >> 8) & 0xff,
1646                        regs[1] & 0xff);
1647         }
1648         if (nreg >= 0x80860002) {
1649                 do_cpuid(0x80860002, regs);
1650                 kprintf("  Code Morphing Software revision %u.%u.%u-%u-%u\n",
1651                        (regs[1] >> 24) & 0xff,
1652                        (regs[1] >> 16) & 0xff,
1653                        (regs[1] >> 8) & 0xff,
1654                        regs[1] & 0xff,
1655                        regs[2]);
1656         }
1657         if (nreg >= 0x80860006) {
1658                 char info[65];
1659                 do_cpuid(0x80860003, (u_int*) &info[0]);
1660                 do_cpuid(0x80860004, (u_int*) &info[16]);
1661                 do_cpuid(0x80860005, (u_int*) &info[32]);
1662                 do_cpuid(0x80860006, (u_int*) &info[48]);
1663                 info[64] = 0;
1664                 kprintf("  %s\n", info);
1665         }
1666 }
1667
1668 static void
1669 print_via_padlock_info(void)
1670 {
1671         u_int regs[4];
1672
1673         /* Check for supported models. */
1674         switch (cpu_id & 0xff0) {
1675         case 0x690:
1676                 if ((cpu_id & 0xf) < 3)
1677                         return;
1678         case 0x6a0:
1679         case 0x6d0:
1680         case 0x6f0:
1681                 break;
1682         default:
1683                 return;
1684         }
1685
1686         do_cpuid(0xc0000000, regs);
1687         if (regs[0] >= 0xc0000001)
1688                 do_cpuid(0xc0000001, regs);
1689         else
1690                 return;
1691
1692         kprintf("\n  VIA Padlock Features=0x%b", regs[3],
1693         "\020"
1694         "\003RNG"               /* RNG */
1695         "\007AES"               /* ACE */
1696         "\011AES-CTR"           /* ACE2 */
1697         "\013SHA1,SHA256"       /* PHE */
1698         "\015RSA"               /* PMM */
1699         );
1700 }
1701
1702 void
1703 additional_cpu_info(const char *line)
1704 {
1705         int i;
1706
1707         if ((i = additional_cpu_info_count) < MAX_ADDITIONAL_INFO) {
1708                 additional_cpu_info_ary[i] = line;
1709                 ++additional_cpu_info_count;
1710         }
1711 }