2 * Copyright (c) 2007 The DragonFly Project. All rights reserved.
4 * This code is derived from software contributed to The DragonFly Project
5 * by Sepherosa Ziehau <sepherosa@gmail.com>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * $DragonFly: src/sys/dev/netif/bwi/if_bwi.c,v 1.21 2008/05/14 11:59:19 sephe Exp $
37 #include <sys/param.h>
38 #include <sys/bitops.h>
39 #include <sys/endian.h>
40 #include <sys/kernel.h>
42 #include <sys/interrupt.h>
43 #include <sys/malloc.h>
46 #include <sys/serialize.h>
47 #include <sys/socket.h>
48 #include <sys/sockio.h>
49 #include <sys/sysctl.h>
51 #include <net/ethernet.h>
54 #include <net/if_arp.h>
55 #include <net/if_dl.h>
56 #include <net/if_media.h>
57 #include <net/ifq_var.h>
59 #include <netproto/802_11/ieee80211_radiotap.h>
60 #include <netproto/802_11/ieee80211_var.h>
61 #include <netproto/802_11/wlan_ratectl/onoe/ieee80211_onoe_param.h>
63 #include <bus/pci/pcireg.h>
64 #include <bus/pci/pcivar.h>
65 #include <bus/pci/pcidevs.h>
67 #include <dev/netif/bwi/if_bwireg.h>
68 #include <dev/netif/bwi/if_bwivar.h>
69 #include <dev/netif/bwi/bwimac.h>
70 #include <dev/netif/bwi/bwirf.h>
72 struct bwi_clock_freq {
77 struct bwi_myaddr_bssid {
78 uint8_t myaddr[IEEE80211_ADDR_LEN];
79 uint8_t bssid[IEEE80211_ADDR_LEN];
82 static int bwi_probe(device_t);
83 static int bwi_attach(device_t);
84 static int bwi_detach(device_t);
85 static int bwi_shutdown(device_t);
87 static void bwi_init(void *);
88 static int bwi_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
89 static void bwi_start(struct ifnet *);
90 static void bwi_watchdog(struct ifnet *);
91 static int bwi_newstate(struct ieee80211com *, enum ieee80211_state, int);
92 static void bwi_updateslot(struct ifnet *);
93 static int bwi_media_change(struct ifnet *);
94 static void *bwi_ratectl_attach(struct ieee80211com *, u_int);
96 static void bwi_next_scan(void *);
97 static void bwi_calibrate(void *);
99 static void bwi_newstate_begin(struct bwi_softc *, enum ieee80211_state);
100 static void bwi_init_statechg(struct bwi_softc *, int);
101 static int bwi_stop(struct bwi_softc *, int);
102 static int bwi_newbuf(struct bwi_softc *, int, int);
103 static int bwi_encap(struct bwi_softc *, int, struct mbuf *,
104 struct ieee80211_node **, int);
106 static void bwi_init_rxdesc_ring32(struct bwi_softc *, uint32_t,
107 bus_addr_t, int, int);
108 static void bwi_reset_rx_ring32(struct bwi_softc *, uint32_t);
110 static int bwi_init_tx_ring32(struct bwi_softc *, int);
111 static int bwi_init_rx_ring32(struct bwi_softc *);
112 static int bwi_init_txstats32(struct bwi_softc *);
113 static void bwi_free_tx_ring32(struct bwi_softc *, int);
114 static void bwi_free_rx_ring32(struct bwi_softc *);
115 static void bwi_free_txstats32(struct bwi_softc *);
116 static void bwi_setup_rx_desc32(struct bwi_softc *, int, bus_addr_t, int);
117 static void bwi_setup_tx_desc32(struct bwi_softc *, struct bwi_ring_data *,
118 int, bus_addr_t, int);
119 static int bwi_rxeof32(struct bwi_softc *);
120 static void bwi_start_tx32(struct bwi_softc *, uint32_t, int);
121 static void bwi_txeof_status32(struct bwi_softc *);
123 static int bwi_init_tx_ring64(struct bwi_softc *, int);
124 static int bwi_init_rx_ring64(struct bwi_softc *);
125 static int bwi_init_txstats64(struct bwi_softc *);
126 static void bwi_free_tx_ring64(struct bwi_softc *, int);
127 static void bwi_free_rx_ring64(struct bwi_softc *);
128 static void bwi_free_txstats64(struct bwi_softc *);
129 static void bwi_setup_rx_desc64(struct bwi_softc *, int, bus_addr_t, int);
130 static void bwi_setup_tx_desc64(struct bwi_softc *, struct bwi_ring_data *,
131 int, bus_addr_t, int);
132 static int bwi_rxeof64(struct bwi_softc *);
133 static void bwi_start_tx64(struct bwi_softc *, uint32_t, int);
134 static void bwi_txeof_status64(struct bwi_softc *);
136 static void bwi_intr(void *);
137 static int bwi_rxeof(struct bwi_softc *, int);
138 static void _bwi_txeof(struct bwi_softc *, uint16_t, int, int);
139 static void bwi_txeof(struct bwi_softc *);
140 static void bwi_txeof_status(struct bwi_softc *, int);
141 static void bwi_enable_intrs(struct bwi_softc *, uint32_t);
142 static void bwi_disable_intrs(struct bwi_softc *, uint32_t);
143 static int bwi_calc_rssi(struct bwi_softc *, const struct bwi_rxbuf_hdr *);
144 static void bwi_rx_radiotap(struct bwi_softc *, struct mbuf *,
145 struct bwi_rxbuf_hdr *, const void *, int, int);
147 static int bwi_dma_alloc(struct bwi_softc *);
148 static void bwi_dma_free(struct bwi_softc *);
149 static int bwi_dma_ring_alloc(struct bwi_softc *, bus_dma_tag_t,
150 struct bwi_ring_data *, bus_size_t,
152 static int bwi_dma_mbuf_create(struct bwi_softc *);
153 static void bwi_dma_mbuf_destroy(struct bwi_softc *, int, int);
154 static int bwi_dma_txstats_alloc(struct bwi_softc *, uint32_t, bus_size_t);
155 static void bwi_dma_txstats_free(struct bwi_softc *);
156 static void bwi_dma_ring_addr(void *, bus_dma_segment_t *, int, int);
157 static void bwi_dma_buf_addr(void *, bus_dma_segment_t *, int,
160 static void bwi_power_on(struct bwi_softc *, int);
161 static int bwi_power_off(struct bwi_softc *, int);
162 static int bwi_set_clock_mode(struct bwi_softc *, enum bwi_clock_mode);
163 static int bwi_set_clock_delay(struct bwi_softc *);
164 static void bwi_get_clock_freq(struct bwi_softc *, struct bwi_clock_freq *);
165 static int bwi_get_pwron_delay(struct bwi_softc *sc);
166 static void bwi_set_addr_filter(struct bwi_softc *, uint16_t,
168 static void bwi_set_bssid(struct bwi_softc *, const uint8_t *);
169 static int bwi_set_chan(struct bwi_softc *, struct ieee80211_channel *);
171 static void bwi_get_card_flags(struct bwi_softc *);
172 static void bwi_get_eaddr(struct bwi_softc *, uint16_t, uint8_t *);
174 static int bwi_bus_attach(struct bwi_softc *);
175 static int bwi_bbp_attach(struct bwi_softc *);
176 static int bwi_bbp_power_on(struct bwi_softc *, enum bwi_clock_mode);
177 static void bwi_bbp_power_off(struct bwi_softc *);
179 static const char *bwi_regwin_name(const struct bwi_regwin *);
180 static uint32_t bwi_regwin_disable_bits(struct bwi_softc *);
181 static void bwi_regwin_info(struct bwi_softc *, uint16_t *, uint8_t *);
182 static int bwi_regwin_select(struct bwi_softc *, int);
184 static void bwi_led_attach(struct bwi_softc *);
185 static void bwi_led_newstate(struct bwi_softc *, enum ieee80211_state);
186 static void bwi_led_event(struct bwi_softc *, int);
187 static void bwi_led_blink_start(struct bwi_softc *, int, int);
188 static void bwi_led_blink_next(void *);
189 static void bwi_led_blink_end(void *);
191 static const struct bwi_dev {
196 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4301,
197 "Broadcom BCM4301 802.11 Wireless Lan" },
199 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4307,
200 "Broadcom BCM4307 802.11 Wireless Lan" },
202 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4311,
203 "Broadcom BCM4311 802.11 Wireless Lan" },
205 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4312,
206 "Broadcom BCM4312 802.11 Wireless Lan" },
208 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4306_1,
209 "Broadcom BCM4306 802.11 Wireless Lan" },
211 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4306_2,
212 "Broadcom BCM4306 802.11 Wireless Lan" },
214 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4306_3,
215 "Broadcom BCM4306 802.11 Wireless Lan" },
217 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4309,
218 "Broadcom BCM4309 802.11 Wireless Lan" },
220 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4318,
221 "Broadcom BCM4318 802.11 Wireless Lan" },
223 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM4319,
224 "Broadcom BCM4319 802.11 Wireless Lan" }
227 static device_method_t bwi_methods[] = {
228 DEVMETHOD(device_probe, bwi_probe),
229 DEVMETHOD(device_attach, bwi_attach),
230 DEVMETHOD(device_detach, bwi_detach),
231 DEVMETHOD(device_shutdown, bwi_shutdown),
233 DEVMETHOD(device_suspend, bwi_suspend),
234 DEVMETHOD(device_resume, bwi_resume),
239 static driver_t bwi_driver = {
242 sizeof(struct bwi_softc)
245 static devclass_t bwi_devclass;
247 DRIVER_MODULE(bwi, pci, bwi_driver, bwi_devclass, 0, 0);
248 DRIVER_MODULE(bwi, cardbus, bwi_driver, bwi_devclass, 0, 0);
250 MODULE_DEPEND(bwi, wlan, 1, 1, 1);
251 MODULE_DEPEND(bwi, wlan_ratectl_onoe, 1, 1, 1);
253 MODULE_DEPEND(bwi, wlan_ratectl_amrr, 1, 1, 1);
255 MODULE_DEPEND(bwi, pci, 1, 1, 1);
256 MODULE_DEPEND(bwi, cardbus, 1, 1, 1);
258 static const struct {
262 } bwi_bbpid_map[] = {
263 { 0x4301, 0x4301, 0x4301 },
264 { 0x4305, 0x4307, 0x4307 },
265 { 0x4403, 0x4403, 0x4402 },
266 { 0x4610, 0x4615, 0x4610 },
267 { 0x4710, 0x4715, 0x4710 },
268 { 0x4720, 0x4725, 0x4309 }
271 static const struct {
274 } bwi_regwin_count[] = {
287 #define CLKSRC(src) \
288 [BWI_CLKSRC_ ## src] = { \
289 .freq_min = BWI_CLKSRC_ ##src## _FMIN, \
290 .freq_max = BWI_CLKSRC_ ##src## _FMAX \
293 static const struct {
296 } bwi_clkfreq[BWI_CLKSRC_MAX] = {
304 #define VENDOR_LED_ACT(vendor) \
306 .vid = PCI_VENDOR_##vendor, \
307 .led_act = { BWI_VENDOR_LED_ACT_##vendor } \
310 static const struct {
312 uint8_t led_act[BWI_LED_MAX];
313 } bwi_vendor_led_act[] = {
314 VENDOR_LED_ACT(COMPAQ),
315 VENDOR_LED_ACT(LINKSYS)
318 static const uint8_t bwi_default_led_act[BWI_LED_MAX] =
319 { BWI_VENDOR_LED_ACT_DEFAULT };
321 #undef VENDOR_LED_ACT
323 static const struct {
326 } bwi_led_duration[109] = {
343 #ifdef BWI_DEBUG_VERBOSE
344 static uint32_t bwi_debug = BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_TXPOWER;
346 static uint32_t bwi_debug;
348 TUNABLE_INT("hw.bwi.debug", (int *)&bwi_debug);
349 #endif /* BWI_DEBUG */
351 static const uint8_t bwi_zero_addr[IEEE80211_ADDR_LEN];
353 static const struct ieee80211_rateset bwi_rateset_11b =
354 { 4, { 2, 4, 11, 22 } };
355 static const struct ieee80211_rateset bwi_rateset_11g =
356 { 12, { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 } };
359 bwi_read_sprom(struct bwi_softc *sc, uint16_t ofs)
361 return CSR_READ_2(sc, ofs + BWI_SPROM_START);
365 bwi_setup_desc32(struct bwi_softc *sc, struct bwi_desc32 *desc_array,
366 int ndesc, int desc_idx, bus_addr_t paddr, int buf_len,
369 struct bwi_desc32 *desc = &desc_array[desc_idx];
370 uint32_t ctrl, addr, addr_hi, addr_lo;
372 addr_lo = __SHIFTOUT(paddr, BWI_DESC32_A_ADDR_MASK);
373 addr_hi = __SHIFTOUT(paddr, BWI_DESC32_A_FUNC_MASK);
375 addr = __SHIFTIN(addr_lo, BWI_DESC32_A_ADDR_MASK) |
376 __SHIFTIN(BWI_DESC32_A_FUNC_TXRX, BWI_DESC32_A_FUNC_MASK);
378 ctrl = __SHIFTIN(buf_len, BWI_DESC32_C_BUFLEN_MASK) |
379 __SHIFTIN(addr_hi, BWI_DESC32_C_ADDRHI_MASK);
380 if (desc_idx == ndesc - 1)
381 ctrl |= BWI_DESC32_C_EOR;
384 ctrl |= BWI_DESC32_C_FRAME_START |
385 BWI_DESC32_C_FRAME_END |
389 desc->addr = htole32(addr);
390 desc->ctrl = htole32(ctrl);
393 /* XXX does not belong here */
395 bwi_rate2plcp(uint8_t rate)
397 rate &= IEEE80211_RATE_VAL;
402 case 11: return 0x37;
403 case 22: return 0x6e;
404 case 44: return 0xdc;
413 case 108: return 0xc;
416 panic("unsupported rate %u\n", rate);
420 /* XXX does not belong here */
421 #define IEEE80211_OFDM_PLCP_RATE_MASK __BITS(3, 0)
422 #define IEEE80211_OFDM_PLCP_LEN_MASK __BITS(16, 5)
425 bwi_ofdm_plcp_header(uint32_t *plcp0, int pkt_len, uint8_t rate)
429 plcp = __SHIFTIN(bwi_rate2plcp(rate), IEEE80211_OFDM_PLCP_RATE_MASK) |
430 __SHIFTIN(pkt_len, IEEE80211_OFDM_PLCP_LEN_MASK);
431 *plcp0 = htole32(plcp);
434 /* XXX does not belong here */
435 struct ieee80211_ds_plcp_hdr {
442 #define IEEE80211_DS_PLCP_SERVICE_LOCKED 0x04
443 #define IEEE80211_DS_PLCL_SERVICE_PBCC 0x08
444 #define IEEE80211_DS_PLCP_SERVICE_LENEXT5 0x20
445 #define IEEE80211_DS_PLCP_SERVICE_LENEXT6 0x40
446 #define IEEE80211_DS_PLCP_SERVICE_LENEXT7 0x80
449 bwi_ds_plcp_header(struct ieee80211_ds_plcp_hdr *plcp, int pkt_len,
452 int len, service, pkt_bitlen;
454 pkt_bitlen = pkt_len * NBBY;
455 len = howmany(pkt_bitlen * 2, rate);
457 service = IEEE80211_DS_PLCP_SERVICE_LOCKED;
458 if (rate == (11 * 2)) {
462 * PLCP service field needs to be adjusted,
463 * if TX rate is 11Mbytes/s
465 pkt_bitlen1 = len * 11;
466 if (pkt_bitlen1 - pkt_bitlen >= NBBY)
467 service |= IEEE80211_DS_PLCP_SERVICE_LENEXT7;
470 plcp->i_signal = bwi_rate2plcp(rate);
471 plcp->i_service = service;
472 plcp->i_length = htole16(len);
473 /* NOTE: do NOT touch i_crc */
477 bwi_plcp_header(void *plcp, int pkt_len, uint8_t rate)
479 enum ieee80211_modtype modtype;
482 * Assume caller has zeroed 'plcp'
485 modtype = ieee80211_rate2modtype(rate);
486 if (modtype == IEEE80211_MODTYPE_OFDM)
487 bwi_ofdm_plcp_header(plcp, pkt_len, rate);
488 else if (modtype == IEEE80211_MODTYPE_DS)
489 bwi_ds_plcp_header(plcp, pkt_len, rate);
491 panic("unsupport modulation type %u\n", modtype);
494 static __inline uint8_t
495 bwi_ofdm_plcp2rate(const uint32_t *plcp0)
500 plcp = le32toh(*plcp0);
501 plcp_rate = __SHIFTOUT(plcp, IEEE80211_OFDM_PLCP_RATE_MASK);
502 return ieee80211_plcp2rate(plcp_rate, 1);
505 static __inline uint8_t
506 bwi_ds_plcp2rate(const struct ieee80211_ds_plcp_hdr *hdr)
508 return ieee80211_plcp2rate(hdr->i_signal, 0);
512 bwi_probe(device_t dev)
514 const struct bwi_dev *b;
517 did = pci_get_device(dev);
518 vid = pci_get_vendor(dev);
520 for (b = bwi_devices; b->desc != NULL; ++b) {
521 if (b->did == did && b->vid == vid) {
522 device_set_desc(dev, b->desc);
530 bwi_attach(device_t dev)
532 struct bwi_softc *sc = device_get_softc(dev);
533 struct ieee80211com *ic = &sc->sc_ic;
534 struct ifnet *ifp = &ic->ic_if;
539 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
543 * Initialize sysctl variables
545 sc->sc_fw_version = BWI_FW_VERSION3;
546 sc->sc_dwell_time = 200;
547 sc->sc_led_idle = (2350 * hz) / 1000;
548 sc->sc_led_blink = 1;
549 sc->sc_txpwr_calib = 1;
551 sc->sc_debug = bwi_debug;
554 callout_init(&sc->sc_scan_ch);
555 callout_init(&sc->sc_calib_ch);
558 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
561 /* XXX Save more PCIR */
562 irq = pci_read_config(dev, PCIR_INTLINE, 4);
563 mem = pci_read_config(dev, BWI_PCIR_BAR, 4);
565 device_printf(dev, "chip is in D%d power mode "
566 "-- setting to D0\n", pci_get_powerstate(dev));
568 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
570 pci_write_config(dev, PCIR_INTLINE, irq, 4);
571 pci_write_config(dev, BWI_PCIR_BAR, mem, 4);
573 #endif /* !BURN_BRIDGE */
575 pci_enable_busmaster(dev);
577 /* Get more PCI information */
578 sc->sc_pci_revid = pci_get_revid(dev);
579 sc->sc_pci_subvid = pci_get_subvendor(dev);
580 sc->sc_pci_subdid = pci_get_subdevice(dev);
585 sc->sc_mem_rid = BWI_PCIR_BAR;
586 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
587 &sc->sc_mem_rid, RF_ACTIVE);
588 if (sc->sc_mem_res == NULL) {
589 device_printf(dev, "can't allocate IO memory\n");
592 sc->sc_mem_bt = rman_get_bustag(sc->sc_mem_res);
593 sc->sc_mem_bh = rman_get_bushandle(sc->sc_mem_res);
599 sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
601 RF_SHAREABLE | RF_ACTIVE);
602 if (sc->sc_irq_res == NULL) {
603 device_printf(dev, "can't allocate irq\n");
611 sysctl_ctx_init(&sc->sc_sysctl_ctx);
612 sc->sc_sysctl_tree = SYSCTL_ADD_NODE(&sc->sc_sysctl_ctx,
613 SYSCTL_STATIC_CHILDREN(_hw),
615 device_get_nameunit(dev),
617 if (sc->sc_sysctl_tree == NULL) {
618 device_printf(dev, "can't add sysctl node\n");
623 SYSCTL_ADD_UINT(&sc->sc_sysctl_ctx,
624 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
625 "dwell_time", CTLFLAG_RW, &sc->sc_dwell_time, 0,
626 "Channel dwell time during scan (msec)");
627 SYSCTL_ADD_UINT(&sc->sc_sysctl_ctx,
628 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
629 "fw_version", CTLFLAG_RD, &sc->sc_fw_version, 0,
631 SYSCTL_ADD_UINT(&sc->sc_sysctl_ctx,
632 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
633 "led_idle", CTLFLAG_RW, &sc->sc_led_idle, 0,
634 "# ticks before LED enters idle state");
635 SYSCTL_ADD_INT(&sc->sc_sysctl_ctx,
636 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
637 "led_blink", CTLFLAG_RW, &sc->sc_led_blink, 0,
638 "Allow LED to blink");
639 SYSCTL_ADD_INT(&sc->sc_sysctl_ctx,
640 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
641 "txpwr_calib", CTLFLAG_RW, &sc->sc_txpwr_calib, 0,
642 "Enable software TX power calibration");
644 SYSCTL_ADD_UINT(&sc->sc_sysctl_ctx,
645 SYSCTL_CHILDREN(sc->sc_sysctl_tree), OID_AUTO,
646 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "Debug flags");
651 error = bwi_bbp_attach(sc);
655 error = bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST);
659 if (BWI_REGWIN_EXIST(&sc->sc_com_regwin)) {
660 error = bwi_set_clock_delay(sc);
664 error = bwi_set_clock_mode(sc, BWI_CLOCK_MODE_FAST);
668 error = bwi_get_pwron_delay(sc);
673 error = bwi_bus_attach(sc);
677 bwi_get_card_flags(sc);
681 for (i = 0; i < sc->sc_nmac; ++i) {
682 struct bwi_regwin *old;
684 mac = &sc->sc_mac[i];
685 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old);
689 error = bwi_mac_lateattach(mac);
693 error = bwi_regwin_switch(sc, old, NULL);
699 * XXX First MAC is known to exist
702 mac = &sc->sc_mac[0];
705 bwi_bbp_power_off(sc);
707 error = bwi_dma_alloc(sc);
712 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
713 ifp->if_init = bwi_init;
714 ifp->if_ioctl = bwi_ioctl;
715 ifp->if_start = bwi_start;
716 ifp->if_watchdog = bwi_watchdog;
717 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN);
718 ifq_set_ready(&ifp->if_snd);
721 sc->sc_locale = __SHIFTOUT(bwi_read_sprom(sc, BWI_SPROM_CARD_INFO),
722 BWI_SPROM_CARD_INFO_LOCALE);
723 DPRINTF(sc, BWI_DBG_ATTACH, "locale: %d\n", sc->sc_locale);
726 * Setup ratesets, phytype, channels and get MAC address
728 if (phy->phy_mode == IEEE80211_MODE_11B ||
729 phy->phy_mode == IEEE80211_MODE_11G) {
732 ic->ic_sup_rates[IEEE80211_MODE_11B] = bwi_rateset_11b;
734 if (phy->phy_mode == IEEE80211_MODE_11B) {
735 chan_flags = IEEE80211_CHAN_B;
736 ic->ic_phytype = IEEE80211_T_DS;
738 chan_flags = IEEE80211_CHAN_CCK |
739 IEEE80211_CHAN_OFDM |
742 ic->ic_phytype = IEEE80211_T_OFDM;
743 ic->ic_sup_rates[IEEE80211_MODE_11G] =
747 /* XXX depend on locale */
748 for (i = 1; i <= 14; ++i) {
749 ic->ic_channels[i].ic_freq =
750 ieee80211_ieee2mhz(i, IEEE80211_CHAN_2GHZ);
751 ic->ic_channels[i].ic_flags = chan_flags;
754 bwi_get_eaddr(sc, BWI_SPROM_11BG_EADDR, ic->ic_myaddr);
755 if (IEEE80211_IS_MULTICAST(ic->ic_myaddr)) {
756 bwi_get_eaddr(sc, BWI_SPROM_11A_EADDR, ic->ic_myaddr);
757 if (IEEE80211_IS_MULTICAST(ic->ic_myaddr)) {
758 device_printf(dev, "invalid MAC address: "
759 "%6D\n", ic->ic_myaddr, ":");
762 } else if (phy->phy_mode == IEEE80211_MODE_11A) {
767 panic("unknown phymode %d\n", phy->phy_mode);
770 ic->ic_caps = IEEE80211_C_SHSLOT |
771 IEEE80211_C_SHPREAMBLE |
774 ic->ic_state = IEEE80211_S_INIT;
775 ic->ic_opmode = IEEE80211_M_STA;
777 IEEE80211_ONOE_PARAM_SETUP(&sc->sc_onoe_param);
778 ic->ic_ratectl.rc_st_ratectl_cap = IEEE80211_RATECTL_CAP_ONOE;
779 ic->ic_ratectl.rc_st_ratectl = IEEE80211_RATECTL_ONOE;
780 ic->ic_ratectl.rc_st_attach = bwi_ratectl_attach;
782 ic->ic_updateslot = bwi_updateslot;
784 ieee80211_ifattach(ic);
786 ic->ic_headroom = sizeof(struct bwi_txbuf_hdr);
787 ic->ic_flags_ext |= IEEE80211_FEXT_SWBMISS;
789 sc->sc_newstate = ic->ic_newstate;
790 ic->ic_newstate = bwi_newstate;
792 ieee80211_media_init(ic, bwi_media_change, ieee80211_media_status);
797 bpfattach_dlt(ifp, DLT_IEEE802_11_RADIO,
798 sizeof(struct ieee80211_frame) + sizeof(sc->sc_tx_th),
801 sc->sc_tx_th_len = roundup(sizeof(sc->sc_tx_th), sizeof(uint32_t));
802 sc->sc_tx_th.wt_ihdr.it_len = htole16(sc->sc_tx_th_len);
803 sc->sc_tx_th.wt_ihdr.it_present = htole32(BWI_TX_RADIOTAP_PRESENT);
805 sc->sc_rx_th_len = roundup(sizeof(sc->sc_rx_th), sizeof(uint32_t));
806 sc->sc_rx_th.wr_ihdr.it_len = htole16(sc->sc_rx_th_len);
807 sc->sc_rx_th.wr_ihdr.it_present = htole32(BWI_RX_RADIOTAP_PRESENT);
809 error = bus_setup_intr(dev, sc->sc_irq_res, INTR_MPSAFE, bwi_intr, sc,
810 &sc->sc_irq_handle, ifp->if_serializer);
812 device_printf(dev, "can't setup intr\n");
814 ieee80211_ifdetach(ic);
818 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->sc_irq_res));
819 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
822 ieee80211_announce(ic);
831 bwi_detach(device_t dev)
833 struct bwi_softc *sc = device_get_softc(dev);
835 if (device_is_attached(dev)) {
836 struct ifnet *ifp = &sc->sc_ic.ic_if;
839 lwkt_serialize_enter(ifp->if_serializer);
841 bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_handle);
842 lwkt_serialize_exit(ifp->if_serializer);
845 ieee80211_ifdetach(&sc->sc_ic);
847 for (i = 0; i < sc->sc_nmac; ++i)
848 bwi_mac_detach(&sc->sc_mac[i]);
851 if (sc->sc_sysctl_tree != NULL)
852 sysctl_ctx_free(&sc->sc_sysctl_ctx);
854 if (sc->sc_irq_res != NULL) {
855 bus_release_resource(dev, SYS_RES_IRQ, sc->sc_irq_rid,
859 if (sc->sc_mem_res != NULL) {
860 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid,
870 bwi_shutdown(device_t dev)
872 struct bwi_softc *sc = device_get_softc(dev);
873 struct ifnet *ifp = &sc->sc_ic.ic_if;
875 lwkt_serialize_enter(ifp->if_serializer);
877 lwkt_serialize_exit(ifp->if_serializer);
882 bwi_power_on(struct bwi_softc *sc, int with_pll)
884 uint32_t gpio_in, gpio_out, gpio_en;
887 gpio_in = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4);
888 if (gpio_in & BWI_PCIM_GPIO_PWR_ON)
891 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
892 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4);
894 gpio_out |= BWI_PCIM_GPIO_PWR_ON;
895 gpio_en |= BWI_PCIM_GPIO_PWR_ON;
897 /* Turn off PLL first */
898 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF;
899 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF;
902 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
903 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4);
908 gpio_out &= ~BWI_PCIM_GPIO_PLL_PWR_OFF;
909 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
914 /* Clear "Signaled Target Abort" */
915 status = pci_read_config(sc->sc_dev, PCIR_STATUS, 2);
916 status &= ~PCIM_STATUS_STABORT;
917 pci_write_config(sc->sc_dev, PCIR_STATUS, status, 2);
921 bwi_power_off(struct bwi_softc *sc, int with_pll)
923 uint32_t gpio_out, gpio_en;
925 pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4); /* dummy read */
926 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
927 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4);
929 gpio_out &= ~BWI_PCIM_GPIO_PWR_ON;
930 gpio_en |= BWI_PCIM_GPIO_PWR_ON;
932 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF;
933 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF;
936 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
937 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4);
942 bwi_regwin_switch(struct bwi_softc *sc, struct bwi_regwin *rw,
943 struct bwi_regwin **old_rw)
950 if (!BWI_REGWIN_EXIST(rw))
953 if (sc->sc_cur_regwin != rw) {
954 error = bwi_regwin_select(sc, rw->rw_id);
956 if_printf(&sc->sc_ic.ic_if, "can't select regwin %d\n",
963 *old_rw = sc->sc_cur_regwin;
964 sc->sc_cur_regwin = rw;
969 bwi_regwin_select(struct bwi_softc *sc, int id)
971 uint32_t win = BWI_PCIM_REGWIN(id);
975 for (i = 0; i < RETRY_MAX; ++i) {
976 pci_write_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, win, 4);
977 if (pci_read_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, 4) == win)
987 bwi_regwin_info(struct bwi_softc *sc, uint16_t *type, uint8_t *rev)
991 val = CSR_READ_4(sc, BWI_ID_HI);
992 *type = BWI_ID_HI_REGWIN_TYPE(val);
993 *rev = BWI_ID_HI_REGWIN_REV(val);
995 DPRINTF(sc, BWI_DBG_ATTACH, "regwin: type 0x%03x, rev %d, "
996 "vendor 0x%04x\n", *type, *rev,
997 __SHIFTOUT(val, BWI_ID_HI_REGWIN_VENDOR_MASK));
1001 bwi_bbp_attach(struct bwi_softc *sc)
1003 #define N(arr) (int)(sizeof(arr) / sizeof(arr[0]))
1004 uint16_t bbp_id, rw_type;
1007 int error, nregwin, i;
1010 * Get 0th regwin information
1011 * NOTE: 0th regwin should exist
1013 error = bwi_regwin_select(sc, 0);
1015 device_printf(sc->sc_dev, "can't select regwin 0\n");
1018 bwi_regwin_info(sc, &rw_type, &rw_rev);
1025 if (rw_type == BWI_REGWIN_T_COM) {
1026 info = CSR_READ_4(sc, BWI_INFO);
1027 bbp_id = __SHIFTOUT(info, BWI_INFO_BBPID_MASK);
1029 BWI_CREATE_REGWIN(&sc->sc_com_regwin, 0, rw_type, rw_rev);
1031 sc->sc_cap = CSR_READ_4(sc, BWI_CAPABILITY);
1033 uint16_t did = pci_get_device(sc->sc_dev);
1034 uint8_t revid = pci_get_revid(sc->sc_dev);
1036 for (i = 0; i < N(bwi_bbpid_map); ++i) {
1037 if (did >= bwi_bbpid_map[i].did_min &&
1038 did <= bwi_bbpid_map[i].did_max) {
1039 bbp_id = bwi_bbpid_map[i].bbp_id;
1044 device_printf(sc->sc_dev, "no BBP id for device id "
1049 info = __SHIFTIN(revid, BWI_INFO_BBPREV_MASK) |
1050 __SHIFTIN(0, BWI_INFO_BBPPKG_MASK);
1054 * Find out number of regwins
1057 if (rw_type == BWI_REGWIN_T_COM && rw_rev >= 4) {
1058 nregwin = __SHIFTOUT(info, BWI_INFO_NREGWIN_MASK);
1060 for (i = 0; i < N(bwi_regwin_count); ++i) {
1061 if (bwi_regwin_count[i].bbp_id == bbp_id) {
1062 nregwin = bwi_regwin_count[i].nregwin;
1067 device_printf(sc->sc_dev, "no number of win for "
1068 "BBP id 0x%04x\n", bbp_id);
1073 /* Record BBP id/rev for later using */
1074 sc->sc_bbp_id = bbp_id;
1075 sc->sc_bbp_rev = __SHIFTOUT(info, BWI_INFO_BBPREV_MASK);
1076 sc->sc_bbp_pkg = __SHIFTOUT(info, BWI_INFO_BBPPKG_MASK);
1077 device_printf(sc->sc_dev, "BBP: id 0x%04x, rev 0x%x, pkg %d\n",
1078 sc->sc_bbp_id, sc->sc_bbp_rev, sc->sc_bbp_pkg);
1080 DPRINTF(sc, BWI_DBG_ATTACH, "nregwin %d, cap 0x%08x\n",
1081 nregwin, sc->sc_cap);
1084 * Create rest of the regwins
1087 /* Don't re-create common regwin, if it is already created */
1088 i = BWI_REGWIN_EXIST(&sc->sc_com_regwin) ? 1 : 0;
1090 for (; i < nregwin; ++i) {
1092 * Get regwin information
1094 error = bwi_regwin_select(sc, i);
1096 device_printf(sc->sc_dev,
1097 "can't select regwin %d\n", i);
1100 bwi_regwin_info(sc, &rw_type, &rw_rev);
1104 * 1) Bus (PCI/PCIE) regwin
1106 * Ignore rest types of regwin
1108 if (rw_type == BWI_REGWIN_T_BUSPCI ||
1109 rw_type == BWI_REGWIN_T_BUSPCIE) {
1110 if (BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) {
1111 device_printf(sc->sc_dev,
1112 "bus regwin already exists\n");
1114 BWI_CREATE_REGWIN(&sc->sc_bus_regwin, i,
1117 } else if (rw_type == BWI_REGWIN_T_MAC) {
1118 /* XXX ignore return value */
1119 bwi_mac_attach(sc, i, rw_rev);
1123 /* At least one MAC shold exist */
1124 if (!BWI_REGWIN_EXIST(&sc->sc_mac[0].mac_regwin)) {
1125 device_printf(sc->sc_dev, "no MAC was found\n");
1128 KKASSERT(sc->sc_nmac > 0);
1130 /* Bus regwin must exist */
1131 if (!BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) {
1132 device_printf(sc->sc_dev, "no bus regwin was found\n");
1136 /* Start with first MAC */
1137 error = bwi_regwin_switch(sc, &sc->sc_mac[0].mac_regwin, NULL);
1146 bwi_bus_init(struct bwi_softc *sc, struct bwi_mac *mac)
1148 struct bwi_regwin *old, *bus;
1152 bus = &sc->sc_bus_regwin;
1153 KKASSERT(sc->sc_cur_regwin == &mac->mac_regwin);
1156 * Tell bus to generate requested interrupts
1158 if (bus->rw_rev < 6 && bus->rw_type == BWI_REGWIN_T_BUSPCI) {
1160 * NOTE: Read BWI_FLAGS from MAC regwin
1162 val = CSR_READ_4(sc, BWI_FLAGS);
1164 error = bwi_regwin_switch(sc, bus, &old);
1168 CSR_SETBITS_4(sc, BWI_INTRVEC, (val & BWI_FLAGS_INTR_MASK));
1172 mac_mask = 1 << mac->mac_id;
1174 error = bwi_regwin_switch(sc, bus, &old);
1178 val = pci_read_config(sc->sc_dev, BWI_PCIR_INTCTL, 4);
1179 val |= mac_mask << 8;
1180 pci_write_config(sc->sc_dev, BWI_PCIR_INTCTL, val, 4);
1183 if (sc->sc_flags & BWI_F_BUS_INITED)
1186 if (bus->rw_type == BWI_REGWIN_T_BUSPCI) {
1188 * Enable prefetch and burst
1190 CSR_SETBITS_4(sc, BWI_BUS_CONFIG,
1191 BWI_BUS_CONFIG_PREFETCH | BWI_BUS_CONFIG_BURST);
1193 if (bus->rw_rev < 5) {
1194 struct bwi_regwin *com = &sc->sc_com_regwin;
1197 * Configure timeouts for bus operation
1201 * Set service timeout and request timeout
1203 CSR_SETBITS_4(sc, BWI_CONF_LO,
1204 __SHIFTIN(BWI_CONF_LO_SERVTO, BWI_CONF_LO_SERVTO_MASK) |
1205 __SHIFTIN(BWI_CONF_LO_REQTO, BWI_CONF_LO_REQTO_MASK));
1208 * If there is common regwin, we switch to that regwin
1209 * and switch back to bus regwin once we have done.
1211 if (BWI_REGWIN_EXIST(com)) {
1212 error = bwi_regwin_switch(sc, com, NULL);
1217 /* Let bus know what we have changed */
1218 CSR_WRITE_4(sc, BWI_BUS_ADDR, BWI_BUS_ADDR_MAGIC);
1219 CSR_READ_4(sc, BWI_BUS_ADDR); /* Flush */
1220 CSR_WRITE_4(sc, BWI_BUS_DATA, 0);
1221 CSR_READ_4(sc, BWI_BUS_DATA); /* Flush */
1223 if (BWI_REGWIN_EXIST(com)) {
1224 error = bwi_regwin_switch(sc, bus, NULL);
1228 } else if (bus->rw_rev >= 11) {
1230 * Enable memory read multiple
1232 CSR_SETBITS_4(sc, BWI_BUS_CONFIG, BWI_BUS_CONFIG_MRM);
1238 sc->sc_flags |= BWI_F_BUS_INITED;
1240 return bwi_regwin_switch(sc, old, NULL);
1244 bwi_get_card_flags(struct bwi_softc *sc)
1246 sc->sc_card_flags = bwi_read_sprom(sc, BWI_SPROM_CARD_FLAGS);
1247 if (sc->sc_card_flags == 0xffff)
1248 sc->sc_card_flags = 0;
1250 if (sc->sc_pci_subvid == PCI_VENDOR_APPLE &&
1251 sc->sc_pci_subdid == 0x4e && /* XXX */
1252 sc->sc_pci_revid > 0x40)
1253 sc->sc_card_flags |= BWI_CARD_F_PA_GPIO9;
1255 DPRINTF(sc, BWI_DBG_ATTACH, "card flags 0x%04x\n", sc->sc_card_flags);
1259 bwi_get_eaddr(struct bwi_softc *sc, uint16_t eaddr_ofs, uint8_t *eaddr)
1263 for (i = 0; i < 3; ++i) {
1264 *((uint16_t *)eaddr + i) =
1265 htobe16(bwi_read_sprom(sc, eaddr_ofs + 2 * i));
1270 bwi_get_clock_freq(struct bwi_softc *sc, struct bwi_clock_freq *freq)
1272 struct bwi_regwin *com;
1277 bzero(freq, sizeof(*freq));
1278 com = &sc->sc_com_regwin;
1280 KKASSERT(BWI_REGWIN_EXIST(com));
1281 KKASSERT(sc->sc_cur_regwin == com);
1282 KKASSERT(sc->sc_cap & BWI_CAP_CLKMODE);
1285 * Calculate clock frequency
1289 if (com->rw_rev < 6) {
1290 val = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
1291 if (val & BWI_PCIM_GPIO_OUT_CLKSRC) {
1292 src = BWI_CLKSRC_PCI;
1295 src = BWI_CLKSRC_CS_OSC;
1298 } else if (com->rw_rev < 10) {
1299 val = CSR_READ_4(sc, BWI_CLOCK_CTRL);
1301 src = __SHIFTOUT(val, BWI_CLOCK_CTRL_CLKSRC);
1302 if (src == BWI_CLKSRC_LP_OSC) {
1305 div = (__SHIFTOUT(val, BWI_CLOCK_CTRL_FDIV) + 1) << 2;
1307 /* Unknown source */
1308 if (src >= BWI_CLKSRC_MAX)
1309 src = BWI_CLKSRC_CS_OSC;
1312 val = CSR_READ_4(sc, BWI_CLOCK_INFO);
1314 src = BWI_CLKSRC_CS_OSC;
1315 div = (__SHIFTOUT(val, BWI_CLOCK_INFO_FDIV) + 1) << 2;
1318 KKASSERT(src >= 0 && src < BWI_CLKSRC_MAX);
1321 DPRINTF(sc, BWI_DBG_ATTACH, "clksrc %s\n",
1322 src == BWI_CLKSRC_PCI ? "PCI" :
1323 (src == BWI_CLKSRC_LP_OSC ? "LP_OSC" : "CS_OSC"));
1325 freq->clkfreq_min = bwi_clkfreq[src].freq_min / div;
1326 freq->clkfreq_max = bwi_clkfreq[src].freq_max / div;
1328 DPRINTF(sc, BWI_DBG_ATTACH, "clkfreq min %u, max %u\n",
1329 freq->clkfreq_min, freq->clkfreq_max);
1333 bwi_set_clock_mode(struct bwi_softc *sc, enum bwi_clock_mode clk_mode)
1335 struct bwi_regwin *old, *com;
1336 uint32_t clk_ctrl, clk_src;
1337 int error, pwr_off = 0;
1339 com = &sc->sc_com_regwin;
1340 if (!BWI_REGWIN_EXIST(com))
1343 if (com->rw_rev >= 10 || com->rw_rev < 6)
1347 * For common regwin whose rev is [6, 10), the chip
1348 * must be capable to change clock mode.
1350 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0)
1353 error = bwi_regwin_switch(sc, com, &old);
1357 if (clk_mode == BWI_CLOCK_MODE_FAST)
1358 bwi_power_on(sc, 0); /* Don't turn on PLL */
1360 clk_ctrl = CSR_READ_4(sc, BWI_CLOCK_CTRL);
1361 clk_src = __SHIFTOUT(clk_ctrl, BWI_CLOCK_CTRL_CLKSRC);
1364 case BWI_CLOCK_MODE_FAST:
1365 clk_ctrl &= ~BWI_CLOCK_CTRL_SLOW;
1366 clk_ctrl |= BWI_CLOCK_CTRL_IGNPLL;
1368 case BWI_CLOCK_MODE_SLOW:
1369 clk_ctrl |= BWI_CLOCK_CTRL_SLOW;
1371 case BWI_CLOCK_MODE_DYN:
1372 clk_ctrl &= ~(BWI_CLOCK_CTRL_SLOW |
1373 BWI_CLOCK_CTRL_IGNPLL |
1374 BWI_CLOCK_CTRL_NODYN);
1375 if (clk_src != BWI_CLKSRC_CS_OSC) {
1376 clk_ctrl |= BWI_CLOCK_CTRL_NODYN;
1381 CSR_WRITE_4(sc, BWI_CLOCK_CTRL, clk_ctrl);
1384 bwi_power_off(sc, 0); /* Leave PLL as it is */
1386 return bwi_regwin_switch(sc, old, NULL);
1390 bwi_set_clock_delay(struct bwi_softc *sc)
1392 struct bwi_regwin *old, *com;
1395 com = &sc->sc_com_regwin;
1396 if (!BWI_REGWIN_EXIST(com))
1399 error = bwi_regwin_switch(sc, com, &old);
1403 if (sc->sc_bbp_id == BWI_BBPID_BCM4321) {
1404 if (sc->sc_bbp_rev == 0)
1405 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC0);
1406 else if (sc->sc_bbp_rev == 1)
1407 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC1);
1410 if (sc->sc_cap & BWI_CAP_CLKMODE) {
1411 if (com->rw_rev >= 10) {
1412 CSR_FILT_SETBITS_4(sc, BWI_CLOCK_INFO, 0xffff, 0x40000);
1414 struct bwi_clock_freq freq;
1416 bwi_get_clock_freq(sc, &freq);
1417 CSR_WRITE_4(sc, BWI_PLL_ON_DELAY,
1418 howmany(freq.clkfreq_max * 150, 1000000));
1419 CSR_WRITE_4(sc, BWI_FREQ_SEL_DELAY,
1420 howmany(freq.clkfreq_max * 15, 1000000));
1424 return bwi_regwin_switch(sc, old, NULL);
1430 bwi_init_statechg(xsc, 1);
1434 bwi_init_statechg(struct bwi_softc *sc, int statechg)
1436 struct ieee80211com *ic = &sc->sc_ic;
1437 struct ifnet *ifp = &ic->ic_if;
1438 struct bwi_mac *mac;
1441 ASSERT_SERIALIZED(ifp->if_serializer);
1443 error = bwi_stop(sc, statechg);
1445 if_printf(ifp, "can't stop\n");
1449 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST);
1453 mac = &sc->sc_mac[0];
1454 error = bwi_regwin_switch(sc, &mac->mac_regwin, NULL);
1458 error = bwi_mac_init(mac);
1462 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_DYN);
1464 bcopy(IF_LLADDR(ifp), ic->ic_myaddr, sizeof(ic->ic_myaddr));
1466 bwi_set_bssid(sc, bwi_zero_addr); /* Clear BSSID */
1467 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_MYADDR, ic->ic_myaddr);
1469 bwi_mac_reset_hwkeys(mac);
1471 if ((mac->mac_flags & BWI_MAC_F_HAS_TXSTATS) == 0) {
1476 * Drain any possible pending TX status
1478 for (i = 0; i < NRETRY; ++i) {
1479 if ((CSR_READ_4(sc, BWI_TXSTATUS0) &
1480 BWI_TXSTATUS0_VALID) == 0)
1482 CSR_READ_4(sc, BWI_TXSTATUS1);
1485 if_printf(ifp, "can't drain TX status\n");
1489 if (mac->mac_phy.phy_mode == IEEE80211_MODE_11G)
1490 bwi_mac_updateslot(mac, 1);
1493 error = bwi_mac_start(mac);
1498 bwi_enable_intrs(sc, BWI_INIT_INTRS);
1500 ifp->if_flags |= IFF_RUNNING;
1501 ifp->if_flags &= ~IFF_OACTIVE;
1504 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
1505 if (ic->ic_roaming != IEEE80211_ROAMING_MANUAL)
1506 ieee80211_new_state(ic, IEEE80211_S_SCAN, -1);
1508 ieee80211_new_state(ic, IEEE80211_S_RUN, -1);
1511 ieee80211_new_state(ic, ic->ic_state, -1);
1521 bwi_ioctl(struct ifnet *ifp, u_long cmd, caddr_t req, struct ucred *cr)
1523 struct bwi_softc *sc = ifp->if_softc;
1526 ASSERT_SERIALIZED(ifp->if_serializer);
1530 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) ==
1531 (IFF_UP | IFF_RUNNING)) {
1532 struct bwi_mac *mac;
1535 KKASSERT(sc->sc_cur_regwin->rw_type ==
1537 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1539 if ((ifp->if_flags & IFF_PROMISC) &&
1540 (sc->sc_flags & BWI_F_PROMISC) == 0) {
1542 sc->sc_flags |= BWI_F_PROMISC;
1543 } else if ((ifp->if_flags & IFF_PROMISC) == 0 &&
1544 (sc->sc_flags & BWI_F_PROMISC)) {
1546 sc->sc_flags &= ~BWI_F_PROMISC;
1550 bwi_mac_set_promisc(mac, promisc);
1553 if (ifp->if_flags & IFF_UP) {
1554 if ((ifp->if_flags & IFF_RUNNING) == 0)
1557 if (ifp->if_flags & IFF_RUNNING)
1562 error = ieee80211_ioctl(&sc->sc_ic, cmd, req, cr);
1566 if (error == ENETRESET) {
1567 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) ==
1568 (IFF_UP | IFF_RUNNING))
1576 bwi_start(struct ifnet *ifp)
1578 struct bwi_softc *sc = ifp->if_softc;
1579 struct ieee80211com *ic = &sc->sc_ic;
1580 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
1583 ASSERT_SERIALIZED(ifp->if_serializer);
1585 if ((ifp->if_flags & IFF_OACTIVE) ||
1586 (ifp->if_flags & IFF_RUNNING) == 0)
1592 while (tbd->tbd_buf[idx].tb_mbuf == NULL) {
1593 struct ieee80211_frame *wh;
1594 struct ieee80211_node *ni;
1598 if (!IF_QEMPTY(&ic->ic_mgtq)) {
1599 IF_DEQUEUE(&ic->ic_mgtq, m);
1601 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif;
1602 m->m_pkthdr.rcvif = NULL;
1605 } else if (!ifq_is_empty(&ifp->if_snd)) {
1606 struct ether_header *eh;
1608 if (ic->ic_state != IEEE80211_S_RUN) {
1609 ifq_purge(&ifp->if_snd);
1613 m = ifq_dequeue(&ifp->if_snd, NULL);
1617 if (m->m_len < sizeof(*eh)) {
1618 m = m_pullup(m, sizeof(*eh));
1624 eh = mtod(m, struct ether_header *);
1626 ni = ieee80211_find_txnode(ic, eh->ether_dhost);
1637 m = ieee80211_encap(ic, m, ni);
1639 ieee80211_free_node(ni);
1647 if (ic->ic_rawbpf != NULL)
1648 bpf_mtap(ic->ic_rawbpf, m);
1650 wh = mtod(m, struct ieee80211_frame *);
1651 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
1652 if (ieee80211_crypto_encap(ic, ni, m) == NULL) {
1653 ieee80211_free_node(ni);
1659 wh = NULL; /* Catch any invalid use */
1661 if (bwi_encap(sc, idx, m, &ni, mgt_pkt) != 0) {
1662 /* 'm' is freed in bwi_encap() if we reach here */
1664 ieee80211_free_node(ni);
1671 idx = (idx + 1) % BWI_TX_NDESC;
1673 if (tbd->tbd_used + BWI_TX_NSPRDESC >= BWI_TX_NDESC) {
1674 ifp->if_flags |= IFF_OACTIVE;
1681 sc->sc_tx_timer = 5;
1686 bwi_watchdog(struct ifnet *ifp)
1688 struct bwi_softc *sc = ifp->if_softc;
1690 ASSERT_SERIALIZED(ifp->if_serializer);
1694 if ((ifp->if_flags & IFF_RUNNING) == 0)
1697 if (sc->sc_tx_timer) {
1698 if (--sc->sc_tx_timer == 0) {
1699 if_printf(ifp, "watchdog timeout\n");
1706 ieee80211_watchdog(&sc->sc_ic);
1710 bwi_stop(struct bwi_softc *sc, int state_chg)
1712 struct ieee80211com *ic = &sc->sc_ic;
1713 struct ifnet *ifp = &ic->ic_if;
1714 struct bwi_mac *mac;
1715 int i, error, pwr_off = 0;
1717 ASSERT_SERIALIZED(ifp->if_serializer);
1720 ieee80211_new_state(ic, IEEE80211_S_INIT, -1);
1722 bwi_newstate_begin(sc, IEEE80211_S_INIT);
1724 if (ifp->if_flags & IFF_RUNNING) {
1725 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
1726 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1728 bwi_disable_intrs(sc, BWI_ALL_INTRS);
1729 CSR_READ_4(sc, BWI_MAC_INTR_MASK);
1733 for (i = 0; i < sc->sc_nmac; ++i) {
1734 struct bwi_regwin *old_rw;
1736 mac = &sc->sc_mac[i];
1737 if ((mac->mac_flags & BWI_MAC_F_INITED) == 0)
1740 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old_rw);
1744 bwi_mac_shutdown(mac);
1747 bwi_regwin_switch(sc, old_rw, NULL);
1751 bwi_bbp_power_off(sc);
1753 sc->sc_tx_timer = 0;
1755 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1762 struct bwi_softc *sc = xsc;
1763 struct bwi_mac *mac;
1764 struct ifnet *ifp = &sc->sc_ic.ic_if;
1765 uint32_t intr_status;
1766 uint32_t txrx_intr_status[BWI_TXRX_NRING];
1767 int i, txrx_error, tx = 0, rx_data = -1;
1769 ASSERT_SERIALIZED(ifp->if_serializer);
1771 if ((ifp->if_flags & IFF_RUNNING) == 0)
1775 * Get interrupt status
1777 intr_status = CSR_READ_4(sc, BWI_MAC_INTR_STATUS);
1778 if (intr_status == 0xffffffff) /* Not for us */
1781 DPRINTF(sc, BWI_DBG_INTR, "intr status 0x%08x\n", intr_status);
1783 intr_status &= CSR_READ_4(sc, BWI_MAC_INTR_MASK);
1784 if (intr_status == 0) /* Nothing is interesting */
1787 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
1788 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1791 DPRINTF(sc, BWI_DBG_INTR, "%s\n", "TX/RX intr");
1792 for (i = 0; i < BWI_TXRX_NRING; ++i) {
1795 if (BWI_TXRX_IS_RX(i))
1796 mask = BWI_TXRX_RX_INTRS;
1798 mask = BWI_TXRX_TX_INTRS;
1800 txrx_intr_status[i] =
1801 CSR_READ_4(sc, BWI_TXRX_INTR_STATUS(i)) & mask;
1803 _DPRINTF(sc, BWI_DBG_INTR, ", %d 0x%08x",
1804 i, txrx_intr_status[i]);
1806 if (txrx_intr_status[i] & BWI_TXRX_INTR_ERROR) {
1807 if_printf(ifp, "intr fatal TX/RX (%d) error 0x%08x\n",
1808 i, txrx_intr_status[i]);
1812 _DPRINTF(sc, BWI_DBG_INTR, "%s\n", "");
1815 * Acknowledge interrupt
1817 CSR_WRITE_4(sc, BWI_MAC_INTR_STATUS, intr_status);
1819 for (i = 0; i < BWI_TXRX_NRING; ++i)
1820 CSR_WRITE_4(sc, BWI_TXRX_INTR_STATUS(i), txrx_intr_status[i]);
1822 /* Disable all interrupts */
1823 bwi_disable_intrs(sc, BWI_ALL_INTRS);
1825 if (intr_status & BWI_INTR_PHY_TXERR) {
1826 if (mac->mac_flags & BWI_MAC_F_PHYE_RESET) {
1827 if_printf(ifp, "intr PHY TX error\n");
1828 /* XXX to netisr0? */
1829 bwi_init_statechg(sc, 0);
1835 /* TODO: reset device */
1838 if (intr_status & BWI_INTR_TBTT)
1839 bwi_mac_config_ps(mac);
1841 if (intr_status & BWI_INTR_EO_ATIM)
1842 if_printf(ifp, "EO_ATIM\n");
1844 if (intr_status & BWI_INTR_PMQ) {
1846 if ((CSR_READ_4(sc, BWI_MAC_PS_STATUS) & 0x8) == 0)
1849 CSR_WRITE_2(sc, BWI_MAC_PS_STATUS, 0x2);
1852 if (intr_status & BWI_INTR_NOISE)
1853 if_printf(ifp, "intr noise\n");
1855 if (txrx_intr_status[0] & BWI_TXRX_INTR_RX)
1856 rx_data = sc->sc_rxeof(sc);
1858 if (txrx_intr_status[3] & BWI_TXRX_INTR_RX) {
1859 sc->sc_txeof_status(sc);
1863 if (intr_status & BWI_INTR_TX_DONE) {
1868 /* Re-enable interrupts */
1869 bwi_enable_intrs(sc, BWI_INIT_INTRS);
1871 if (sc->sc_blink_led != NULL && sc->sc_led_blink) {
1872 int evt = BWI_LED_EVENT_NONE;
1874 if (tx && rx_data > 0) {
1875 if (sc->sc_rx_rate > sc->sc_tx_rate)
1876 evt = BWI_LED_EVENT_RX;
1878 evt = BWI_LED_EVENT_TX;
1880 evt = BWI_LED_EVENT_TX;
1881 } else if (rx_data > 0) {
1882 evt = BWI_LED_EVENT_RX;
1883 } else if (rx_data == 0) {
1884 evt = BWI_LED_EVENT_POLL;
1887 if (evt != BWI_LED_EVENT_NONE)
1888 bwi_led_event(sc, evt);
1893 bwi_newstate_begin(struct bwi_softc *sc, enum ieee80211_state nstate)
1895 callout_stop(&sc->sc_scan_ch);
1896 callout_stop(&sc->sc_calib_ch);
1898 ieee80211_ratectl_newstate(&sc->sc_ic, nstate);
1899 bwi_led_newstate(sc, nstate);
1901 if (nstate == IEEE80211_S_INIT)
1902 sc->sc_txpwrcb_type = BWI_TXPWR_INIT;
1906 bwi_newstate(struct ieee80211com *ic, enum ieee80211_state nstate, int arg)
1908 struct bwi_softc *sc = ic->ic_if.if_softc;
1909 struct ifnet *ifp = &ic->ic_if;
1912 ASSERT_SERIALIZED(ifp->if_serializer);
1914 bwi_newstate_begin(sc, nstate);
1916 if (nstate == IEEE80211_S_INIT)
1919 error = bwi_set_chan(sc, ic->ic_curchan);
1921 if_printf(ifp, "can't set channel to %u\n",
1922 ieee80211_chan2ieee(ic, ic->ic_curchan));
1926 if (ic->ic_opmode == IEEE80211_M_MONITOR) {
1928 } else if (nstate == IEEE80211_S_RUN) {
1929 struct bwi_mac *mac;
1931 bwi_set_bssid(sc, ic->ic_bss->ni_bssid);
1933 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
1934 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1936 /* Initial TX power calibration */
1937 bwi_mac_calibrate_txpower(mac, BWI_TXPWR_INIT);
1939 sc->sc_txpwrcb_type = BWI_TXPWR_FORCE;
1941 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB;
1944 bwi_set_bssid(sc, bwi_zero_addr);
1948 error = sc->sc_newstate(ic, nstate, arg);
1950 if (nstate == IEEE80211_S_SCAN) {
1951 callout_reset(&sc->sc_scan_ch,
1952 (sc->sc_dwell_time * hz) / 1000,
1954 } else if (nstate == IEEE80211_S_RUN) {
1955 callout_reset(&sc->sc_calib_ch, hz, bwi_calibrate, sc);
1961 bwi_media_change(struct ifnet *ifp)
1965 ASSERT_SERIALIZED(ifp->if_serializer);
1967 error = ieee80211_media_change(ifp);
1968 if (error != ENETRESET)
1971 if ((ifp->if_flags & (IFF_UP | IFF_RUNNING)) == (IFF_UP | IFF_RUNNING))
1972 bwi_init(ifp->if_softc);
1977 bwi_dma_alloc(struct bwi_softc *sc)
1979 int error, i, has_txstats;
1980 bus_addr_t lowaddr = 0;
1981 bus_size_t tx_ring_sz, rx_ring_sz, desc_sz = 0;
1982 uint32_t txrx_ctrl_step = 0;
1985 for (i = 0; i < sc->sc_nmac; ++i) {
1986 if (sc->sc_mac[i].mac_flags & BWI_MAC_F_HAS_TXSTATS) {
1992 switch (sc->sc_bus_space) {
1993 case BWI_BUS_SPACE_30BIT:
1994 case BWI_BUS_SPACE_32BIT:
1995 if (sc->sc_bus_space == BWI_BUS_SPACE_30BIT)
1996 lowaddr = BWI_BUS_SPACE_MAXADDR;
1998 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1999 desc_sz = sizeof(struct bwi_desc32);
2000 txrx_ctrl_step = 0x20;
2002 sc->sc_init_tx_ring = bwi_init_tx_ring32;
2003 sc->sc_free_tx_ring = bwi_free_tx_ring32;
2004 sc->sc_init_rx_ring = bwi_init_rx_ring32;
2005 sc->sc_free_rx_ring = bwi_free_rx_ring32;
2006 sc->sc_setup_rxdesc = bwi_setup_rx_desc32;
2007 sc->sc_setup_txdesc = bwi_setup_tx_desc32;
2008 sc->sc_rxeof = bwi_rxeof32;
2009 sc->sc_start_tx = bwi_start_tx32;
2011 sc->sc_init_txstats = bwi_init_txstats32;
2012 sc->sc_free_txstats = bwi_free_txstats32;
2013 sc->sc_txeof_status = bwi_txeof_status32;
2017 case BWI_BUS_SPACE_64BIT:
2018 lowaddr = BUS_SPACE_MAXADDR; /* XXX */
2019 desc_sz = sizeof(struct bwi_desc64);
2020 txrx_ctrl_step = 0x40;
2022 sc->sc_init_tx_ring = bwi_init_tx_ring64;
2023 sc->sc_free_tx_ring = bwi_free_tx_ring64;
2024 sc->sc_init_rx_ring = bwi_init_rx_ring64;
2025 sc->sc_free_rx_ring = bwi_free_rx_ring64;
2026 sc->sc_setup_rxdesc = bwi_setup_rx_desc64;
2027 sc->sc_setup_txdesc = bwi_setup_tx_desc64;
2028 sc->sc_rxeof = bwi_rxeof64;
2029 sc->sc_start_tx = bwi_start_tx64;
2031 sc->sc_init_txstats = bwi_init_txstats64;
2032 sc->sc_free_txstats = bwi_free_txstats64;
2033 sc->sc_txeof_status = bwi_txeof_status64;
2038 KKASSERT(lowaddr != 0);
2039 KKASSERT(desc_sz != 0);
2040 KKASSERT(txrx_ctrl_step != 0);
2042 tx_ring_sz = roundup(desc_sz * BWI_TX_NDESC, BWI_RING_ALIGN);
2043 rx_ring_sz = roundup(desc_sz * BWI_RX_NDESC, BWI_RING_ALIGN);
2046 * Create top level DMA tag
2048 error = bus_dma_tag_create(NULL, BWI_ALIGN, 0,
2049 lowaddr, BUS_SPACE_MAXADDR,
2052 BUS_SPACE_UNRESTRICTED,
2053 BUS_SPACE_MAXSIZE_32BIT,
2054 0, &sc->sc_parent_dtag);
2056 device_printf(sc->sc_dev, "can't create parent DMA tag\n");
2060 #define TXRX_CTRL(idx) (BWI_TXRX_CTRL_BASE + (idx) * txrx_ctrl_step)
2063 * Create TX ring DMA stuffs
2065 error = bus_dma_tag_create(sc->sc_parent_dtag, BWI_RING_ALIGN, 0,
2066 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2068 tx_ring_sz, 1, BUS_SPACE_MAXSIZE_32BIT,
2069 0, &sc->sc_txring_dtag);
2071 device_printf(sc->sc_dev, "can't create TX ring DMA tag\n");
2075 for (i = 0; i < BWI_TX_NRING; ++i) {
2076 error = bwi_dma_ring_alloc(sc, sc->sc_txring_dtag,
2077 &sc->sc_tx_rdata[i], tx_ring_sz,
2080 device_printf(sc->sc_dev, "%dth TX ring "
2081 "DMA alloc failed\n", i);
2087 * Create RX ring DMA stuffs
2089 error = bus_dma_tag_create(sc->sc_parent_dtag, BWI_RING_ALIGN, 0,
2090 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2092 rx_ring_sz, 1, BUS_SPACE_MAXSIZE_32BIT,
2093 0, &sc->sc_rxring_dtag);
2095 device_printf(sc->sc_dev, "can't create RX ring DMA tag\n");
2099 error = bwi_dma_ring_alloc(sc, sc->sc_rxring_dtag, &sc->sc_rx_rdata,
2100 rx_ring_sz, TXRX_CTRL(0));
2102 device_printf(sc->sc_dev, "RX ring DMA alloc failed\n");
2107 error = bwi_dma_txstats_alloc(sc, TXRX_CTRL(3), desc_sz);
2109 device_printf(sc->sc_dev,
2110 "TX stats DMA alloc failed\n");
2117 return bwi_dma_mbuf_create(sc);
2121 bwi_dma_free(struct bwi_softc *sc)
2123 if (sc->sc_txring_dtag != NULL) {
2126 for (i = 0; i < BWI_TX_NRING; ++i) {
2127 struct bwi_ring_data *rd = &sc->sc_tx_rdata[i];
2129 if (rd->rdata_desc != NULL) {
2130 bus_dmamap_unload(sc->sc_txring_dtag,
2132 bus_dmamem_free(sc->sc_txring_dtag,
2137 bus_dma_tag_destroy(sc->sc_txring_dtag);
2140 if (sc->sc_rxring_dtag != NULL) {
2141 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2143 if (rd->rdata_desc != NULL) {
2144 bus_dmamap_unload(sc->sc_rxring_dtag, rd->rdata_dmap);
2145 bus_dmamem_free(sc->sc_rxring_dtag, rd->rdata_desc,
2148 bus_dma_tag_destroy(sc->sc_rxring_dtag);
2151 bwi_dma_txstats_free(sc);
2152 bwi_dma_mbuf_destroy(sc, BWI_TX_NRING, 1);
2154 if (sc->sc_parent_dtag != NULL)
2155 bus_dma_tag_destroy(sc->sc_parent_dtag);
2159 bwi_dma_ring_alloc(struct bwi_softc *sc, bus_dma_tag_t dtag,
2160 struct bwi_ring_data *rd, bus_size_t size,
2165 error = bus_dmamem_alloc(dtag, &rd->rdata_desc,
2166 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2169 device_printf(sc->sc_dev, "can't allocate DMA mem\n");
2173 error = bus_dmamap_load(dtag, rd->rdata_dmap, rd->rdata_desc, size,
2174 bwi_dma_ring_addr, &rd->rdata_paddr,
2177 device_printf(sc->sc_dev, "can't load DMA mem\n");
2178 bus_dmamem_free(dtag, rd->rdata_desc, rd->rdata_dmap);
2179 rd->rdata_desc = NULL;
2183 rd->rdata_txrx_ctrl = txrx_ctrl;
2188 bwi_dma_txstats_alloc(struct bwi_softc *sc, uint32_t ctrl_base,
2191 struct bwi_txstats_data *st;
2192 bus_size_t dma_size;
2195 st = kmalloc(sizeof(*st), M_DEVBUF, M_WAITOK | M_ZERO);
2196 sc->sc_txstats = st;
2199 * Create TX stats descriptor DMA stuffs
2201 dma_size = roundup(desc_sz * BWI_TXSTATS_NDESC, BWI_RING_ALIGN);
2203 error = bus_dma_tag_create(sc->sc_parent_dtag, BWI_RING_ALIGN, 0,
2204 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2206 dma_size, 1, BUS_SPACE_MAXSIZE_32BIT,
2207 0, &st->stats_ring_dtag);
2209 device_printf(sc->sc_dev, "can't create txstats ring "
2214 error = bus_dmamem_alloc(st->stats_ring_dtag, &st->stats_ring,
2215 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2216 &st->stats_ring_dmap);
2218 device_printf(sc->sc_dev, "can't allocate txstats ring "
2220 bus_dma_tag_destroy(st->stats_ring_dtag);
2221 st->stats_ring_dtag = NULL;
2225 error = bus_dmamap_load(st->stats_ring_dtag, st->stats_ring_dmap,
2226 st->stats_ring, dma_size,
2227 bwi_dma_ring_addr, &st->stats_ring_paddr,
2230 device_printf(sc->sc_dev, "can't load txstats ring DMA mem\n");
2231 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring,
2232 st->stats_ring_dmap);
2233 bus_dma_tag_destroy(st->stats_ring_dtag);
2234 st->stats_ring_dtag = NULL;
2239 * Create TX stats DMA stuffs
2241 dma_size = roundup(sizeof(struct bwi_txstats) * BWI_TXSTATS_NDESC,
2244 error = bus_dma_tag_create(sc->sc_parent_dtag, BWI_ALIGN, 0,
2245 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2247 dma_size, 1, BUS_SPACE_MAXSIZE_32BIT,
2248 0, &st->stats_dtag);
2250 device_printf(sc->sc_dev, "can't create txstats DMA tag\n");
2254 error = bus_dmamem_alloc(st->stats_dtag, (void **)&st->stats,
2255 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2258 device_printf(sc->sc_dev, "can't allocate txstats DMA mem\n");
2259 bus_dma_tag_destroy(st->stats_dtag);
2260 st->stats_dtag = NULL;
2264 error = bus_dmamap_load(st->stats_dtag, st->stats_dmap, st->stats,
2265 dma_size, bwi_dma_ring_addr, &st->stats_paddr,
2268 device_printf(sc->sc_dev, "can't load txstats DMA mem\n");
2269 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap);
2270 bus_dma_tag_destroy(st->stats_dtag);
2271 st->stats_dtag = NULL;
2275 st->stats_ctrl_base = ctrl_base;
2280 bwi_dma_txstats_free(struct bwi_softc *sc)
2282 struct bwi_txstats_data *st;
2284 if (sc->sc_txstats == NULL)
2286 st = sc->sc_txstats;
2288 if (st->stats_ring_dtag != NULL) {
2289 bus_dmamap_unload(st->stats_ring_dtag, st->stats_ring_dmap);
2290 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring,
2291 st->stats_ring_dmap);
2292 bus_dma_tag_destroy(st->stats_ring_dtag);
2295 if (st->stats_dtag != NULL) {
2296 bus_dmamap_unload(st->stats_dtag, st->stats_dmap);
2297 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap);
2298 bus_dma_tag_destroy(st->stats_dtag);
2301 kfree(st, M_DEVBUF);
2305 bwi_dma_ring_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error)
2307 KASSERT(nseg == 1, ("too many segments\n"));
2308 *((bus_addr_t *)arg) = seg->ds_addr;
2312 bwi_dma_mbuf_create(struct bwi_softc *sc)
2314 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2315 int i, j, k, ntx, error;
2318 * Create TX/RX mbuf DMA tag
2320 error = bus_dma_tag_create(sc->sc_parent_dtag, 1, 0,
2321 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2322 NULL, NULL, MCLBYTES, 1,
2323 BUS_SPACE_MAXSIZE_32BIT,
2324 0, &sc->sc_buf_dtag);
2326 device_printf(sc->sc_dev, "can't create mbuf DMA tag\n");
2333 * Create TX mbuf DMA map
2335 for (i = 0; i < BWI_TX_NRING; ++i) {
2336 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i];
2338 for (j = 0; j < BWI_TX_NDESC; ++j) {
2339 error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2340 &tbd->tbd_buf[j].tb_dmap);
2342 device_printf(sc->sc_dev, "can't create "
2343 "%dth tbd, %dth DMA map\n", i, j);
2346 for (k = 0; k < j; ++k) {
2347 bus_dmamap_destroy(sc->sc_buf_dtag,
2348 tbd->tbd_buf[k].tb_dmap);
2357 * Create RX mbuf DMA map and a spare DMA map
2359 error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2360 &rbd->rbd_tmp_dmap);
2362 device_printf(sc->sc_dev,
2363 "can't create spare RX buf DMA map\n");
2367 for (j = 0; j < BWI_RX_NDESC; ++j) {
2368 error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2369 &rbd->rbd_buf[j].rb_dmap);
2371 device_printf(sc->sc_dev, "can't create %dth "
2372 "RX buf DMA map\n", j);
2374 for (k = 0; k < j; ++k) {
2375 bus_dmamap_destroy(sc->sc_buf_dtag,
2376 rbd->rbd_buf[j].rb_dmap);
2378 bus_dmamap_destroy(sc->sc_buf_dtag,
2386 bwi_dma_mbuf_destroy(sc, ntx, 0);
2391 bwi_dma_mbuf_destroy(struct bwi_softc *sc, int ntx, int nrx)
2395 if (sc->sc_buf_dtag == NULL)
2398 for (i = 0; i < ntx; ++i) {
2399 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i];
2401 for (j = 0; j < BWI_TX_NDESC; ++j) {
2402 struct bwi_txbuf *tb = &tbd->tbd_buf[j];
2404 if (tb->tb_mbuf != NULL) {
2405 bus_dmamap_unload(sc->sc_buf_dtag,
2407 m_freem(tb->tb_mbuf);
2409 if (tb->tb_ni != NULL)
2410 ieee80211_free_node(tb->tb_ni);
2411 bus_dmamap_destroy(sc->sc_buf_dtag, tb->tb_dmap);
2416 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2418 bus_dmamap_destroy(sc->sc_buf_dtag, rbd->rbd_tmp_dmap);
2419 for (j = 0; j < BWI_RX_NDESC; ++j) {
2420 struct bwi_rxbuf *rb = &rbd->rbd_buf[j];
2422 if (rb->rb_mbuf != NULL) {
2423 bus_dmamap_unload(sc->sc_buf_dtag,
2425 m_freem(rb->rb_mbuf);
2427 bus_dmamap_destroy(sc->sc_buf_dtag, rb->rb_dmap);
2431 bus_dma_tag_destroy(sc->sc_buf_dtag);
2432 sc->sc_buf_dtag = NULL;
2436 bwi_enable_intrs(struct bwi_softc *sc, uint32_t enable_intrs)
2438 CSR_SETBITS_4(sc, BWI_MAC_INTR_MASK, enable_intrs);
2442 bwi_disable_intrs(struct bwi_softc *sc, uint32_t disable_intrs)
2444 CSR_CLRBITS_4(sc, BWI_MAC_INTR_MASK, disable_intrs);
2448 bwi_init_tx_ring32(struct bwi_softc *sc, int ring_idx)
2450 struct bwi_ring_data *rd;
2451 struct bwi_txbuf_data *tbd;
2452 uint32_t val, addr_hi, addr_lo;
2454 KKASSERT(ring_idx < BWI_TX_NRING);
2455 rd = &sc->sc_tx_rdata[ring_idx];
2456 tbd = &sc->sc_tx_bdata[ring_idx];
2461 bzero(rd->rdata_desc, sizeof(struct bwi_desc32) * BWI_TX_NDESC);
2462 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap,
2463 BUS_DMASYNC_PREWRITE);
2465 addr_lo = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_ADDR_MASK);
2466 addr_hi = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_FUNC_MASK);
2468 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) |
2469 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX,
2470 BWI_TXRX32_RINGINFO_FUNC_MASK);
2471 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, val);
2473 val = __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) |
2474 BWI_TXRX32_CTRL_ENABLE;
2475 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, val);
2481 bwi_init_rxdesc_ring32(struct bwi_softc *sc, uint32_t ctrl_base,
2482 bus_addr_t paddr, int hdr_size, int ndesc)
2484 uint32_t val, addr_hi, addr_lo;
2486 addr_lo = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_ADDR_MASK);
2487 addr_hi = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_FUNC_MASK);
2489 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) |
2490 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX,
2491 BWI_TXRX32_RINGINFO_FUNC_MASK);
2492 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_RINGINFO, val);
2494 val = __SHIFTIN(hdr_size, BWI_RX32_CTRL_HDRSZ_MASK) |
2495 __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) |
2496 BWI_TXRX32_CTRL_ENABLE;
2497 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_CTRL, val);
2499 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX,
2500 (ndesc - 1) * sizeof(struct bwi_desc32));
2504 bwi_init_rx_ring32(struct bwi_softc *sc)
2506 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2509 sc->sc_rx_bdata.rbd_idx = 0;
2511 for (i = 0; i < BWI_RX_NDESC; ++i) {
2512 error = bwi_newbuf(sc, i, 1);
2514 if_printf(&sc->sc_ic.ic_if,
2515 "can't allocate %dth RX buffer\n", i);
2519 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap,
2520 BUS_DMASYNC_PREWRITE);
2522 bwi_init_rxdesc_ring32(sc, rd->rdata_txrx_ctrl, rd->rdata_paddr,
2523 sizeof(struct bwi_rxbuf_hdr), BWI_RX_NDESC);
2528 bwi_init_txstats32(struct bwi_softc *sc)
2530 struct bwi_txstats_data *st = sc->sc_txstats;
2531 bus_addr_t stats_paddr;
2534 bzero(st->stats, BWI_TXSTATS_NDESC * sizeof(struct bwi_txstats));
2535 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_PREWRITE);
2539 stats_paddr = st->stats_paddr;
2540 for (i = 0; i < BWI_TXSTATS_NDESC; ++i) {
2541 bwi_setup_desc32(sc, st->stats_ring, BWI_TXSTATS_NDESC, i,
2542 stats_paddr, sizeof(struct bwi_txstats), 0);
2543 stats_paddr += sizeof(struct bwi_txstats);
2545 bus_dmamap_sync(st->stats_ring_dtag, st->stats_ring_dmap,
2546 BUS_DMASYNC_PREWRITE);
2548 bwi_init_rxdesc_ring32(sc, st->stats_ctrl_base,
2549 st->stats_ring_paddr, 0, BWI_TXSTATS_NDESC);
2554 bwi_setup_rx_desc32(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr,
2557 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2559 KKASSERT(buf_idx < BWI_RX_NDESC);
2560 bwi_setup_desc32(sc, rd->rdata_desc, BWI_RX_NDESC, buf_idx,
2565 bwi_setup_tx_desc32(struct bwi_softc *sc, struct bwi_ring_data *rd,
2566 int buf_idx, bus_addr_t paddr, int buf_len)
2568 KKASSERT(buf_idx < BWI_TX_NDESC);
2569 bwi_setup_desc32(sc, rd->rdata_desc, BWI_TX_NDESC, buf_idx,
2574 bwi_init_tx_ring64(struct bwi_softc *sc, int ring_idx)
2581 bwi_init_rx_ring64(struct bwi_softc *sc)
2588 bwi_init_txstats64(struct bwi_softc *sc)
2595 bwi_setup_rx_desc64(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr,
2602 bwi_setup_tx_desc64(struct bwi_softc *sc, struct bwi_ring_data *rd,
2603 int buf_idx, bus_addr_t paddr, int buf_len)
2609 bwi_dma_buf_addr(void *arg, bus_dma_segment_t *seg, int nseg,
2610 bus_size_t mapsz __unused, int error)
2613 KASSERT(nseg == 1, ("too many segments(%d)\n", nseg));
2614 *((bus_addr_t *)arg) = seg->ds_addr;
2619 bwi_newbuf(struct bwi_softc *sc, int buf_idx, int init)
2621 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2622 struct bwi_rxbuf *rxbuf = &rbd->rbd_buf[buf_idx];
2623 struct bwi_rxbuf_hdr *hdr;
2629 KKASSERT(buf_idx < BWI_RX_NDESC);
2631 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2636 * If the NIC is up and running, we need to:
2637 * - Clear RX buffer's header.
2638 * - Restore RX descriptor settings.
2645 m->m_len = m->m_pkthdr.len = MCLBYTES;
2648 * Try to load RX buf into temporary DMA map
2650 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, rbd->rbd_tmp_dmap, m,
2651 bwi_dma_buf_addr, &paddr,
2652 init ? BUS_DMA_WAITOK : BUS_DMA_NOWAIT);
2657 * See the comment above
2666 bus_dmamap_unload(sc->sc_buf_dtag, rxbuf->rb_dmap);
2668 rxbuf->rb_paddr = paddr;
2671 * Swap RX buf's DMA map with the loaded temporary one
2673 map = rxbuf->rb_dmap;
2674 rxbuf->rb_dmap = rbd->rbd_tmp_dmap;
2675 rbd->rbd_tmp_dmap = map;
2679 * Clear RX buf header
2681 hdr = mtod(rxbuf->rb_mbuf, struct bwi_rxbuf_hdr *);
2682 bzero(hdr, sizeof(*hdr));
2683 bus_dmamap_sync(sc->sc_buf_dtag, rxbuf->rb_dmap, BUS_DMASYNC_PREWRITE);
2686 * Setup RX buf descriptor
2688 sc->sc_setup_rxdesc(sc, buf_idx, rxbuf->rb_paddr,
2689 rxbuf->rb_mbuf->m_len - sizeof(*hdr));
2694 bwi_set_addr_filter(struct bwi_softc *sc, uint16_t addr_ofs,
2695 const uint8_t *addr)
2699 CSR_WRITE_2(sc, BWI_ADDR_FILTER_CTRL,
2700 BWI_ADDR_FILTER_CTRL_SET | addr_ofs);
2702 for (i = 0; i < (IEEE80211_ADDR_LEN / 2); ++i) {
2705 addr_val = (uint16_t)addr[i * 2] |
2706 (((uint16_t)addr[(i * 2) + 1]) << 8);
2707 CSR_WRITE_2(sc, BWI_ADDR_FILTER_DATA, addr_val);
2712 bwi_set_chan(struct bwi_softc *sc, struct ieee80211_channel *c)
2714 struct ieee80211com *ic = &sc->sc_ic;
2716 struct ifnet *ifp = &ic->ic_if;
2718 struct bwi_mac *mac;
2722 ASSERT_SERIALIZED(ifp->if_serializer);
2724 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
2725 mac = (struct bwi_mac *)sc->sc_cur_regwin;
2727 chan = ieee80211_chan2ieee(ic, c);
2729 bwi_rf_set_chan(mac, chan, 0);
2732 * Setup radio tap channel freq and flags
2734 if (IEEE80211_IS_CHAN_G(c))
2735 flags = IEEE80211_CHAN_G;
2737 flags = IEEE80211_CHAN_B;
2739 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq =
2740 htole16(c->ic_freq);
2741 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags =
2748 bwi_next_scan(void *xsc)
2750 struct bwi_softc *sc = xsc;
2751 struct ieee80211com *ic = &sc->sc_ic;
2752 struct ifnet *ifp = &ic->ic_if;
2754 lwkt_serialize_enter(ifp->if_serializer);
2756 if (ic->ic_state == IEEE80211_S_SCAN)
2757 ieee80211_next_scan(ic);
2759 lwkt_serialize_exit(ifp->if_serializer);
2763 bwi_rxeof(struct bwi_softc *sc, int end_idx)
2765 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2766 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2767 struct ieee80211com *ic = &sc->sc_ic;
2768 struct ifnet *ifp = &ic->ic_if;
2769 int idx, rx_data = 0;
2772 while (idx != end_idx) {
2773 struct bwi_rxbuf *rb = &rbd->rbd_buf[idx];
2774 struct bwi_rxbuf_hdr *hdr;
2775 struct ieee80211_frame_min *wh;
2776 struct ieee80211_node *ni;
2780 int buflen, wh_ofs, hdr_extra, rssi, type, rate;
2783 bus_dmamap_sync(sc->sc_buf_dtag, rb->rb_dmap,
2784 BUS_DMASYNC_POSTREAD);
2786 if (bwi_newbuf(sc, idx, 0)) {
2791 hdr = mtod(m, struct bwi_rxbuf_hdr *);
2792 flags2 = le16toh(hdr->rxh_flags2);
2795 if (flags2 & BWI_RXH_F2_TYPE2FRAME)
2797 wh_ofs = hdr_extra + 6; /* XXX magic number */
2799 buflen = le16toh(hdr->rxh_buflen);
2800 if (buflen < BWI_FRAME_MIN_LEN(wh_ofs)) {
2801 if_printf(ifp, "short frame %d, hdr_extra %d\n",
2808 plcp = ((const uint8_t *)(hdr + 1) + hdr_extra);
2809 rssi = bwi_calc_rssi(sc, hdr);
2811 m->m_pkthdr.rcvif = ifp;
2812 m->m_len = m->m_pkthdr.len = buflen + sizeof(*hdr);
2813 m_adj(m, sizeof(*hdr) + wh_ofs);
2815 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_OFDM)
2816 rate = bwi_ofdm_plcp2rate(plcp);
2818 rate = bwi_ds_plcp2rate(plcp);
2821 if (sc->sc_drvbpf != NULL)
2822 bwi_rx_radiotap(sc, m, hdr, plcp, rate, rssi);
2824 m_adj(m, -IEEE80211_CRC_LEN);
2826 wh = mtod(m, struct ieee80211_frame_min *);
2827 ni = ieee80211_find_rxnode(ic, wh);
2829 type = ieee80211_input(ic, m, ni, rssi - BWI_NOISE_FLOOR,
2830 le16toh(hdr->rxh_tsf));
2831 ieee80211_free_node(ni);
2833 if (type == IEEE80211_FC0_TYPE_DATA) {
2835 sc->sc_rx_rate = rate;
2838 idx = (idx + 1) % BWI_RX_NDESC;
2842 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap,
2843 BUS_DMASYNC_PREWRITE);
2848 bwi_rxeof32(struct bwi_softc *sc)
2850 uint32_t val, rx_ctrl;
2851 int end_idx, rx_data;
2853 rx_ctrl = sc->sc_rx_rdata.rdata_txrx_ctrl;
2855 val = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS);
2856 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) /
2857 sizeof(struct bwi_desc32);
2859 rx_data = bwi_rxeof(sc, end_idx);
2861 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_INDEX,
2862 end_idx * sizeof(struct bwi_desc32));
2868 bwi_rxeof64(struct bwi_softc *sc)
2875 bwi_reset_rx_ring32(struct bwi_softc *sc, uint32_t rx_ctrl)
2879 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_CTRL, 0);
2883 for (i = 0; i < NRETRY; ++i) {
2886 status = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS);
2887 if (__SHIFTOUT(status, BWI_RX32_STATUS_STATE_MASK) ==
2888 BWI_RX32_STATUS_STATE_DISABLED)
2894 if_printf(&sc->sc_ic.ic_if, "reset rx ring timedout\n");
2898 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_RINGINFO, 0);
2902 bwi_free_txstats32(struct bwi_softc *sc)
2904 bwi_reset_rx_ring32(sc, sc->sc_txstats->stats_ctrl_base);
2908 bwi_free_rx_ring32(struct bwi_softc *sc)
2910 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2911 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2914 bwi_reset_rx_ring32(sc, rd->rdata_txrx_ctrl);
2916 for (i = 0; i < BWI_RX_NDESC; ++i) {
2917 struct bwi_rxbuf *rb = &rbd->rbd_buf[i];
2919 if (rb->rb_mbuf != NULL) {
2920 bus_dmamap_unload(sc->sc_buf_dtag, rb->rb_dmap);
2921 m_freem(rb->rb_mbuf);
2928 bwi_free_tx_ring32(struct bwi_softc *sc, int ring_idx)
2930 struct bwi_ring_data *rd;
2931 struct bwi_txbuf_data *tbd;
2932 struct ifnet *ifp = &sc->sc_ic.ic_if;
2933 uint32_t state, val;
2936 KKASSERT(ring_idx < BWI_TX_NRING);
2937 rd = &sc->sc_tx_rdata[ring_idx];
2938 tbd = &sc->sc_tx_bdata[ring_idx];
2942 for (i = 0; i < NRETRY; ++i) {
2943 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS);
2944 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK);
2945 if (state == BWI_TX32_STATUS_STATE_DISABLED ||
2946 state == BWI_TX32_STATUS_STATE_IDLE ||
2947 state == BWI_TX32_STATUS_STATE_STOPPED)
2953 if_printf(ifp, "wait for TX ring(%d) stable timed out\n",
2957 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, 0);
2958 for (i = 0; i < NRETRY; ++i) {
2959 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS);
2960 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK);
2961 if (state == BWI_TX32_STATUS_STATE_DISABLED)
2967 if_printf(ifp, "reset TX ring (%d) timed out\n", ring_idx);
2973 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, 0);
2975 for (i = 0; i < BWI_TX_NDESC; ++i) {
2976 struct bwi_txbuf *tb = &tbd->tbd_buf[i];
2978 if (tb->tb_mbuf != NULL) {
2979 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap);
2980 m_freem(tb->tb_mbuf);
2983 if (tb->tb_ni != NULL) {
2984 ieee80211_free_node(tb->tb_ni);
2991 bwi_free_txstats64(struct bwi_softc *sc)
2997 bwi_free_rx_ring64(struct bwi_softc *sc)
3003 bwi_free_tx_ring64(struct bwi_softc *sc, int ring_idx)
3009 bwi_encap(struct bwi_softc *sc, int idx, struct mbuf *m,
3010 struct ieee80211_node **ni0, int mgt_pkt)
3012 struct ieee80211com *ic = &sc->sc_ic;
3013 struct ieee80211_node *ni = *ni0;
3014 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING];
3015 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
3016 struct bwi_txbuf *tb = &tbd->tbd_buf[idx];
3017 struct bwi_mac *mac;
3018 struct bwi_txbuf_hdr *hdr;
3019 struct ieee80211_frame *wh;
3020 uint8_t rate, rate_fb;
3024 int pkt_len, error, mcast_pkt = 0;
3030 KKASSERT(ni != NULL);
3031 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
3032 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3034 wh = mtod(m, struct ieee80211_frame *);
3036 /* Get 802.11 frame len before prepending TX header */
3037 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN;
3042 bzero(tb->tb_rateidx, sizeof(tb->tb_rateidx));
3044 if (ic->ic_fixed_rate != IEEE80211_FIXED_RATE_NONE) {
3047 rate = IEEE80211_RS_RATE(&ni->ni_rates,
3050 if (ic->ic_fixed_rate >= 1)
3051 idx = ic->ic_fixed_rate - 1;
3054 rate_fb = IEEE80211_RS_RATE(&ni->ni_rates, idx);
3056 tb->tb_rateidx_cnt = ieee80211_ratectl_findrate(ni,
3057 m->m_pkthdr.len, tb->tb_rateidx, BWI_NTXRATE);
3059 rate = IEEE80211_RS_RATE(&ni->ni_rates,
3061 if (tb->tb_rateidx_cnt == BWI_NTXRATE) {
3062 rate_fb = IEEE80211_RS_RATE(&ni->ni_rates,
3067 tb->tb_buflen = m->m_pkthdr.len;
3070 /* Fixed at 1Mbits/s for mgt frames */
3071 rate = rate_fb = (1 * 2);
3074 if (IEEE80211_IS_MULTICAST(wh->i_addr1)) {
3075 rate = rate_fb = ic->ic_mcast_rate;
3079 if (rate == 0 || rate_fb == 0) {
3080 /* XXX this should not happen */
3081 if_printf(&ic->ic_if, "invalid rate %u or fallback rate %u",
3083 rate = rate_fb = (1 * 2); /* Force 1Mbits/s */
3085 sc->sc_tx_rate = rate;
3090 if (sc->sc_drvbpf != NULL) {
3091 sc->sc_tx_th.wt_flags = 0;
3092 if (wh->i_fc[1] & IEEE80211_FC1_WEP)
3093 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
3094 if (ieee80211_rate2modtype(rate) == IEEE80211_MODTYPE_DS &&
3095 (ic->ic_flags & IEEE80211_F_SHPREAMBLE) &&
3097 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
3099 sc->sc_tx_th.wt_rate = rate;
3101 bpf_ptap(sc->sc_drvbpf, m, &sc->sc_tx_th, sc->sc_tx_th_len);
3105 * Setup the embedded TX header
3107 M_PREPEND(m, sizeof(*hdr), MB_DONTWAIT);
3109 if_printf(&ic->ic_if, "prepend TX header failed\n");
3112 hdr = mtod(m, struct bwi_txbuf_hdr *);
3114 bzero(hdr, sizeof(*hdr));
3116 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc));
3117 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1));
3123 ack_rate = ieee80211_ack_rate(ni, rate_fb);
3124 dur = ieee80211_txtime(ni,
3125 sizeof(struct ieee80211_frame_ack) + IEEE80211_CRC_LEN,
3126 ack_rate, ic->ic_flags & IEEE80211_F_SHPREAMBLE);
3128 hdr->txh_fb_duration = htole16(dur);
3131 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) |
3132 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK);
3134 bwi_plcp_header(hdr->txh_plcp, pkt_len, rate);
3135 bwi_plcp_header(hdr->txh_fb_plcp, pkt_len, rate_fb);
3137 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode,
3138 BWI_TXH_PHY_C_ANTMODE_MASK);
3139 if (ieee80211_rate2modtype(rate) == IEEE80211_MODTYPE_OFDM)
3140 phy_ctrl |= BWI_TXH_PHY_C_OFDM;
3141 else if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && rate != (2 * 1))
3142 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE;
3144 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG;
3145 if (!IEEE80211_IS_MULTICAST(wh->i_addr1))
3146 mac_ctrl |= BWI_TXH_MAC_C_ACK;
3147 if (ieee80211_rate2modtype(rate_fb) == IEEE80211_MODTYPE_OFDM)
3148 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM;
3150 hdr->txh_mac_ctrl = htole32(mac_ctrl);
3151 hdr->txh_phy_ctrl = htole16(phy_ctrl);
3153 /* Catch any further usage */
3158 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
3159 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT);
3160 if (error && error != EFBIG) {
3161 if_printf(&ic->ic_if, "can't load TX buffer (1) %d\n", error);
3165 if (error) { /* error == EFBIG */
3168 m_new = m_defrag(m, MB_DONTWAIT);
3169 if (m_new == NULL) {
3170 if_printf(&ic->ic_if, "can't defrag TX buffer\n");
3177 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
3178 bwi_dma_buf_addr, &paddr,
3181 if_printf(&ic->ic_if, "can't load TX buffer (2) %d\n",
3188 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE);
3190 if (mgt_pkt || mcast_pkt) {
3191 /* Don't involve mcast/mgt packets into TX rate control */
3192 ieee80211_free_node(ni);
3199 p = mtod(m, const uint8_t *);
3200 for (i = 0; i < m->m_pkthdr.len; ++i) {
3201 if (i != 0 && i % 8 == 0)
3203 kprintf("%02x ", p[i]);
3208 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n",
3209 idx, pkt_len, m->m_pkthdr.len);
3211 /* Setup TX descriptor */
3212 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len);
3213 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap,
3214 BUS_DMASYNC_PREWRITE);
3217 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx);
3226 bwi_start_tx32(struct bwi_softc *sc, uint32_t tx_ctrl, int idx)
3228 idx = (idx + 1) % BWI_TX_NDESC;
3229 CSR_WRITE_4(sc, tx_ctrl + BWI_TX32_INDEX,
3230 idx * sizeof(struct bwi_desc32));
3234 bwi_start_tx64(struct bwi_softc *sc, uint32_t tx_ctrl, int idx)
3240 bwi_txeof_status32(struct bwi_softc *sc)
3242 struct ifnet *ifp = &sc->sc_ic.ic_if;
3243 uint32_t val, ctrl_base;
3246 ctrl_base = sc->sc_txstats->stats_ctrl_base;
3248 val = CSR_READ_4(sc, ctrl_base + BWI_RX32_STATUS);
3249 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) /
3250 sizeof(struct bwi_desc32);
3252 bwi_txeof_status(sc, end_idx);
3254 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX,
3255 end_idx * sizeof(struct bwi_desc32));
3257 if ((ifp->if_flags & IFF_OACTIVE) == 0)
3262 bwi_txeof_status64(struct bwi_softc *sc)
3268 _bwi_txeof(struct bwi_softc *sc, uint16_t tx_id, int acked, int data_txcnt)
3270 struct ifnet *ifp = &sc->sc_ic.ic_if;
3271 struct bwi_txbuf_data *tbd;
3272 struct bwi_txbuf *tb;
3273 int ring_idx, buf_idx;
3276 if_printf(ifp, "zero tx id\n");
3280 ring_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_RING_MASK);
3281 buf_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_IDX_MASK);
3283 KKASSERT(ring_idx == BWI_TX_DATA_RING);
3284 KKASSERT(buf_idx < BWI_TX_NDESC);
3286 tbd = &sc->sc_tx_bdata[ring_idx];
3287 KKASSERT(tbd->tbd_used > 0);
3290 tb = &tbd->tbd_buf[buf_idx];
3292 DPRINTF(sc, BWI_DBG_TXEOF, "txeof idx %d, "
3293 "acked %d, data_txcnt %d, ni %p\n",
3294 buf_idx, acked, data_txcnt, tb->tb_ni);
3296 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap);
3297 m_freem(tb->tb_mbuf);
3300 if (tb->tb_ni != NULL) {
3301 struct ieee80211_ratectl_res res[BWI_NTXRATE];
3304 if (data_txcnt <= BWI_SHRETRY_FB || tb->tb_rateidx_cnt == 1) {
3306 res[0].rc_res_rateidx = tb->tb_rateidx[0];
3307 res[0].rc_res_tries = data_txcnt;
3309 res_len = BWI_NTXRATE;
3310 res[0].rc_res_rateidx = tb->tb_rateidx[0];
3311 res[0].rc_res_tries = BWI_SHRETRY_FB;
3312 res[1].rc_res_rateidx = tb->tb_rateidx[1];
3313 res[1].rc_res_tries = data_txcnt - BWI_SHRETRY_FB;
3317 retry = data_txcnt > 0 ? data_txcnt - 1 : 0;
3321 ieee80211_ratectl_tx_complete(tb->tb_ni, tb->tb_buflen,
3322 res, res_len, retry, 0, !acked);
3324 ieee80211_free_node(tb->tb_ni);
3328 if (tbd->tbd_used == 0)
3329 sc->sc_tx_timer = 0;
3331 ifp->if_flags &= ~IFF_OACTIVE;
3335 bwi_txeof_status(struct bwi_softc *sc, int end_idx)
3337 struct bwi_txstats_data *st = sc->sc_txstats;
3340 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_POSTREAD);
3342 idx = st->stats_idx;
3343 while (idx != end_idx) {
3344 const struct bwi_txstats *stats = &st->stats[idx];
3346 if ((stats->txs_flags & BWI_TXS_F_PENDING) == 0) {
3349 data_txcnt = __SHIFTOUT(stats->txs_txcnt,
3350 BWI_TXS_TXCNT_DATA);
3351 _bwi_txeof(sc, le16toh(stats->txs_id),
3352 stats->txs_flags & BWI_TXS_F_ACKED,
3355 idx = (idx + 1) % BWI_TXSTATS_NDESC;
3357 st->stats_idx = idx;
3361 bwi_txeof(struct bwi_softc *sc)
3363 struct ifnet *ifp = &sc->sc_ic.ic_if;
3366 uint32_t tx_status0, tx_status1;
3370 tx_status0 = CSR_READ_4(sc, BWI_TXSTATUS0);
3371 if ((tx_status0 & BWI_TXSTATUS0_VALID) == 0)
3373 tx_status1 = CSR_READ_4(sc, BWI_TXSTATUS1);
3375 tx_id = __SHIFTOUT(tx_status0, BWI_TXSTATUS0_TXID_MASK);
3376 data_txcnt = __SHIFTOUT(tx_status0,
3377 BWI_TXSTATUS0_DATA_TXCNT_MASK);
3379 if (tx_status0 & (BWI_TXSTATUS0_AMPDU | BWI_TXSTATUS0_PENDING))
3382 _bwi_txeof(sc, tx_id, tx_status0 & BWI_TXSTATUS0_ACKED,
3386 if ((ifp->if_flags & IFF_OACTIVE) == 0)
3391 bwi_bbp_power_on(struct bwi_softc *sc, enum bwi_clock_mode clk_mode)
3393 bwi_power_on(sc, 1);
3394 return bwi_set_clock_mode(sc, clk_mode);
3398 bwi_bbp_power_off(struct bwi_softc *sc)
3400 bwi_set_clock_mode(sc, BWI_CLOCK_MODE_SLOW);
3401 bwi_power_off(sc, 1);
3405 bwi_get_pwron_delay(struct bwi_softc *sc)
3407 struct bwi_regwin *com, *old;
3408 struct bwi_clock_freq freq;
3412 com = &sc->sc_com_regwin;
3413 KKASSERT(BWI_REGWIN_EXIST(com));
3415 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0)
3418 error = bwi_regwin_switch(sc, com, &old);
3422 bwi_get_clock_freq(sc, &freq);
3424 val = CSR_READ_4(sc, BWI_PLL_ON_DELAY);
3425 sc->sc_pwron_delay = howmany((val + 2) * 1000000, freq.clkfreq_min);
3426 DPRINTF(sc, BWI_DBG_ATTACH, "power on delay %u\n", sc->sc_pwron_delay);
3428 return bwi_regwin_switch(sc, old, NULL);
3432 bwi_bus_attach(struct bwi_softc *sc)
3434 struct bwi_regwin *bus, *old;
3437 bus = &sc->sc_bus_regwin;
3439 error = bwi_regwin_switch(sc, bus, &old);
3443 if (!bwi_regwin_is_enabled(sc, bus))
3444 bwi_regwin_enable(sc, bus, 0);
3446 /* Disable interripts */
3447 CSR_WRITE_4(sc, BWI_INTRVEC, 0);
3449 return bwi_regwin_switch(sc, old, NULL);
3453 bwi_regwin_name(const struct bwi_regwin *rw)
3455 switch (rw->rw_type) {
3456 case BWI_REGWIN_T_COM:
3458 case BWI_REGWIN_T_BUSPCI:
3460 case BWI_REGWIN_T_MAC:
3462 case BWI_REGWIN_T_BUSPCIE:
3465 panic("unknown regwin type 0x%04x\n", rw->rw_type);
3470 bwi_regwin_disable_bits(struct bwi_softc *sc)
3474 /* XXX cache this */
3475 busrev = __SHIFTOUT(CSR_READ_4(sc, BWI_ID_LO), BWI_ID_LO_BUSREV_MASK);
3476 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_MISC,
3477 "bus rev %u\n", busrev);
3479 if (busrev == BWI_BUSREV_0)
3480 return BWI_STATE_LO_DISABLE1;
3481 else if (busrev == BWI_BUSREV_1)
3482 return BWI_STATE_LO_DISABLE2;
3484 return (BWI_STATE_LO_DISABLE1 | BWI_STATE_LO_DISABLE2);
3488 bwi_regwin_is_enabled(struct bwi_softc *sc, struct bwi_regwin *rw)
3490 uint32_t val, disable_bits;
3492 disable_bits = bwi_regwin_disable_bits(sc);
3493 val = CSR_READ_4(sc, BWI_STATE_LO);
3495 if ((val & (BWI_STATE_LO_CLOCK |
3496 BWI_STATE_LO_RESET |
3497 disable_bits)) == BWI_STATE_LO_CLOCK) {
3498 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is enabled\n",
3499 bwi_regwin_name(rw));
3502 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is disabled\n",
3503 bwi_regwin_name(rw));
3509 bwi_regwin_disable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags)
3511 uint32_t state_lo, disable_bits;
3514 state_lo = CSR_READ_4(sc, BWI_STATE_LO);
3517 * If current regwin is in 'reset' state, it was already disabled.
3519 if (state_lo & BWI_STATE_LO_RESET) {
3520 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT,
3521 "%s was already disabled\n", bwi_regwin_name(rw));
3525 disable_bits = bwi_regwin_disable_bits(sc);
3528 * Disable normal clock
3530 state_lo = BWI_STATE_LO_CLOCK | disable_bits;
3531 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3534 * Wait until normal clock is disabled
3537 for (i = 0; i < NRETRY; ++i) {
3538 state_lo = CSR_READ_4(sc, BWI_STATE_LO);
3539 if (state_lo & disable_bits)
3544 device_printf(sc->sc_dev, "%s disable clock timeout\n",
3545 bwi_regwin_name(rw));
3548 for (i = 0; i < NRETRY; ++i) {
3551 state_hi = CSR_READ_4(sc, BWI_STATE_HI);
3552 if ((state_hi & BWI_STATE_HI_BUSY) == 0)
3557 device_printf(sc->sc_dev, "%s wait BUSY unset timeout\n",
3558 bwi_regwin_name(rw));
3563 * Reset and disable regwin with gated clock
3565 state_lo = BWI_STATE_LO_RESET | disable_bits |
3566 BWI_STATE_LO_CLOCK | BWI_STATE_LO_GATED_CLOCK |
3567 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3568 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3570 /* Flush pending bus write */
3571 CSR_READ_4(sc, BWI_STATE_LO);
3574 /* Reset and disable regwin */
3575 state_lo = BWI_STATE_LO_RESET | disable_bits |
3576 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3577 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3579 /* Flush pending bus write */
3580 CSR_READ_4(sc, BWI_STATE_LO);
3585 bwi_regwin_enable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags)
3587 uint32_t state_lo, state_hi, imstate;
3589 bwi_regwin_disable(sc, rw, flags);
3591 /* Reset regwin with gated clock */
3592 state_lo = BWI_STATE_LO_RESET |
3593 BWI_STATE_LO_CLOCK |
3594 BWI_STATE_LO_GATED_CLOCK |
3595 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3596 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3598 /* Flush pending bus write */
3599 CSR_READ_4(sc, BWI_STATE_LO);
3602 state_hi = CSR_READ_4(sc, BWI_STATE_HI);
3603 if (state_hi & BWI_STATE_HI_SERROR)
3604 CSR_WRITE_4(sc, BWI_STATE_HI, 0);
3606 imstate = CSR_READ_4(sc, BWI_IMSTATE);
3607 if (imstate & (BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT)) {
3608 imstate &= ~(BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT);
3609 CSR_WRITE_4(sc, BWI_IMSTATE, imstate);
3612 /* Enable regwin with gated clock */
3613 state_lo = BWI_STATE_LO_CLOCK |
3614 BWI_STATE_LO_GATED_CLOCK |
3615 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3616 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3618 /* Flush pending bus write */
3619 CSR_READ_4(sc, BWI_STATE_LO);
3622 /* Enable regwin with normal clock */
3623 state_lo = BWI_STATE_LO_CLOCK |
3624 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3625 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3627 /* Flush pending bus write */
3628 CSR_READ_4(sc, BWI_STATE_LO);
3633 bwi_set_bssid(struct bwi_softc *sc, const uint8_t *bssid)
3635 struct ieee80211com *ic = &sc->sc_ic;
3636 struct bwi_mac *mac;
3637 struct bwi_myaddr_bssid buf;
3642 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
3643 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3645 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_BSSID, bssid);
3647 bcopy(ic->ic_myaddr, buf.myaddr, sizeof(buf.myaddr));
3648 bcopy(bssid, buf.bssid, sizeof(buf.bssid));
3650 n = sizeof(buf) / sizeof(val);
3651 p = (const uint8_t *)&buf;
3652 for (i = 0; i < n; ++i) {
3656 for (j = 0; j < sizeof(val); ++j)
3657 val |= ((uint32_t)(*p++)) << (j * 8);
3659 TMPLT_WRITE_4(mac, 0x20 + (i * sizeof(val)), val);
3664 bwi_updateslot(struct ifnet *ifp)
3666 struct bwi_softc *sc = ifp->if_softc;
3667 struct ieee80211com *ic = &sc->sc_ic;
3668 struct bwi_mac *mac;
3670 if ((ifp->if_flags & IFF_RUNNING) == 0)
3673 ASSERT_SERIALIZED(ifp->if_serializer);
3675 DPRINTF(sc, BWI_DBG_80211, "%s\n", __func__);
3677 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
3678 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3680 bwi_mac_updateslot(mac, (ic->ic_flags & IEEE80211_F_SHSLOT));
3684 bwi_calibrate(void *xsc)
3686 struct bwi_softc *sc = xsc;
3687 struct ieee80211com *ic = &sc->sc_ic;
3688 struct ifnet *ifp = &ic->ic_if;
3690 lwkt_serialize_enter(ifp->if_serializer);
3692 if (ic->ic_state == IEEE80211_S_RUN) {
3693 struct bwi_mac *mac;
3695 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
3696 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3698 if (ic->ic_opmode != IEEE80211_M_MONITOR) {
3699 bwi_mac_calibrate_txpower(mac, sc->sc_txpwrcb_type);
3700 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB;
3703 /* XXX 15 seconds */
3704 callout_reset(&sc->sc_calib_ch, hz * 15, bwi_calibrate, sc);
3707 lwkt_serialize_exit(ifp->if_serializer);
3711 bwi_calc_rssi(struct bwi_softc *sc, const struct bwi_rxbuf_hdr *hdr)
3713 struct bwi_mac *mac;
3715 KKASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC);
3716 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3718 return bwi_rf_calc_rssi(mac, hdr);
3722 bwi_rx_radiotap(struct bwi_softc *sc, struct mbuf *m,
3723 struct bwi_rxbuf_hdr *hdr, const void *plcp,
3726 const struct ieee80211_frame_min *wh;
3728 KKASSERT(sc->sc_drvbpf != NULL);
3730 sc->sc_rx_th.wr_flags = IEEE80211_RADIOTAP_F_FCS;
3731 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_SHPREAMBLE)
3732 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
3734 wh = mtod(m, const struct ieee80211_frame_min *);
3735 if (wh->i_fc[1] & IEEE80211_FC1_WEP)
3736 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_WEP;
3738 sc->sc_rx_th.wr_tsf = hdr->rxh_tsf; /* No endian convertion */
3739 sc->sc_rx_th.wr_rate = rate;
3740 sc->sc_rx_th.wr_antsignal = rssi;
3741 sc->sc_rx_th.wr_antnoise = BWI_NOISE_FLOOR;
3743 bpf_ptap(sc->sc_drvbpf, m, &sc->sc_rx_th, sc->sc_rx_th_len);
3747 bwi_led_attach(struct bwi_softc *sc)
3749 const uint8_t *led_act = NULL;
3750 uint16_t gpio, val[BWI_LED_MAX];
3753 #define N(arr) (int)(sizeof(arr) / sizeof(arr[0]))
3755 for (i = 0; i < N(bwi_vendor_led_act); ++i) {
3756 if (sc->sc_pci_subvid == bwi_vendor_led_act[i].vid) {
3757 led_act = bwi_vendor_led_act[i].led_act;
3761 if (led_act == NULL)
3762 led_act = bwi_default_led_act;
3766 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO01);
3767 val[0] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_0);
3768 val[1] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_1);
3770 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO23);
3771 val[2] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_2);
3772 val[3] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_3);
3774 for (i = 0; i < BWI_LED_MAX; ++i) {
3775 struct bwi_led *led = &sc->sc_leds[i];
3777 if (val[i] == 0xff) {
3778 led->l_act = led_act[i];
3780 if (val[i] & BWI_LED_ACT_LOW)
3781 led->l_flags |= BWI_LED_F_ACTLOW;
3782 led->l_act = __SHIFTOUT(val[i], BWI_LED_ACT_MASK);
3784 led->l_mask = (1 << i);
3786 if (led->l_act == BWI_LED_ACT_BLINK_SLOW ||
3787 led->l_act == BWI_LED_ACT_BLINK_POLL ||
3788 led->l_act == BWI_LED_ACT_BLINK) {
3789 led->l_flags |= BWI_LED_F_BLINK;
3790 if (led->l_act == BWI_LED_ACT_BLINK_POLL)
3791 led->l_flags |= BWI_LED_F_POLLABLE;
3792 else if (led->l_act == BWI_LED_ACT_BLINK_SLOW)
3793 led->l_flags |= BWI_LED_F_SLOW;
3795 if (sc->sc_blink_led == NULL) {
3796 sc->sc_blink_led = led;
3797 if (led->l_flags & BWI_LED_F_SLOW)
3798 BWI_LED_SLOWDOWN(sc->sc_led_idle);
3802 DPRINTF(sc, BWI_DBG_LED | BWI_DBG_ATTACH,
3803 "%dth led, act %d, lowact %d\n", i,
3804 led->l_act, led->l_flags & BWI_LED_F_ACTLOW);
3806 callout_init(&sc->sc_led_blink_ch);
3809 static __inline uint16_t
3810 bwi_led_onoff(const struct bwi_led *led, uint16_t val, int on)
3812 if (led->l_flags & BWI_LED_F_ACTLOW)
3817 val &= ~led->l_mask;
3822 bwi_led_newstate(struct bwi_softc *sc, enum ieee80211_state nstate)
3824 struct ieee80211com *ic = &sc->sc_ic;
3828 if (nstate == IEEE80211_S_INIT) {
3829 callout_stop(&sc->sc_led_blink_ch);
3830 sc->sc_led_blinking = 0;
3833 if ((ic->ic_if.if_flags & IFF_RUNNING) == 0)
3836 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
3837 for (i = 0; i < BWI_LED_MAX; ++i) {
3838 struct bwi_led *led = &sc->sc_leds[i];
3841 if (led->l_act == BWI_LED_ACT_UNKN ||
3842 led->l_act == BWI_LED_ACT_NULL)
3845 if ((led->l_flags & BWI_LED_F_BLINK) &&
3846 nstate != IEEE80211_S_INIT)
3849 switch (led->l_act) {
3850 case BWI_LED_ACT_ON: /* Always on */
3853 case BWI_LED_ACT_OFF: /* Always off */
3854 case BWI_LED_ACT_5GHZ: /* TODO: 11A */
3860 case IEEE80211_S_INIT:
3863 case IEEE80211_S_RUN:
3864 if (led->l_act == BWI_LED_ACT_11G &&
3865 ic->ic_curmode != IEEE80211_MODE_11G)
3869 if (led->l_act == BWI_LED_ACT_ASSOC)
3876 val = bwi_led_onoff(led, val, on);
3878 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
3882 bwi_led_event(struct bwi_softc *sc, int event)
3884 struct bwi_led *led = sc->sc_blink_led;
3887 if (event == BWI_LED_EVENT_POLL) {
3888 if ((led->l_flags & BWI_LED_F_POLLABLE) == 0)
3890 if (ticks - sc->sc_led_ticks < sc->sc_led_idle)
3894 sc->sc_led_ticks = ticks;
3895 if (sc->sc_led_blinking)
3899 case BWI_LED_EVENT_RX:
3900 rate = sc->sc_rx_rate;
3902 case BWI_LED_EVENT_TX:
3903 rate = sc->sc_tx_rate;
3905 case BWI_LED_EVENT_POLL:
3909 panic("unknown LED event %d\n", event);
3912 bwi_led_blink_start(sc, bwi_led_duration[rate].on_dur,
3913 bwi_led_duration[rate].off_dur);
3917 bwi_led_blink_start(struct bwi_softc *sc, int on_dur, int off_dur)
3919 struct bwi_led *led = sc->sc_blink_led;
3922 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
3923 val = bwi_led_onoff(led, val, 1);
3924 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
3926 if (led->l_flags & BWI_LED_F_SLOW) {
3927 BWI_LED_SLOWDOWN(on_dur);
3928 BWI_LED_SLOWDOWN(off_dur);
3931 sc->sc_led_blinking = 1;
3932 sc->sc_led_blink_offdur = off_dur;
3934 callout_reset(&sc->sc_led_blink_ch, on_dur, bwi_led_blink_next, sc);
3938 bwi_led_blink_next(void *xsc)
3940 struct bwi_softc *sc = xsc;
3943 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
3944 val = bwi_led_onoff(sc->sc_blink_led, val, 0);
3945 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
3947 callout_reset(&sc->sc_led_blink_ch, sc->sc_led_blink_offdur,
3948 bwi_led_blink_end, sc);
3952 bwi_led_blink_end(void *xsc)
3954 struct bwi_softc *sc = xsc;
3956 sc->sc_led_blinking = 0;
3960 bwi_ratectl_attach(struct ieee80211com *ic, u_int rc)
3962 struct bwi_softc *sc = ic->ic_if.if_softc;
3965 case IEEE80211_RATECTL_ONOE:
3966 return &sc->sc_onoe_param;
3967 case IEEE80211_RATECTL_NONE:
3968 /* This could only happen during detaching */
3971 panic("unknown rate control algo %u\n", rc);