sys/dev/drm/i915/i915_debug.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Keith Packard <keithp@keithp.com>
  26  *
  27  * $FreeBSD: src/sys/dev/drm2/i915/i915_debug.c,v 1.1 2012/05/22 11:07:44 kib Exp $
  28  */
  29
  30 #include <drm/drmP.h>
  31 #include <drm/i915_drm.h>
  32 #include "i915_drv.h"
  33 #include "intel_drv.h"
  34 #include "intel_ringbuffer.h"
  35
  36 #include <sys/sysctl.h>
  37
  38 enum {
  39         ACTIVE_LIST,
  40         FLUSHING_LIST,
  41         INACTIVE_LIST,
  42         PINNED_LIST,
  43         DEFERRED_FREE_LIST,
  44 };
  45
  46 static const char *
  47 yesno(int v)
  48 {
  49         return (v ? "yes" : "no");
  50 }
  51
  52 static int
  53 i915_capabilities(struct drm_device *dev, struct sbuf *m, void *data)
  54 {
  55         const struct intel_device_info *info = INTEL_INFO(dev);
  56
  57         sbuf_printf(m, "gen: %d\n", info->gen);
  58         if (HAS_PCH_SPLIT(dev))
  59                 sbuf_printf(m, "pch: %d\n", INTEL_PCH_TYPE(dev));
  60 #define B(x) sbuf_printf(m, #x ": %s\n", yesno(info->x))
  61         B(is_mobile);
  62         B(is_i85x);
  63         B(is_i915g);
  64         B(is_i945gm);
  65         B(is_g33);
  66         B(need_gfx_hws);
  67         B(is_g4x);
  68         B(is_pineview);
  69         B(has_fbc);
  70         B(has_pipe_cxsr);
  71         B(has_hotplug);
  72         B(cursor_needs_physical);
  73         B(has_overlay);
  74         B(overlay_needs_physical);
  75         B(supports_tv);
  76         B(has_bsd_ring);
  77         B(has_blt_ring);
  78         B(has_llc);
  79 #undef B
  80
  81         return (0);
  82 }
  83
  84 static const char *
  85 get_pin_flag(struct drm_i915_gem_object *obj)
  86 {
  87         if (obj->user_pin_count > 0)
  88                 return "P";
  89         else if (obj->pin_count > 0)
  90                 return "p";
  91         else
  92                 return " ";
  93 }
  94
  95 static const char *
  96 get_tiling_flag(struct drm_i915_gem_object *obj)
  97 {
  98         switch (obj->tiling_mode) {
  99         default:
 100         case I915_TILING_NONE: return (" ");
 101         case I915_TILING_X: return ("X");
 102         case I915_TILING_Y: return ("Y");
 103         }
 104 }
 105
 106 static const char *
 107 cache_level_str(int type)
 108 {
 109         switch (type) {
 110         case I915_CACHE_NONE: return " uncached";
 111         case I915_CACHE_LLC: return " snooped (LLC)";
 112         case I915_CACHE_LLC_MLC: return " snooped (LLC+MLC)";
 113         default: return ("");
 114         }
 115 }
 116
 117 static void
 118 describe_obj(struct sbuf *m, struct drm_i915_gem_object *obj)
 119 {
 120
 121         sbuf_printf(m, "%p: %s%s %8zdKiB %04x %04x %d %d%s%s%s",
 122                    &obj->base,
 123                    get_pin_flag(obj),
 124                    get_tiling_flag(obj),
 125                    obj->base.size / 1024,
 126                    obj->base.read_domains,
 127                    obj->base.write_domain,
 128                    obj->last_rendering_seqno,
 129                    obj->last_fenced_seqno,
 130                    cache_level_str(obj->cache_level),
 131                    obj->dirty ? " dirty" : "",
 132                    obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
 133         if (obj->base.name)
 134                 sbuf_printf(m, " (name: %d)", obj->base.name);
 135         if (obj->fence_reg != I915_FENCE_REG_NONE)
 136                 sbuf_printf(m, " (fence: %d)", obj->fence_reg);
 137         if (obj->gtt_space != NULL)
 138                 sbuf_printf(m, " (gtt offset: %08x, size: %08x)",
 139                            obj->gtt_offset, (unsigned int)obj->gtt_space->size);
 140         if (obj->pin_mappable || obj->fault_mappable) {
 141                 char s[3], *t = s;
 142                 if (obj->pin_mappable)
 143                         *t++ = 'p';
 144                 if (obj->fault_mappable)
 145                         *t++ = 'f';
 146                 *t = '\0';
 147                 sbuf_printf(m, " (%s mappable)", s);
 148         }
 149         if (obj->ring != NULL)
 150                 sbuf_printf(m, " (%s)", obj->ring->name);
 151 }
 152
 153 static int
 154 i915_gem_object_list_info(struct drm_device *dev, struct sbuf *m, void *data)
 155 {
 156         uintptr_t list = (uintptr_t)data;
 157         struct list_head *head;
 158         drm_i915_private_t *dev_priv = dev->dev_private;
 159         struct drm_i915_gem_object *obj;
 160         size_t total_obj_size, total_gtt_size;
 161         int count;
 162
 163         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 164                 return (EINTR);
 165
 166         switch (list) {
 167         case ACTIVE_LIST:
 168                 sbuf_printf(m, "Active:\n");
 169                 head = &dev_priv->mm.active_list;
 170                 break;
 171         case INACTIVE_LIST:
 172                 sbuf_printf(m, "Inactive:\n");
 173                 head = &dev_priv->mm.inactive_list;
 174                 break;
 175         case PINNED_LIST:
 176                 sbuf_printf(m, "Pinned:\n");
 177                 head = &dev_priv->mm.pinned_list;
 178                 break;
 179         case FLUSHING_LIST:
 180                 sbuf_printf(m, "Flushing:\n");
 181                 head = &dev_priv->mm.flushing_list;
 182                 break;
 183         case DEFERRED_FREE_LIST:
 184                 sbuf_printf(m, "Deferred free:\n");
 185                 head = &dev_priv->mm.deferred_free_list;
 186                 break;
 187         default:
 188                 DRM_UNLOCK(dev);
 189                 return (EINVAL);
 190         }
 191
 192         total_obj_size = total_gtt_size = count = 0;
 193         list_for_each_entry(obj, head, mm_list) {
 194                 sbuf_printf(m, "   ");
 195                 describe_obj(m, obj);
 196                 sbuf_printf(m, "\n");
 197                 total_obj_size += obj->base.size;
 198                 total_gtt_size += obj->gtt_space->size;
 199                 count++;
 200         }
 201         DRM_UNLOCK(dev);
 202
 203         sbuf_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
 204                    count, total_obj_size, total_gtt_size);
 205         return (0);
 206 }
 207
 208 #define count_objects(list, member) do { \
 209         list_for_each_entry(obj, list, member) { \
 210                 size += obj->gtt_space->size; \
 211                 ++count; \
 212                 if (obj->map_and_fenceable) { \
 213                         mappable_size += obj->gtt_space->size; \
 214                         ++mappable_count; \
 215                 } \
 216         } \
 217 } while (0)
 218
 219 static int
 220 i915_gem_object_info(struct drm_device *dev, struct sbuf *m, void *data)
 221 {
 222         struct drm_i915_private *dev_priv = dev->dev_private;
 223         u32 count, mappable_count;
 224         size_t size, mappable_size;
 225         struct drm_i915_gem_object *obj;
 226
 227         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 228                 return (EINTR);
 229         sbuf_printf(m, "%u objects, %zu bytes\n",
 230                    dev_priv->mm.object_count,
 231                    dev_priv->mm.object_memory);
 232
 233         size = count = mappable_size = mappable_count = 0;
 234         count_objects(&dev_priv->mm.gtt_list, gtt_list);
 235         sbuf_printf(m, "%u [%u] objects, %zu [%zu] bytes in gtt\n",
 236                    count, mappable_count, size, mappable_size);
 237
 238         size = count = mappable_size = mappable_count = 0;
 239         count_objects(&dev_priv->mm.active_list, mm_list);
 240         count_objects(&dev_priv->mm.flushing_list, mm_list);
 241         sbuf_printf(m, "  %u [%u] active objects, %zu [%zu] bytes\n",
 242                    count, mappable_count, size, mappable_size);
 243
 244         size = count = mappable_size = mappable_count = 0;
 245         count_objects(&dev_priv->mm.pinned_list, mm_list);
 246         sbuf_printf(m, "  %u [%u] pinned objects, %zu [%zu] bytes\n",
 247                    count, mappable_count, size, mappable_size);
 248
 249         size = count = mappable_size = mappable_count = 0;
 250         count_objects(&dev_priv->mm.inactive_list, mm_list);
 251         sbuf_printf(m, "  %u [%u] inactive objects, %zu [%zu] bytes\n",
 252                    count, mappable_count, size, mappable_size);
 253
 254         size = count = mappable_size = mappable_count = 0;
 255         count_objects(&dev_priv->mm.deferred_free_list, mm_list);
 256         sbuf_printf(m, "  %u [%u] freed objects, %zu [%zu] bytes\n",
 257                    count, mappable_count, size, mappable_size);
 258
 259         size = count = mappable_size = mappable_count = 0;
 260         list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
 261                 if (obj->fault_mappable) {
 262                         size += obj->gtt_space->size;
 263                         ++count;
 264                 }
 265                 if (obj->pin_mappable) {
 266                         mappable_size += obj->gtt_space->size;
 267                         ++mappable_count;
 268                 }
 269         }
 270         sbuf_printf(m, "%u pinned mappable objects, %zu bytes\n",
 271                    mappable_count, mappable_size);
 272         sbuf_printf(m, "%u fault mappable objects, %zu bytes\n",
 273                    count, size);
 274
 275         sbuf_printf(m, "%zu [%zu] gtt total\n",
 276                    dev_priv->mm.gtt_total, dev_priv->mm.mappable_gtt_total);
 277         DRM_UNLOCK(dev);
 278
 279         return (0);
 280 }
 281
 282 static int
 283 i915_gem_gtt_info(struct drm_device *dev, struct sbuf *m, void* data)
 284 {
 285         struct drm_i915_private *dev_priv = dev->dev_private;
 286         struct drm_i915_gem_object *obj;
 287         size_t total_obj_size, total_gtt_size;
 288         int count;
 289
 290         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 291                 return (EINTR);
 292
 293         total_obj_size = total_gtt_size = count = 0;
 294         list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
 295                 sbuf_printf(m, "   ");
 296                 describe_obj(m, obj);
 297                 sbuf_printf(m, "\n");
 298                 total_obj_size += obj->base.size;
 299                 total_gtt_size += obj->gtt_space->size;
 300                 count++;
 301         }
 302
 303         DRM_UNLOCK(dev);
 304
 305         sbuf_printf(m, "Total %d objects, %zu bytes, %zu GTT size\n",
 306                    count, total_obj_size, total_gtt_size);
 307
 308         return (0);
 309 }
 310
 311 static int
 312 i915_gem_pageflip_info(struct drm_device *dev, struct sbuf *m, void *data)
 313 {
 314         struct intel_crtc *crtc;
 315         struct drm_i915_gem_object *obj;
 316         struct intel_unpin_work *work;
 317         char pipe;
 318         char plane;
 319
 320         if ((dev->driver->driver_features & DRIVER_MODESET) == 0)
 321                 return (0);
 322         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
 323                 pipe = pipe_name(crtc->pipe);
 324                 plane = plane_name(crtc->plane);
 325
 326                 lockmgr(&dev->event_lock, LK_EXCLUSIVE);
 327                 work = crtc->unpin_work;
 328                 if (work == NULL) {
 329                         sbuf_printf(m, "No flip due on pipe %c (plane %c)\n",
 330                                    pipe, plane);
 331                 } else {
 332                         if (!work->pending) {
 333                                 sbuf_printf(m, "Flip queued on pipe %c (plane %c)\n",
 334                                            pipe, plane);
 335                         } else {
 336                                 sbuf_printf(m, "Flip pending (waiting for vsync) on pipe %c (plane %c)\n",
 337                                            pipe, plane);
 338                         }
 339                         if (work->enable_stall_check)
 340                                 sbuf_printf(m, "Stall check enabled, ");
 341                         else
 342                                 sbuf_printf(m, "Stall check waiting for page flip ioctl, ");
 343                         sbuf_printf(m, "%d prepares\n", work->pending);
 344
 345                         if (work->old_fb_obj) {
 346                                 obj = work->old_fb_obj;
 347                                 if (obj)
 348                                         sbuf_printf(m, "Old framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
 349                         }
 350                         if (work->pending_flip_obj) {
 351                                 obj = work->pending_flip_obj;
 352                                 if (obj)
 353                                         sbuf_printf(m, "New framebuffer gtt_offset 0x%08x\n", obj->gtt_offset);
 354                         }
 355                 }
 356                 lockmgr(&dev->event_lock, LK_RELEASE);
 357         }
 358
 359         return (0);
 360 }
 361
 362 static int
 363 i915_gem_request_info(struct drm_device *dev, struct sbuf *m, void *data)
 364 {
 365         drm_i915_private_t *dev_priv = dev->dev_private;
 366         struct drm_i915_gem_request *gem_request;
 367         int count;
 368
 369         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 370                 return (EINTR);
 371
 372         count = 0;
 373         if (!list_empty(&dev_priv->rings[RCS].request_list)) {
 374                 sbuf_printf(m, "Render requests:\n");
 375                 list_for_each_entry(gem_request,
 376                                     &dev_priv->rings[RCS].request_list,
 377                                     list) {
 378                         sbuf_printf(m, "    %d @ %d\n",
 379                                    gem_request->seqno,
 380                                    (int) (jiffies - gem_request->emitted_jiffies));
 381                 }
 382                 count++;
 383         }
 384         if (!list_empty(&dev_priv->rings[VCS].request_list)) {
 385                 sbuf_printf(m, "BSD requests:\n");
 386                 list_for_each_entry(gem_request,
 387                                     &dev_priv->rings[VCS].request_list,
 388                                     list) {
 389                         sbuf_printf(m, "    %d @ %d\n",
 390                                    gem_request->seqno,
 391                                    (int) (jiffies - gem_request->emitted_jiffies));
 392                 }
 393                 count++;
 394         }
 395         if (!list_empty(&dev_priv->rings[BCS].request_list)) {
 396                 sbuf_printf(m, "BLT requests:\n");
 397                 list_for_each_entry(gem_request,
 398                                     &dev_priv->rings[BCS].request_list,
 399                                     list) {
 400                         sbuf_printf(m, "    %d @ %d\n",
 401                                    gem_request->seqno,
 402                                    (int) (jiffies - gem_request->emitted_jiffies));
 403                 }
 404                 count++;
 405         }
 406         DRM_UNLOCK(dev);
 407
 408         if (count == 0)
 409                 sbuf_printf(m, "No requests\n");
 410
 411         return 0;
 412 }
 413
 414 static void
 415 i915_ring_seqno_info(struct sbuf *m, struct intel_ring_buffer *ring)
 416 {
 417         if (ring->get_seqno) {
 418                 sbuf_printf(m, "Current sequence (%s): %d\n",
 419                            ring->name, ring->get_seqno(ring));
 420                 sbuf_printf(m, "Waiter sequence (%s):  %d\n",
 421                            ring->name, ring->waiting_seqno);
 422                 sbuf_printf(m, "IRQ sequence (%s):     %d\n",
 423                            ring->name, ring->irq_seqno);
 424         }
 425 }
 426
 427 static int
 428 i915_gem_seqno_info(struct drm_device *dev, struct sbuf *m, void *data)
 429 {
 430         drm_i915_private_t *dev_priv = dev->dev_private;
 431         int i;
 432
 433         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 434                 return (EINTR);
 435         for (i = 0; i < I915_NUM_RINGS; i++)
 436                 i915_ring_seqno_info(m, &dev_priv->rings[i]);
 437         DRM_UNLOCK(dev);
 438         return (0);
 439 }
 440
 441
 442 static int
 443 i915_interrupt_info(struct drm_device *dev, struct sbuf *m, void *data)
 444 {
 445         drm_i915_private_t *dev_priv = dev->dev_private;
 446         int i, pipe;
 447
 448         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 449                 return (EINTR);
 450
 451         if (!HAS_PCH_SPLIT(dev)) {
 452                 sbuf_printf(m, "Interrupt enable:    %08x\n",
 453                            I915_READ(IER));
 454                 sbuf_printf(m, "Interrupt identity:  %08x\n",
 455                            I915_READ(IIR));
 456                 sbuf_printf(m, "Interrupt mask:      %08x\n",
 457                            I915_READ(IMR));
 458                 for_each_pipe(pipe)
 459                         sbuf_printf(m, "Pipe %c stat:         %08x\n",
 460                                    pipe_name(pipe),
 461                                    I915_READ(PIPESTAT(pipe)));
 462         } else {
 463                 sbuf_printf(m, "North Display Interrupt enable:         %08x\n",
 464                            I915_READ(DEIER));
 465                 sbuf_printf(m, "North Display Interrupt identity:       %08x\n",
 466                            I915_READ(DEIIR));
 467                 sbuf_printf(m, "North Display Interrupt mask:           %08x\n",
 468                            I915_READ(DEIMR));
 469                 sbuf_printf(m, "South Display Interrupt enable:         %08x\n",
 470                            I915_READ(SDEIER));
 471                 sbuf_printf(m, "South Display Interrupt identity:       %08x\n",
 472                            I915_READ(SDEIIR));
 473                 sbuf_printf(m, "South Display Interrupt mask:           %08x\n",
 474                            I915_READ(SDEIMR));
 475                 sbuf_printf(m, "Graphics Interrupt enable:              %08x\n",
 476                            I915_READ(GTIER));
 477                 sbuf_printf(m, "Graphics Interrupt identity:            %08x\n",
 478                            I915_READ(GTIIR));
 479                 sbuf_printf(m, "Graphics Interrupt mask:                %08x\n",
 480                            I915_READ(GTIMR));
 481         }
 482         sbuf_printf(m, "Interrupts received: %d\n",
 483                    atomic_read(&dev_priv->irq_received));
 484         for (i = 0; i < I915_NUM_RINGS; i++) {
 485                 if (IS_GEN6(dev) || IS_GEN7(dev)) {
 486                         sbuf_printf(m, "Graphics Interrupt mask (%s):   %08x\n",
 487                                    dev_priv->rings[i].name,
 488                                    I915_READ_IMR(&dev_priv->rings[i]));
 489                 }
 490                 i915_ring_seqno_info(m, &dev_priv->rings[i]);
 491         }
 492         DRM_UNLOCK(dev);
 493
 494         return (0);
 495 }
 496
 497 static int
 498 i915_gem_fence_regs_info(struct drm_device *dev, struct sbuf *m, void *data)
 499 {
 500         drm_i915_private_t *dev_priv = dev->dev_private;
 501         int i;
 502
 503         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 504                 return (EINTR);
 505
 506         sbuf_printf(m, "Reserved fences = %d\n", dev_priv->fence_reg_start);
 507         sbuf_printf(m, "Total fences = %d\n", dev_priv->num_fence_regs);
 508         for (i = 0; i < dev_priv->num_fence_regs; i++) {
 509                 struct drm_i915_gem_object *obj = dev_priv->fence_regs[i].obj;
 510
 511                 sbuf_printf(m, "Fenced object[%2d] = ", i);
 512                 if (obj == NULL)
 513                         sbuf_printf(m, "unused");
 514                 else
 515                         describe_obj(m, obj);
 516                 sbuf_printf(m, "\n");
 517         }
 518
 519         DRM_UNLOCK(dev);
 520         return (0);
 521 }
 522
 523 static int
 524 i915_hws_info(struct drm_device *dev, struct sbuf *m, void *data)
 525 {
 526         drm_i915_private_t *dev_priv = dev->dev_private;
 527         struct intel_ring_buffer *ring;
 528         const volatile u32 *hws;
 529         int i;
 530
 531         ring = &dev_priv->rings[(uintptr_t)data];
 532         hws = (volatile u32 *)ring->status_page.page_addr;
 533         if (hws == NULL)
 534                 return (0);
 535
 536         for (i = 0; i < 4096 / sizeof(u32) / 4; i += 4) {
 537                 sbuf_printf(m, "0x%08x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
 538                            i * 4,
 539                            hws[i], hws[i + 1], hws[i + 2], hws[i + 3]);
 540         }
 541         return (0);
 542 }
 543
 544 static int
 545 i915_ringbuffer_data(struct drm_device *dev, struct sbuf *m, void *data)
 546 {
 547         drm_i915_private_t *dev_priv = dev->dev_private;
 548         struct intel_ring_buffer *ring;
 549
 550         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 551                 return (EINTR);
 552         ring = &dev_priv->rings[(uintptr_t)data];
 553         if (!ring->obj) {
 554                 sbuf_printf(m, "No ringbuffer setup\n");
 555         } else {
 556                 u8 *virt = ring->virtual_start;
 557                 uint32_t off;
 558
 559                 for (off = 0; off < ring->size; off += 4) {
 560                         uint32_t *ptr = (uint32_t *)(virt + off);
 561                         sbuf_printf(m, "%08x :  %08x\n", off, *ptr);
 562                 }
 563         }
 564         DRM_UNLOCK(dev);
 565         return (0);
 566 }
 567
 568 static int
 569 i915_ringbuffer_info(struct drm_device *dev, struct sbuf *m, void *data)
 570 {
 571         drm_i915_private_t *dev_priv = dev->dev_private;
 572         struct intel_ring_buffer *ring;
 573
 574         ring = &dev_priv->rings[(uintptr_t)data];
 575         if (ring->size == 0)
 576                 return (0);
 577
 578         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 579                 return (EINTR);
 580
 581         sbuf_printf(m, "Ring %s:\n", ring->name);
 582         sbuf_printf(m, "  Head :    %08x\n", I915_READ_HEAD(ring) & HEAD_ADDR);
 583         sbuf_printf(m, "  Tail :    %08x\n", I915_READ_TAIL(ring) & TAIL_ADDR);
 584         sbuf_printf(m, "  Size :    %08x\n", ring->size);
 585         sbuf_printf(m, "  Active :  %08x\n", intel_ring_get_active_head(ring));
 586         sbuf_printf(m, "  NOPID :   %08x\n", I915_READ_NOPID(ring));
 587         if (IS_GEN6(dev) || IS_GEN7(dev)) {
 588                 sbuf_printf(m, "  Sync 0 :   %08x\n", I915_READ_SYNC_0(ring));
 589                 sbuf_printf(m, "  Sync 1 :   %08x\n", I915_READ_SYNC_1(ring));
 590         }
 591         sbuf_printf(m, "  Control : %08x\n", I915_READ_CTL(ring));
 592         sbuf_printf(m, "  Start :   %08x\n", I915_READ_START(ring));
 593
 594         DRM_UNLOCK(dev);
 595
 596         return (0);
 597 }
 598
 599 static const char *
 600 ring_str(int ring)
 601 {
 602         switch (ring) {
 603         case RCS: return (" render");
 604         case VCS: return (" bsd");
 605         case BCS: return (" blt");
 606         default: return ("");
 607         }
 608 }
 609
 610 static const char *
 611 pin_flag(int pinned)
 612 {
 613         if (pinned > 0)
 614                 return (" P");
 615         else if (pinned < 0)
 616                 return (" p");
 617         else
 618                 return ("");
 619 }
 620
 621 static const char *tiling_flag(int tiling)
 622 {
 623         switch (tiling) {
 624         default:
 625         case I915_TILING_NONE: return "";
 626         case I915_TILING_X: return " X";
 627         case I915_TILING_Y: return " Y";
 628         }
 629 }
 630
 631 static const char *dirty_flag(int dirty)
 632 {
 633         return dirty ? " dirty" : "";
 634 }
 635
 636 static const char *purgeable_flag(int purgeable)
 637 {
 638         return purgeable ? " purgeable" : "";
 639 }
 640
 641 static void print_error_buffers(struct sbuf *m, const char *name,
 642     struct drm_i915_error_buffer *err, int count)
 643 {
 644
 645         sbuf_printf(m, "%s [%d]:\n", name, count);
 646
 647         while (count--) {
 648                 sbuf_printf(m, "  %08x %8u %04x %04x %08x%s%s%s%s%s%s%s",
 649                            err->gtt_offset,
 650                            err->size,
 651                            err->read_domains,
 652                            err->write_domain,
 653                            err->seqno,
 654                            pin_flag(err->pinned),
 655                            tiling_flag(err->tiling),
 656                            dirty_flag(err->dirty),
 657                            purgeable_flag(err->purgeable),
 658                            err->ring != -1 ? " " : "",
 659                            ring_str(err->ring),
 660                            cache_level_str(err->cache_level));
 661
 662                 if (err->name)
 663                         sbuf_printf(m, " (name: %d)", err->name);
 664                 if (err->fence_reg != I915_FENCE_REG_NONE)
 665                         sbuf_printf(m, " (fence: %d)", err->fence_reg);
 666
 667                 sbuf_printf(m, "\n");
 668                 err++;
 669         }
 670 }
 671
 672 static void
 673 i915_ring_error_state(struct sbuf *m, struct drm_device *dev,
 674     struct drm_i915_error_state *error, unsigned ring)
 675 {
 676
 677         sbuf_printf(m, "%s command stream:\n", ring_str(ring));
 678         sbuf_printf(m, "  HEAD: 0x%08x\n", error->head[ring]);
 679         sbuf_printf(m, "  TAIL: 0x%08x\n", error->tail[ring]);
 680         sbuf_printf(m, "  ACTHD: 0x%08x\n", error->acthd[ring]);
 681         sbuf_printf(m, "  IPEIR: 0x%08x\n", error->ipeir[ring]);
 682         sbuf_printf(m, "  IPEHR: 0x%08x\n", error->ipehr[ring]);
 683         sbuf_printf(m, "  INSTDONE: 0x%08x\n", error->instdone[ring]);
 684         if (ring == RCS && INTEL_INFO(dev)->gen >= 4) {
 685                 sbuf_printf(m, "  INSTDONE1: 0x%08x\n", error->instdone1);
 686                 sbuf_printf(m, "  BBADDR: 0x%08jx\n", (uintmax_t)error->bbaddr);
 687         }
 688         if (INTEL_INFO(dev)->gen >= 4)
 689                 sbuf_printf(m, "  INSTPS: 0x%08x\n", error->instps[ring]);
 690         sbuf_printf(m, "  INSTPM: 0x%08x\n", error->instpm[ring]);
 691         if (INTEL_INFO(dev)->gen >= 6) {
 692                 sbuf_printf(m, "  FADDR: 0x%08x\n", error->faddr[ring]);
 693                 sbuf_printf(m, "  FAULT_REG: 0x%08x\n", error->fault_reg[ring]);
 694                 sbuf_printf(m, "  SYNC_0: 0x%08x\n",
 695                            error->semaphore_mboxes[ring][0]);
 696                 sbuf_printf(m, "  SYNC_1: 0x%08x\n",
 697                            error->semaphore_mboxes[ring][1]);
 698         }
 699         sbuf_printf(m, "  seqno: 0x%08x\n", error->seqno[ring]);
 700         sbuf_printf(m, "  ring->head: 0x%08x\n", error->cpu_ring_head[ring]);
 701         sbuf_printf(m, "  ring->tail: 0x%08x\n", error->cpu_ring_tail[ring]);
 702 }
 703
 704 static int i915_error_state(struct drm_device *dev, struct sbuf *m,
 705     void *unused)
 706 {
 707         drm_i915_private_t *dev_priv = dev->dev_private;
 708         struct drm_i915_error_state *error;
 709         int i, j, page, offset, elt;
 710
 711         lockmgr(&dev_priv->error_lock, LK_EXCLUSIVE);
 712         if (!dev_priv->first_error) {
 713                 sbuf_printf(m, "no error state collected\n");
 714                 goto out;
 715         }
 716
 717         error = dev_priv->first_error;
 718
 719         sbuf_printf(m, "Time: %jd s %jd us\n", (intmax_t)error->time.tv_sec,
 720             (intmax_t)error->time.tv_usec);
 721         sbuf_printf(m, "PCI ID: 0x%04x\n", dev->pci_device);
 722         sbuf_printf(m, "EIR: 0x%08x\n", error->eir);
 723         sbuf_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
 724
 725         for (i = 0; i < dev_priv->num_fence_regs; i++)
 726                 sbuf_printf(m, "  fence[%d] = %08jx\n", i,
 727                     (uintmax_t)error->fence[i]);
 728
 729         if (INTEL_INFO(dev)->gen >= 6) {
 730                 sbuf_printf(m, "ERROR: 0x%08x\n", error->error);
 731                 sbuf_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
 732         }
 733
 734         i915_ring_error_state(m, dev, error, RCS);
 735         if (HAS_BLT(dev))
 736                 i915_ring_error_state(m, dev, error, BCS);
 737         if (HAS_BSD(dev))
 738                 i915_ring_error_state(m, dev, error, VCS);
 739
 740         if (error->active_bo)
 741                 print_error_buffers(m, "Active",
 742                                     error->active_bo,
 743                                     error->active_bo_count);
 744
 745         if (error->pinned_bo)
 746                 print_error_buffers(m, "Pinned",
 747                                     error->pinned_bo,
 748                                     error->pinned_bo_count);
 749
 750         for (i = 0; i < DRM_ARRAY_SIZE(error->ring); i++) {
 751                 struct drm_i915_error_object *obj;
 752
 753                 if ((obj = error->ring[i].batchbuffer)) {
 754                         sbuf_printf(m, "%s --- gtt_offset = 0x%08x\n",
 755                                    dev_priv->rings[i].name,
 756                                    obj->gtt_offset);
 757                         offset = 0;
 758                         for (page = 0; page < obj->page_count; page++) {
 759                                 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
 760                                         sbuf_printf(m, "%08x :  %08x\n",
 761                                             offset, obj->pages[page][elt]);
 762                                         offset += 4;
 763                                 }
 764                         }
 765                 }
 766
 767                 if (error->ring[i].num_requests) {
 768                         sbuf_printf(m, "%s --- %d requests\n",
 769                                    dev_priv->rings[i].name,
 770                                    error->ring[i].num_requests);
 771                         for (j = 0; j < error->ring[i].num_requests; j++) {
 772                                 sbuf_printf(m, "  seqno 0x%08x, emitted %ld, tail 0x%08x\n",
 773                                            error->ring[i].requests[j].seqno,
 774                                            error->ring[i].requests[j].jiffies,
 775                                            error->ring[i].requests[j].tail);
 776                         }
 777                 }
 778
 779                 if ((obj = error->ring[i].ringbuffer)) {
 780                         sbuf_printf(m, "%s --- ringbuffer = 0x%08x\n",
 781                                    dev_priv->rings[i].name,
 782                                    obj->gtt_offset);
 783                         offset = 0;
 784                         for (page = 0; page < obj->page_count; page++) {
 785                                 for (elt = 0; elt < PAGE_SIZE/4; elt++) {
 786                                         sbuf_printf(m, "%08x :  %08x\n",
 787                                                    offset,
 788                                                    obj->pages[page][elt]);
 789                                         offset += 4;
 790                                 }
 791                         }
 792                 }
 793         }
 794
 795         if (error->overlay)
 796                 intel_overlay_print_error_state(m, error->overlay);
 797
 798         if (error->display)
 799                 intel_display_print_error_state(m, dev, error->display);
 800
 801 out:
 802         lockmgr(&dev_priv->error_lock, LK_RELEASE);
 803
 804         return (0);
 805 }
 806
 807 static int
 808 i915_rstdby_delays(struct drm_device *dev, struct sbuf *m, void *unused)
 809 {
 810         drm_i915_private_t *dev_priv = dev->dev_private;
 811         u16 crstanddelay;
 812
 813         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 814                 return (EINTR);
 815         crstanddelay = I915_READ16(CRSTANDVID);
 816         DRM_UNLOCK(dev);
 817
 818         sbuf_printf(m, "w/ctx: %d, w/o ctx: %d\n",
 819             (crstanddelay >> 8) & 0x3f, (crstanddelay & 0x3f));
 820
 821         return 0;
 822 }
 823
 824 static int
 825 i915_cur_delayinfo(struct drm_device *dev, struct sbuf *m, void *unused)
 826 {
 827         drm_i915_private_t *dev_priv = dev->dev_private;
 828
 829         if (IS_GEN5(dev)) {
 830                 u16 rgvswctl = I915_READ16(MEMSWCTL);
 831                 u16 rgvstat = I915_READ16(MEMSTAT_ILK);
 832
 833                 sbuf_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
 834                 sbuf_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
 835                 sbuf_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
 836                            MEMSTAT_VID_SHIFT);
 837                 sbuf_printf(m, "Current P-state: %d\n",
 838                            (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
 839         } else if (IS_GEN6(dev)) {
 840                 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
 841                 u32 rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
 842                 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
 843                 u32 rpstat;
 844                 u32 rpupei, rpcurup, rpprevup;
 845                 u32 rpdownei, rpcurdown, rpprevdown;
 846                 int max_freq;
 847
 848                 /* RPSTAT1 is in the GT power well */
 849                 if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 850                         return (EINTR);
 851                 gen6_gt_force_wake_get(dev_priv);
 852
 853                 rpstat = I915_READ(GEN6_RPSTAT1);
 854                 rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
 855                 rpcurup = I915_READ(GEN6_RP_CUR_UP);
 856                 rpprevup = I915_READ(GEN6_RP_PREV_UP);
 857                 rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI);
 858                 rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
 859                 rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
 860
 861                 gen6_gt_force_wake_put(dev_priv);
 862                 DRM_UNLOCK(dev);
 863
 864                 sbuf_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
 865                 sbuf_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
 866                 sbuf_printf(m, "Render p-state ratio: %d\n",
 867                            (gt_perf_status & 0xff00) >> 8);
 868                 sbuf_printf(m, "Render p-state VID: %d\n",
 869                            gt_perf_status & 0xff);
 870                 sbuf_printf(m, "Render p-state limit: %d\n",
 871                            rp_state_limits & 0xff);
 872                 sbuf_printf(m, "CAGF: %dMHz\n", ((rpstat & GEN6_CAGF_MASK) >>
 873                                                 GEN6_CAGF_SHIFT) * 50);
 874                 sbuf_printf(m, "RP CUR UP EI: %dus\n", rpupei &
 875                            GEN6_CURICONT_MASK);
 876                 sbuf_printf(m, "RP CUR UP: %dus\n", rpcurup &
 877                            GEN6_CURBSYTAVG_MASK);
 878                 sbuf_printf(m, "RP PREV UP: %dus\n", rpprevup &
 879                            GEN6_CURBSYTAVG_MASK);
 880                 sbuf_printf(m, "RP CUR DOWN EI: %dus\n", rpdownei &
 881                            GEN6_CURIAVG_MASK);
 882                 sbuf_printf(m, "RP CUR DOWN: %dus\n", rpcurdown &
 883                            GEN6_CURBSYTAVG_MASK);
 884                 sbuf_printf(m, "RP PREV DOWN: %dus\n", rpprevdown &
 885                            GEN6_CURBSYTAVG_MASK);
 886
 887                 max_freq = (rp_state_cap & 0xff0000) >> 16;
 888                 sbuf_printf(m, "Lowest (RPN) frequency: %dMHz\n",
 889                            max_freq * 50);
 890
 891                 max_freq = (rp_state_cap & 0xff00) >> 8;
 892                 sbuf_printf(m, "Nominal (RP1) frequency: %dMHz\n",
 893                            max_freq * 50);
 894
 895                 max_freq = rp_state_cap & 0xff;
 896                 sbuf_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
 897                            max_freq * 50);
 898         } else {
 899                 sbuf_printf(m, "no P-state info available\n");
 900         }
 901
 902         return 0;
 903 }
 904
 905 static int
 906 i915_delayfreq_table(struct drm_device *dev, struct sbuf *m, void *unused)
 907 {
 908         drm_i915_private_t *dev_priv = dev->dev_private;
 909         u32 delayfreq;
 910         int i;
 911
 912         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 913                 return (EINTR);
 914         for (i = 0; i < 16; i++) {
 915                 delayfreq = I915_READ(PXVFREQ_BASE + i * 4);
 916                 sbuf_printf(m, "P%02dVIDFREQ: 0x%08x (VID: %d)\n", i, delayfreq,
 917                            (delayfreq & PXVFREQ_PX_MASK) >> PXVFREQ_PX_SHIFT);
 918         }
 919         DRM_UNLOCK(dev);
 920         return (0);
 921 }
 922
 923 static inline int
 924 MAP_TO_MV(int map)
 925 {
 926         return 1250 - (map * 25);
 927 }
 928
 929 static int
 930 i915_inttoext_table(struct drm_device *dev, struct sbuf *m, void *unused)
 931 {
 932         drm_i915_private_t *dev_priv = dev->dev_private;
 933         u32 inttoext;
 934         int i;
 935
 936         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 937                 return (EINTR);
 938         for (i = 1; i <= 32; i++) {
 939                 inttoext = I915_READ(INTTOEXT_BASE_ILK + i * 4);
 940                 sbuf_printf(m, "INTTOEXT%02d: 0x%08x\n", i, inttoext);
 941         }
 942         DRM_UNLOCK(dev);
 943
 944         return (0);
 945 }
 946
 947 static int
 948 ironlake_drpc_info(struct drm_device *dev, struct sbuf *m)
 949 {
 950         drm_i915_private_t *dev_priv = dev->dev_private;
 951         u32 rgvmodectl;
 952         u32 rstdbyctl;
 953         u16 crstandvid;
 954
 955         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
 956                 return (EINTR);
 957         rgvmodectl = I915_READ(MEMMODECTL);
 958         rstdbyctl = I915_READ(RSTDBYCTL);
 959         crstandvid = I915_READ16(CRSTANDVID);
 960         DRM_UNLOCK(dev);
 961
 962         sbuf_printf(m, "HD boost: %s\n", (rgvmodectl & MEMMODE_BOOST_EN) ?
 963                    "yes" : "no");
 964         sbuf_printf(m, "Boost freq: %d\n",
 965                    (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
 966                    MEMMODE_BOOST_FREQ_SHIFT);
 967         sbuf_printf(m, "HW control enabled: %s\n",
 968                    rgvmodectl & MEMMODE_HWIDLE_EN ? "yes" : "no");
 969         sbuf_printf(m, "SW control enabled: %s\n",
 970                    rgvmodectl & MEMMODE_SWMODE_EN ? "yes" : "no");
 971         sbuf_printf(m, "Gated voltage change: %s\n",
 972                    rgvmodectl & MEMMODE_RCLK_GATE ? "yes" : "no");
 973         sbuf_printf(m, "Starting frequency: P%d\n",
 974                    (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
 975         sbuf_printf(m, "Max P-state: P%d\n",
 976                    (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
 977         sbuf_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
 978         sbuf_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
 979         sbuf_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
 980         sbuf_printf(m, "Render standby enabled: %s\n",
 981                    (rstdbyctl & RCX_SW_EXIT) ? "no" : "yes");
 982         sbuf_printf(m, "Current RS state: ");
 983         switch (rstdbyctl & RSX_STATUS_MASK) {
 984         case RSX_STATUS_ON:
 985                 sbuf_printf(m, "on\n");
 986                 break;
 987         case RSX_STATUS_RC1:
 988                 sbuf_printf(m, "RC1\n");
 989                 break;
 990         case RSX_STATUS_RC1E:
 991                 sbuf_printf(m, "RC1E\n");
 992                 break;
 993         case RSX_STATUS_RS1:
 994                 sbuf_printf(m, "RS1\n");
 995                 break;
 996         case RSX_STATUS_RS2:
 997                 sbuf_printf(m, "RS2 (RC6)\n");
 998                 break;
 999         case RSX_STATUS_RS3:
1000                 sbuf_printf(m, "RC3 (RC6+)\n");
1001                 break;
1002         default:
1003                 sbuf_printf(m, "unknown\n");
1004                 break;
1005         }
1006
1007         return 0;
1008 }
1009
1010 static int
1011 gen6_drpc_info(struct drm_device *dev, struct sbuf *m)
1012 {
1013         drm_i915_private_t *dev_priv = dev->dev_private;
1014         u32 rpmodectl1, gt_core_status, rcctl1;
1015         unsigned forcewake_count;
1016         int count=0;
1017
1018         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
1019                 return (EINTR);
1020
1021         lockmgr(&dev_priv->gt_lock, LK_EXCLUSIVE);
1022         forcewake_count = dev_priv->forcewake_count;
1023         lockmgr(&dev_priv->gt_lock, LK_RELEASE);
1024
1025         if (forcewake_count) {
1026                 sbuf_printf(m, "RC information inaccurate because userspace "
1027                               "holds a reference \n");
1028         } else {
1029                 /* NB: we cannot use forcewake, else we read the wrong values */
1030                 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
1031                         DRM_UDELAY(10);
1032                 sbuf_printf(m, "RC information accurate: %s\n", yesno(count < 51));
1033         }
1034
1035         gt_core_status = DRM_READ32(dev_priv->mmio_map, GEN6_GT_CORE_STATUS);
1036         trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4);
1037
1038         rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
1039         rcctl1 = I915_READ(GEN6_RC_CONTROL);
1040         DRM_UNLOCK(dev);
1041
1042         sbuf_printf(m, "Video Turbo Mode: %s\n",
1043                    yesno(rpmodectl1 & GEN6_RP_MEDIA_TURBO));
1044         sbuf_printf(m, "HW control enabled: %s\n",
1045                    yesno(rpmodectl1 & GEN6_RP_ENABLE));
1046         sbuf_printf(m, "SW control enabled: %s\n",
1047                    yesno((rpmodectl1 & GEN6_RP_MEDIA_MODE_MASK) ==
1048                           GEN6_RP_MEDIA_SW_MODE));
1049         sbuf_printf(m, "RC1e Enabled: %s\n",
1050                    yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
1051         sbuf_printf(m, "RC6 Enabled: %s\n",
1052                    yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
1053         sbuf_printf(m, "Deep RC6 Enabled: %s\n",
1054                    yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
1055         sbuf_printf(m, "Deepest RC6 Enabled: %s\n",
1056                    yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
1057         sbuf_printf(m, "Current RC state: ");
1058         switch (gt_core_status & GEN6_RCn_MASK) {
1059         case GEN6_RC0:
1060                 if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
1061                         sbuf_printf(m, "Core Power Down\n");
1062                 else
1063                         sbuf_printf(m, "on\n");
1064                 break;
1065         case GEN6_RC3:
1066                 sbuf_printf(m, "RC3\n");
1067                 break;
1068         case GEN6_RC6:
1069                 sbuf_printf(m, "RC6\n");
1070                 break;
1071         case GEN6_RC7:
1072                 sbuf_printf(m, "RC7\n");
1073                 break;
1074         default:
1075                 sbuf_printf(m, "Unknown\n");
1076                 break;
1077         }
1078
1079         sbuf_printf(m, "Core Power Down: %s\n",
1080                    yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
1081         return 0;
1082 }
1083
1084 static int i915_drpc_info(struct drm_device *dev, struct sbuf *m, void *unused)
1085 {
1086
1087         if (IS_GEN6(dev) || IS_GEN7(dev))
1088                 return (gen6_drpc_info(dev, m));
1089         else
1090                 return (ironlake_drpc_info(dev, m));
1091 }
1092 static int
1093 i915_fbc_status(struct drm_device *dev, struct sbuf *m, void *unused)
1094 {
1095         drm_i915_private_t *dev_priv = dev->dev_private;
1096
1097         if (!I915_HAS_FBC(dev)) {
1098                 sbuf_printf(m, "FBC unsupported on this chipset");
1099                 return 0;
1100         }
1101
1102         if (intel_fbc_enabled(dev)) {
1103                 sbuf_printf(m, "FBC enabled");
1104         } else {
1105                 sbuf_printf(m, "FBC disabled: ");
1106                 switch (dev_priv->no_fbc_reason) {
1107                 case FBC_NO_OUTPUT:
1108                         sbuf_printf(m, "no outputs");
1109                         break;
1110                 case FBC_STOLEN_TOO_SMALL:
1111                         sbuf_printf(m, "not enough stolen memory");
1112                         break;
1113                 case FBC_UNSUPPORTED_MODE:
1114                         sbuf_printf(m, "mode not supported");
1115                         break;
1116                 case FBC_MODE_TOO_LARGE:
1117                         sbuf_printf(m, "mode too large");
1118                         break;
1119                 case FBC_BAD_PLANE:
1120                         sbuf_printf(m, "FBC unsupported on plane");
1121                         break;
1122                 case FBC_NOT_TILED:
1123                         sbuf_printf(m, "scanout buffer not tiled");
1124                         break;
1125                 case FBC_MULTIPLE_PIPES:
1126                         sbuf_printf(m, "multiple pipes are enabled");
1127                         break;
1128                 default:
1129                         sbuf_printf(m, "unknown reason");
1130                 }
1131         }
1132         return 0;
1133 }
1134
1135 static int
1136 i915_sr_status(struct drm_device *dev, struct sbuf *m, void *unused)
1137 {
1138         drm_i915_private_t *dev_priv = dev->dev_private;
1139         bool sr_enabled = false;
1140
1141         if (HAS_PCH_SPLIT(dev))
1142                 sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
1143         else if (IS_CRESTLINE(dev) || IS_I945G(dev) || IS_I945GM(dev))
1144                 sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
1145         else if (IS_I915GM(dev))
1146                 sr_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN;
1147         else if (IS_PINEVIEW(dev))
1148                 sr_enabled = I915_READ(DSPFW3) & PINEVIEW_SELF_REFRESH_EN;
1149
1150         sbuf_printf(m, "self-refresh: %s",
1151                    sr_enabled ? "enabled" : "disabled");
1152
1153         return (0);
1154 }
1155
1156 static int i915_ring_freq_table(struct drm_device *dev, struct sbuf *m,
1157     void *unused)
1158 {
1159         drm_i915_private_t *dev_priv = dev->dev_private;
1160         int gpu_freq, ia_freq;
1161
1162         if (!(IS_GEN6(dev) || IS_GEN7(dev))) {
1163                 sbuf_printf(m, "unsupported on this chipset");
1164                 return (0);
1165         }
1166
1167         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
1168                 return (EINTR);
1169
1170         sbuf_printf(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\n");
1171
1172         for (gpu_freq = dev_priv->min_delay; gpu_freq <= dev_priv->max_delay;
1173              gpu_freq++) {
1174                 I915_WRITE(GEN6_PCODE_DATA, gpu_freq);
1175                 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
1176                            GEN6_PCODE_READ_MIN_FREQ_TABLE);
1177                 if (_intel_wait_for(dev,
1178                     (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
1179                     10, 1, "915frq")) {
1180                         DRM_ERROR("pcode read of freq table timed out\n");
1181                         continue;
1182                 }
1183                 ia_freq = I915_READ(GEN6_PCODE_DATA);
1184                 sbuf_printf(m, "%d\t\t%d\n", gpu_freq * 50, ia_freq * 100);
1185         }
1186
1187         DRM_UNLOCK(dev);
1188
1189         return (0);
1190 }
1191
1192 static int
1193 i915_emon_status(struct drm_device *dev, struct sbuf *m, void *unused)
1194 {
1195         drm_i915_private_t *dev_priv = dev->dev_private;
1196         unsigned long temp, chipset, gfx;
1197
1198         if (!IS_GEN5(dev)) {
1199                 sbuf_printf(m, "Not supported\n");
1200                 return (0);
1201         }
1202
1203         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
1204                 return (EINTR);
1205         temp = i915_mch_val(dev_priv);
1206         chipset = i915_chipset_val(dev_priv);
1207         gfx = i915_gfx_val(dev_priv);
1208         DRM_UNLOCK(dev);
1209
1210         sbuf_printf(m, "GMCH temp: %ld\n", temp);
1211         sbuf_printf(m, "Chipset power: %ld\n", chipset);
1212         sbuf_printf(m, "GFX power: %ld\n", gfx);
1213         sbuf_printf(m, "Total power: %ld\n", chipset + gfx);
1214
1215         return (0);
1216 }
1217
1218 static int
1219 i915_gfxec(struct drm_device *dev, struct sbuf *m, void *unused)
1220 {
1221         drm_i915_private_t *dev_priv = dev->dev_private;
1222
1223         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
1224                 return (EINTR);
1225         sbuf_printf(m, "GFXEC: %ld\n", (unsigned long)I915_READ(0x112f4));
1226         DRM_UNLOCK(dev);
1227
1228         return (0);
1229 }
1230
1231 #if 0
1232 static int
1233 i915_opregion(struct drm_device *dev, struct sbuf *m, void *unused)
1234 {
1235         drm_i915_private_t *dev_priv = dev->dev_private;
1236         struct intel_opregion *opregion = &dev_priv->opregion;
1237
1238         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
1239                 return (EINTR);
1240         if (opregion->header)
1241                 seq_write(m, opregion->header, OPREGION_SIZE);
1242         DRM_UNLOCK(dev);
1243
1244         return 0;
1245 }
1246 #endif
1247
1248 static int
1249 i915_gem_framebuffer_info(struct drm_device *dev, struct sbuf *m, void *data)
1250 {
1251         drm_i915_private_t *dev_priv = dev->dev_private;
1252         struct intel_fbdev *ifbdev;
1253         struct intel_framebuffer *fb;
1254
1255         if (lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL))
1256                 return (EINTR);
1257
1258         ifbdev = dev_priv->fbdev;
1259         if (ifbdev == NULL) {
1260                 DRM_UNLOCK(dev);
1261                 return (0);
1262         }
1263         fb = to_intel_framebuffer(ifbdev->helper.fb);
1264
1265         sbuf_printf(m, "fbcon size: %d x %d, depth %d, %d bpp, obj ",
1266                    fb->base.width,
1267                    fb->base.height,
1268                    fb->base.depth,
1269                    fb->base.bits_per_pixel);
1270         describe_obj(m, fb->obj);
1271         sbuf_printf(m, "\n");
1272
1273         list_for_each_entry(fb, &dev->mode_config.fb_list, base.head) {
1274                 if (&fb->base == ifbdev->helper.fb)
1275                         continue;
1276
1277                 sbuf_printf(m, "user size: %d x %d, depth %d, %d bpp, obj ",
1278                            fb->base.width,
1279                            fb->base.height,
1280                            fb->base.depth,
1281                            fb->base.bits_per_pixel);
1282                 describe_obj(m, fb->obj);
1283                 sbuf_printf(m, "\n");
1284         }
1285
1286         DRM_UNLOCK(dev);
1287
1288         return (0);
1289 }
1290
1291 static int
1292 i915_context_status(struct drm_device *dev, struct sbuf *m, void *data)
1293 {
1294         drm_i915_private_t *dev_priv;
1295         int ret;
1296
1297         if ((dev->driver->driver_features & DRIVER_MODESET) == 0)
1298                 return (0);
1299
1300         dev_priv = dev->dev_private;
1301         ret = lockmgr(&dev->mode_config.lock, LK_EXCLUSIVE|LK_SLEEPFAIL);
1302         if (ret != 0)
1303                 return (EINTR);
1304
1305         if (dev_priv->pwrctx != NULL) {
1306                 sbuf_printf(m, "power context ");
1307                 describe_obj(m, dev_priv->pwrctx);
1308                 sbuf_printf(m, "\n");
1309         }
1310
1311         if (dev_priv->renderctx != NULL) {
1312                 sbuf_printf(m, "render context ");
1313                 describe_obj(m, dev_priv->renderctx);
1314                 sbuf_printf(m, "\n");
1315         }
1316
1317         lockmgr(&dev->mode_config.lock, LK_RELEASE);
1318
1319         return (0);
1320 }
1321
1322 static int
1323 i915_gen6_forcewake_count_info(struct drm_device *dev, struct sbuf *m,
1324     void *data)
1325 {
1326         struct drm_i915_private *dev_priv;
1327         unsigned forcewake_count;
1328
1329         dev_priv = dev->dev_private;
1330         lockmgr(&dev_priv->gt_lock, LK_EXCLUSIVE);
1331         forcewake_count = dev_priv->forcewake_count;
1332         lockmgr(&dev_priv->gt_lock, LK_RELEASE);
1333
1334         sbuf_printf(m, "forcewake count = %u\n", forcewake_count);
1335
1336         return (0);
1337 }
1338
1339 static const char *
1340 swizzle_string(unsigned swizzle)
1341 {
1342
1343         switch(swizzle) {
1344         case I915_BIT_6_SWIZZLE_NONE:
1345                 return "none";
1346         case I915_BIT_6_SWIZZLE_9:
1347                 return "bit9";
1348         case I915_BIT_6_SWIZZLE_9_10:
1349                 return "bit9/bit10";
1350         case I915_BIT_6_SWIZZLE_9_11:
1351                 return "bit9/bit11";
1352         case I915_BIT_6_SWIZZLE_9_10_11:
1353                 return "bit9/bit10/bit11";
1354         case I915_BIT_6_SWIZZLE_9_17:
1355                 return "bit9/bit17";
1356         case I915_BIT_6_SWIZZLE_9_10_17:
1357                 return "bit9/bit10/bit17";
1358         case I915_BIT_6_SWIZZLE_UNKNOWN:
1359                 return "unknown";
1360         }
1361
1362         return "bug";
1363 }
1364
1365 static int
1366 i915_swizzle_info(struct drm_device *dev, struct sbuf *m, void *data)
1367 {
1368         struct drm_i915_private *dev_priv;
1369         int ret;
1370
1371         dev_priv = dev->dev_private;
1372         ret = lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL);
1373         if (ret != 0)
1374                 return (EINTR);
1375
1376         sbuf_printf(m, "bit6 swizzle for X-tiling = %s\n",
1377                    swizzle_string(dev_priv->mm.bit_6_swizzle_x));
1378         sbuf_printf(m, "bit6 swizzle for Y-tiling = %s\n",
1379                    swizzle_string(dev_priv->mm.bit_6_swizzle_y));
1380
1381         if (IS_GEN3(dev) || IS_GEN4(dev)) {
1382                 sbuf_printf(m, "DDC = 0x%08x\n",
1383                            I915_READ(DCC));
1384                 sbuf_printf(m, "C0DRB3 = 0x%04x\n",
1385                            I915_READ16(C0DRB3));
1386                 sbuf_printf(m, "C1DRB3 = 0x%04x\n",
1387                            I915_READ16(C1DRB3));
1388         } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1389                 sbuf_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
1390                            I915_READ(MAD_DIMM_C0));
1391                 sbuf_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
1392                            I915_READ(MAD_DIMM_C1));
1393                 sbuf_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
1394                            I915_READ(MAD_DIMM_C2));
1395                 sbuf_printf(m, "TILECTL = 0x%08x\n",
1396                            I915_READ(TILECTL));
1397                 sbuf_printf(m, "ARB_MODE = 0x%08x\n",
1398                            I915_READ(ARB_MODE));
1399                 sbuf_printf(m, "DISP_ARB_CTL = 0x%08x\n",
1400                            I915_READ(DISP_ARB_CTL));
1401         }
1402         DRM_UNLOCK(dev);
1403
1404         return (0);
1405 }
1406
1407 static int
1408 i915_ppgtt_info(struct drm_device *dev, struct sbuf *m, void *data)
1409 {
1410         struct drm_i915_private *dev_priv;
1411         struct intel_ring_buffer *ring;
1412         int i, ret;
1413
1414         dev_priv = dev->dev_private;
1415
1416         ret = lockmgr(&dev->dev_struct_lock, LK_EXCLUSIVE|LK_SLEEPFAIL);
1417         if (ret != 0)
1418                 return (EINTR);
1419         if (INTEL_INFO(dev)->gen == 6)
1420                 sbuf_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(GFX_MODE));
1421
1422         for (i = 0; i < I915_NUM_RINGS; i++) {
1423                 ring = &dev_priv->rings[i];
1424
1425                 sbuf_printf(m, "%s\n", ring->name);
1426                 if (INTEL_INFO(dev)->gen == 7)
1427                         sbuf_printf(m, "GFX_MODE: 0x%08x\n", I915_READ(RING_MODE_GEN7(ring)));
1428                 sbuf_printf(m, "PP_DIR_BASE: 0x%08x\n", I915_READ(RING_PP_DIR_BASE(ring)));
1429                 sbuf_printf(m, "PP_DIR_BASE_READ: 0x%08x\n", I915_READ(RING_PP_DIR_BASE_READ(ring)));
1430                 sbuf_printf(m, "PP_DIR_DCLV: 0x%08x\n", I915_READ(RING_PP_DIR_DCLV(ring)));
1431         }
1432         if (dev_priv->mm.aliasing_ppgtt) {
1433                 struct i915_hw_ppgtt *ppgtt = dev_priv->mm.aliasing_ppgtt;
1434
1435                 sbuf_printf(m, "aliasing PPGTT:\n");
1436                 sbuf_printf(m, "pd gtt offset: 0x%08x\n", ppgtt->pd_offset);
1437         }
1438         sbuf_printf(m, "ECOCHK: 0x%08x\n", I915_READ(GAM_ECOCHK));
1439         DRM_UNLOCK(dev);
1440
1441         return (0);
1442 }
1443
1444 static int
1445 i915_debug_set_wedged(SYSCTL_HANDLER_ARGS)
1446 {
1447         struct drm_device *dev;
1448         drm_i915_private_t *dev_priv;
1449         int error, wedged;
1450
1451         dev = arg1;
1452         dev_priv = dev->dev_private;
1453         if (dev_priv == NULL)
1454                 return (EBUSY);
1455         wedged = dev_priv->mm.wedged;
1456         error = sysctl_handle_int(oidp, &wedged, 0, req);
1457         if (error || !req->newptr)
1458                 return (error);
1459         DRM_INFO("Manually setting wedged to %d\n", wedged);
1460         i915_handle_error(dev, wedged);
1461         return (error);
1462 }
1463
1464 static int
1465 i915_max_freq(SYSCTL_HANDLER_ARGS)
1466 {
1467         struct drm_device *dev;
1468         drm_i915_private_t *dev_priv;
1469         int error, max_freq;
1470
1471         dev = arg1;
1472         dev_priv = dev->dev_private;
1473         if (dev_priv == NULL)
1474                 return (EBUSY);
1475         max_freq = dev_priv->max_delay * 50;
1476         error = sysctl_handle_int(oidp, &max_freq, 0, req);
1477         if (error || !req->newptr)
1478                 return (error);
1479         DRM_DEBUG("Manually setting max freq to %d\n", max_freq);
1480         /*
1481          * Turbo will still be enabled, but won't go above the set value.
1482          */
1483         dev_priv->max_delay = max_freq / 50;
1484         gen6_set_rps(dev, max_freq / 50);
1485         return (error);
1486 }
1487
1488 static int
1489 i915_cache_sharing(SYSCTL_HANDLER_ARGS)
1490 {
1491         struct drm_device *dev;
1492         drm_i915_private_t *dev_priv;
1493         int error, snpcr, cache_sharing;
1494
1495         dev = arg1;
1496         dev_priv = dev->dev_private;
1497         if (dev_priv == NULL)
1498                 return (EBUSY);
1499         DRM_LOCK(dev);
1500         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
1501         DRM_UNLOCK(dev);
1502         cache_sharing = (snpcr & GEN6_MBC_SNPCR_MASK) >> GEN6_MBC_SNPCR_SHIFT;
1503         error = sysctl_handle_int(oidp, &cache_sharing, 0, req);
1504         if (error || !req->newptr)
1505                 return (error);
1506         if (cache_sharing < 0 || cache_sharing > 3)
1507                 return (EINVAL);
1508         DRM_DEBUG("Manually setting uncore sharing to %d\n", cache_sharing);
1509
1510         DRM_LOCK(dev);
1511         /* Update the cache sharing policy here as well */
1512         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
1513         snpcr &= ~GEN6_MBC_SNPCR_MASK;
1514         snpcr |= (cache_sharing << GEN6_MBC_SNPCR_SHIFT);
1515         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
1516         DRM_UNLOCK(dev);
1517         return (0);
1518 }
1519
1520 static struct i915_info_sysctl_list {
1521         const char *name;
1522         int (*ptr)(struct drm_device *dev, struct sbuf *m, void *data);
1523         int flags;
1524         void *data;
1525 } i915_info_sysctl_list[] = {
1526         {"i915_capabilities", i915_capabilities, 0},
1527         {"i915_gem_objects", i915_gem_object_info, 0},
1528         {"i915_gem_gtt", i915_gem_gtt_info, 0},
1529         {"i915_gem_active", i915_gem_object_list_info, 0, (void *)ACTIVE_LIST},
1530         {"i915_gem_flushing", i915_gem_object_list_info, 0,
1531             (void *)FLUSHING_LIST},
1532         {"i915_gem_inactive", i915_gem_object_list_info, 0,
1533             (void *)INACTIVE_LIST},
1534         {"i915_gem_pinned", i915_gem_object_list_info, 0,
1535             (void *)PINNED_LIST},
1536         {"i915_gem_deferred_free", i915_gem_object_list_info, 0,
1537             (void *)DEFERRED_FREE_LIST},
1538         {"i915_gem_pageflip", i915_gem_pageflip_info, 0},
1539         {"i915_gem_request", i915_gem_request_info, 0},
1540         {"i915_gem_seqno", i915_gem_seqno_info, 0},
1541         {"i915_gem_fence_regs", i915_gem_fence_regs_info, 0},
1542         {"i915_gem_interrupt", i915_interrupt_info, 0},
1543         {"i915_gem_hws", i915_hws_info, 0, (void *)RCS},
1544         {"i915_gem_hws_blt", i915_hws_info, 0, (void *)BCS},
1545         {"i915_gem_hws_bsd", i915_hws_info, 0, (void *)VCS},
1546         {"i915_ringbuffer_data", i915_ringbuffer_data, 0, (void *)RCS},
1547         {"i915_ringbuffer_info", i915_ringbuffer_info, 0, (void *)RCS},
1548         {"i915_bsd_ringbuffer_data", i915_ringbuffer_data, 0, (void *)VCS},
1549         {"i915_bsd_ringbuffer_info", i915_ringbuffer_info, 0, (void *)VCS},
1550         {"i915_blt_ringbuffer_data", i915_ringbuffer_data, 0, (void *)BCS},
1551         {"i915_blt_ringbuffer_info", i915_ringbuffer_info, 0, (void *)BCS},
1552         {"i915_error_state", i915_error_state, 0},
1553         {"i915_rstdby_delays", i915_rstdby_delays, 0},
1554         {"i915_cur_delayinfo", i915_cur_delayinfo, 0},
1555         {"i915_delayfreq_table", i915_delayfreq_table, 0},
1556         {"i915_inttoext_table", i915_inttoext_table, 0},
1557         {"i915_drpc_info", i915_drpc_info, 0},
1558         {"i915_emon_status", i915_emon_status, 0},
1559         {"i915_ring_freq_table", i915_ring_freq_table, 0},
1560         {"i915_gfxec", i915_gfxec, 0},
1561         {"i915_fbc_status", i915_fbc_status, 0},
1562         {"i915_sr_status", i915_sr_status, 0},
1563 #if 0
1564         {"i915_opregion", i915_opregion, 0},
1565 #endif
1566         {"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
1567         {"i915_context_status", i915_context_status, 0},
1568         {"i915_gen6_forcewake_count_info", i915_gen6_forcewake_count_info, 0},
1569         {"i915_swizzle_info", i915_swizzle_info, 0},
1570         {"i915_ppgtt_info", i915_ppgtt_info, 0},
1571 };
1572
1573 struct i915_info_sysctl_thunk {
1574         struct drm_device *dev;
1575         int idx;
1576         void *arg;
1577 };
1578
1579 static int
1580 i915_info_sysctl_handler(SYSCTL_HANDLER_ARGS)
1581 {
1582 #if 0
1583         struct sbuf m;
1584 #endif
1585         struct i915_info_sysctl_thunk *thunk;
1586         struct drm_device *dev;
1587         drm_i915_private_t *dev_priv;
1588         int error;
1589
1590         thunk = arg1;
1591         dev = thunk->dev;
1592         dev_priv = dev->dev_private;
1593         if (dev_priv == NULL)
1594                 return (EBUSY);
1595 #if 0
1596         error = sysctl_wire_old_buffer(req, 0);
1597         if (error != 0)
1598                 return (error);
1599         sbuf_new_for_sysctl(&m, NULL, 128, req);
1600         error = i915_info_sysctl_list[thunk->idx].ptr(dev, &m,
1601             thunk->arg);
1602         if (error == 0)
1603                 error = sbuf_finish(&m);
1604         sbuf_delete(&m);
1605 #else
1606         error = 0;
1607 #endif
1608         return (error);
1609 }
1610
1611 extern int i915_gem_sync_exec_requests;
1612 extern int i915_fix_mi_batchbuffer_end;
1613 extern int i915_intr_pf;
1614 extern long i915_gem_wired_pages_cnt;
1615
1616 int
1617 i915_sysctl_init(struct drm_device *dev, struct sysctl_ctx_list *ctx,
1618     struct sysctl_oid *top)
1619 {
1620         struct sysctl_oid *oid, *info;
1621         struct i915_info_sysctl_thunk *thunks;
1622         int i, error;
1623
1624         thunks = kmalloc(sizeof(*thunks) * DRM_ARRAY_SIZE(i915_info_sysctl_list),
1625             DRM_MEM_DRIVER, M_WAITOK | M_ZERO);
1626         for (i = 0; i < DRM_ARRAY_SIZE(i915_info_sysctl_list); i++) {
1627                 thunks[i].dev = dev;
1628                 thunks[i].idx = i;
1629                 thunks[i].arg = i915_info_sysctl_list[i].data;
1630         }
1631         dev->sysctl_private = thunks;
1632         info = SYSCTL_ADD_NODE(ctx, SYSCTL_CHILDREN(top), OID_AUTO, "info",
1633             CTLFLAG_RW, NULL, NULL);
1634         if (info == NULL)
1635                 return (ENOMEM);
1636         for (i = 0; i < DRM_ARRAY_SIZE(i915_info_sysctl_list); i++) {
1637                 oid = SYSCTL_ADD_OID(ctx, SYSCTL_CHILDREN(info), OID_AUTO,
1638                     i915_info_sysctl_list[i].name, CTLTYPE_STRING | CTLFLAG_RD,
1639                     &thunks[i], 0, i915_info_sysctl_handler, "A", NULL);
1640                 if (oid == NULL)
1641                         return (ENOMEM);
1642         }
1643         oid = SYSCTL_ADD_LONG(ctx, SYSCTL_CHILDREN(info), OID_AUTO,
1644             "i915_gem_wired_pages", CTLFLAG_RD, &i915_gem_wired_pages_cnt,
1645             NULL);
1646         oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(top), OID_AUTO, "wedged",
1647             CTLTYPE_INT | CTLFLAG_RW, dev, 0,
1648             i915_debug_set_wedged, "I", NULL);
1649         if (oid == NULL)
1650                 return (ENOMEM);
1651         oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(top), OID_AUTO, "max_freq",
1652             CTLTYPE_INT | CTLFLAG_RW, dev, 0, i915_max_freq,
1653             "I", NULL);
1654         if (oid == NULL)
1655                 return (ENOMEM);
1656         oid = SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(top), OID_AUTO,
1657             "cache_sharing", CTLTYPE_INT | CTLFLAG_RW, dev,
1658             0, i915_cache_sharing, "I", NULL);
1659         if (oid == NULL)
1660                 return (ENOMEM);
1661         oid = SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(top), OID_AUTO, "sync_exec",
1662             CTLFLAG_RW, &i915_gem_sync_exec_requests, 0, NULL);
1663         if (oid == NULL)
1664                 return (ENOMEM);
1665         oid = SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(top), OID_AUTO, "fix_mi",
1666             CTLFLAG_RW, &i915_fix_mi_batchbuffer_end, 0, NULL);
1667         if (oid == NULL)
1668                 return (ENOMEM);
1669         oid = SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(top), OID_AUTO, "intr_pf",
1670             CTLFLAG_RW, &i915_intr_pf, 0, NULL);
1671         if (oid == NULL)
1672                 return (ENOMEM);
1673
1674         error = drm_add_busid_modesetting(dev, ctx, top);
1675         if (error != 0)
1676                 return (error);
1677
1678         return (0);
1679 }
1680
1681 void
1682 i915_sysctl_cleanup(struct drm_device *dev)
1683 {
1684
1685         drm_free(dev->sysctl_private, DRM_MEM_DRIVER);
1686 }