sys/platform/pc32/i386/identcpu.c

   1 /*-
   2  * Copyright (c) 1992 Terrence R. Lambert.
   3  * Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
   4  * Copyright (c) 1997 KATO Takenori.
   5  * All rights reserved.
   6  *
   7  * This code is derived from software contributed to Berkeley by
   8  * William Jolitz.
   9  *
  10  * Redistribution and use in source and binary forms, with or without
  11  * modification, are permitted provided that the following conditions
  12  * are met:
  13  * 1. Redistributions of source code must retain the above copyright
  14  *    notice, this list of conditions and the following disclaimer.
  15  * 2. Redistributions in binary form must reproduce the above copyright
  16  *    notice, this list of conditions and the following disclaimer in the
  17  *    documentation and/or other materials provided with the distribution.
  18  * 3. All advertising materials mentioning features or use of this software
  19  *    must display the following acknowledgement:
  20  *      This product includes software developed by the University of
  21  *      California, Berkeley and its contributors.
  22  * 4. Neither the name of the University nor the names of its contributors
  23  *    may be used to endorse or promote products derived from this software
  24  *    without specific prior written permission.
  25  *
  26  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  27  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  28  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  29  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  30  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  31  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  32  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  33  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  34  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  35  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  36  * SUCH DAMAGE.
  37  *
  38  *      from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
  39  * $FreeBSD: src/sys/i386/i386/identcpu.c,v 1.206 2009/11/12 10:59:00 nyan
  40  */
  41 #include "opt_cpu.h"
  42
  43 #include <sys/param.h>
  44 #include <sys/systm.h>
  45 #include <sys/kernel.h>
  46 #include <sys/sysctl.h>
  47 #include <sys/lock.h>
  48
  49 #include <machine/asmacros.h>
  50 #include <machine/clock.h>
  51 #include <machine/cputypes.h>
  52 #include <machine/segments.h>
  53 #include <machine/specialreg.h>
  54 #include <machine/md_var.h>
  55
  56 #include <machine_base/isa/intr_machdep.h>
  57
  58 #define IDENTBLUE_CYRIX486      0
  59 #define IDENTBLUE_IBMCPU        1
  60 #define IDENTBLUE_CYRIXM2       2
  61
  62 /* XXX - should be in header file: */
  63 void printcpuinfo(void);
  64 void finishidentcpu(void);
  65 void earlysetcpuclass(void);
  66 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
  67 void    enable_K5_wt_alloc(void);
  68 void    enable_K6_wt_alloc(void);
  69 void    enable_K6_2_wt_alloc(void);
  70 #endif
  71 void panicifcpuunsupported(void);
  72
  73 static void identifycyrix(void);
  74 static void init_exthigh(void);
  75 static u_int find_cpu_vendor_id(void);
  76 static void print_AMD_info(void);
  77 static void print_INTEL_info(void);
  78 static void print_INTEL_TLB(u_int data);
  79 static void print_AMD_assoc(int i);
  80 static void print_transmeta_info(void);
  81 static void print_via_padlock_info(void);
  82
  83 int     cpu_class;
  84 u_int   cpu_exthigh;            /* Highest arg to extended CPUID */
  85 u_int   cyrix_did;              /* Device ID of Cyrix CPU */
  86 char machine[] = MACHINE;
  87 SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
  88     machine, 0, "Machine class");
  89
  90 static char cpu_model[128];
  91 SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD,
  92     cpu_model, 0, "Machine model");
  93
  94 static int hw_clockrate;
  95 SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
  96     &hw_clockrate, 0, "CPU instruction clock rate");
  97
  98 static char cpu_brand[48];
  99
 100 #define MAX_ADDITIONAL_INFO     16
 101
 102 static const char *additional_cpu_info_ary[MAX_ADDITIONAL_INFO];
 103 static u_int additional_cpu_info_count;
 104
 105 #define MAX_BRAND_INDEX 8
 106
 107 static const char *cpu_brandtable[MAX_BRAND_INDEX + 1] = {
 108         NULL,                   /* No brand */
 109         "Intel Celeron",
 110         "Intel Pentium III",
 111         "Intel Pentium III Xeon",
 112         NULL,
 113         NULL,
 114         NULL,
 115         NULL,
 116         "Intel Pentium 4"
 117 };
 118
 119 static struct {
 120         char    *cpu_name;
 121         int     cpu_class;
 122 } i386_cpus[] = {
 123         { "Intel 80286",        CPUCLASS_286 },         /* CPU_286   */
 124         { "i386SX",             CPUCLASS_386 },         /* CPU_386SX */
 125         { "i386DX",             CPUCLASS_386 },         /* CPU_386   */
 126         { "i486SX",             CPUCLASS_486 },         /* CPU_486SX */
 127         { "i486DX",             CPUCLASS_486 },         /* CPU_486   */
 128         { "Pentium",            CPUCLASS_586 },         /* CPU_586   */
 129         { "Cyrix 486",          CPUCLASS_486 },         /* CPU_486DLC */
 130         { "Pentium Pro",        CPUCLASS_686 },         /* CPU_686 */
 131         { "Cyrix 5x86",         CPUCLASS_486 },         /* CPU_M1SC */
 132         { "Cyrix 6x86",         CPUCLASS_486 },         /* CPU_M1 */
 133         { "Blue Lightning",     CPUCLASS_486 },         /* CPU_BLUE */
 134         { "Cyrix 6x86MX",       CPUCLASS_686 },         /* CPU_M2 */
 135         { "NexGen 586",         CPUCLASS_386 },         /* CPU_NX586 (XXX) */
 136         { "Cyrix 486S/DX",      CPUCLASS_486 },         /* CPU_CY486DX */
 137         { "Pentium II",         CPUCLASS_686 },         /* CPU_PII */
 138         { "Pentium III",        CPUCLASS_686 },         /* CPU_PIII */
 139         { "Pentium 4",          CPUCLASS_686 },         /* CPU_P4 */
 140 };
 141
 142 static struct {
 143         char    *vendor;
 144         u_int   vendor_id;
 145 } cpu_vendors[] = {
 146         { INTEL_VENDOR_ID,      CPU_VENDOR_INTEL },     /* GenuineIntel */
 147         { AMD_VENDOR_ID,        CPU_VENDOR_AMD },       /* AuthenticAMD */
 148         { CENTAUR_VENDOR_ID,    CPU_VENDOR_CENTAUR },   /* CentaurHauls */
 149         { NSC_VENDOR_ID,        CPU_VENDOR_NSC },       /* Geode by NSC */
 150         { CYRIX_VENDOR_ID,      CPU_VENDOR_CYRIX },     /* CyrixInstead */
 151         { TRANSMETA_VENDOR_ID,  CPU_VENDOR_TRANSMETA }, /* GenuineTMx86 */
 152         { SIS_VENDOR_ID,        CPU_VENDOR_SIS },       /* SiS SiS SiS  */
 153         { UMC_VENDOR_ID,        CPU_VENDOR_UMC },       /* UMC UMC UMC  */
 154         { NEXGEN_VENDOR_ID,     CPU_VENDOR_NEXGEN },    /* NexGenDriven */
 155         { RISE_VENDOR_ID,       CPU_VENDOR_RISE },      /* RiseRiseRise */
 156 #if 0
 157         /* XXX CPUID 8000_0000h and 8086_0000h, not 0000_0000h */
 158         { "TransmetaCPU",       CPU_VENDOR_TRANSMETA },
 159 #endif
 160 };
 161
 162 int cpu_cores;
 163 int cpu_logical;
 164
 165 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
 166 int has_f00f_bug = 0;           /* Initialized so that it can be patched. */
 167 #endif
 168
 169 static void
 170 init_exthigh(void)
 171 {
 172         static int done = 0;
 173         u_int regs[4];
 174
 175         if (done == 0) {
 176                 if (cpu_high > 0 &&
 177                     (cpu_vendor_id == CPU_VENDOR_INTEL ||
 178                     cpu_vendor_id == CPU_VENDOR_AMD ||
 179                     cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
 180                     cpu_vendor_id == CPU_VENDOR_CENTAUR ||
 181                     cpu_vendor_id == CPU_VENDOR_NSC)) {
 182                         do_cpuid(0x80000000, regs);
 183                         if (regs[0] >= 0x80000000)
 184                                 cpu_exthigh = regs[0];
 185                 }
 186
 187                 done = 1;
 188         }
 189 }
 190
 191 void
 192 printcpuinfo(void)
 193 {
 194         u_int regs[4], i;
 195         char *brand;
 196
 197         cpu_class = i386_cpus[cpu].cpu_class;
 198         kprintf("CPU: ");
 199         strncpy(cpu_model, i386_cpus[cpu].cpu_name, sizeof (cpu_model));
 200
 201         /* Check for extended CPUID information and a processor name. */
 202         init_exthigh();
 203         if (cpu_exthigh >= 0x80000004) {
 204                 brand = cpu_brand;
 205                 for (i = 0x80000002; i < 0x80000005; i++) {
 206                         do_cpuid(i, regs);
 207                         memcpy(brand, regs, sizeof(regs));
 208                         brand += sizeof(regs);
 209                 }
 210         }
 211
 212         if (cpu_vendor_id == CPU_VENDOR_INTEL) {
 213                 if ((cpu_id & 0xf00) > 0x300) {
 214                         u_int brand_index;
 215
 216                         cpu_model[0] = '\0';
 217
 218                         switch (cpu_id & 0x3000) {
 219                         case 0x1000:
 220                                 strcpy(cpu_model, "Overdrive ");
 221                                 break;
 222                         case 0x2000:
 223                                 strcpy(cpu_model, "Dual ");
 224                                 break;
 225                         }
 226
 227                         switch (cpu_id & 0xf00) {
 228                         case 0x400:
 229                                 strcat(cpu_model, "i486 ");
 230                                 /* Check the particular flavor of 486 */
 231                                 switch (cpu_id & 0xf0) {
 232                                 case 0x00:
 233                                 case 0x10:
 234                                         strcat(cpu_model, "DX");
 235                                         break;
 236                                 case 0x20:
 237                                         strcat(cpu_model, "SX");
 238                                         break;
 239                                 case 0x30:
 240                                         strcat(cpu_model, "DX2");
 241                                         break;
 242                                 case 0x40:
 243                                         strcat(cpu_model, "SL");
 244                                         break;
 245                                 case 0x50:
 246                                         strcat(cpu_model, "SX2");
 247                                         break;
 248                                 case 0x70:
 249                                         strcat(cpu_model,
 250                                             "DX2 Write-Back Enhanced");
 251                                         break;
 252                                 case 0x80:
 253                                         strcat(cpu_model, "DX4");
 254                                         break;
 255                                 }
 256                                 break;
 257                         case 0x500:
 258                                 /* Check the particular flavor of 586 */
 259                                 strcat(cpu_model, "Pentium");
 260                                 switch (cpu_id & 0xf0) {
 261                                 case 0x00:
 262                                         strcat(cpu_model, " A-step");
 263                                         break;
 264                                 case 0x10:
 265                                         strcat(cpu_model, "/P5");
 266                                         break;
 267                                 case 0x20:
 268                                         strcat(cpu_model, "/P54C");
 269                                         break;
 270                                 case 0x30:
 271                                         strcat(cpu_model, "/P24T");
 272                                         break;
 273                                 case 0x40:
 274                                         strcat(cpu_model, "/P55C");
 275                                         break;
 276                                 case 0x70:
 277                                         strcat(cpu_model, "/P54C");
 278                                         break;
 279                                 case 0x80:
 280                                         strcat(cpu_model, "/P55C (quarter-micron)");
 281                                         break;
 282                                 default:
 283                                         /* nothing */
 284                                         break;
 285                                 }
 286 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
 287                                 /*
 288                                  * XXX - If/when Intel fixes the bug, this
 289                                  * should also check the version of the
 290                                  * CPU, not just that it's a Pentium.
 291                                  */
 292                                 has_f00f_bug = 1;
 293 #endif
 294                                 break;
 295                         case 0x600:
 296                                 /* Check the particular flavor of 686 */
 297                                 switch (cpu_id & 0xf0) {
 298                                 case 0x00:
 299                                         strcat(cpu_model, "Pentium Pro A-step");
 300                                         break;
 301                                 case 0x10:
 302                                         strcat(cpu_model, "Pentium Pro");
 303                                         break;
 304                                 case 0x30:
 305                                 case 0x50:
 306                                 case 0x60:
 307                                         strcat(cpu_model,
 308                                 "Pentium II/Pentium II Xeon/Celeron");
 309                                         cpu = CPU_PII;
 310                                         break;
 311                                 case 0x70:
 312                                 case 0x80:
 313                                 case 0xa0:
 314                                 case 0xb0:
 315                                         strcat(cpu_model,
 316                                         "Pentium III/Pentium III Xeon/Celeron");
 317                                         cpu = CPU_PIII;
 318                                         break;
 319                                 default:
 320                                         strcat(cpu_model, "Unknown 80686");
 321                                         break;
 322                                 }
 323                                 break;
 324                         case 0xf00:
 325                                 strcat(cpu_model, "Pentium 4");
 326                                 cpu = CPU_P4;
 327                                 break;
 328                         default:
 329                                 strcat(cpu_model, "unknown");
 330                                 break;
 331                         }
 332
 333                         /*
 334                          * If we didn't get a brand name from the extended
 335                          * CPUID, try to look it up in the brand table.
 336                          */
 337                         if (cpu_high > 0 && *cpu_brand == '\0') {
 338                                 brand_index = cpu_procinfo & CPUID_BRAND_INDEX;
 339                                 if (brand_index <= MAX_BRAND_INDEX &&
 340                                     cpu_brandtable[brand_index] != NULL)
 341                                         strcpy(cpu_brand,
 342                                             cpu_brandtable[brand_index]);
 343                         }
 344                 }
 345         } else if (cpu_vendor_id == CPU_VENDOR_AMD) {
 346                 /*
 347                  * Values taken from AMD Processor Recognition
 348                  * http://www.amd.com/K6/k6docs/pdf/20734g.pdf
 349                  * (also describes ``Features'' encodings.
 350                  */
 351                 strcpy(cpu_model, "AMD ");
 352                 switch (cpu_id & 0xFF0) {
 353                 case 0x410:
 354                         strcat(cpu_model, "Standard Am486DX");
 355                         break;
 356                 case 0x430:
 357                         strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
 358                         break;
 359                 case 0x470:
 360                         strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
 361                         break;
 362                 case 0x480:
 363                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
 364                         break;
 365                 case 0x490:
 366                         strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
 367                         break;
 368                 case 0x4E0:
 369                         strcat(cpu_model, "Am5x86 Write-Through");
 370                         break;
 371                 case 0x4F0:
 372                         strcat(cpu_model, "Am5x86 Write-Back");
 373                         break;
 374                 case 0x500:
 375                         strcat(cpu_model, "K5 model 0");
 376                         tsc_is_broken = 1;
 377                         break;
 378                 case 0x510:
 379                         strcat(cpu_model, "K5 model 1");
 380                         break;
 381                 case 0x520:
 382                         strcat(cpu_model, "K5 PR166 (model 2)");
 383                         break;
 384                 case 0x530:
 385                         strcat(cpu_model, "K5 PR200 (model 3)");
 386                         break;
 387                 case 0x560:
 388                         strcat(cpu_model, "K6");
 389                         break;
 390                 case 0x570:
 391                         strcat(cpu_model, "K6 266 (model 1)");
 392                         break;
 393                 case 0x580:
 394                         strcat(cpu_model, "K6-2");
 395                         break;
 396                 case 0x590:
 397                         strcat(cpu_model, "K6-III");
 398                         break;
 399                 case 0x5a0:
 400                         strcat(cpu_model, "Geode LX");
 401                         /*
 402                          * Make sure the TSC runs through suspension,
 403                          * otherwise we can't use it as timecounter
 404                          */
 405                         wrmsr(0x1900, rdmsr(0x1900) | 0x20ULL);
 406                         break;
 407                 default:
 408                         strcat(cpu_model, "Unknown");
 409                         break;
 410                 }
 411 #if defined(I586_CPU) && defined(CPU_WT_ALLOC)
 412                 if ((cpu_id & 0xf00) == 0x500) {
 413                         if (((cpu_id & 0x0f0) > 0)
 414                             && ((cpu_id & 0x0f0) < 0x60)
 415                             && ((cpu_id & 0x00f) > 3))
 416                                 enable_K5_wt_alloc();
 417                         else if (((cpu_id & 0x0f0) > 0x80)
 418                                  || (((cpu_id & 0x0f0) == 0x80)
 419                                      && (cpu_id & 0x00f) > 0x07))
 420                                 enable_K6_2_wt_alloc();
 421                         else if ((cpu_id & 0x0f0) > 0x50)
 422                                 enable_K6_wt_alloc();
 423                 }
 424 #endif
 425         } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
 426                 strcpy(cpu_model, "Cyrix ");
 427                 switch (cpu_id & 0xff0) {
 428                 case 0x440:
 429                         strcat(cpu_model, "MediaGX");
 430                         break;
 431                 case 0x520:
 432                         strcat(cpu_model, "6x86");
 433                         break;
 434                 case 0x540:
 435                         cpu_class = CPUCLASS_586;
 436                         strcat(cpu_model, "GXm");
 437                         break;
 438                 case 0x600:
 439                         strcat(cpu_model, "6x86MX");
 440                         break;
 441                 default:
 442                         /*
 443                          * Even though CPU supports the cpuid
 444                          * instruction, it can be disabled.
 445                          * Therefore, this routine supports all Cyrix
 446                          * CPUs.
 447                          */
 448                         switch (cyrix_did & 0xf0) {
 449                         case 0x00:
 450                                 switch (cyrix_did & 0x0f) {
 451                                 case 0x00:
 452                                         strcat(cpu_model, "486SLC");
 453                                         break;
 454                                 case 0x01:
 455                                         strcat(cpu_model, "486DLC");
 456                                         break;
 457                                 case 0x02:
 458                                         strcat(cpu_model, "486SLC2");
 459                                         break;
 460                                 case 0x03:
 461                                         strcat(cpu_model, "486DLC2");
 462                                         break;
 463                                 case 0x04:
 464                                         strcat(cpu_model, "486SRx");
 465                                         break;
 466                                 case 0x05:
 467                                         strcat(cpu_model, "486DRx");
 468                                         break;
 469                                 case 0x06:
 470                                         strcat(cpu_model, "486SRx2");
 471                                         break;
 472                                 case 0x07:
 473                                         strcat(cpu_model, "486DRx2");
 474                                         break;
 475                                 case 0x08:
 476                                         strcat(cpu_model, "486SRu");
 477                                         break;
 478                                 case 0x09:
 479                                         strcat(cpu_model, "486DRu");
 480                                         break;
 481                                 case 0x0a:
 482                                         strcat(cpu_model, "486SRu2");
 483                                         break;
 484                                 case 0x0b:
 485                                         strcat(cpu_model, "486DRu2");
 486                                         break;
 487                                 default:
 488                                         strcat(cpu_model, "Unknown");
 489                                         break;
 490                                 }
 491                                 break;
 492                         case 0x10:
 493                                 switch (cyrix_did & 0x0f) {
 494                                 case 0x00:
 495                                         strcat(cpu_model, "486S");
 496                                         break;
 497                                 case 0x01:
 498                                         strcat(cpu_model, "486S2");
 499                                         break;
 500                                 case 0x02:
 501                                         strcat(cpu_model, "486Se");
 502                                         break;
 503                                 case 0x03:
 504                                         strcat(cpu_model, "486S2e");
 505                                         break;
 506                                 case 0x0a:
 507                                         strcat(cpu_model, "486DX");
 508                                         break;
 509                                 case 0x0b:
 510                                         strcat(cpu_model, "486DX2");
 511                                         break;
 512                                 case 0x0f:
 513                                         strcat(cpu_model, "486DX4");
 514                                         break;
 515                                 default:
 516                                         strcat(cpu_model, "Unknown");
 517                                         break;
 518                                 }
 519                                 break;
 520                         case 0x20:
 521                                 if ((cyrix_did & 0x0f) < 8)
 522                                         strcat(cpu_model, "6x86");      /* Where did you get it? */
 523                                 else
 524                                         strcat(cpu_model, "5x86");
 525                                 break;
 526                         case 0x30:
 527                                 strcat(cpu_model, "6x86");
 528                                 break;
 529                         case 0x40:
 530                                 if ((cyrix_did & 0xf000) == 0x3000) {
 531                                         cpu_class = CPUCLASS_586;
 532                                         strcat(cpu_model, "GXm");
 533                                 } else
 534                                         strcat(cpu_model, "MediaGX");
 535                                 break;
 536                         case 0x50:
 537                                 strcat(cpu_model, "6x86MX");
 538                                 break;
 539                         case 0xf0:
 540                                 switch (cyrix_did & 0x0f) {
 541                                 case 0x0d:
 542                                         strcat(cpu_model, "Overdrive CPU");
 543                                         break;
 544                                 case 0x0e:
 545                                         strcpy(cpu_model, "Texas Instruments 486SXL");
 546                                         break;
 547                                 case 0x0f:
 548                                         strcat(cpu_model, "486SLC/DLC");
 549                                         break;
 550                                 default:
 551                                         strcat(cpu_model, "Unknown");
 552                                         break;
 553                                 }
 554                                 break;
 555                         default:
 556                                 strcat(cpu_model, "Unknown");
 557                                 break;
 558                         }
 559                         break;
 560                 }
 561         } else if (cpu_vendor_id == CPU_VENDOR_RISE) {
 562                 strcpy(cpu_model, "Rise ");
 563                 switch (cpu_id & 0xff0) {
 564                 case 0x500:
 565                         strcat(cpu_model, "mP6");
 566                         break;
 567                 default:
 568                         strcat(cpu_model, "Unknown");
 569                 }
 570         } else if (cpu_vendor_id == CPU_VENDOR_CENTAUR) {
 571                 switch (cpu_id & 0xff0) {
 572                 case 0x540:
 573                         strcpy(cpu_model, "IDT WinChip C6");
 574                         tsc_is_broken = 1;
 575                         break;
 576                 case 0x580:
 577                         strcpy(cpu_model, "IDT WinChip 2");
 578                         break;
 579                 case 0x660:
 580                         strcpy(cpu_model, "VIA C3 Samuel");
 581                         break;
 582                 case 0x670:
 583                         if (cpu_id & 0x8)
 584                                 strcpy(cpu_model, "VIA C3 Ezra");
 585                         else
 586                                 strcpy(cpu_model, "VIA C3 Samuel 2");
 587                         break;
 588                 case 0x680:
 589                         strcpy(cpu_model, "VIA C3 Ezra-T");
 590                         break;
 591                 case 0x690:
 592                         strcpy(cpu_model, "VIA C3 Nehemiah");
 593                         break;
 594                 case 0x6a0:
 595                 case 0x6d0:
 596                         strcpy(cpu_model, "VIA C7 Esther");
 597                         break;
 598                 case 0x6f0:
 599                         strcpy(cpu_model, "VIA Nano");
 600                         break;
 601                 default:
 602                         strcpy(cpu_model, "VIA/IDT Unknown");
 603                 }
 604         } else if (cpu_vendor_id == CPU_VENDOR_IBM) {
 605                 strcpy(cpu_model, "Blue Lightning CPU");
 606         } else if (cpu_vendor_id == CPU_VENDOR_NSC) {
 607                 switch (cpu_id & 0xfff) {
 608                 case 0x540:
 609                         strcpy(cpu_model, "Geode SC1100");
 610                         cpu = CPU_GEODE1100;
 611                         tsc_is_broken = 1;
 612                         break;
 613                 default:
 614                         strcpy(cpu_model, "Geode/NSC unknown");
 615                         break;
 616                 }
 617         }
 618
 619         /*
 620          * Replace cpu_model with cpu_brand minus leading spaces if
 621          * we have one.
 622          */
 623         brand = cpu_brand;
 624         while (*brand == ' ')
 625                 ++brand;
 626         if (*brand != '\0')
 627                 strcpy(cpu_model, brand);
 628
 629         kprintf("%s (", cpu_model);
 630         switch(cpu_class) {
 631         case CPUCLASS_286:
 632                 kprintf("286");
 633                 break;
 634         case CPUCLASS_386:
 635                 kprintf("386");
 636                 break;
 637 #if defined(I486_CPU)
 638         case CPUCLASS_486:
 639                 kprintf("486");
 640                 /* bzero_vector = i486_bzero; */
 641                 break;
 642 #endif
 643 #if defined(I586_CPU)
 644         case CPUCLASS_586:
 645                 hw_clockrate = (tsc_frequency + 5000) / 1000000;
 646                 kprintf("%jd.%02d-MHz ",
 647                        (intmax_t)(tsc_frequency + 4999) / 1000000,
 648                        (u_int)((tsc_frequency + 4999) / 10000) % 100);
 649                 kprintf("586");
 650                 break;
 651 #endif
 652 #if defined(I686_CPU)
 653         case CPUCLASS_686:
 654                 hw_clockrate = (tsc_frequency + 5000) / 1000000;
 655                 kprintf("%jd.%02d-MHz ",
 656                        (intmax_t)(tsc_frequency + 4999) / 1000000,
 657                        (u_int)((tsc_frequency + 4999) / 10000) % 100);
 658                 kprintf("686");
 659                 break;
 660 #endif
 661         default:
 662                 kprintf("Unknown");     /* will panic below... */
 663         }
 664         kprintf("-class CPU)\n");
 665         if(*cpu_vendor)
 666                 kprintf("  Origin = \"%s\"",cpu_vendor);
 667         if(cpu_id)
 668                 kprintf("  Id = 0x%x", cpu_id);
 669
 670         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
 671             cpu_vendor_id == CPU_VENDOR_AMD ||
 672             cpu_vendor_id == CPU_VENDOR_TRANSMETA ||
 673             cpu_vendor_id == CPU_VENDOR_RISE ||
 674             cpu_vendor_id == CPU_VENDOR_CENTAUR ||
 675             cpu_vendor_id == CPU_VENDOR_NSC ||
 676                 (cpu_vendor_id == CPU_VENDOR_CYRIX &&
 677                  ((cpu_id & 0xf00) > 0x500))) {
 678                 kprintf("  Stepping = %u", cpu_id & 0xf);
 679                 if (cpu_vendor_id == CPU_VENDOR_CYRIX)
 680                         kprintf("  DIR=0x%04x", cyrix_did);
 681                 if (cpu_high > 0) {
 682                         u_int cmp = 1, htt = 1;
 683
 684                         /*
 685                          * Here we should probably set up flags indicating
 686                          * whether or not various features are available.
 687                          * The interesting ones are probably VME, PSE, PAE,
 688                          * and PGE.  The code already assumes without bothering
 689                          * to check that all CPUs >= Pentium have a TSC and
 690                          * MSRs.
 691                          */
 692                         kprintf("\n  Features=0x%b", cpu_feature,
 693                         "\020"
 694                         "\001FPU"       /* Integral FPU */
 695                         "\002VME"       /* Extended VM86 mode support */
 696                         "\003DE"        /* Debugging Extensions (CR4.DE) */
 697                         "\004PSE"       /* 4MByte page tables */
 698                         "\005TSC"       /* Timestamp counter */
 699                         "\006MSR"       /* Machine specific registers */
 700                         "\007PAE"       /* Physical address extension */
 701                         "\010MCE"       /* Machine Check support */
 702                         "\011CX8"       /* CMPEXCH8 instruction */
 703                         "\012APIC"      /* SMP local APIC */
 704                         "\013oldMTRR"   /* Previous implementation of MTRR */
 705                         "\014SEP"       /* Fast System Call */
 706                         "\015MTRR"      /* Memory Type Range Registers */
 707                         "\016PGE"       /* PG_G (global bit) support */
 708                         "\017MCA"       /* Machine Check Architecture */
 709                         "\020CMOV"      /* CMOV instruction */
 710                         "\021PAT"       /* Page attributes table */
 711                         "\022PSE36"     /* 36 bit address space support */
 712                         "\023PN"        /* Processor Serial number */
 713                         "\024CLFLUSH"   /* Has the CLFLUSH instruction */
 714                         "\025<b20>"
 715                         "\026DTS"       /* Debug Trace Store */
 716                         "\027ACPI"      /* ACPI support */
 717                         "\030MMX"       /* MMX instructions */
 718                         "\031FXSR"      /* FXSAVE/FXRSTOR */
 719                         "\032SSE"       /* Streaming SIMD Extensions */
 720                         "\033SSE2"      /* Streaming SIMD Extensions #2 */
 721                         "\034SS"        /* Self snoop */
 722                         "\035HTT"       /* Hyperthreading (see EBX bit 16-23) */
 723                         "\036TM"        /* Thermal Monitor clock slowdown */
 724                         "\037IA64"      /* CPU can execute IA64 instructions */
 725                         "\040PBE"       /* Pending Break Enable */
 726                         );
 727
 728                         if (cpu_feature2 != 0) {
 729                                 kprintf("\n  Features2=0x%b", cpu_feature2,
 730                                 "\020"
 731                                 "\001SSE3"      /* SSE3 */
 732                                 "\002PCLMULDQ"  /* PCLMULDQ instruction */
 733                                 "\003DTES64"    /* 64-bit Debug Trace */
 734                                 "\004MON"       /* MONITOR/MWAIT Instructions */
 735                                 "\005DS_CPL"    /* CPL Qualified Debug Store */
 736                                 "\006VMX"       /* Virtual Machine Extensions */
 737                                 "\007SMX"       /* Safer Mode Extensions */
 738                                 "\010EST"       /* Enhanced SpeedStep */
 739                                 "\011TM2"       /* Thermal Monitor 2 */
 740                                 "\012SSSE3"     /* SSSE3 */
 741                                 "\013CNXT-ID"   /* L1 context ID available */
 742                                 "\014<b11>"
 743                                 "\015<b12>"
 744                                 "\016CX16"      /* CMPXCHG16B Instruction */
 745                                 "\017xTPR"      /* Send Task Priority Messages*/
 746                                 "\020PDCM"      /* Perf/Debug Capability MSR */
 747                                 "\021<b16>"
 748                                 "\022<b17>"
 749                                 "\023DCA"       /* Direct Cache Access */
 750                                 "\024SSE4.1"
 751                                 "\025SSE4.2"
 752                                 "\026x2APIC"    /* xAPIC Extensions */
 753                                 "\027MOVBE"     /* MOVBE Instruction */
 754                                 "\030POPCNT"
 755                                 "\031<b24>"
 756                                 "\032AES"       /* AES Instruction */
 757                                 "\033XSAVE"
 758                                 "\034OSXSAVE"
 759                                 "\035<b28>"
 760                                 "\036<b29>"
 761                                 "\037<b30>"
 762                                 "\040VMM"        /* Running on a hypervisor */
 763                                 );
 764                         }
 765
 766                         /*
 767                          * AMD64 Architecture Programmer's Manual Volume 3:
 768                          * General-Purpose and System Instructions
 769                          * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/24594.pdf
 770                          *
 771                          * IA-32 Intel Architecture Software Developer's Manual,
 772                          * Volume 2A: Instruction Set Reference, A-M
 773                          * ftp://download.intel.com/design/Pentium4/manuals/25366617.pdf
 774                          */
 775                         if (amd_feature != 0) {
 776                                 kprintf("\n  AMD Features=0x%b", amd_feature,
 777                                 "\020"          /* in hex */
 778                                 "\001<s0>"      /* Same */
 779                                 "\002<s1>"      /* Same */
 780                                 "\003<s2>"      /* Same */
 781                                 "\004<s3>"      /* Same */
 782                                 "\005<s4>"      /* Same */
 783                                 "\006<s5>"      /* Same */
 784                                 "\007<s6>"      /* Same */
 785                                 "\010<s7>"      /* Same */
 786                                 "\011<s8>"      /* Same */
 787                                 "\012<s9>"      /* Same */
 788                                 "\013<b10>"     /* Undefined */
 789                                 "\014SYSCALL"   /* Have SYSCALL/SYSRET */
 790                                 "\015<s12>"     /* Same */
 791                                 "\016<s13>"     /* Same */
 792                                 "\017<s14>"     /* Same */
 793                                 "\020<s15>"     /* Same */
 794                                 "\021<s16>"     /* Same */
 795                                 "\022<s17>"     /* Same */
 796                                 "\023<b18>"     /* Reserved, unknown */
 797                                 "\024MP"        /* Multiprocessor Capable */
 798                                 "\025NX"        /* Has EFER.NXE, NX */
 799                                 "\026<b21>"     /* Undefined */
 800                                 "\027MMX+"      /* AMD MMX Extensions */
 801                                 "\030<s23>"     /* Same */
 802                                 "\031<s24>"     /* Same */
 803                                 "\032FFXSR"     /* Fast FXSAVE/FXRSTOR */
 804                                 "\033Page1GB"   /* 1-GB large page support */
 805                                 "\034RDTSCP"    /* RDTSCP */
 806                                 "\035<b28>"     /* Undefined */
 807                                 "\036LM"        /* 64 bit long mode */
 808                                 "\0373DNow!+"   /* AMD 3DNow! Extensions */
 809                                 "\0403DNow!"    /* AMD 3DNow! */
 810                                 );
 811                         }
 812
 813                         if (amd_feature2 != 0) {
 814                                 kprintf("\n  AMD Features2=0x%b", amd_feature2,
 815                                 "\020"
 816                                 "\001LAHF"      /* LAHF/SAHF in long mode */
 817                                 "\002CMP"       /* CMP legacy */
 818                                 "\003SVM"       /* Secure Virtual Mode */
 819                                 "\004ExtAPIC"   /* Extended APIC register */
 820                                 "\005CR8"       /* CR8 in legacy mode */
 821                                 "\006ABM"       /* LZCNT instruction */
 822                                 "\007SSE4A"     /* SSE4A */
 823                                 "\010MAS"       /* Misaligned SSE mode */
 824                                 "\011Prefetch"  /* 3DNow! Prefetch/PrefetchW */
 825                                 "\012OSVW"      /* OS visible workaround */
 826                                 "\013IBS"       /* Instruction based sampling */
 827                                 "\014SSE5"      /* SSE5 */
 828                                 "\015SKINIT"    /* SKINIT/STGI */
 829                                 "\016WDT"       /* Watchdog timer */
 830                                 "\017<b14>"
 831                                 "\020<b15>"
 832                                 "\021<b16>"
 833                                 "\022<b17>"
 834                                 "\023<b18>"
 835                                 "\024<b19>"
 836                                 "\025<b20>"
 837                                 "\026<b21>"
 838                                 "\027<b22>"
 839                                 "\030<b23>"
 840                                 "\031<b24>"
 841                                 "\032<b25>"
 842                                 "\033<b26>"
 843                                 "\034<b27>"
 844                                 "\035<b28>"
 845                                 "\036<b29>"
 846                                 "\037<b30>"
 847                                 "\040<b31>"
 848                                 );
 849                         }
 850
 851                         if (cpu_vendor_id == CPU_VENDOR_CENTAUR)
 852                                 print_via_padlock_info();
 853
 854                         if ((cpu_feature & CPUID_HTT) &&
 855                             cpu_vendor_id == CPU_VENDOR_AMD)
 856                                 cpu_feature &= ~CPUID_HTT;
 857
 858                         /*
 859                          * If this CPU supports HTT or CMP then mention the
 860                          * number of physical/logical cores it contains.
 861                          */
 862                         if (cpu_feature & CPUID_HTT)
 863                                 htt = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
 864                         if (cpu_vendor_id == CPU_VENDOR_AMD &&
 865                             (amd_feature2 & AMDID2_CMP))
 866                                 cmp = (cpu_procinfo2 & AMDID_CMP_CORES) + 1;
 867                         else if (cpu_vendor_id == CPU_VENDOR_INTEL &&
 868                             (cpu_high >= 4)) {
 869                                 cpuid_count(4, 0, regs);
 870                                 if ((regs[0] & 0x1f) != 0)
 871                                         cmp = ((regs[0] >> 26) & 0x3f) + 1;
 872                         }
 873                         cpu_cores = cmp;
 874                         cpu_logical = htt / cmp;
 875                         if (cmp > 1)
 876                                 kprintf("\n  Cores per package: %d", cmp);
 877                         if ((htt / cmp) > 1)
 878                                 kprintf("\n  Logical CPUs per core: %d",
 879                                     cpu_logical);
 880 #if 0
 881                         /*
 882                          * If this CPU supports P-state invariant TSC then
 883                          * mention the capability.
 884                          */
 885                         switch (cpu_vendor_id) {
 886                         case CPU_VENDOR_AMD:
 887                                 if ((amd_pminfo & AMDPM_TSC_INVARIANT) ||
 888                                     CPUID_TO_FAMILY(cpu_id) >= 0x10 ||
 889                                     cpu_id == 0x60fb2)
 890                                         tsc_is_invariant = 1;
 891                                 break;
 892                         case CPU_VENDOR_INTEL:
 893                                 if ((amd_pminfo & AMDPM_TSC_INVARIANT) ||
 894                                     (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
 895                                     CPUID_TO_MODEL(cpu_id) >= 0xe) ||
 896                                     (CPUID_TO_FAMILY(cpu_id) == 0xf &&
 897                                     CPUID_TO_MODEL(cpu_id) >= 0x3))
 898                                         tsc_is_invariant = 1;
 899                                 break;
 900                         case CPU_VENDOR_CENTAUR:
 901                                 if (CPUID_TO_FAMILY(cpu_id) == 0x6 &&
 902                                     CPUID_TO_MODEL(cpu_id) >= 0xf &&
 903                                     (rdmsr(0x1203) & 0x100000000ULL) == 0)
 904                                         tsc_is_invariant = 1;
 905                                 break;
 906                         }
 907                         if (tsc_is_invariant)
 908                                 kprintf("\n  TSC: P-state invariant");
 909 #endif
 910
 911                 }
 912         } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
 913                 kprintf("  DIR=0x%04x", cyrix_did);
 914                 kprintf("  Stepping=%u", (cyrix_did & 0xf000) >> 12);
 915                 kprintf("  Revision=%u", (cyrix_did & 0x0f00) >> 8);
 916 #ifndef CYRIX_CACHE_REALLY_WORKS
 917                 if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
 918                         kprintf("\n  CPU cache: write-through mode");
 919 #endif
 920         }
 921
 922         /* Avoid ugly blank lines: only print newline when we have to. */
 923         if (*cpu_vendor || cpu_id)
 924                 kprintf("\n");
 925
 926         for (i = 0; i < additional_cpu_info_count; ++i) {
 927                 kprintf("  %s\n", additional_cpu_info_ary[i]);
 928         }
 929
 930         if (!bootverbose)
 931                 return;
 932
 933         if (cpu_vendor_id == CPU_VENDOR_AMD)
 934                 print_AMD_info();
 935         else if (cpu_vendor_id == CPU_VENDOR_INTEL)
 936                 print_INTEL_info();
 937         else if (cpu_vendor_id == CPU_VENDOR_TRANSMETA)
 938                 print_transmeta_info();
 939 }
 940
 941 void
 942 panicifcpuunsupported(void)
 943 {
 944
 945 #if !defined(lint)
 946 #if !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
 947 #error This kernel is not configured for one of the supported CPUs
 948 #endif
 949 #else /* lint */
 950 #endif /* lint */
 951         /*
 952          * Now that we have told the user what they have,
 953          * let them know if that machine type isn't configured.
 954          */
 955         switch (cpu_class) {
 956         case CPUCLASS_286:      /* a 286 should not make it this far, anyway */
 957         case CPUCLASS_386:
 958 #if !defined(I486_CPU)
 959         case CPUCLASS_486:
 960 #endif
 961 #if !defined(I586_CPU)
 962         case CPUCLASS_586:
 963 #endif
 964 #if !defined(I686_CPU)
 965         case CPUCLASS_686:
 966 #endif
 967                 panic("CPU class not configured");
 968         default:
 969                 break;
 970         }
 971 }
 972
 973
 974 static  volatile u_int trap_by_rdmsr;
 975
 976 /*
 977  * Special exception 6 handler.
 978  * The rdmsr instruction generates invalid opcodes fault on 486-class
 979  * Cyrix CPU.  Stacked eip register points the rdmsr instruction in the
 980  * function identblue() when this handler is called.  Stacked eip should
 981  * be advanced.
 982  */
 983 inthand_t       bluetrap6;
 984
 985 __asm
 986 ("                                                                      \n\
 987         .text                                                           \n\
 988         .p2align 2,0x90                                                 \n\
 989         .type   " __XSTRING(CNAME(bluetrap6)) ",@function               \n\
 990 " __XSTRING(CNAME(bluetrap6)) ":                                        \n\
 991         ss                                                              \n\
 992         movl    $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
 993         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
 994         iret                                                            \n\
 995 ");
 996
 997 /*
 998  * Special exception 13 handler.
 999  * Accessing non-existent MSR generates general protection fault.
1000  */
1001 inthand_t       bluetrap13;
1002
1003 __asm
1004 ("                                                                      \n\
1005         .text                                                           \n\
1006         .p2align 2,0x90                                                 \n\
1007         .type   " __XSTRING(CNAME(bluetrap13)) ",@function              \n\
1008 " __XSTRING(CNAME(bluetrap13)) ":                                       \n\
1009         ss                                                              \n\
1010         movl    $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) "            \n\
1011         popl    %eax            /* discard error code */                \n\
1012         addl    $2, (%esp)      /* rdmsr is a 2-byte instruction */     \n\
1013         iret                                                            \n\
1014 ");
1015
1016 /*
1017  * Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
1018  * support cpuid instruction.  This function should be called after
1019  * loading interrupt descriptor table register.
1020  *
1021  * I don't like this method that handles fault, but I couldn't get
1022  * information for any other methods.  Does blue giant know?
1023  */
1024 static int
1025 identblue(void)
1026 {
1027
1028         trap_by_rdmsr = 0;
1029
1030         /*
1031          * Cyrix 486-class CPU does not support rdmsr instruction.
1032          * The rdmsr instruction generates invalid opcode fault, and exception
1033          * will be trapped by bluetrap6() on Cyrix 486-class CPU.  The
1034          * bluetrap6() set the magic number to trap_by_rdmsr.
1035          */
1036         setidt(6, bluetrap6, SDT_SYS386TGT, SEL_KPL,
1037             GSEL(GCODE_SEL, SEL_KPL));
1038
1039         /*
1040          * Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
1041          * In this case, rdmsr generates general protection fault, and
1042          * exception will be trapped by bluetrap13().
1043          */
1044         setidt(13, bluetrap13, SDT_SYS386TGT, SEL_KPL,
1045             GSEL(GCODE_SEL, SEL_KPL));
1046
1047         rdmsr(0x1002);          /* Cyrix CPU generates fault. */
1048
1049         if (trap_by_rdmsr == 0xa8c1d)
1050                 return IDENTBLUE_CYRIX486;
1051         else if (trap_by_rdmsr == 0xa89c4)
1052                 return IDENTBLUE_CYRIXM2;
1053         return IDENTBLUE_IBMCPU;
1054 }
1055
1056
1057 /*
1058  * identifycyrix() set lower 16 bits of cyrix_did as follows:
1059  *
1060  *  F E D C B A 9 8 7 6 5 4 3 2 1 0
1061  * +-------+-------+---------------+
1062  * |  SID  |  RID  |   Device ID   |
1063  * |    (DIR 1)    |    (DIR 0)    |
1064  * +-------+-------+---------------+
1065  */
1066 static void
1067 identifycyrix(void)
1068 {
1069         int     ccr2_test = 0, dir_test = 0;
1070         u_char  ccr2, ccr3;
1071
1072         mpintr_lock();
1073
1074         ccr2 = read_cyrix_reg(CCR2);
1075         write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
1076         read_cyrix_reg(CCR2);
1077         if (read_cyrix_reg(CCR2) != ccr2)
1078                 ccr2_test = 1;
1079         write_cyrix_reg(CCR2, ccr2);
1080
1081         ccr3 = read_cyrix_reg(CCR3);
1082         write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
1083         read_cyrix_reg(CCR3);
1084         if (read_cyrix_reg(CCR3) != ccr3)
1085                 dir_test = 1;                                   /* CPU supports DIRs. */
1086         write_cyrix_reg(CCR3, ccr3);
1087
1088         if (dir_test) {
1089                 /* Device ID registers are available. */
1090                 cyrix_did = read_cyrix_reg(DIR1) << 8;
1091                 cyrix_did += read_cyrix_reg(DIR0);
1092         } else if (ccr2_test)
1093                 cyrix_did = 0x0010;             /* 486S A-step */
1094         else
1095                 cyrix_did = 0x00ff;             /* Old 486SLC/DLC and TI486SXLC/SXL */
1096         mpintr_unlock();
1097 }
1098
1099 #if 0
1100 /* Update TSC freq with the value indicated by the caller. */
1101 static void
1102 tsc_frequency_changed(void *arg, const struct cf_level *level, int status)
1103 {
1104         /*
1105          * If there was an error during the transition or
1106          * TSC is P-state invariant, don't do anything.
1107          */
1108         if (status != 0 || tsc_is_invariant)
1109                 return;
1110
1111         /* Total setting for this level gives the new frequency in MHz. */
1112         hw_clockrate = level->total_set.freq;
1113 }
1114 #endif
1115
1116 /*
1117  * Final stage of CPU identification. -- Should I check TI?
1118  */
1119 void
1120 finishidentcpu(void)
1121 {
1122         int     isblue = 0;
1123         u_char  ccr3;
1124         u_int   regs[4];
1125
1126         cpu_vendor_id = find_cpu_vendor_id();
1127
1128         /*
1129          * Clear "Limit CPUID Maxval" bit and get the largest standard CPUID
1130          * function number again if it is set from BIOS.  It is necessary
1131          * for probing correct CPU topology later.
1132          * XXX This is only done on the BSP package.
1133          */
1134         if (cpu_vendor_id == CPU_VENDOR_INTEL && cpu_high > 0 && cpu_high < 4 &&
1135             ((CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x3) ||
1136             (CPUID_TO_FAMILY(cpu_id) == 0x6 && CPUID_TO_MODEL(cpu_id) >= 0xe))) {
1137                 uint64_t msr;
1138                 msr = rdmsr(MSR_IA32_MISC_ENABLE);
1139                 if ((msr & 0x400000ULL) != 0) {
1140                         wrmsr(MSR_IA32_MISC_ENABLE, msr & ~0x400000ULL);
1141                         do_cpuid(0, regs);
1142                         cpu_high = regs[0];
1143                 }
1144         }
1145
1146         /* Detect AMD features (PTE no-execute bit, 3dnow, 64 bit mode etc) */
1147         if (cpu_vendor_id == CPU_VENDOR_INTEL ||
1148             cpu_vendor_id == CPU_VENDOR_AMD) {
1149                 init_exthigh();
1150                 if (cpu_exthigh >= 0x80000001) {
1151                         do_cpuid(0x80000001, regs);
1152                         amd_feature = regs[3] & ~(cpu_feature & 0x0183f3ff);
1153                         amd_feature2 = regs[2];
1154                 }
1155 #if 0
1156                 if (cpu_exthigh >= 0x80000007) {
1157                         do_cpuid(0x80000007, regs);
1158                         amd_pminfo = regs[3];
1159                 }
1160 #endif
1161                 if (cpu_exthigh >= 0x80000008) {
1162                         do_cpuid(0x80000008, regs);
1163                         cpu_procinfo2 = regs[2];
1164                 }
1165         } else if (cpu_vendor_id == CPU_VENDOR_CYRIX) {
1166                 if (cpu == CPU_486) {
1167                         /*
1168                          * These conditions are equivalent to:
1169                          *     - CPU does not support cpuid instruction.
1170                          *     - Cyrix/IBM CPU is detected.
1171                          */
1172                         isblue = identblue();
1173                         if (isblue == IDENTBLUE_IBMCPU) {
1174                                 strcpy(cpu_vendor, "IBM");
1175                                 cpu_vendor_id = CPU_VENDOR_IBM;
1176                                 cpu = CPU_BLUE;
1177                                 return;
1178                         }
1179                 }
1180                 switch (cpu_id & 0xf00) {
1181                 case 0x600:
1182                         /*
1183                          * Cyrix's datasheet does not describe DIRs.
1184                          * Therefor, I assume it does not have them
1185                          * and use the result of the cpuid instruction.
1186                          * XXX they seem to have it for now at least. -Peter
1187                          */
1188                         identifycyrix();
1189                         cpu = CPU_M2;
1190                         break;
1191                 default:
1192                         identifycyrix();
1193                         /*
1194                          * This routine contains a trick.
1195                          * Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
1196                          */
1197                         switch (cyrix_did & 0x00f0) {
1198                         case 0x00:
1199                         case 0xf0:
1200                                 cpu = CPU_486DLC;
1201                                 break;
1202                         case 0x10:
1203                                 cpu = CPU_CY486DX;
1204                                 break;
1205                         case 0x20:
1206                                 if ((cyrix_did & 0x000f) < 8)
1207                                         cpu = CPU_M1;
1208                                 else
1209                                         cpu = CPU_M1SC;
1210                                 break;
1211                         case 0x30:
1212                                 cpu = CPU_M1;
1213                                 break;
1214                         case 0x40:
1215                                 /* MediaGX CPU */
1216                                 cpu = CPU_M1SC;
1217                                 break;
1218                         default:
1219                                 /* M2 and later CPUs are treated as M2. */
1220                                 cpu = CPU_M2;
1221
1222                                 /*
1223                                  * enable cpuid instruction.
1224                                  */
1225                                 ccr3 = read_cyrix_reg(CCR3);
1226                                 write_cyrix_reg(CCR3, CCR3_MAPEN0);
1227                                 write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
1228                                 write_cyrix_reg(CCR3, ccr3);
1229
1230                                 do_cpuid(0, regs);
1231                                 cpu_high = regs[0];     /* eax */
1232                                 do_cpuid(1, regs);
1233                                 cpu_id = regs[0];       /* eax */
1234                                 cpu_feature = regs[3];  /* edx */
1235                                 break;
1236                         }
1237                 }
1238         } else if (cpu == CPU_486 && *cpu_vendor == '\0') {
1239                 /*
1240                  * There are BlueLightning CPUs that do not change
1241                  * undefined flags by dividing 5 by 2.  In this case,
1242                  * the CPU identification routine in locore.s leaves
1243                  * cpu_vendor null string and puts CPU_486 into the
1244                  * cpu.
1245                  */
1246                 isblue = identblue();
1247                 if (isblue == IDENTBLUE_IBMCPU) {
1248                         strcpy(cpu_vendor, "IBM");
1249                         cpu_vendor_id = CPU_VENDOR_IBM;
1250                         cpu = CPU_BLUE;
1251                         return;
1252                 }
1253         }
1254 }
1255
1256 static u_int
1257 find_cpu_vendor_id(void)
1258 {
1259         int     i;
1260
1261         for (i = 0; i < sizeof(cpu_vendors) / sizeof(cpu_vendors[0]); i++)
1262                 if (strcmp(cpu_vendor, cpu_vendors[i].vendor) == 0)
1263                         return (cpu_vendors[i].vendor_id);
1264         return (0);
1265 }
1266
1267 static void
1268 print_AMD_assoc(int i)
1269 {
1270         if (i == 255)
1271                 kprintf(", fully associative\n");
1272         else
1273                 kprintf(", %d-way associative\n", i);
1274 }
1275
1276 /*
1277  * #31116 Rev 3.06 section 3.9
1278  * CPUID Fn8000_0006 L2/L3 Cache and L2 TLB Identifiers
1279  */
1280 static void
1281 print_AMD_L2L3_assoc(int i)
1282 {
1283         static const char *assoc_str[] = {
1284                 [0x0] = "disabled",
1285                 [0x1] = "direct mapped",
1286                 [0x2] = "2-way associative",
1287                 [0x4] = "4-way associative",
1288                 [0x6] = "8-way associative",
1289                 [0x8] = "16-way associative",
1290                 [0xa] = "32-way associative",
1291                 [0xb] = "48-way associative",
1292                 [0xc] = "64-way associative",
1293                 [0xd] = "96-way associative",
1294                 [0xe] = "128-way associative",
1295                 [0xf] = "fully associative"
1296         };
1297
1298         i &= 0xf;
1299         if (assoc_str[i] == NULL)
1300                 kprintf(", unknown associative\n");
1301         else
1302                 kprintf(", %s\n", assoc_str[i]);
1303 }
1304
1305 static void
1306 print_AMD_info(void)
1307 {
1308         quad_t amd_whcr;
1309
1310         if (cpu_exthigh >= 0x80000005) {
1311                 u_int regs[4];
1312
1313                 do_cpuid(0x80000005, regs);
1314                 kprintf("Data TLB: %d entries", (regs[1] >> 16) & 0xff);
1315                 print_AMD_assoc(regs[1] >> 24);
1316                 kprintf("Instruction TLB: %d entries", regs[1] & 0xff);
1317                 print_AMD_assoc((regs[1] >> 8) & 0xff);
1318                 kprintf("L1 data cache: %d kbytes", regs[2] >> 24);
1319                 kprintf(", %d bytes/line", regs[2] & 0xff);
1320                 kprintf(", %d lines/tag", (regs[2] >> 8) & 0xff);
1321                 print_AMD_assoc((regs[2] >> 16) & 0xff);
1322                 kprintf("L1 instruction cache: %d kbytes", regs[3] >> 24);
1323                 kprintf(", %d bytes/line", regs[3] & 0xff);
1324                 kprintf(", %d lines/tag", (regs[3] >> 8) & 0xff);
1325                 print_AMD_assoc((regs[3] >> 16) & 0xff);
1326                 if (cpu_exthigh >= 0x80000006) {        /* K6-III or later */
1327                         do_cpuid(0x80000006, regs);
1328                         /*
1329                          * Report right L2 cache size on Duron rev. A0.
1330                          */
1331                         if ((cpu_id & 0xFF0) == 0x630)
1332                                 kprintf("L2 internal cache: 64 kbytes");
1333                         else
1334                                 kprintf("L2 internal cache: %d kbytes", regs[2] >> 16);
1335
1336                         kprintf(", %d bytes/line", regs[2] & 0xff);
1337                         kprintf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
1338                         print_AMD_L2L3_assoc((regs[2] >> 12) & 0x0f);
1339
1340                         /*
1341                          * #31116 Rev 3.06 section 2.16.2:
1342                          * ... If EDX[31:16] is not zero then the processor
1343                          * includes an L3. ...
1344                          */
1345                         if ((regs[3] & 0xffff0000) != 0) {
1346                                 kprintf("L3 shared cache: %d kbytes",
1347                                         (regs[3] >> 18) * 512);
1348                                 kprintf(", %d bytes/line", regs[3] & 0xff);
1349                                 kprintf(", %d lines/tag", (regs[3] >> 8) & 0x0f);
1350                                 print_AMD_L2L3_assoc((regs[3] >> 12) & 0x0f);
1351                         }
1352                 }
1353         }
1354         if (((cpu_id & 0xf00) == 0x500)
1355             && (((cpu_id & 0x0f0) > 0x80)
1356                 || (((cpu_id & 0x0f0) == 0x80)
1357                     && (cpu_id & 0x00f) > 0x07))) {
1358                 /* K6-2(new core [Stepping 8-F]), K6-III or later */
1359                 amd_whcr = rdmsr(0xc0000082);
1360                 if (!(amd_whcr & (0x3ff << 22))) {
1361                         kprintf("Write Allocate Disable\n");
1362                 } else {
1363                         kprintf("Write Allocate Enable Limit: %dM bytes\n",
1364                             (u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
1365                         kprintf("Write Allocate 15-16M bytes: %s\n",
1366                             (amd_whcr & (1 << 16)) ? "Enable" : "Disable");
1367                 }
1368         } else if (((cpu_id & 0xf00) == 0x500)
1369                    && ((cpu_id & 0x0f0) > 0x50)) {
1370                 /* K6, K6-2(old core) */
1371                 amd_whcr = rdmsr(0xc0000082);
1372                 if (!(amd_whcr & (0x7f << 1))) {
1373                         kprintf("Write Allocate Disable\n");
1374                 } else {
1375                         kprintf("Write Allocate Enable Limit: %dM bytes\n",
1376                             (u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
1377                         kprintf("Write Allocate 15-16M bytes: %s\n",
1378                             (amd_whcr & 0x0001) ? "Enable" : "Disable");
1379                         kprintf("Hardware Write Allocate Control: %s\n",
1380                             (amd_whcr & 0x0100) ? "Enable" : "Disable");
1381                 }
1382         }
1383
1384         /*
1385          * Opteron Rev E shows a bug as in very rare occasions a read memory
1386          * barrier is not performed as expected if it is followed by a
1387          * non-atomic read-modify-write instruction.
1388          * As long as that bug pops up very rarely (intensive machine usage
1389          * on other operating systems generally generates one unexplainable
1390          * crash any 2 months) and as long as a model specific fix would be
1391          * impratical at this stage, print out a warning string if the broken
1392          * model and family are identified.
1393          */
1394         if (CPUID_TO_FAMILY(cpu_id) == 0xf && CPUID_TO_MODEL(cpu_id) >= 0x20 &&
1395             CPUID_TO_MODEL(cpu_id) <= 0x3f)
1396                 kprintf("WARNING: This architecture revision has known SMP "
1397                     "hardware bugs which may cause random instability\n");
1398 }
1399
1400 static void
1401 print_INTEL_info(void)
1402 {
1403         u_int regs[4];
1404         u_int rounds, regnum;
1405         u_int nwaycode, nway;
1406
1407         if (cpu_high >= 2) {
1408                 rounds = 0;
1409                 do {
1410                         do_cpuid(0x2, regs);
1411                         if (rounds == 0 && (rounds = (regs[0] & 0xff)) == 0)
1412                                 break;  /* we have a buggy CPU */
1413
1414                         for (regnum = 0; regnum <= 3; ++regnum) {
1415                                 if (regs[regnum] & (1<<31))
1416                                         continue;
1417                                 if (regnum != 0)
1418                                         print_INTEL_TLB(regs[regnum] & 0xff);
1419                                 print_INTEL_TLB((regs[regnum] >> 8) & 0xff);
1420                                 print_INTEL_TLB((regs[regnum] >> 16) & 0xff);
1421                                 print_INTEL_TLB((regs[regnum] >> 24) & 0xff);
1422                         }
1423                 } while (--rounds > 0);
1424         }
1425
1426         if (cpu_exthigh >= 0x80000006) {
1427                 do_cpuid(0x80000006, regs);
1428                 nwaycode = (regs[2] >> 12) & 0x0f;
1429                 if (nwaycode >= 0x02 && nwaycode <= 0x08)
1430                         nway = 1 << (nwaycode / 2);
1431                 else
1432                         nway = 0;
1433                 kprintf("\nL2 cache: %u kbytes, %u-way associative, %u bytes/line",
1434                     (regs[2] >> 16) & 0xffff, nway, regs[2] & 0xff);
1435         }
1436
1437         kprintf("\n");
1438 }
1439
1440 static void
1441 print_INTEL_TLB(u_int data)
1442 {
1443         switch (data) {
1444         case 0x0:
1445         case 0x40:
1446         default:
1447                 break;
1448         case 0x1:
1449                 kprintf("\nInstruction TLB: 4 KB pages, 4-way set associative, 32 entries");
1450                 break;
1451         case 0x2:
1452                 kprintf("\nInstruction TLB: 4 MB pages, fully associative, 2 entries");
1453                 break;
1454         case 0x3:
1455                 kprintf("\nData TLB: 4 KB pages, 4-way set associative, 64 entries");
1456                 break;
1457         case 0x4:
1458                 kprintf("\nData TLB: 4 MB Pages, 4-way set associative, 8 entries");
1459                 break;
1460         case 0x6:
1461                 kprintf("\n1st-level instruction cache: 8 KB, 4-way set associative, 32 byte line size");
1462                 break;
1463         case 0x8:
1464                 kprintf("\n1st-level instruction cache: 16 KB, 4-way set associative, 32 byte line size");
1465                 break;
1466         case 0xa:
1467                 kprintf("\n1st-level data cache: 8 KB, 2-way set associative, 32 byte line size");
1468                 break;
1469         case 0xc:
1470                 kprintf("\n1st-level data cache: 16 KB, 4-way set associative, 32 byte line size");
1471                 break;
1472         case 0x22:
1473                 kprintf("\n3rd-level cache: 512 KB, 4-way set associative, sectored cache, 64 byte line size");
1474                 break;
1475         case 0x23:
1476                 kprintf("\n3rd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size");
1477                 break;
1478         case 0x25:
1479                 kprintf("\n3rd-level cache: 2 MB, 8-way set associative, sectored cache, 64 byte line size");
1480                 break;
1481         case 0x29:
1482                 kprintf("\n3rd-level cache: 4 MB, 8-way set associative, sectored cache, 64 byte line size");
1483                 break;
1484         case 0x2c:
1485                 kprintf("\n1st-level data cache: 32 KB, 8-way set associative, 64 byte line size");
1486                 break;
1487         case 0x30:
1488                 kprintf("\n1st-level instruction cache: 32 KB, 8-way set associative, 64 byte line size");
1489                 break;
1490         case 0x39:
1491                 kprintf("\n2nd-level cache: 128 KB, 4-way set associative, sectored cache, 64 byte line size");
1492                 break;
1493         case 0x3b:
1494                 kprintf("\n2nd-level cache: 128 KB, 2-way set associative, sectored cache, 64 byte line size");
1495                 break;
1496         case 0x3c:
1497                 kprintf("\n2nd-level cache: 256 KB, 4-way set associative, sectored cache, 64 byte line size");
1498                 break;
1499         case 0x41:
1500                 kprintf("\n2nd-level cache: 128 KB, 4-way set associative, 32 byte line size");
1501                 break;
1502         case 0x42:
1503                 kprintf("\n2nd-level cache: 256 KB, 4-way set associative, 32 byte line size");
1504                 break;
1505         case 0x43:
1506                 kprintf("\n2nd-level cache: 512 KB, 4-way set associative, 32 byte line size");
1507                 break;
1508         case 0x44:
1509                 kprintf("\n2nd-level cache: 1 MB, 4-way set associative, 32 byte line size");
1510                 break;
1511         case 0x45:
1512                 kprintf("\n2nd-level cache: 2 MB, 4-way set associative, 32 byte line size");
1513                 break;
1514         case 0x46:
1515                 kprintf("\n3rd-level cache: 4 MB, 4-way set associative, 64 byte line size");
1516                 break;
1517         case 0x47:
1518                 kprintf("\n3rd-level cache: 8 MB, 8-way set associative, 64 byte line size");
1519                 break;
1520         case 0x50:
1521                 kprintf("\nInstruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 64 entries");
1522                 break;
1523         case 0x51:
1524                 kprintf("\nInstruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 128 entries");
1525                 break;
1526         case 0x52:
1527                 kprintf("\nInstruction TLB: 4 KB, 2 MB or 4 MB pages, fully associative, 256 entries");
1528                 break;
1529         case 0x5b:
1530                 kprintf("\nData TLB: 4 KB or 4 MB pages, fully associative, 64 entries");
1531                 break;
1532         case 0x5c:
1533                 kprintf("\nData TLB: 4 KB or 4 MB pages, fully associative, 128 entries");
1534                 break;
1535         case 0x5d:
1536                 kprintf("\nData TLB: 4 KB or 4 MB pages, fully associative, 256 entries");
1537                 break;
1538         case 0x60:
1539                 kprintf("\n1st-level data cache: 16 KB, 8-way set associative, sectored cache, 64 byte line size");
1540                 break;
1541         case 0x66:
1542                 kprintf("\n1st-level data cache: 8 KB, 4-way set associative, sectored cache, 64 byte line size");
1543                 break;
1544         case 0x67:
1545                 kprintf("\n1st-level data cache: 16 KB, 4-way set associative, sectored cache, 64 byte line size");
1546                 break;
1547         case 0x68:
1548                 kprintf("\n1st-level data cache: 32 KB, 4 way set associative, sectored cache, 64 byte line size");
1549                 break;
1550         case 0x70:
1551                 kprintf("\nTrace cache: 12K-uops, 8-way set associative");
1552                 break;
1553         case 0x71:
1554                 kprintf("\nTrace cache: 16K-uops, 8-way set associative");
1555                 break;
1556         case 0x72:
1557                 kprintf("\nTrace cache: 32K-uops, 8-way set associative");
1558                 break;
1559         case 0x78:
1560                 kprintf("\n2nd-level cache: 1 MB, 4-way set associative, 64-byte line size");
1561                 break;
1562         case 0x79:
1563                 kprintf("\n2nd-level cache: 128 KB, 8-way set associative, sectored cache, 64 byte line size");
1564                 break;
1565         case 0x7a:
1566                 kprintf("\n2nd-level cache: 256 KB, 8-way set associative, sectored cache, 64 byte line size");
1567                 break;
1568         case 0x7b:
1569                 kprintf("\n2nd-level cache: 512 KB, 8-way set associative, sectored cache, 64 byte line size");
1570                 break;
1571         case 0x7c:
1572                 kprintf("\n2nd-level cache: 1 MB, 8-way set associative, sectored cache, 64 byte line size");
1573                 break;
1574         case 0x7d:
1575                 kprintf("\n2nd-level cache: 2-MB, 8-way set associative, 64-byte line size");
1576                 break;
1577         case 0x7f:
1578                 kprintf("\n2nd-level cache: 512-KB, 2-way set associative, 64-byte line size");
1579                 break;
1580         case 0x82:
1581                 kprintf("\n2nd-level cache: 256 KB, 8-way set associative, 32 byte line size");
1582                 break;
1583         case 0x83:
1584                 kprintf("\n2nd-level cache: 512 KB, 8-way set associative, 32 byte line size");
1585                 break;
1586         case 0x84:
1587                 kprintf("\n2nd-level cache: 1 MB, 8-way set associative, 32 byte line size");
1588                 break;
1589         case 0x85:
1590                 kprintf("\n2nd-level cache: 2 MB, 8-way set associative, 32 byte line size");
1591                 break;
1592         case 0x86:
1593                 kprintf("\n2nd-level cache: 512 KB, 4-way set associative, 64 byte line size");
1594                 break;
1595         case 0x87:
1596                 kprintf("\n2nd-level cache: 1 MB, 8-way set associative, 64 byte line size");
1597                 break;
1598         case 0xb0:
1599                 kprintf("\nInstruction TLB: 4 KB Pages, 4-way set associative, 128 entries");
1600                 break;
1601         case 0xb3:
1602                 kprintf("\nData TLB: 4 KB Pages, 4-way set associative, 128 entries");
1603                 break;
1604         }
1605 }
1606
1607 static void
1608 print_transmeta_info(void)
1609 {
1610         u_int regs[4], nreg = 0;
1611
1612         do_cpuid(0x80860000, regs);
1613         nreg = regs[0];
1614         if (nreg >= 0x80860001) {
1615                 do_cpuid(0x80860001, regs);
1616                 kprintf("  Processor revision %u.%u.%u.%u\n",
1617                        (regs[1] >> 24) & 0xff,
1618                        (regs[1] >> 16) & 0xff,
1619                        (regs[1] >> 8) & 0xff,
1620                        regs[1] & 0xff);
1621         }
1622         if (nreg >= 0x80860002) {
1623                 do_cpuid(0x80860002, regs);
1624                 kprintf("  Code Morphing Software revision %u.%u.%u-%u-%u\n",
1625                        (regs[1] >> 24) & 0xff,
1626                        (regs[1] >> 16) & 0xff,
1627                        (regs[1] >> 8) & 0xff,
1628                        regs[1] & 0xff,
1629                        regs[2]);
1630         }
1631         if (nreg >= 0x80860006) {
1632                 char info[65];
1633                 do_cpuid(0x80860003, (u_int*) &info[0]);
1634                 do_cpuid(0x80860004, (u_int*) &info[16]);
1635                 do_cpuid(0x80860005, (u_int*) &info[32]);
1636                 do_cpuid(0x80860006, (u_int*) &info[48]);
1637                 info[64] = 0;
1638                 kprintf("  %s\n", info);
1639         }
1640 }
1641
1642 static void
1643 print_via_padlock_info(void)
1644 {
1645         u_int regs[4];
1646
1647         /* Check for supported models. */
1648         switch (cpu_id & 0xff0) {
1649         case 0x690:
1650                 if ((cpu_id & 0xf) < 3)
1651                         return;
1652         case 0x6a0:
1653         case 0x6d0:
1654         case 0x6f0:
1655                 break;
1656         default:
1657                 return;
1658         }
1659
1660         do_cpuid(0xc0000000, regs);
1661         if (regs[0] >= 0xc0000001)
1662                 do_cpuid(0xc0000001, regs);
1663         else
1664                 return;
1665
1666         kprintf("\n  VIA Padlock Features=0x%b", regs[3],
1667         "\020"
1668         "\003RNG"               /* RNG */
1669         "\007AES"               /* ACE */
1670         "\011AES-CTR"           /* ACE2 */
1671         "\013SHA1,SHA256"       /* PHE */
1672         "\015RSA"               /* PMM */
1673         );
1674 }
1675
1676 void
1677 additional_cpu_info(const char *line)
1678 {
1679         int i;
1680
1681         if ((i = additional_cpu_info_count) < MAX_ADDITIONAL_INFO) {
1682                 additional_cpu_info_ary[i] = line;
1683                 ++additional_cpu_info_count;
1684         }
1685 }