2 * Copyright (c) 2003 by Quinton Dolan <q@onthenet.com.au>.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS `AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * $Id: if_nvreg.h,v 1.3 2003/11/08 13:03:01 q Exp $
27 * $DragonFly: src/sys/dev/netif/nv/Attic/if_nvreg.h,v 1.5 2004/11/05 17:13:44 dillon Exp $
37 #ifndef NVIDIA_VENDORID
38 #define NVIDIA_VENDORID 0x10DE
41 #define NFORCE_MCPNET1_DEVICEID 0x01C3
42 #define NFORCE_MCPNET2_DEVICEID 0x0066
43 #define NFORCE_MCPNET3_DEVICEID 0x00D6
44 #define NFORCE_MCPNET4_DEVICEID 0x0086
45 #define NFORCE_MCPNET5_DEVICEID 0x008C
46 #define NFORCE_MCPNET6_DEVICEID 0x00E6
47 #define NFORCE_MCPNET7_DEVICEID 0x00DF
51 #define TX_RING_SIZE 64
52 #define RX_RING_SIZE 64
54 #define NV_MAX_FRAGS 63
56 #define NV_DEBUG_INIT 0x0001
57 #define NV_DEBUG_RUNNING 0x0002
58 #define NV_DEBUG_DEINIT 0x0004
59 #define NV_DEBUG_IOCTL 0x0008
60 #define NV_DEBUG_INTERRUPT 0x0010
61 #define NV_DEBUG_API 0x0020
62 #define NV_DEBUG_LOCK 0x0040
63 #define NV_DEBUG_BROKEN 0x0080
64 #define NV_DEBUG_MII 0x0100
65 #define NV_DEBUG_ALL 0xFFFF
67 #define NV_DEBUG 0x0000
70 #define DEBUGOUT(level, fmt, args...) if (NV_DEBUG & level) \
73 #define DEBUGOUT(level, fmt, args...)
76 typedef unsigned long ulong;
78 struct nv_map_buffer {
79 struct mbuf *mbuf; /* mbuf receiving packet */
80 bus_dmamap_t map; /* DMA map */
85 struct nv_map_buffer buf;
87 caddr_t vaddr; /* Virtual memory address */
88 bus_addr_t paddr; /* DMA physical address */
92 struct nv_rx_desc *next;
93 struct nv_map_buffer buf;
100 /* Don't add anything above this structure */
101 TX_INFO_ADAP TxInfoAdap;
102 struct nv_tx_desc *next;
103 struct nv_map_buffer buf;
106 bus_dma_segment_t frags[NV_MAX_FRAGS + 1];
110 struct arpcom arpcom; /* interface info */
111 struct resource *res;
112 struct resource *irq;
119 struct callout nv_stat_timer;
122 bus_space_tag_t sc_st;
123 bus_space_handle_t sc_sh;
130 struct nv_rx_desc *rx_desc;
131 struct nv_tx_desc *tx_desc;
134 u_int16_t rx_ring_full;
135 u_int16_t tx_ring_full;
138 u_int32_t pending_rxs;
139 u_int32_t pending_txs;
145 /* Stuff for dealing with the NVIDIA OS API */
146 struct callout ostimer;
147 PTIMER_FUNC ostimer_func;
148 void *ostimer_params;
152 unsigned char original_mac_addr[6];
161 #define sc_if arpcom.ac_if
162 #define sc_macaddr arpcom.ac_enaddr
164 #define NV_LOCK(_sc) int s = splimp()
165 #define NV_UNLOCK(_sc) splx(s)
166 #define NV_OSLOCK(_sc) (int)(_sc)->spl = splimp()
167 #define NV_OSUNLOCK(_sc) splx((int)(_sc)->spl)
169 extern int ADAPTER_ReadPhy (PVOID pContext, ULONG ulPhyAddr, ULONG ulReg, ULONG *pulVal);
170 extern int ADAPTER_WritePhy (PVOID pContext, ULONG ulPhyAddr, ULONG ulReg, ULONG ulVal);
171 extern int ADAPTER_Init (PVOID pContext, USHORT usForcedSpeed, UCHAR ucForceDpx, UCHAR ucForceMode, UINT *puiLinkState);