sys/dev/raid/tws/tws_hdm.h

   1 /*
   2  * Copyright (c) 2010, LSI Corp.
   3  * All rights reserved.
   4  * Author : Manjunath Ranganathaiah
   5  * Support: freebsdraid@lsi.com
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  *
  11  * 1. Redistributions of source code must retain the above copyright
  12  *    notice, this list of conditions and the following disclaimer.
  13  * 2. Redistributions in binary form must reproduce the above copyright
  14  *    notice, this list of conditions and the following disclaimer in
  15  *    the documentation and/or other materials provided with the
  16  *    distribution.
  17  * 3. Neither the name of the <ORGANIZATION> nor the names of its
  18  *    contributors may be used to endorse or promote products derived
  19  *    from this software without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
  24  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
  25  * COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
  26  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
  27  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  28  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  29  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  30  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
  31  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  32  * POSSIBILITY OF SUCH DAMAGE.
  33  *
  34  * $FreeBSD: src/sys/dev/tws/tws_hdm.h,v 1.3 2007/05/09 04:16:32 mrangana Exp $
  35  */
  36
  37
  38 /* bit's defination */
  39
  40 #define TWS_BIT0                              0x00000001
  41 #define TWS_BIT1                              0x00000002
  42 #define TWS_BIT2                              0x00000004
  43 #define TWS_BIT3                              0x00000008
  44 #define TWS_BIT4                              0x00000010
  45 #define TWS_BIT5                              0x00000020
  46 #define TWS_BIT6                              0x00000040
  47 #define TWS_BIT7                              0x00000080
  48 #define TWS_BIT8                              0x00000100
  49 #define TWS_BIT9                              0x00000200
  50 #define TWS_BIT10                             0x00000400
  51 #define TWS_BIT11                             0x00000800
  52 #define TWS_BIT12                             0x00001000
  53 #define TWS_BIT13                             0x00002000
  54 #define TWS_BIT14                             0x00004000
  55 #define TWS_BIT15                             0x00008000
  56 #define TWS_BIT16                             0x00010000
  57 #define TWS_BIT17                             0x00020000
  58 #define TWS_BIT18                             0x00040000
  59 #define TWS_BIT19                             0x00080000
  60 #define TWS_BIT20                             0x00100000
  61 #define TWS_BIT21                             0x00200000
  62 #define TWS_BIT22                             0x00400000
  63 #define TWS_BIT23                             0x00800000
  64 #define TWS_BIT24                             0x01000000
  65 #define TWS_BIT25                             0x02000000
  66 #define TWS_BIT26                             0x04000000
  67 #define TWS_BIT27                             0x08000000
  68 #define TWS_BIT28                             0x10000000
  69 #define TWS_BIT29                             0x20000000
  70 #define TWS_BIT30                             0x40000000
  71 #define TWS_BIT31                             0x80000000
  72
  73 #define TWS_SENSE_DATA_LENGTH                 18
  74 #define TWS_ERROR_SPECIFIC_DESC_LEN           98
  75
  76 /* response codes */
  77 #define TWS_SENSE_SCSI_CURRENT_ERROR          0x70
  78 #define TWS_SENSE_SCSI_DEFERRED_ERROR         0x71
  79
  80 #define TWS_SRC_CTRL_ERROR                    3
  81 #define TWS_SRC_CTRL_EVENT                    4
  82 #define TWS_SRC_FREEBSD_DRIVER                5
  83 #define TWS_SRC_FREEBSD_OS                    8
  84
  85
  86 enum tws_sense_severity {
  87     error = 1,
  88     warning ,
  89     info,
  90     debug,
  91 };
  92
  93 /*
  94  * Some errors of interest (in cmd_hdr->status_block.error) when a command
  95  * is completed by the firmware with an error.
  96  */
  97 #define TWS_ERROR_LOGICAL_UNIT_NOT_SUPPORTED    0x010a
  98 #define TWS_ERROR_NOT_SUPPORTED                 0x010D
  99 #define TWS_ERROR_UNIT_OFFLINE                  0x0128
 100 #define TWS_ERROR_MORE_DATA                     0x0231
 101
 102
 103 /* AEN codes of interest. */
 104 #define TWS_AEN_QUEUE_EMPTY                     0x00
 105 #define TWS_AEN_SOFT_RESET                      0x01
 106 #define TWS_AEN_SYNC_TIME_WITH_HOST             0x31
 107
 108
 109 /* AEN severity */
 110 #define TWS_SEVERITY_ERROR                      0x1
 111 #define TWS_SEVERITY_WARNING                    0x2
 112 #define TWS_SEVERITY_INFO                       0x3
 113 #define TWS_SEVERITY_DEBUG                      0x4
 114
 115 #define TWS_64BIT_SG_ADDRESSES                  0x00000001
 116 #define TWS_BIT_EXTEND                          0x00000002
 117
 118 #define TWS_BASE_FW_SRL                         24
 119 #define TWS_BASE_FW_BRANCH                      0
 120 #define TWS_BASE_FW_BUILD                       1
 121 #define TWS_CURRENT_FW_SRL                      40
 122
 123 #define TWS_CURRENT_FW_BRANCH                   8
 124 #define TWS_CURRENT_FW_BUILD                    4
 125 #define TWS_CURRENT_ARCH_ID                     0x000A
 126
 127
 128 #define TWS_FIFO_EMPTY                          0xFFFFFFFFFFFFFFFFull
 129 #define TWS_FIFO_EMPTY32                        0xFFFFFFFFull
 130
 131
 132 /* Register offsets from base address. */
 133 #define TWS_CONTROL_REGISTER_OFFSET             0x0
 134 #define TWS_STATUS_REGISTER_OFFSET              0x4
 135 #define TWS_COMMAND_QUEUE_OFFSET                0x8
 136 #define TWS_RESPONSE_QUEUE_OFFSET               0xC
 137 #define TWS_COMMAND_QUEUE_OFFSET_LOW            0x20
 138 #define TWS_COMMAND_QUEUE_OFFSET_HIGH           0x24
 139 #define TWS_LARGE_RESPONSE_QUEUE_OFFSET         0x30
 140
 141 /* I2O offsets */
 142 #define TWS_I2O0_STATUS                         0x0
 143
 144 #define TWS_I2O0_HIBDB                          0x20
 145
 146 #define TWS_I2O0_HISTAT                         0x30
 147 #define TWS_I2O0_HIMASK                         0x34
 148
 149 #define TWS_I2O0_HIBQP                          0x40
 150 #define TWS_I2O0_HOBQP                          0x44
 151
 152 #define TWS_I2O0_CTL                            0x74
 153
 154 #define TWS_I2O0_IOBDB                          0x9C
 155 #define TWS_I2O0_HOBDBC                         0xA0
 156
 157 #define TWS_I2O0_SCRPD3                         0xBC
 158
 159 #define TWS_I2O0_HIBQPL                         0xC0 /* 64bit inb port low */
 160 #define TWS_I2O0_HIBQPH                         0xC4 /* 64bit inb port high */
 161 #define TWS_I2O0_HOBQPL                         0xC8 /* 64bit out port low */
 162 #define TWS_I2O0_HOBQPH                         0xCC /* 64bit out port high */
 163
 164 /* IOP related */
 165 #define TWS_I2O0_IOPOBQPL                       0xD8 /* OBFL */
 166 #define TWS_I2O0_IOPOBQPH                       0xDC /* OBFH */
 167 #define TWS_I2O0_SRC_ADDRH                      0xF8 /* Msg ASA */
 168
 169 #define TWS_MSG_ACC_MASK                        0x20000000
 170 #define TWS_32BIT_MASK                          0xFFFFFFFF
 171
 172 /* revisit */
 173 #define TWS_FW_CMD_NOP                     0x0
 174 #define TWS_FW_CMD_INIT_CONNECTION         0x01
 175 #define TWS_FW_CMD_EXECUTE_SCSI            0x10
 176
 177 #define TWS_FW_CMD_ATA_PASSTHROUGH         0x11
 178 #define TWS_FW_CMD_GET_PARAM               0x12
 179 #define TWS_FW_CMD_SET_PARAM               0x13
 180
 181
 182 #define BUILD_SGL_OFF__OPCODE(sgl_off, opcode)  \
 183         ((sgl_off << 5) & 0xE0) | (opcode & 0x1F)       /* 3:5 */
 184
 185 #define BUILD_RES__OPCODE(res, opcode)          \
 186         ((res << 5) & 0xE0) | (opcode & 0x1F)           /* 3:5 */
 187
 188 #define GET_OPCODE(sgl_off__opcode)     \
 189         (sgl_off__opcode & 0x1F)                        /* 3:5 */
 190
 191
 192
 193 /* end revisit */
 194
 195
 196 /* Table #'s and id's of parameters of interest in firmware's param table. */
 197 #define TWS_PARAM_VERSION_TABLE         0x0402
 198 #define TWS_PARAM_VERSION_FW            3       /* firmware version [16] */
 199 #define TWS_PARAM_VERSION_BIOS          4       /* BIOSs version [16] */
 200 #define TWS_PARAM_CTLR_MODEL            8       /* Controller model [16] */
 201
 202 #define TWS_PARAM_CONTROLLER_TABLE      0x0403
 203 #define TWS_PARAM_CONTROLLER_PORT_COUNT 3       /* number of ports [1] */
 204
 205 #define TWS_PARAM_TIME_TABLE            0x40A
 206 #define TWS_PARAM_TIME_SCHED_TIME       0x3
 207
 208 #define TWS_PARAM_PHYS_TABLE            0x0001
 209 #define TWS_PARAM_CONTROLLER_PHYS_COUNT 2       /* number of phys */
 210
 211 #define TWS_9K_PARAM_DESCRIPTOR         0x8000
 212
 213
 214 /* ----------- request  ------------- */
 215
 216
 217 #pragma pack(1)
 218
 219 struct tws_cmd_init_connect {
 220     u_int8_t        res1__opcode;   /* 3:5 */
 221     u_int8_t        size;
 222     u_int8_t        request_id;
 223     u_int8_t        res2;
 224     u_int8_t        status;
 225     u_int8_t        flags;
 226     u_int16_t       message_credits;
 227     u_int32_t       features;
 228     u_int16_t       fw_srl;
 229     u_int16_t       fw_arch_id;
 230     u_int16_t       fw_branch;
 231     u_int16_t       fw_build;
 232     u_int32_t       result;
 233 };
 234
 235 /* Structure for downloading firmware onto the controller. */
 236 struct tws_cmd_download_firmware {
 237     u_int8_t        sgl_off__opcode;/* 3:5 */
 238     u_int8_t        size;
 239     u_int8_t        request_id;
 240     u_int8_t        unit;
 241     u_int8_t        status;
 242     u_int8_t        flags;
 243     u_int16_t       param;
 244     u_int8_t        sgl[1];
 245 };
 246
 247 /* Structure for hard resetting the controller. */
 248 struct tws_cmd_reset_firmware {
 249     u_int8_t        res1__opcode;   /* 3:5 */
 250     u_int8_t        size;
 251     u_int8_t        request_id;
 252     u_int8_t        unit;
 253     u_int8_t        status;
 254     u_int8_t        flags;
 255     u_int8_t        res2;
 256     u_int8_t        param;
 257 };
 258
 259
 260 /* Structure for sending get/set param commands. */
 261 struct tws_cmd_param {
 262     u_int8_t        sgl_off__opcode;/* 3:5 */
 263     u_int8_t        size;
 264     u_int8_t        request_id;
 265     u_int8_t        host_id__unit;  /* 4:4 */
 266     u_int8_t        status;
 267     u_int8_t        flags;
 268     u_int16_t       param_count;
 269     u_int8_t        sgl[1];
 270 };
 271
 272 /* Generic command packet. */
 273 struct tws_cmd_generic {
 274     u_int8_t        sgl_off__opcode;/* 3:5 */
 275     u_int8_t        size;
 276     u_int8_t        request_id;
 277     u_int8_t        host_id__unit;  /* 4:4 */
 278     u_int8_t        status;
 279     u_int8_t        flags;
 280     u_int16_t       count;  /* block cnt, parameter cnt, message credits */
 281 };
 282
 283
 284
 285
 286 /* Command packet header. */
 287 struct tws_command_header {
 288     u_int8_t        sense_data[TWS_SENSE_DATA_LENGTH];
 289     struct { /* status block - additional sense data */
 290         u_int16_t       srcnum;
 291         u_int8_t        reserved;
 292         u_int8_t        status;
 293         u_int16_t       error;
 294         u_int8_t        res__srcid;     /* 4:4 */
 295         u_int8_t        res__severity;  /* 5:3 */
 296     } status_block;
 297     u_int8_t        err_specific_desc[TWS_ERROR_SPECIFIC_DESC_LEN];
 298     struct { /* sense buffer descriptor */
 299         u_int8_t        size_header;
 300         u_int16_t       request_id;
 301         u_int8_t        size_sense;
 302     } header_desc;
 303 };
 304
 305 /* Command - 1024 byte size including header (128+24+896)*/
 306 union tws_command_giga {
 307     struct tws_cmd_init_connect       init_connect;
 308     struct tws_cmd_download_firmware  download_fw;
 309     struct tws_cmd_reset_firmware     reset_fw;
 310     struct tws_cmd_param              param;
 311     struct tws_cmd_generic            generic;
 312     u_int8_t        padding[1024 - sizeof(struct tws_command_header)];
 313 };
 314
 315 /* driver command pkt - 1024 byte size including header(128+24+744+128) */
 316 /* h/w & f/w supported command size excluding header 768 */
 317 struct tws_command_apache {
 318     u_int8_t        res__opcode;    /* 3:5 */
 319     u_int8_t        unit;
 320     u_int16_t       lun_l4__req_id; /* 4:12 */
 321     u_int8_t        status;
 322     u_int8_t        sgl_offset;     /* offset (in bytes) to sg_list,
 323                                      from the end of sgl_entries */
 324     u_int16_t       lun_h4__sgl_entries;
 325     u_int8_t        cdb[16];
 326     u_int8_t        sg_list[744];   /* 768 - 24 */
 327     u_int8_t        padding[128];   /* make it 1024 bytes */
 328 };
 329
 330 struct tws_command_packet {
 331     struct tws_command_header hdr;
 332     union {
 333         union tws_command_giga pkt_g;
 334         struct tws_command_apache pkt_a;
 335     } cmd;
 336 };
 337
 338 /* Structure describing payload for get/set param commands. */
 339 struct tws_getset_param {
 340     u_int16_t       table_id;
 341     u_int8_t        parameter_id;
 342     u_int8_t        reserved;
 343     u_int16_t       parameter_size_bytes;
 344     u_int16_t       parameter_actual_size_bytes;
 345     u_int8_t        data[1];
 346 };
 347
 348 struct tws_outbound_response {
 349     u_int32_t     not_mfa   :1;   /* 1 if the structure is valid else MFA */
 350     u_int32_t     reserved  :7;   /* reserved bits */
 351     u_int32_t     status    :8;   /* should be 0 */
 352     u_int32_t     request_id:16;  /* request id */
 353 };
 354
 355
 356 /* Scatter/Gather list entry with 32 bit addresses. */
 357 struct tws_sg_desc32 {
 358     u_int32_t     address;
 359     u_int32_t     length  :24;
 360     u_int32_t     flag    :8;
 361 };
 362
 363 /* Scatter/Gather list entry with 64 bit addresses. */
 364 struct tws_sg_desc64 {
 365     u_int64_t     address;
 366     u_int64_t     length   :32;
 367     u_int64_t     reserved :24;
 368     u_int64_t     flag     :8;
 369 };
 370
 371 /*
 372  * Packet that describes an AEN/error generated by the controller,
 373  * shared with user
 374  */
 375 struct tws_event_packet {
 376     u_int32_t       sequence_id;
 377     u_int32_t       time_stamp_sec;
 378     u_int16_t       aen_code;
 379     u_int8_t        severity;
 380     u_int8_t        retrieved;
 381     u_int8_t        repeat_count;
 382     u_int8_t        parameter_len;
 383     u_int8_t        parameter_data[TWS_ERROR_SPECIFIC_DESC_LEN];
 384     u_int32_t       event_src;
 385     u_int8_t        severity_str[20];
 386 };
 387
 388
 389
 390 #pragma pack()
 391
 392 struct tws_sense {
 393     struct tws_command_header *hdr;
 394     u_int64_t  hdr_pkt_phy;
 395     boolean posted;
 396 };
 397
 398 struct tws_request {
 399     struct tws_command_packet *cmd_pkt; /* command pkt */
 400     u_int64_t    cmd_pkt_phy;    /* cmd pkt physical address */
 401     void         *data;          /* ptr to data being passed to fw */
 402     u_int32_t    length;         /* length of data being passed to fw */
 403
 404     u_int32_t    state;          /* request state */
 405     u_int32_t    type;           /* request type */
 406     u_int32_t    flags;          /* request flags */
 407
 408     u_int32_t    error_code;     /* error encountered before submission
 409                                         of request to fw, if any */
 410
 411     u_int32_t    request_id;     /* request id for tracking with fw */
 412     void         (*cb)(struct tws_request *);      /* callback func */
 413     bus_dmamap_t dma_map;        /* dma map */
 414     union ccb    *ccb_ptr;       /* pointer to ccb */
 415     struct callout thandle;      /* handle to req timeout */
 416     struct tws_softc *sc;        /* pointer back to ctlr softc */
 417
 418     struct tws_request *next;    /* pointer to next request */
 419     struct tws_request *prev;    /* pointer to prev request */
 420 };