hammer2 - update documentation, begin working on callback I/O
[dragonfly.git] / sys / platform / pc32 / isa / clock.c
1 /*-
2  * Copyright (c) 1990 The Regents of the University of California.
3  * All rights reserved.
4  *
5  * This code is derived from software contributed to Berkeley by
6  * William Jolitz and Don Ahn.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  * 3. All advertising materials mentioning features or use of this software
17  *    must display the following acknowledgement:
18  *      This product includes software developed by the University of
19  *      California, Berkeley and its contributors.
20  * 4. Neither the name of the University nor the names of its contributors
21  *    may be used to endorse or promote products derived from this software
22  *    without specific prior written permission.
23  *
24  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34  * SUCH DAMAGE.
35  *
36  *      from: @(#)clock.c       7.2 (Berkeley) 5/12/91
37  * $FreeBSD: src/sys/i386/isa/clock.c,v 1.149.2.6 2002/11/02 04:41:50 iwasaki Exp $
38  */
39
40 /*
41  * Routines to handle clock hardware.
42  */
43
44 /*
45  * inittodr, settodr and support routines written
46  * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at>
47  *
48  * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94
49  */
50
51 #include "opt_clock.h"
52
53 #include <sys/param.h>
54 #include <sys/systm.h>
55 #include <sys/eventhandler.h>
56 #include <sys/time.h>
57 #include <sys/kernel.h>
58 #include <sys/bus.h>
59 #include <sys/sysctl.h>
60 #include <sys/cons.h>
61 #include <sys/systimer.h>
62 #include <sys/globaldata.h>
63 #include <sys/thread2.h>
64 #include <sys/machintr.h>
65 #include <sys/interrupt.h>
66
67 #include <machine/clock.h>
68 #include <machine/cputypes.h>
69 #include <machine/frame.h>
70 #include <machine/ipl.h>
71 #include <machine/limits.h>
72 #include <machine/md_var.h>
73 #include <machine/psl.h>
74 #include <machine/segments.h>
75 #include <machine/smp.h>
76 #include <machine/specialreg.h>
77
78 #include <machine_base/apic/ioapic.h>
79 #include <machine_base/apic/ioapic_abi.h>
80 #include <machine_base/icu/icu.h>
81 #include <bus/isa/isa.h>
82 #include <bus/isa/rtc.h>
83 #include <machine_base/isa/timerreg.h>
84
85 #include <machine/intr_machdep.h>
86
87 static void i8254_restore(void);
88 static void resettodr_on_shutdown(void *arg __unused);
89
90 /*
91  * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we
92  * can use a simple formula for leap years.
93  */
94 #define LEAPYEAR(y) ((u_int)(y) % 4 == 0)
95 #define DAYSPERYEAR   (31+28+31+30+31+30+31+31+30+31+30+31)
96
97 #ifndef TIMER_FREQ
98 #define TIMER_FREQ   1193182
99 #endif
100
101 static uint8_t i8254_walltimer_sel;
102 static uint16_t i8254_walltimer_cntr;
103
104 int     adjkerntz;              /* local offset from GMT in seconds */
105 int     disable_rtc_set;        /* disable resettodr() if != 0 */
106 int     tsc_present;
107 int     tsc_invariant;
108 int     tsc_mpsync;
109 int64_t tsc_frequency;
110 int     tsc_is_broken;
111 int     wall_cmos_clock;        /* wall CMOS clock assumed if != 0 */
112 int     timer0_running;
113 enum tstate { RELEASED, ACQUIRED };
114 enum tstate timer0_state;
115 enum tstate timer1_state;
116 enum tstate timer2_state;
117
118 static  int     beeping = 0;
119 static  const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31};
120 static  u_char  rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
121 static  u_char  rtc_statusb = RTCSB_24HR | RTCSB_PINTR;
122 static  int     rtc_loaded;
123
124 static int i8254_cputimer_div;
125
126 static int i8254_nointr;
127 static int i8254_intr_disable = 1;
128 TUNABLE_INT("hw.i8254.intr_disable", &i8254_intr_disable);
129
130 static struct callout sysbeepstop_ch;
131
132 static sysclock_t i8254_cputimer_count(void);
133 static void i8254_cputimer_construct(struct cputimer *cputimer, sysclock_t last);
134 static void i8254_cputimer_destruct(struct cputimer *cputimer);
135
136 static struct cputimer  i8254_cputimer = {
137     SLIST_ENTRY_INITIALIZER,
138     "i8254",
139     CPUTIMER_PRI_8254,
140     0,
141     i8254_cputimer_count,
142     cputimer_default_fromhz,
143     cputimer_default_fromus,
144     i8254_cputimer_construct,
145     i8254_cputimer_destruct,
146     TIMER_FREQ,
147     0, 0, 0
148 };
149
150 static sysclock_t tsc_cputimer_count(void);
151 static void tsc_cputimer_construct(struct cputimer *, sysclock_t);
152
153 static struct cputimer  tsc_cputimer = {
154     SLIST_ENTRY_INITIALIZER,
155     "TSC",
156     CPUTIMER_PRI_TSC,
157     CPUTIMER_TSC,
158     tsc_cputimer_count,
159     cputimer_default_fromhz,
160     cputimer_default_fromus,
161     tsc_cputimer_construct,
162     cputimer_default_destruct,
163     0,
164     0, 0, 0
165 };
166
167 static void i8254_intr_reload(struct cputimer_intr *, sysclock_t);
168 static void i8254_intr_config(struct cputimer_intr *, const struct cputimer *);
169 static void i8254_intr_initclock(struct cputimer_intr *, boolean_t);
170
171 static struct cputimer_intr i8254_cputimer_intr = {
172     .freq = TIMER_FREQ,
173     .reload = i8254_intr_reload,
174     .enable = cputimer_intr_default_enable,
175     .config = i8254_intr_config,
176     .restart = cputimer_intr_default_restart,
177     .pmfixup = cputimer_intr_default_pmfixup,
178     .initclock = i8254_intr_initclock,
179     .next = SLIST_ENTRY_INITIALIZER,
180     .name = "i8254",
181     .type = CPUTIMER_INTR_8254,
182     .prio = CPUTIMER_INTR_PRIO_8254,
183     .caps = CPUTIMER_INTR_CAP_PS
184 };
185
186 /*
187  * timer0 clock interrupt.  Timer0 is in one-shot mode and has stopped
188  * counting as of this interrupt.  We use timer1 in free-running mode (not
189  * generating any interrupts) as our main counter.  Each cpu has timeouts
190  * pending.
191  *
192  * This code is INTR_MPSAFE and may be called without the BGL held.
193  */
194 static void
195 clkintr(void *dummy, void *frame_arg)
196 {
197         static sysclock_t sysclock_count;       /* NOTE! Must be static */
198         struct globaldata *gd = mycpu;
199         struct globaldata *gscan;
200         int n;
201
202         /*
203          * SWSTROBE mode is a one-shot, the timer is no longer running
204          */
205         timer0_running = 0;
206
207         /*
208          * XXX the dispatcher needs work.  right now we call systimer_intr()
209          * directly or via IPI for any cpu with systimers queued, which is
210          * usually *ALL* of them.  We need to use the LAPIC timer for this.
211          */
212         sysclock_count = sys_cputimer->count();
213         for (n = 0; n < ncpus; ++n) {
214             gscan = globaldata_find(n);
215             if (TAILQ_FIRST(&gscan->gd_systimerq) == NULL)
216                 continue;
217             if (gscan != gd) {
218                 lwkt_send_ipiq3(gscan, (ipifunc3_t)systimer_intr, 
219                                 &sysclock_count, 1);
220             } else {
221                 systimer_intr(&sysclock_count, 0, frame_arg);
222             }
223         }
224 }
225
226
227 /*
228  * NOTE! not MP safe.
229  */
230 int
231 acquire_timer2(int mode)
232 {
233         if (timer2_state != RELEASED)
234                 return (-1);
235         timer2_state = ACQUIRED;
236
237         /*
238          * This access to the timer registers is as atomic as possible
239          * because it is a single instruction.  We could do better if we
240          * knew the rate.
241          */
242         outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f));
243         return (0);
244 }
245
246 int
247 release_timer2(void)
248 {
249         if (timer2_state != ACQUIRED)
250                 return (-1);
251         outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT);
252         timer2_state = RELEASED;
253         return (0);
254 }
255
256 #include "opt_ddb.h"
257 #ifdef DDB
258 #include <ddb/ddb.h>
259
260 DB_SHOW_COMMAND(rtc, rtc)
261 {
262         kprintf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n",
263                rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY),
264                rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC),
265                rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR));
266 }
267 #endif /* DDB */
268
269 /*
270  * Return the current cpu timer count as a 32 bit integer.
271  */
272 static
273 sysclock_t
274 i8254_cputimer_count(void)
275 {
276         static __uint16_t cputimer_last;
277         __uint16_t count;
278         sysclock_t ret;
279
280         clock_lock();
281         outb(TIMER_MODE, i8254_walltimer_sel | TIMER_LATCH);
282         count = (__uint8_t)inb(i8254_walltimer_cntr);           /* get countdown */
283         count |= ((__uint8_t)inb(i8254_walltimer_cntr) << 8);
284         count = -count;                                 /* -> countup */
285         if (count < cputimer_last)                      /* rollover */
286                 i8254_cputimer.base += 0x00010000;
287         ret = i8254_cputimer.base | count;
288         cputimer_last = count;
289         clock_unlock();
290         return(ret);
291 }
292
293 /*
294  * This function is called whenever the system timebase changes, allowing
295  * us to calculate what is needed to convert a system timebase tick 
296  * into an 8254 tick for the interrupt timer.  If we can convert to a
297  * simple shift, multiplication, or division, we do so.  Otherwise 64
298  * bit arithmatic is required every time the interrupt timer is reloaded.
299  */
300 static void
301 i8254_intr_config(struct cputimer_intr *cti, const struct cputimer *timer)
302 {
303     int freq;
304     int div;
305
306     /*
307      * Will a simple divide do the trick?
308      */
309     div = (timer->freq + (cti->freq / 2)) / cti->freq;
310     freq = cti->freq * div;
311
312     if (freq >= timer->freq - 1 && freq <= timer->freq + 1)
313         i8254_cputimer_div = div;
314     else
315         i8254_cputimer_div = 0;
316 }
317
318 /*
319  * Reload for the next timeout.  It is possible for the reload value
320  * to be 0 or negative, indicating that an immediate timer interrupt
321  * is desired.  For now make the minimum 2 ticks.
322  *
323  * We may have to convert from the system timebase to the 8254 timebase.
324  */
325 static void
326 i8254_intr_reload(struct cputimer_intr *cti, sysclock_t reload)
327 {
328     __uint16_t count;
329
330     if (i8254_cputimer_div)
331         reload /= i8254_cputimer_div;
332     else
333         reload = (int64_t)reload * cti->freq / sys_cputimer->freq;
334
335     if ((int)reload < 2)
336         reload = 2;
337
338     clock_lock();
339     if (timer0_running) {
340         outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);     /* count-down timer */
341         count = (__uint8_t)inb(TIMER_CNTR0);            /* lsb */
342         count |= ((__uint8_t)inb(TIMER_CNTR0) << 8);    /* msb */
343         if (reload < count) {
344             outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
345             outb(TIMER_CNTR0, (__uint8_t)reload);       /* lsb */
346             outb(TIMER_CNTR0, (__uint8_t)(reload >> 8)); /* msb */
347         }
348     } else {
349         timer0_running = 1;
350         if (reload > 0xFFFF)
351             reload = 0;         /* full count */
352         outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
353         outb(TIMER_CNTR0, (__uint8_t)reload);           /* lsb */
354         outb(TIMER_CNTR0, (__uint8_t)(reload >> 8));    /* msb */
355     }
356     clock_unlock();
357 }
358
359 /*
360  * DELAY(usec)       - Spin for the specified number of microseconds.
361  * DRIVERSLEEP(usec) - Spin for the specified number of microseconds,
362  *                     but do a thread switch in the loop
363  *
364  * Relies on timer 1 counting down from (cputimer_freq / hz)
365  * Note: timer had better have been programmed before this is first used!
366  */
367 static void
368 DODELAY(int n, int doswitch)
369 {
370         ssysclock_t delta, ticks_left;
371         sysclock_t prev_tick, tick;
372
373 #ifdef DELAYDEBUG
374         int getit_calls = 1;
375         int n1;
376         static int state = 0;
377
378         if (state == 0) {
379                 state = 1;
380                 for (n1 = 1; n1 <= 10000000; n1 *= 10)
381                         DELAY(n1);
382                 state = 2;
383         }
384         if (state == 1)
385                 kprintf("DELAY(%d)...", n);
386 #endif
387         /*
388          * Guard against the timer being uninitialized if we are called
389          * early for console i/o.
390          */
391         if (timer0_state == RELEASED)
392                 i8254_restore();
393
394         /*
395          * Read the counter first, so that the rest of the setup overhead is
396          * counted.  Then calculate the number of hardware timer ticks
397          * required, rounding up to be sure we delay at least the requested
398          * number of microseconds.
399          */
400         prev_tick = sys_cputimer->count();
401         ticks_left = ((u_int)n * (int64_t)sys_cputimer->freq + 999999) /
402                      1000000;
403
404         /*
405          * Loop until done.
406          */
407         while (ticks_left > 0) {
408                 tick = sys_cputimer->count();
409 #ifdef DELAYDEBUG
410                 ++getit_calls;
411 #endif
412                 delta = tick - prev_tick;
413                 prev_tick = tick;
414                 if (delta < 0)
415                         delta = 0;
416                 ticks_left -= delta;
417                 if (doswitch && ticks_left > 0)
418                         lwkt_switch();
419                 cpu_pause();
420         }
421 #ifdef DELAYDEBUG
422         if (state == 1)
423                 kprintf(" %d calls to getit() at %d usec each\n",
424                        getit_calls, (n + 5) / getit_calls);
425 #endif
426 }
427
428 /*
429  * DELAY() never switches
430  */
431 void
432 DELAY(int n)
433 {
434         DODELAY(n, 0);
435 }
436
437 int
438 CHECKTIMEOUT(TOTALDELAY *tdd)
439 {
440         sysclock_t delta;
441         int us;
442
443         if (tdd->started == 0) {
444                if (timer0_state == RELEASED)
445                        i8254_restore();
446                tdd->last_clock = sys_cputimer->count();
447                tdd->started = 1;
448                return(0);
449         }
450         delta = sys_cputimer->count() - tdd->last_clock;
451         us = (u_int64_t)delta * (u_int64_t)1000000 /
452              (u_int64_t)sys_cputimer->freq;
453         tdd->last_clock += (u_int64_t)us * (u_int64_t)sys_cputimer->freq /
454                            1000000;
455         tdd->us -= us;
456         return (tdd->us < 0);
457 }
458
459 /*
460  * DRIVERSLEEP() does not switch if called with a spinlock held or
461  * from a hard interrupt.
462  */
463 void
464 DRIVERSLEEP(int usec)
465 {
466         globaldata_t gd = mycpu;
467
468         if (gd->gd_intr_nesting_level || gd->gd_spinlocks) {
469                 DODELAY(usec, 0);
470         } else {
471                 DODELAY(usec, 1);
472         }
473 }
474
475 static void
476 sysbeepstop(void *chan)
477 {
478         outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */
479         beeping = 0;
480         release_timer2();
481 }
482
483 int
484 sysbeep(int pitch, int period)
485 {
486         if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT))
487                 return(-1);
488         if (sysbeep_enable == 0)
489                 return(-1);
490         /*
491          * Nobody else is using timer2, we do not need the clock lock
492          */
493         outb(TIMER_CNTR2, pitch);
494         outb(TIMER_CNTR2, (pitch>>8));
495         if (!beeping) {
496                 /* enable counter2 output to speaker */
497                 outb(IO_PPI, inb(IO_PPI) | 3);
498                 beeping = period;
499                 callout_reset(&sysbeepstop_ch, period, sysbeepstop, NULL);
500         }
501         return (0);
502 }
503
504 /*
505  * RTC support routines
506  */
507
508 int
509 rtcin(int reg)
510 {
511         u_char val;
512
513         crit_enter();
514         outb(IO_RTC, reg);
515         inb(0x84);
516         val = inb(IO_RTC + 1);
517         inb(0x84);
518         crit_exit();
519         return (val);
520 }
521
522 static __inline void
523 writertc(u_char reg, u_char val)
524 {
525         crit_enter();
526         inb(0x84);
527         outb(IO_RTC, reg);
528         inb(0x84);
529         outb(IO_RTC + 1, val);
530         inb(0x84);              /* XXX work around wrong order in rtcin() */
531         crit_exit();
532 }
533
534 static __inline int
535 readrtc(int port)
536 {
537         return(bcd2bin(rtcin(port)));
538 }
539
540 static u_int
541 calibrate_clocks(void)
542 {
543         u_int64_t old_tsc;
544         u_int tot_count;
545         sysclock_t count, prev_count;
546         int sec, start_sec, timeout;
547
548         if (bootverbose)
549                 kprintf("Calibrating clock(s) ...\n");
550         if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
551                 goto fail;
552         timeout = 100000000;
553
554         /* Read the mc146818A seconds counter. */
555         for (;;) {
556                 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
557                         sec = rtcin(RTC_SEC);
558                         break;
559                 }
560                 if (--timeout == 0)
561                         goto fail;
562         }
563
564         /* Wait for the mC146818A seconds counter to change. */
565         start_sec = sec;
566         for (;;) {
567                 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
568                         sec = rtcin(RTC_SEC);
569                         if (sec != start_sec)
570                                 break;
571                 }
572                 if (--timeout == 0)
573                         goto fail;
574         }
575
576         /* Start keeping track of the i8254 counter. */
577         prev_count = sys_cputimer->count();
578         tot_count = 0;
579
580         if (tsc_present) 
581                 old_tsc = rdtsc();
582         else
583                 old_tsc = 0;            /* shut up gcc */
584
585         /*
586          * Wait for the mc146818A seconds counter to change.  Read the i8254
587          * counter for each iteration since this is convenient and only
588          * costs a few usec of inaccuracy. The timing of the final reads
589          * of the counters almost matches the timing of the initial reads,
590          * so the main cause of inaccuracy is the varying latency from 
591          * inside getit() or rtcin(RTC_STATUSA) to the beginning of the
592          * rtcin(RTC_SEC) that returns a changed seconds count.  The
593          * maximum inaccuracy from this cause is < 10 usec on 486's.
594          */
595         start_sec = sec;
596         for (;;) {
597                 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP))
598                         sec = rtcin(RTC_SEC);
599                 count = sys_cputimer->count();
600                 tot_count += (int)(count - prev_count);
601                 prev_count = count;
602                 if (sec != start_sec)
603                         break;
604                 if (--timeout == 0)
605                         goto fail;
606         }
607
608         /*
609          * Read the cpu cycle counter.  The timing considerations are
610          * similar to those for the i8254 clock.
611          */
612         if (tsc_present) {
613                 tsc_frequency = rdtsc() - old_tsc;
614         }
615
616         if (tsc_present) {
617                 kprintf("TSC%s clock: %llu Hz, ",
618                     tsc_invariant ? " invariant" : "",
619                     (long long)tsc_frequency);
620         }
621         kprintf("i8254 clock: %u Hz\n", tot_count);
622         return (tot_count);
623
624 fail:
625         kprintf("failed, using default i8254 clock of %u Hz\n",
626                 i8254_cputimer.freq);
627         return (i8254_cputimer.freq);
628 }
629
630 static void
631 i8254_restore(void)
632 {
633         timer0_state = ACQUIRED;
634
635         clock_lock();
636
637         /*
638          * Timer0 is our fine-grained variable clock interrupt
639          */
640         outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
641         outb(TIMER_CNTR0, 2);   /* lsb */
642         outb(TIMER_CNTR0, 0);   /* msb */
643         clock_unlock();
644
645         if (!i8254_nointr) {
646                 cputimer_intr_register(&i8254_cputimer_intr);
647                 cputimer_intr_select(&i8254_cputimer_intr, 0);
648         }
649
650         /*
651          * Timer1 or timer2 is our free-running clock, but only if another
652          * has not been selected.
653          */
654         cputimer_register(&i8254_cputimer);
655         cputimer_select(&i8254_cputimer, 0);
656 }
657
658 static void
659 i8254_cputimer_construct(struct cputimer *timer, sysclock_t oldclock)
660 {
661         int which;
662
663         /*
664          * Should we use timer 1 or timer 2 ?
665          */
666         which = 0;
667         TUNABLE_INT_FETCH("hw.i8254.walltimer", &which);
668         if (which != 1 && which != 2)
669                 which = 2;
670
671         switch(which) {
672         case 1:
673                 timer->name = "i8254_timer1";
674                 timer->type = CPUTIMER_8254_SEL1;
675                 i8254_walltimer_sel = TIMER_SEL1;
676                 i8254_walltimer_cntr = TIMER_CNTR1;
677                 timer1_state = ACQUIRED;
678                 break;
679         case 2:
680                 timer->name = "i8254_timer2";
681                 timer->type = CPUTIMER_8254_SEL2;
682                 i8254_walltimer_sel = TIMER_SEL2;
683                 i8254_walltimer_cntr = TIMER_CNTR2;
684                 timer2_state = ACQUIRED;
685                 break;
686         }
687
688         timer->base = (oldclock + 0xFFFF) & ~0xFFFF;
689
690         clock_lock();
691         outb(TIMER_MODE, i8254_walltimer_sel | TIMER_RATEGEN | TIMER_16BIT);
692         outb(i8254_walltimer_cntr, 0);  /* lsb */
693         outb(i8254_walltimer_cntr, 0);  /* msb */
694         outb(IO_PPI, inb(IO_PPI) | 1);  /* bit 0: enable gate, bit 1: spkr */
695         clock_unlock();
696 }
697
698 static void
699 i8254_cputimer_destruct(struct cputimer *timer)
700 {
701         switch(timer->type) {
702         case CPUTIMER_8254_SEL1:
703             timer1_state = RELEASED;
704             break;
705         case CPUTIMER_8254_SEL2:
706             timer2_state = RELEASED;
707             break;
708         default:
709             break;
710         }
711         timer->type = 0;
712 }
713
714 static void
715 rtc_restore(void)
716 {
717         /* Restore all of the RTC's "status" (actually, control) registers. */
718         writertc(RTC_STATUSB, RTCSB_24HR);
719         writertc(RTC_STATUSA, rtc_statusa);
720         writertc(RTC_STATUSB, rtc_statusb);
721 }
722
723 /*
724  * Restore all the timers.
725  *
726  * This function is called to resynchronize our core timekeeping after a
727  * long halt, e.g. from apm_default_resume() and friends.  It is also 
728  * called if after a BIOS call we have detected munging of the 8254.
729  * It is necessary because cputimer_count() counter's delta may have grown
730  * too large for nanouptime() and friends to handle, or (in the case of 8254
731  * munging) might cause the SYSTIMER code to prematurely trigger.
732  */
733 void
734 timer_restore(void)
735 {
736         crit_enter();
737         i8254_restore();                /* restore timer_freq and hz */
738         rtc_restore();                  /* reenable RTC interrupts */
739         crit_exit();
740 }
741
742 /*
743  * Initialize 8254 timer 0 early so that it can be used in DELAY().
744  */
745 void
746 startrtclock(void)
747 {
748         u_int delta, freq;
749
750         /* 
751          * Can we use the TSC?
752          */
753         if (cpu_feature & CPUID_TSC) {
754                 tsc_present = 1;
755                 if ((cpu_vendor_id == CPU_VENDOR_INTEL ||
756                      cpu_vendor_id == CPU_VENDOR_AMD) &&
757                     cpu_exthigh >= 0x80000007) {
758                         u_int regs[4];
759
760                         do_cpuid(0x80000007, regs);
761                         if (regs[3] & 0x100)
762                                 tsc_invariant = 1;
763                 }
764         } else {
765                 tsc_present = 0;
766         }
767
768         /*
769          * Initial RTC state, don't do anything unexpected
770          */
771         writertc(RTC_STATUSA, rtc_statusa);
772         writertc(RTC_STATUSB, RTCSB_24HR);
773
774         /*
775          * Set the 8254 timer0 in TIMER_SWSTROBE mode and cause it to 
776          * generate an interrupt, which we will ignore for now.
777          *
778          * Set the 8254 timer1 in TIMER_RATEGEN mode and load 0x0000
779          * (so it counts a full 2^16 and repeats).  We will use this timer
780          * for our counting.
781          */
782         i8254_restore();
783         freq = calibrate_clocks();
784 #ifdef CLK_CALIBRATION_LOOP
785         if (bootverbose) {
786                 kprintf(
787                 "Press a key on the console to abort clock calibration\n");
788                 while (cncheckc() == -1)
789                         calibrate_clocks();
790         }
791 #endif
792
793         /*
794          * Use the calibrated i8254 frequency if it seems reasonable.
795          * Otherwise use the default, and don't use the calibrated i586
796          * frequency.
797          */
798         delta = freq > i8254_cputimer.freq ? 
799                         freq - i8254_cputimer.freq : i8254_cputimer.freq - freq;
800         if (delta < i8254_cputimer.freq / 100) {
801 #ifndef CLK_USE_I8254_CALIBRATION
802                 if (bootverbose)
803                         kprintf(
804 "CLK_USE_I8254_CALIBRATION not specified - using default frequency\n");
805                 freq = i8254_cputimer.freq;
806 #endif
807                 /*
808                  * NOTE:
809                  * Interrupt timer's freq must be adjusted
810                  * before we change the cuptimer's frequency.
811                  */
812                 i8254_cputimer_intr.freq = freq;
813                 cputimer_set_frequency(&i8254_cputimer, freq);
814         } else {
815                 if (bootverbose)
816                         kprintf(
817                     "%d Hz differs from default of %d Hz by more than 1%%\n",
818                                freq, i8254_cputimer.freq);
819                 tsc_frequency = 0;
820         }
821
822 #ifndef CLK_USE_TSC_CALIBRATION
823         if (tsc_frequency != 0) {
824                 if (bootverbose)
825                         kprintf(
826 "CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n");
827                 tsc_frequency = 0;
828         }
829 #endif
830         if (tsc_present && tsc_frequency == 0) {
831                 /*
832                  * Calibration of the i586 clock relative to the mc146818A
833                  * clock failed.  Do a less accurate calibration relative
834                  * to the i8254 clock.
835                  */
836                 u_int64_t old_tsc = rdtsc();
837
838                 DELAY(1000000);
839                 tsc_frequency = rdtsc() - old_tsc;
840 #ifdef CLK_USE_TSC_CALIBRATION
841                 if (bootverbose) {
842                         kprintf("TSC clock: %llu Hz (Method B)\n",
843                                 tsc_frequency);
844                 }
845 #endif
846         }
847
848         EVENTHANDLER_REGISTER(shutdown_post_sync, resettodr_on_shutdown, NULL, SHUTDOWN_PRI_LAST);
849 }
850
851 /*
852  * Sync the time of day back to the RTC on shutdown, but only if
853  * we have already loaded it and have not crashed.
854  */
855 static void
856 resettodr_on_shutdown(void *arg __unused)
857 {
858         if (rtc_loaded && panicstr == NULL) {
859                 resettodr();
860         }
861 }
862
863 /*
864  * Initialize the time of day register, based on the time base which is, e.g.
865  * from a filesystem.
866  */
867 void
868 inittodr(time_t base)
869 {
870         unsigned long   sec, days;
871         int             year, month;
872         int             y, m;
873         struct timespec ts;
874
875         if (base) {
876                 ts.tv_sec = base;
877                 ts.tv_nsec = 0;
878                 set_timeofday(&ts);
879         }
880
881         /* Look if we have a RTC present and the time is valid */
882         if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
883                 goto wrong_time;
884
885         /* wait for time update to complete */
886         /* If RTCSA_TUP is zero, we have at least 244us before next update */
887         crit_enter();
888         while (rtcin(RTC_STATUSA) & RTCSA_TUP) {
889                 crit_exit();
890                 crit_enter();
891         }
892
893         days = 0;
894 #ifdef USE_RTC_CENTURY
895         year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100;
896 #else
897         year = readrtc(RTC_YEAR) + 1900;
898         if (year < 1970)
899                 year += 100;
900 #endif
901         if (year < 1970) {
902                 crit_exit();
903                 goto wrong_time;
904         }
905         month = readrtc(RTC_MONTH);
906         for (m = 1; m < month; m++)
907                 days += daysinmonth[m-1];
908         if ((month > 2) && LEAPYEAR(year))
909                 days ++;
910         days += readrtc(RTC_DAY) - 1;
911         for (y = 1970; y < year; y++)
912                 days += DAYSPERYEAR + LEAPYEAR(y);
913         sec = ((( days * 24 +
914                   readrtc(RTC_HRS)) * 60 +
915                   readrtc(RTC_MIN)) * 60 +
916                   readrtc(RTC_SEC));
917         /* sec now contains the number of seconds, since Jan 1 1970,
918            in the local time zone */
919
920         sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
921
922         y = (int)(time_second - sec);
923         if (y <= -2 || y >= 2) {
924                 /* badly off, adjust it */
925                 ts.tv_sec = sec;
926                 ts.tv_nsec = 0;
927                 set_timeofday(&ts);
928         }
929         rtc_loaded = 1;
930         crit_exit();
931         return;
932
933 wrong_time:
934         kprintf("Invalid time in real time clock.\n");
935         kprintf("Check and reset the date immediately!\n");
936 }
937
938 /*
939  * Write system time back to RTC
940  */
941 void
942 resettodr(void)
943 {
944         struct timeval tv;
945         unsigned long tm;
946         int m;
947         int y;
948
949         if (disable_rtc_set)
950                 return;
951
952         microtime(&tv);
953         tm = tv.tv_sec;
954
955         crit_enter();
956         /* Disable RTC updates and interrupts. */
957         writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR);
958
959         /* Calculate local time to put in RTC */
960
961         tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
962
963         writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60;    /* Write back Seconds */
964         writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60;    /* Write back Minutes */
965         writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24;    /* Write back Hours   */
966
967         /* We have now the days since 01-01-1970 in tm */
968         writertc(RTC_WDAY, (tm+4)%7);                   /* Write back Weekday */
969         for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y);
970              tm >= m;
971              y++,      m = DAYSPERYEAR + LEAPYEAR(y))
972              tm -= m;
973
974         /* Now we have the years in y and the day-of-the-year in tm */
975         writertc(RTC_YEAR, bin2bcd(y%100));             /* Write back Year    */
976 #ifdef USE_RTC_CENTURY
977         writertc(RTC_CENTURY, bin2bcd(y/100));          /* ... and Century    */
978 #endif
979         for (m = 0; ; m++) {
980                 int ml;
981
982                 ml = daysinmonth[m];
983                 if (m == 1 && LEAPYEAR(y))
984                         ml++;
985                 if (tm < ml)
986                         break;
987                 tm -= ml;
988         }
989
990         writertc(RTC_MONTH, bin2bcd(m + 1));            /* Write back Month   */
991         writertc(RTC_DAY, bin2bcd(tm + 1));             /* Write back Month Day */
992
993         /* Reenable RTC updates and interrupts. */
994         writertc(RTC_STATUSB, rtc_statusb);
995         crit_exit();
996 }
997
998 static int
999 i8254_ioapic_trial(int irq, struct cputimer_intr *cti)
1000 {
1001         sysclock_t base;
1002         long lastcnt;
1003
1004         /*
1005          * Following code assumes the 8254 is the cpu timer,
1006          * so make sure it is.
1007          */
1008         KKASSERT(sys_cputimer == &i8254_cputimer);
1009         KKASSERT(cti == &i8254_cputimer_intr);
1010
1011         lastcnt = get_interrupt_counter(irq, mycpuid);
1012
1013         /*
1014          * Force an 8254 Timer0 interrupt and wait 1/100s for
1015          * it to happen, then see if we got it.
1016          */
1017         kprintf("IOAPIC: testing 8254 interrupt delivery\n");
1018
1019         i8254_intr_reload(cti, 2);
1020         base = sys_cputimer->count();
1021         while (sys_cputimer->count() - base < sys_cputimer->freq / 100)
1022                 ; /* nothing */
1023
1024         if (get_interrupt_counter(irq, mycpuid) - lastcnt == 0)
1025                 return ENOENT;
1026         return 0;
1027 }
1028
1029 /*
1030  * Start both clocks running.  DragonFly note: the stat clock is no longer
1031  * used.  Instead, 8254 based systimers are used for all major clock
1032  * interrupts.
1033  */
1034 static void
1035 i8254_intr_initclock(struct cputimer_intr *cti, boolean_t selected)
1036 {
1037         void *clkdesc = NULL;
1038         int irq = 0, mixed_mode = 0, error;
1039
1040         KKASSERT(mycpuid == 0);
1041         callout_init(&sysbeepstop_ch);
1042
1043         if (!selected && i8254_intr_disable)
1044                 goto nointr;
1045
1046         /*
1047          * The stat interrupt mask is different without the
1048          * statistics clock.  Also, don't set the interrupt
1049          * flag which would normally cause the RTC to generate
1050          * interrupts.
1051          */
1052         rtc_statusb = RTCSB_24HR;
1053
1054         /* Finish initializing 8253 timer 0. */
1055         if (ioapic_enable) {
1056                 irq = machintr_legacy_intr_find(0, INTR_TRIGGER_EDGE,
1057                         INTR_POLARITY_HIGH);
1058                 if (irq < 0) {
1059 mixed_mode_setup:
1060                         error = ioapic_conf_legacy_extint(0);
1061                         if (!error) {
1062                                 irq = machintr_legacy_intr_find(0,
1063                                     INTR_TRIGGER_EDGE, INTR_POLARITY_HIGH);
1064                                 if (irq < 0)
1065                                         error = ENOENT;
1066                         }
1067
1068                         if (error) {
1069                                 if (!selected) {
1070                                         kprintf("IOAPIC: setup mixed mode for "
1071                                                 "irq 0 failed: %d\n", error);
1072                                         goto nointr;
1073                                 } else {
1074                                         panic("IOAPIC: setup mixed mode for "
1075                                               "irq 0 failed: %d\n", error);
1076                                 }
1077                         }
1078                         mixed_mode = 1;
1079                 }
1080                 clkdesc = register_int(irq, clkintr, NULL, "clk",
1081                                        NULL,
1082                                        INTR_EXCL | INTR_CLOCK |
1083                                        INTR_NOPOLL | INTR_MPSAFE |
1084                                        INTR_NOENTROPY, 0);
1085         } else {
1086                 register_int(0, clkintr, NULL, "clk", NULL,
1087                              INTR_EXCL | INTR_CLOCK |
1088                              INTR_NOPOLL | INTR_MPSAFE |
1089                              INTR_NOENTROPY, 0);
1090         }
1091
1092         /* Initialize RTC. */
1093         writertc(RTC_STATUSA, rtc_statusa);
1094         writertc(RTC_STATUSB, RTCSB_24HR);
1095
1096         if (ioapic_enable) {
1097                 error = i8254_ioapic_trial(irq, cti);
1098                 if (error) {
1099                         if (mixed_mode) {
1100                                 if (!selected) {
1101                                         kprintf("IOAPIC: mixed mode for irq %d "
1102                                                 "trial failed: %d\n",
1103                                                 irq, error);
1104                                         goto nointr;
1105                                 } else {
1106                                         panic("IOAPIC: mixed mode for irq %d "
1107                                               "trial failed: %d\n", irq, error);
1108                                 }
1109                         } else {
1110                                 kprintf("IOAPIC: warning 8254 is not connected "
1111                                         "to the correct pin, try mixed mode\n");
1112                                 unregister_int(clkdesc, 0);
1113                                 goto mixed_mode_setup;
1114                         }
1115                 }
1116         }
1117         return;
1118
1119 nointr:
1120         i8254_nointr = 1; /* don't try to register again */
1121         cputimer_intr_deregister(cti);
1122 }
1123
1124 void
1125 setstatclockrate(int newhz)
1126 {
1127         if (newhz == RTC_PROFRATE)
1128                 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF;
1129         else
1130                 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
1131         writertc(RTC_STATUSA, rtc_statusa);
1132 }
1133
1134 #if 0
1135 static unsigned
1136 tsc_get_timecount(struct timecounter *tc)
1137 {
1138         return (rdtsc());
1139 }
1140 #endif
1141
1142 #ifdef KERN_TIMESTAMP
1143 #define KERN_TIMESTAMP_SIZE 16384
1144 static u_long tsc[KERN_TIMESTAMP_SIZE] ;
1145 SYSCTL_OPAQUE(_debug, OID_AUTO, timestamp, CTLFLAG_RD, tsc,
1146         sizeof(tsc), "LU", "Kernel timestamps");
1147 void  
1148 _TSTMP(u_int32_t x)
1149 {
1150         static int i;
1151
1152         tsc[i] = (u_int32_t)rdtsc();
1153         tsc[i+1] = x;
1154         i = i + 2;
1155         if (i >= KERN_TIMESTAMP_SIZE)
1156                 i = 0;
1157         tsc[i] = 0; /* mark last entry */
1158 }
1159 #endif /* KERN_TIMESTAMP */
1160
1161 /*
1162  *
1163  */
1164
1165 static int
1166 hw_i8254_timestamp(SYSCTL_HANDLER_ARGS)
1167 {
1168     sysclock_t count;
1169     __uint64_t tscval;
1170     char buf[32];
1171
1172     crit_enter();
1173     if (sys_cputimer == &i8254_cputimer)
1174         count = sys_cputimer->count();
1175     else
1176         count = 0;
1177     if (tsc_present)
1178         tscval = rdtsc();
1179     else
1180         tscval = 0;
1181     crit_exit();
1182     ksnprintf(buf, sizeof(buf), "%08x %016llx", count, (long long)tscval);
1183     return(SYSCTL_OUT(req, buf, strlen(buf) + 1));
1184 }
1185
1186 static uint64_t         tsc_mpsync_target;
1187
1188 static void
1189 tsc_mpsync_test_remote(void *arg __unused)
1190 {
1191         uint64_t tsc;
1192
1193         tsc = rdtsc();
1194         if (tsc < tsc_mpsync_target)
1195                 tsc_mpsync = 0;
1196 }
1197
1198 static void
1199 tsc_mpsync_test(void)
1200 {
1201         struct globaldata *gd = mycpu;
1202         uint64_t test_end, test_begin;
1203         u_int i;
1204
1205         if (!tsc_invariant) {
1206                 /* Not even invariant TSC */
1207                 return;
1208         }
1209
1210         if (ncpus == 1) {
1211                 /* Only one CPU */
1212                 tsc_mpsync = 1;
1213                 return;
1214         }
1215
1216         if (cpu_vendor_id != CPU_VENDOR_INTEL) {
1217                 /* XXX only Intel works */
1218                 return;
1219         }
1220
1221         kprintf("TSC testing MP synchronization ...\n");
1222         tsc_mpsync = 1;
1223
1224         /* Run test for 100ms */
1225         test_begin = rdtsc();
1226         test_end = test_begin + (tsc_frequency / 10);
1227
1228 #define TSC_TEST_TRYMAX         1000000 /* Make sure we could stop */
1229
1230         for (i = 0; i < TSC_TEST_TRYMAX; ++i) {
1231                 struct lwkt_cpusync cs;
1232
1233                 crit_enter();
1234                 lwkt_cpusync_init(&cs, gd->gd_other_cpus,
1235                     tsc_mpsync_test_remote, NULL);
1236                 lwkt_cpusync_interlock(&cs);
1237                 tsc_mpsync_target = rdtsc();
1238                 cpu_mfence();
1239                 lwkt_cpusync_deinterlock(&cs);
1240                 crit_exit();
1241
1242                 if (!tsc_mpsync) {
1243                         kprintf("TSC is not MP synchronized @%u\n", i);
1244                         break;
1245                 }
1246                 if (tsc_mpsync_target > test_end)
1247                         break;
1248         }
1249
1250 #undef TSC_TEST_TRYMAX
1251
1252         if (tsc_mpsync) {
1253                 if (tsc_mpsync_target == test_begin) {
1254                         kprintf("TSC does not tick?!");
1255                         /* XXX disable TSC? */
1256                         tsc_invariant = 0;
1257                         tsc_mpsync = 0;
1258                         return;
1259                 }
1260
1261                 kprintf("TSC is MP synchronized");
1262                 if (bootverbose)
1263                         kprintf(", after %u tries", i);
1264                 kprintf("\n");
1265         }
1266 }
1267 SYSINIT(tsc_mpsync, SI_BOOT2_FINISH_SMP, SI_ORDER_ANY, tsc_mpsync_test, NULL);
1268
1269 #define TSC_CPUTIMER_FREQMAX    128000000       /* 128Mhz */
1270
1271 static int tsc_cputimer_shift;
1272
1273 static void
1274 tsc_cputimer_construct(struct cputimer *timer, sysclock_t oldclock)
1275 {
1276         timer->base = 0;
1277         timer->base = oldclock - tsc_cputimer_count();
1278 }
1279
1280 static sysclock_t
1281 tsc_cputimer_count(void)
1282 {
1283         uint64_t tsc;
1284
1285         tsc = rdtsc();
1286         tsc >>= tsc_cputimer_shift;
1287
1288         return (tsc + tsc_cputimer.base);
1289 }
1290
1291 static void
1292 tsc_cputimer_register(void)
1293 {
1294         uint64_t freq;
1295         int enable = 1;
1296
1297         if (!tsc_mpsync)
1298                 return;
1299
1300         TUNABLE_INT_FETCH("hw.tsc_cputimer_enable", &enable);
1301         if (!enable)
1302                 return;
1303
1304         freq = tsc_frequency;
1305         while (freq > TSC_CPUTIMER_FREQMAX) {
1306                 freq >>= 1;
1307                 ++tsc_cputimer_shift;
1308         }
1309         kprintf("TSC: cputimer freq %ju, shift %d\n",
1310             (uintmax_t)freq, tsc_cputimer_shift);
1311
1312         tsc_cputimer.freq = freq;
1313
1314         cputimer_register(&tsc_cputimer);
1315         cputimer_select(&tsc_cputimer, 0);
1316 }
1317 SYSINIT(tsc_cputimer_reg, SI_BOOT2_MACHDEP, SI_ORDER_ANY,
1318     tsc_cputimer_register, NULL);
1319
1320 SYSCTL_NODE(_hw, OID_AUTO, i8254, CTLFLAG_RW, 0, "I8254");
1321 SYSCTL_UINT(_hw_i8254, OID_AUTO, freq, CTLFLAG_RD, &i8254_cputimer.freq, 0,
1322             "frequency");
1323 SYSCTL_PROC(_hw_i8254, OID_AUTO, timestamp, CTLTYPE_STRING|CTLFLAG_RD,
1324             0, 0, hw_i8254_timestamp, "A", "");
1325
1326 SYSCTL_INT(_hw, OID_AUTO, tsc_present, CTLFLAG_RD,
1327             &tsc_present, 0, "TSC Available");
1328 SYSCTL_INT(_hw, OID_AUTO, tsc_invariant, CTLFLAG_RD,
1329             &tsc_invariant, 0, "Invariant TSC");
1330 SYSCTL_INT(_hw, OID_AUTO, tsc_mpsync, CTLFLAG_RD,
1331             &tsc_mpsync, 0, "TSC is synchronized across CPUs");
1332 SYSCTL_QUAD(_hw, OID_AUTO, tsc_frequency, CTLFLAG_RD,
1333             &tsc_frequency, 0, "TSC Frequency");