sys/contrib/dev/ath/ath_hal/ar9300/ar9300_freebsd_inc.h

   1 #ifndef __AR9300_FREEBSD_INC_H__
   2 #define __AR9300_FREEBSD_INC_H__
   3
   4 /*
   5  * Define some configuration entries for the AR9300 HAL, so #if entries
   6  * don't have to be removed.
   7  */
   8 #define ATH_DRIVER_SIM          0       /* SIM */
   9 #define ATH_WOW                 0       /* Wake on Wireless */
  10 #define ATH_SUPPORT_MCI         1       /* MCI btcoex */
  11 #define ATH_SUPPORT_AIC         0       /* XXX to do with btcoex? */
  12 #define AH_NEED_TX_DATA_SWAP    0       /* TX descriptor swap? */
  13 #define AH_NEED_RX_DATA_SWAP    0       /* TX descriptor swap? */
  14 #define ATH_SUPPORT_WIRESHARK   0       /* Radiotap HAL code */
  15 #define AH_SUPPORT_WRITE_EEPROM 0       /* EEPROM write support */
  16 #define ATH_SUPPORT_WAPI        0       /* China WAPI support */
  17 #define ATH_ANT_DIV_COMB        1       /* Antenna combining */
  18 #define ATH_SUPPORT_RAW_ADC_CAPTURE     0       /* Raw ADC capture support */
  19 #define ATH_TRAFFIC_FAST_RECOVER        0       /* XXX not sure yet */
  20 #define ATH_SUPPORT_SPECTRAL    0       /* Spectral scan support */
  21 #define ATH_BT_COEX             1       /* Enable BT Coex code */
  22 #define ATH_PCIE_ERROR_MONITOR  0       /* ??? */
  23 #define ATH_SUPPORT_CRDC        0       /* ??? */
  24 #define ATH_LOW_POWER_ENABLE    0       /* ??? */
  25 #define ATH_SUPPORT_VOW_DCS     0       /* Video over wireless dynamic channel select */
  26 #define REMOVE_PKT_LOG          1
  27 #define ATH_VC_MODE_PROXY_STA   0       /* Azimuth + proxysta? */
  28 #define ATH_GEN_RANDOMNESS      0
  29 #define __PKT_SERIOUS_ERRORS__  0
  30 #define HAL_INTR_REFCOUNT_DISABLE       1       /* XXX wha? And atomics in the HAL!? */
  31 #define UMAC_SUPPORT_SMARTANTENNA       0       /* sigh.. */
  32 #define ATH_SMARTANTENNA_DISABLE_JTAG   0
  33 #define ATH_SUPPORT_WIRESHARK           0
  34 #define ATH_SUPPORT_WIFIPOS     0
  35 #define ATH_SUPPORT_PAPRD       1
  36 #define ATH_SUPPORT_TxBF        0
  37 #define AH_PRIVATE_DIAG         1
  38
  39 /* XXX need to reverify these; they came in with qcamain */
  40 #define ATH_SUPPORT_FAST_CC 0
  41 #define ATH_SUPPORT_RADIO_RETENTION 0
  42 #define ATH_SUPPORT_CAL_REUSE 0
  43
  44 #define ATH_WOW_OFFLOAD 0
  45
  46 #define HAL_NO_INTERSPERSED_READS
  47
  48 /* Required or things will probe/attach, but not work right */
  49 #define AH_SUPPORT_OSPREY               1
  50 #define AH_SUPPORT_POSEIDON             1
  51 #define AH_SUPPORT_AR9300               1
  52
  53 /* These are the embedded boards; we don't currently support these */
  54 #ifdef  AH_SUPPORT_AR9330
  55 #define AH_SUPPORT_HORNET               1
  56 #endif  /* AH_SUPPORT_AR9330 */
  57 #ifdef  AH_SUPPORT_AR9340
  58 #define AH_SUPPORT_WASP                 1
  59 #endif  /* AH_SUPPORT_AR9340 */
  60 //#define AH_SUPPORT_SCORPION             1
  61 #define FIX_NOISE_FLOOR                 1
  62
  63 /* XXX this needs to be removed! No atomics in the HAL! */
  64 typedef int os_atomic_t;                /* XXX shouldn't do atomics here! */
  65 #define OS_ATOMIC_INC(a)        (*a)++
  66 #define OS_ATOMIC_DEC(a)        (*a)--
  67
  68 /*
  69  * HAL definitions which aren't necessarily for public consumption (yet).
  70  */
  71
  72 enum {
  73         HAL_TRUE_CHIP = 1,
  74         HAL_MAC_TO_MAC_EMU,
  75         HAL_MAC_BB_EMU,
  76 };
  77
  78 /* HAL_KEY_TYPE */
  79 enum {
  80         HAL_KEY_PROXY_STA_MASK = 0x10,
  81 };
  82
  83 typedef enum {
  84         HAL_SMPS_DEFAULT = 0,
  85         HAL_SMPS_SW_CTRL_LOW_PWR,       /* Software control, low power setting */
  86         HAL_SMPS_SW_CTRL_HIGH_PWR,      /* Software control, high power setting */
  87         HAL_SMPS_HW_CTRL                /* Hardware Control */
  88 } HAL_SMPS_MODE;
  89
  90 /*
  91  * Green Tx, Based on different RSSI of Received Beacon thresholds,
  92  * using different tx power by modified register tx power related values.
  93  * The thresholds are decided by system team.
  94  */
  95 #define GreenTX_thres1  56      /* in dB */
  96 #define GreenTX_thres2  36      /* in dB */
  97
  98 typedef enum {
  99         HAL_RSSI_TX_POWER_NONE          = 0,
 100         HAL_RSSI_TX_POWER_SHORT         = 1,    /* short range, reduce OB/DB bias current and disable PAL */
 101         HAL_RSSI_TX_POWER_MIDDLE        = 2,    /* middle range, reduce OB/DB bias current and PAL is enabled */
 102         HAL_RSSI_TX_POWER_LONG          = 3,    /* long range, orig. OB/DB bias current and PAL is enabled */
 103 } HAL_RSSI_TX_POWER;
 104
 105 struct  dfs_pulse {
 106         u_int32_t       rp_numpulses    ;       /* Num of pulses in radar burst */
 107         u_int32_t       rp_pulsedur;            /* Duration of each pulse in usecs */
 108         u_int32_t       rp_pulsefreq;           /* Frequency of pulses in burst */
 109         u_int32_t       rp_max_pulsefreq;       /* Frequency of pulses in burst */
 110         u_int32_t       rp_patterntype;         /* fixed or variable pattern type*/
 111         u_int32_t       rp_pulsevar;            /* Time variation of pulse duration for
 112                                                           matched filter (single-sided) in usecs */
 113         u_int32_t       rp_threshold;           /* Threshold for MF output to indicate
 114                                                           radar match */
 115         u_int32_t       rp_mindur;              /* Min pulse duration to be considered for
 116                                                           this pulse type */
 117         u_int32_t       rp_maxdur;              /* Max pusle duration to be considered for
 118                                                           this pulse type */
 119         u_int32_t       rp_rssithresh;          /* Minimum rssi to be considered a radar pulse */
 120         u_int32_t       rp_meanoffset;          /* Offset for timing adjustment */
 121         int32_t         rp_rssimargin;          /* rssi threshold margin. In Turbo Mode HW reports rssi 3dBm */
 122                                                        /* lower than in non TURBO mode.
 123                                                           This will be used to offset that diff.*/
 124         u_int32_t       rp_ignore_pri_window;
 125         u_int32_t       rp_pulseid;             /* Unique ID for identifying filter */
 126 };
 127
 128 struct  dfs_staggered_pulse {
 129        u_int32_t       rp_numpulses;           /* Num of pulses in radar burst */
 130        u_int32_t       rp_pulsedur;            /* Duration of each pulse in usecs */
 131        u_int32_t       rp_min_pulsefreq;       /* Frequency of pulses in burst */
 132        u_int32_t       rp_max_pulsefreq;       /* Frequency of pulses in burst */
 133        u_int32_t       rp_patterntype;         /* fixed or variable pattern type*/
 134        u_int32_t       rp_pulsevar;            /* Time variation of pulse duration for
 135                                                    matched filter (single-sided) in usecs */
 136        u_int32_t       rp_threshold;           /* Thershold for MF output to indicateC
 137                                                   radar match */
 138        u_int32_t       rp_mindur;              /* Min pulse duration to be considered for
 139                                                   this pulse type */
 140        u_int32_t       rp_maxdur;              /* Max pusle duration to be considered for
 141                                                   this pulse type */
 142        u_int32_t       rp_rssithresh;          /* Minimum rssi to be considered a radar pulse */
 143        u_int32_t       rp_meanoffset;          /* Offset for timing adjustment */
 144        int32_t         rp_rssimargin;          /* rssi threshold margin. In Turbo Mode HW reports rssi 3dBm */
 145                                                /* lower than in non TURBO mode. This will be used to offset that diff.*/
 146        u_int32_t       rp_pulseid;             /* Unique ID for identifying filter */
 147        };
 148
 149 struct dfs_bin5pulse {
 150         u_int32_t       b5_threshold;          /* Number of bin5 pulses to indicate detection */
 151         u_int32_t       b5_mindur;             /* Min duration for a bin5 pulse */
 152         u_int32_t       b5_maxdur;             /* Max duration for a bin5 pulse */
 153         u_int32_t       b5_timewindow;         /* Window over which to count bin5 pulses */
 154         u_int32_t       b5_rssithresh;         /* Min rssi to be considered a pulse */
 155         u_int32_t       b5_rssimargin;         /* rssi threshold margin. In Turbo Mode HW reports rssi 3dB */
 156 };
 157
 158 #if 0
 159 /* SPECTRAL SCAN defines begin */
 160 typedef struct {
 161         u_int16_t       ss_fft_period;  /* Skip interval for FFT reports */
 162         u_int16_t       ss_period;      /* Spectral scan period */
 163         u_int16_t       ss_count;       /* # of reports to return from ss_active */
 164         u_int16_t       ss_short_report;/* Set to report ony 1 set of FFT results */
 165         u_int8_t        radar_bin_thresh_sel;
 166         u_int16_t       ss_spectral_pri;                /* are we doing a noise power cal ? */
 167         int8_t          ss_nf_cal[AH_MAX_CHAINS*2];     /* nf calibrated values for ctl+ext from eeprom */
 168         int8_t          ss_nf_pwr[AH_MAX_CHAINS*2];     /* nf pwr values for ctl+ext from eeprom */
 169         int32_t         ss_nf_temp_data;                /* temperature data taken during nf scan */
 170 } HAL_SPECTRAL_PARAM;
 171 #define HAL_SPECTRAL_PARAM_NOVAL        0xFFFF
 172 #define HAL_SPECTRAL_PARAM_ENABLE       0x8000  /* Enable/Disable if applicable */
 173 #endif
 174
 175 /*
 176  * Noise power data definitions
 177  * units are: 4 x dBm - NOISE_PWR_DATA_OFFSET (e.g. -25 = (-25/4 - 90) = -96.25 dBm)
 178  * range (for 6 signed bits) is (-32 to 31) + offset => -122dBm to -59dBm
 179  * resolution (2 bits) is 0.25dBm
 180  */
 181 #define NOISE_PWR_DATA_OFFSET           -90 /* dbm - all pwr report data is represented offset by this */
 182 #define INT_2_NOISE_PWR_DBM(_p)         (((_p) - NOISE_PWR_DATA_OFFSET) << 2)
 183 #define NOISE_PWR_DBM_2_INT(_p)         ((((_p) + 3) >> 2) + NOISE_PWR_DATA_OFFSET)
 184 #define NOISE_PWR_DBM_2_DEC(_p)         (((-(_p)) & 3) * 25)
 185 #define N2DBM(_x,_y)                    ((((_x) - NOISE_PWR_DATA_OFFSET) << 2) - (_y)/25)
 186 /* SPECTRAL SCAN defines end */
 187
 188 typedef struct halvowstats {
 189     u_int32_t   tx_frame_count;
 190     u_int32_t   rx_frame_count;
 191     u_int32_t   rx_clear_count;
 192     u_int32_t   cycle_count;
 193     u_int32_t   ext_cycle_count;
 194 } HAL_VOWSTATS;
 195
 196 #define HAL_BT_COEX_FLAG_LOW_ACK_PWR        0x00000001
 197 #define HAL_BT_COEX_FLAG_LOWER_TX_PWR       0x00000002
 198 #define HAL_BT_COEX_FLAG_ANT_DIV_ALLOW      0x00000004    /* Check Rx Diversity is allowed */
 199 #define HAL_BT_COEX_FLAG_ANT_DIV_ENABLE     0x00000008    /* Check Diversity is on or off */
 200 #define HAL_BT_COEX_FLAG_MCI_MAX_TX_PWR     0x00000010
 201 #define HAL_BT_COEX_FLAG_MCI_FTP_STOMP_RX   0x00000020
 202
 203 /*
 204  * Weight table configurations.
 205  */
 206 #define AR9300_BT_WGHT                     0xcccc4444
 207 #define AR9300_STOMP_ALL_WLAN_WGHT0        0xfffffff0
 208 #define AR9300_STOMP_ALL_WLAN_WGHT1        0xfffffff0
 209 #define AR9300_STOMP_LOW_WLAN_WGHT0        0x88888880
 210 #define AR9300_STOMP_LOW_WLAN_WGHT1        0x88888880
 211 #define AR9300_STOMP_NONE_WLAN_WGHT0       0x00000000
 212 #define AR9300_STOMP_NONE_WLAN_WGHT1       0x00000000
 213 #define AR9300_STOMP_ALL_FORCE_WLAN_WGHT0  0xffffffff   // Stomp BT even when WLAN is idle
 214 #define AR9300_STOMP_ALL_FORCE_WLAN_WGHT1  0xffffffff
 215 #define AR9300_STOMP_LOW_FORCE_WLAN_WGHT0  0x88888888   // Stomp BT even when WLAN is idle
 216 #define AR9300_STOMP_LOW_FORCE_WLAN_WGHT1  0x88888888
 217
 218 #define JUPITER_STOMP_ALL_WLAN_WGHT0       0x01017d01
 219 #define JUPITER_STOMP_ALL_WLAN_WGHT1       0x41414101
 220 #define JUPITER_STOMP_ALL_WLAN_WGHT2       0x41414101
 221 #define JUPITER_STOMP_ALL_WLAN_WGHT3       0x41414141
 222 #define JUPITER_STOMP_LOW_WLAN_WGHT0       0x01017d01
 223 #define JUPITER_STOMP_LOW_WLAN_WGHT1       0x3b3b3b01
 224 #define JUPITER_STOMP_LOW_WLAN_WGHT2       0x3b3b3b01
 225 #define JUPITER_STOMP_LOW_WLAN_WGHT3       0x3b3b3b3b
 226 #define JUPITER_STOMP_LOW_FTP_WLAN_WGHT0   0x01017d01
 227 #define JUPITER_STOMP_LOW_FTP_WLAN_WGHT1   0x013b0101
 228 #define JUPITER_STOMP_LOW_FTP_WLAN_WGHT2   0x3b3b0101
 229 #define JUPITER_STOMP_LOW_FTP_WLAN_WGHT3   0x3b3b013b
 230 #define JUPITER_STOMP_NONE_WLAN_WGHT0      0x01017d01
 231 #define JUPITER_STOMP_NONE_WLAN_WGHT1      0x01010101
 232 #define JUPITER_STOMP_NONE_WLAN_WGHT2      0x01010101
 233 #define JUPITER_STOMP_NONE_WLAN_WGHT3      0x01010101
 234 #define JUPITER_STOMP_ALL_FORCE_WLAN_WGHT0 0x01017d7d
 235 #define JUPITER_STOMP_ALL_FORCE_WLAN_WGHT1 0x7d7d7d01
 236 #define JUPITER_STOMP_ALL_FORCE_WLAN_WGHT2 0x7d7d7d7d
 237 #define JUPITER_STOMP_ALL_FORCE_WLAN_WGHT3 0x7d7d7d7d
 238 #define JUPITER_STOMP_LOW_FORCE_WLAN_WGHT0 0x01013b3b
 239 #define JUPITER_STOMP_LOW_FORCE_WLAN_WGHT1 0x3b3b3b01
 240 #define JUPITER_STOMP_LOW_FORCE_WLAN_WGHT2 0x3b3b3b3b
 241 #define JUPITER_STOMP_LOW_FORCE_WLAN_WGHT3 0x3b3b3b3b
 242
 243 #define MCI_CONCUR_TX_WLAN_WGHT1_MASK      0xff000000
 244 #define MCI_CONCUR_TX_WLAN_WGHT1_MASK_S    24
 245 #define MCI_CONCUR_TX_WLAN_WGHT2_MASK      0x00ff0000
 246 #define MCI_CONCUR_TX_WLAN_WGHT2_MASK_S    16
 247 #define MCI_CONCUR_TX_WLAN_WGHT3_MASK      0x000000ff
 248 #define MCI_CONCUR_TX_WLAN_WGHT3_MASK_S    0
 249 #define MCI_CONCUR_TX_WLAN_WGHT3_MASK2     0x00ff0000
 250 #define MCI_CONCUR_TX_WLAN_WGHT3_MASK2_S   16
 251
 252 #define MCI_QUERY_BT_VERSION_VERBOSE            0
 253 #define MCI_LINKID_INDEX_MGMT_PENDING           1
 254
 255 #define HAL_MCI_FLAG_DISABLE_TIMESTAMP      0x00000001      /* Disable time stamp */
 256
 257 typedef enum mci_message_header {
 258     MCI_LNA_CTRL     = 0x10,        /* len = 0 */
 259     MCI_CONT_NACK    = 0x20,        /* len = 0 */
 260     MCI_CONT_INFO    = 0x30,        /* len = 4 */
 261     MCI_CONT_RST     = 0x40,        /* len = 0 */
 262     MCI_SCHD_INFO    = 0x50,        /* len = 16 */
 263     MCI_CPU_INT      = 0x60,        /* len = 4 */
 264     MCI_SYS_WAKING   = 0x70,        /* len = 0 */
 265     MCI_GPM          = 0x80,        /* len = 16 */
 266     MCI_LNA_INFO     = 0x90,        /* len = 1 */
 267     MCI_LNA_STATE    = 0x94,
 268     MCI_LNA_TAKE     = 0x98,
 269     MCI_LNA_TRANS    = 0x9c,
 270     MCI_SYS_SLEEPING = 0xa0,        /* len = 0 */
 271     MCI_REQ_WAKE     = 0xc0,        /* len = 0 */
 272     MCI_DEBUG_16     = 0xfe,        /* len = 2 */
 273     MCI_REMOTE_RESET = 0xff         /* len = 16 */
 274 } MCI_MESSAGE_HEADER;
 275
 276 /* Default remote BT device MCI COEX version */
 277 #define MCI_GPM_COEX_MAJOR_VERSION_DEFAULT  3
 278 #define MCI_GPM_COEX_MINOR_VERSION_DEFAULT  0
 279 /* Local WLAN MCI COEX version */
 280 #define MCI_GPM_COEX_MAJOR_VERSION_WLAN     3
 281 #define MCI_GPM_COEX_MINOR_VERSION_WLAN     0
 282
 283 typedef enum mci_gpm_subtype {
 284     MCI_GPM_BT_CAL_REQ      = 0,
 285     MCI_GPM_BT_CAL_GRANT    = 1,
 286     MCI_GPM_BT_CAL_DONE     = 2,
 287     MCI_GPM_WLAN_CAL_REQ    = 3,
 288     MCI_GPM_WLAN_CAL_GRANT  = 4,
 289     MCI_GPM_WLAN_CAL_DONE   = 5,
 290     MCI_GPM_COEX_AGENT      = 0x0C,
 291     MCI_GPM_RSVD_PATTERN    = 0xFE,
 292     MCI_GPM_RSVD_PATTERN32  = 0xFEFEFEFE,
 293     MCI_GPM_BT_DEBUG        = 0xFF
 294 } MCI_GPM_SUBTYPE_T;
 295
 296 typedef enum mci_gpm_coex_opcode {
 297     MCI_GPM_COEX_VERSION_QUERY      = 0,
 298     MCI_GPM_COEX_VERSION_RESPONSE   = 1,
 299     MCI_GPM_COEX_STATUS_QUERY       = 2,
 300     MCI_GPM_COEX_HALT_BT_GPM        = 3,
 301     MCI_GPM_COEX_WLAN_CHANNELS      = 4,
 302     MCI_GPM_COEX_BT_PROFILE_INFO    = 5,
 303     MCI_GPM_COEX_BT_STATUS_UPDATE   = 6,
 304     MCI_GPM_COEX_BT_UPDATE_FLAGS    = 7
 305 } MCI_GPM_COEX_OPCODE_T;
 306
 307 typedef enum mci_gpm_coex_query_type {
 308     /* WLAN information */
 309     MCI_GPM_COEX_QUERY_WLAN_ALL_INFO    = 0x01,
 310     /* BT information */
 311     MCI_GPM_COEX_QUERY_BT_ALL_INFO      = 0x01,
 312     MCI_GPM_COEX_QUERY_BT_TOPOLOGY      = 0x02,
 313     MCI_GPM_COEX_QUERY_BT_DEBUG         = 0x04
 314 } MCI_GPM_COEX_QUERY_TYPE_T;
 315
 316 typedef enum mci_gpm_coex_halt_bt_gpm {
 317     MCI_GPM_COEX_BT_GPM_UNHALT      = 0,
 318     MCI_GPM_COEX_BT_GPM_HALT        = 1
 319 } MCI_GPM_COEX_HALT_BT_GPM_T;
 320
 321 typedef enum mci_gpm_coex_profile_type {
 322     MCI_GPM_COEX_PROFILE_UNKNOWN    = 0,
 323     MCI_GPM_COEX_PROFILE_RFCOMM     = 1,
 324     MCI_GPM_COEX_PROFILE_A2DP       = 2,
 325     MCI_GPM_COEX_PROFILE_HID        = 3,
 326     MCI_GPM_COEX_PROFILE_BNEP       = 4,
 327     MCI_GPM_COEX_PROFILE_VOICE      = 5,
 328     MCI_GPM_COEX_PROFILE_MAX
 329 } MCI_GPM_COEX_PROFILE_TYPE_T;
 330
 331 typedef enum mci_gpm_coex_profile_state {
 332     MCI_GPM_COEX_PROFILE_STATE_END      = 0,
 333     MCI_GPM_COEX_PROFILE_STATE_START    = 1
 334 } MCI_GPM_COEX_PROFILE_STATE_T;
 335
 336 typedef enum mci_gpm_coex_profile_role {
 337     MCI_GPM_COEX_PROFILE_SLAVE      = 0,
 338     MCI_GPM_COEX_PROFILE_MASTER     = 1
 339 } MCI_GPM_COEX_PROFILE_ROLE_T;
 340
 341 typedef enum mci_gpm_coex_bt_status_type {
 342     MCI_GPM_COEX_BT_NONLINK_STATUS  = 0,
 343     MCI_GPM_COEX_BT_LINK_STATUS     = 1
 344 } MCI_GPM_COEX_BT_STATUS_TYPE_T;
 345
 346 typedef enum mci_gpm_coex_bt_status_state {
 347     MCI_GPM_COEX_BT_NORMAL_STATUS   = 0,
 348     MCI_GPM_COEX_BT_CRITICAL_STATUS = 1
 349 } MCI_GPM_COEX_BT_STATUS_STATE_T;
 350
 351 #define MCI_GPM_INVALID_PROFILE_HANDLE  0xff
 352
 353 typedef enum mci_gpm_coex_bt_updata_flags_op {
 354     MCI_GPM_COEX_BT_FLAGS_READ          = 0x00,
 355     MCI_GPM_COEX_BT_FLAGS_SET           = 0x01,
 356     MCI_GPM_COEX_BT_FLAGS_CLEAR         = 0x02
 357 } MCI_GPM_COEX_BT_FLAGS_OP_T;
 358
 359 /* MCI GPM/Coex opcode/type definitions */
 360 enum {
 361     MCI_GPM_COEX_W_GPM_PAYLOAD      = 1,
 362     MCI_GPM_COEX_B_GPM_TYPE         = 4,
 363     MCI_GPM_COEX_B_GPM_OPCODE       = 5,
 364     /* MCI_GPM_WLAN_CAL_REQ, MCI_GPM_WLAN_CAL_DONE */
 365     MCI_GPM_WLAN_CAL_W_SEQUENCE     = 2,
 366     /* MCI_GPM_COEX_VERSION_QUERY */
 367     /* MCI_GPM_COEX_VERSION_RESPONSE */
 368     MCI_GPM_COEX_B_MAJOR_VERSION    = 6,
 369     MCI_GPM_COEX_B_MINOR_VERSION    = 7,
 370     /* MCI_GPM_COEX_STATUS_QUERY */
 371     MCI_GPM_COEX_B_BT_BITMAP        = 6,
 372     MCI_GPM_COEX_B_WLAN_BITMAP      = 7,
 373     /* MCI_GPM_COEX_HALT_BT_GPM */
 374     MCI_GPM_COEX_B_HALT_STATE       = 6,
 375     /* MCI_GPM_COEX_WLAN_CHANNELS */
 376     MCI_GPM_COEX_B_CHANNEL_MAP      = 6,
 377     /* MCI_GPM_COEX_BT_PROFILE_INFO */
 378     MCI_GPM_COEX_B_PROFILE_TYPE     = 6,
 379     MCI_GPM_COEX_B_PROFILE_LINKID   = 7,
 380     MCI_GPM_COEX_B_PROFILE_STATE    = 8,
 381     MCI_GPM_COEX_B_PROFILE_ROLE     = 9,
 382     MCI_GPM_COEX_B_PROFILE_RATE     = 10,
 383     MCI_GPM_COEX_B_PROFILE_VOTYPE   = 11,
 384     MCI_GPM_COEX_H_PROFILE_T        = 12,
 385     MCI_GPM_COEX_B_PROFILE_W        = 14,
 386     MCI_GPM_COEX_B_PROFILE_A        = 15,
 387     /* MCI_GPM_COEX_BT_STATUS_UPDATE */
 388     MCI_GPM_COEX_B_STATUS_TYPE      = 6,
 389     MCI_GPM_COEX_B_STATUS_LINKID    = 7,
 390     MCI_GPM_COEX_B_STATUS_STATE     = 8,
 391     /* MCI_GPM_COEX_BT_UPDATE_FLAGS */
 392     MCI_GPM_COEX_B_BT_FLAGS_OP      = 10,
 393     MCI_GPM_COEX_W_BT_FLAGS         = 6
 394 };
 395
 396 #define MCI_GPM_RECYCLE(_p_gpm) \
 397     {                           \
 398         *(((u_int32_t *)(_p_gpm)) + MCI_GPM_COEX_W_GPM_PAYLOAD) = MCI_GPM_RSVD_PATTERN32; \
 399     }
 400 #define MCI_GPM_TYPE(_p_gpm)    \
 401     (*(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) & 0xff)
 402 #define MCI_GPM_OPCODE(_p_gpm)  \
 403     (*(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_OPCODE) & 0xff)
 404
 405 #define MCI_GPM_SET_CAL_TYPE(_p_gpm, _cal_type)             \
 406     {                                                       \
 407         *(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) = (_cal_type) & 0xff; \
 408     }
 409 #define MCI_GPM_SET_TYPE_OPCODE(_p_gpm, _type, _opcode)     \
 410     {                                                       \
 411         *(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_TYPE) = (_type) & 0xff;     \
 412         *(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_GPM_OPCODE) = (_opcode) & 0xff;   \
 413     }
 414 #define MCI_GPM_IS_CAL_TYPE(_type) ((_type) <= MCI_GPM_WLAN_CAL_DONE)
 415
 416 #define MCI_NUM_BT_CHANNELS     79
 417
 418 #define MCI_GPM_SET_CHANNEL_BIT(_p_gpm, _bt_chan)                   \
 419     {                                                               \
 420         if (_bt_chan < MCI_NUM_BT_CHANNELS) {                       \
 421             *(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_CHANNEL_MAP + \
 422                 (_bt_chan / 8)) |= 1 << (_bt_chan & 7);             \
 423         }                                                           \
 424     }
 425
 426 #define MCI_GPM_CLR_CHANNEL_BIT(_p_gpm, _bt_chan)                   \
 427     {                                                               \
 428         if (_bt_chan < MCI_NUM_BT_CHANNELS) {                       \
 429             *(((u_int8_t *)(_p_gpm)) + MCI_GPM_COEX_B_CHANNEL_MAP + \
 430                 (_bt_chan / 8)) &= ~(1 << (_bt_chan & 7));          \
 431         }                                                           \
 432     }
 433
 434 #define HAL_MCI_INTERRUPT_SW_MSG_DONE            0x00000001
 435 #define HAL_MCI_INTERRUPT_CPU_INT_MSG            0x00000002
 436 #define HAL_MCI_INTERRUPT_RX_CHKSUM_FAIL         0x00000004
 437 #define HAL_MCI_INTERRUPT_RX_INVALID_HDR         0x00000008
 438 #define HAL_MCI_INTERRUPT_RX_HW_MSG_FAIL         0x00000010
 439 #define HAL_MCI_INTERRUPT_RX_SW_MSG_FAIL         0x00000020
 440 #define HAL_MCI_INTERRUPT_TX_HW_MSG_FAIL         0x00000080
 441 #define HAL_MCI_INTERRUPT_TX_SW_MSG_FAIL         0x00000100
 442 #define HAL_MCI_INTERRUPT_RX_MSG                 0x00000200
 443 #define HAL_MCI_INTERRUPT_REMOTE_SLEEP_UPDATE    0x00000400
 444 #define HAL_MCI_INTERRUPT_CONT_INFO_TIMEOUT      0x80000000
 445 #define HAL_MCI_INTERRUPT_MSG_FAIL_MASK ( HAL_MCI_INTERRUPT_RX_HW_MSG_FAIL | \
 446                                           HAL_MCI_INTERRUPT_RX_SW_MSG_FAIL | \
 447                                           HAL_MCI_INTERRUPT_TX_HW_MSG_FAIL | \
 448                                           HAL_MCI_INTERRUPT_TX_SW_MSG_FAIL )
 449
 450 #define HAL_MCI_INTERRUPT_RX_MSG_REMOTE_RESET    0x00000001
 451 #define HAL_MCI_INTERRUPT_RX_MSG_LNA_CONTROL     0x00000002
 452 #define HAL_MCI_INTERRUPT_RX_MSG_CONT_NACK       0x00000004
 453 #define HAL_MCI_INTERRUPT_RX_MSG_CONT_INFO       0x00000008
 454 #define HAL_MCI_INTERRUPT_RX_MSG_CONT_RST        0x00000010
 455 #define HAL_MCI_INTERRUPT_RX_MSG_SCHD_INFO       0x00000020
 456 #define HAL_MCI_INTERRUPT_RX_MSG_CPU_INT         0x00000040
 457 #define HAL_MCI_INTERRUPT_RX_MSG_GPM             0x00000100
 458 #define HAL_MCI_INTERRUPT_RX_MSG_LNA_INFO        0x00000200
 459 #define HAL_MCI_INTERRUPT_RX_MSG_SYS_SLEEPING    0x00000400
 460 #define HAL_MCI_INTERRUPT_RX_MSG_SYS_WAKING      0x00000800
 461 #define HAL_MCI_INTERRUPT_RX_MSG_REQ_WAKE        0x00001000
 462 #define HAL_MCI_INTERRUPT_RX_MSG_MONITOR         (HAL_MCI_INTERRUPT_RX_MSG_LNA_CONTROL | \
 463                                                   HAL_MCI_INTERRUPT_RX_MSG_LNA_INFO    | \
 464                                                   HAL_MCI_INTERRUPT_RX_MSG_CONT_NACK   | \
 465                                                   HAL_MCI_INTERRUPT_RX_MSG_CONT_INFO   | \
 466                                                   HAL_MCI_INTERRUPT_RX_MSG_CONT_RST)
 467
 468 typedef enum mci_bt_state {
 469     MCI_BT_SLEEP,
 470     MCI_BT_AWAKE,
 471     MCI_BT_CAL_START,
 472     MCI_BT_CAL
 473 } MCI_BT_STATE_T;
 474
 475 /* Type of state query */
 476 typedef enum mci_state_type {
 477     HAL_MCI_STATE_ENABLE,
 478     HAL_MCI_STATE_INIT_GPM_OFFSET,
 479     HAL_MCI_STATE_NEXT_GPM_OFFSET,
 480     HAL_MCI_STATE_LAST_GPM_OFFSET,
 481     HAL_MCI_STATE_BT,
 482     HAL_MCI_STATE_SET_BT_SLEEP,
 483     HAL_MCI_STATE_SET_BT_AWAKE,
 484     HAL_MCI_STATE_SET_BT_CAL_START,
 485     HAL_MCI_STATE_SET_BT_CAL,
 486     HAL_MCI_STATE_LAST_SCHD_MSG_OFFSET,
 487     HAL_MCI_STATE_REMOTE_SLEEP,
 488     HAL_MCI_STATE_CONT_RSSI_POWER,
 489     HAL_MCI_STATE_CONT_PRIORITY,
 490     HAL_MCI_STATE_CONT_TXRX,
 491     HAL_MCI_STATE_RESET_REQ_WAKE,
 492     HAL_MCI_STATE_SEND_WLAN_COEX_VERSION,
 493     HAL_MCI_STATE_SET_BT_COEX_VERSION,
 494     HAL_MCI_STATE_SEND_WLAN_CHANNELS,
 495     HAL_MCI_STATE_SEND_VERSION_QUERY,
 496     HAL_MCI_STATE_SEND_STATUS_QUERY,
 497     HAL_MCI_STATE_NEED_FLUSH_BT_INFO,
 498     HAL_MCI_STATE_SET_CONCUR_TX_PRI,
 499     HAL_MCI_STATE_RECOVER_RX,
 500     HAL_MCI_STATE_NEED_FTP_STOMP,
 501     HAL_MCI_STATE_NEED_TUNING,
 502     HAL_MCI_STATE_SHARED_CHAIN_CONCUR_TX,
 503     HAL_MCI_STATE_DEBUG,
 504     HAL_MCI_STATE_MAX
 505 } HAL_MCI_STATE_TYPE;
 506
 507 #define HAL_MCI_STATE_DEBUG_REQ_BT_DEBUG    1
 508
 509 #define HAL_MCI_BT_MCI_FLAGS_UPDATE_CORR          0x00000002
 510 #define HAL_MCI_BT_MCI_FLAGS_UPDATE_HDR           0x00000004
 511 #define HAL_MCI_BT_MCI_FLAGS_UPDATE_PLD           0x00000008
 512 #define HAL_MCI_BT_MCI_FLAGS_LNA_CTRL             0x00000010
 513 #define HAL_MCI_BT_MCI_FLAGS_DEBUG                0x00000020
 514 #define HAL_MCI_BT_MCI_FLAGS_SCHED_MSG            0x00000040
 515 #define HAL_MCI_BT_MCI_FLAGS_CONT_MSG             0x00000080
 516 #define HAL_MCI_BT_MCI_FLAGS_COEX_GPM             0x00000100
 517 #define HAL_MCI_BT_MCI_FLAGS_CPU_INT_MSG          0x00000200
 518 #define HAL_MCI_BT_MCI_FLAGS_MCI_MODE             0x00000400
 519 #define HAL_MCI_BT_MCI_FLAGS_EGRET_MODE           0x00000800
 520 #define HAL_MCI_BT_MCI_FLAGS_JUPITER_MODE         0x00001000
 521 #define HAL_MCI_BT_MCI_FLAGS_OTHER                0x00010000
 522
 523 #define HAL_MCI_DEFAULT_BT_MCI_FLAGS        0x00011dde
 524 /*
 525     HAL_MCI_BT_MCI_FLAGS_UPDATE_CORR  = 1
 526     HAL_MCI_BT_MCI_FLAGS_UPDATE_HDR   = 1
 527     HAL_MCI_BT_MCI_FLAGS_UPDATE_PLD   = 1
 528     HAL_MCI_BT_MCI_FLAGS_LNA_CTRL     = 1
 529     HAL_MCI_BT_MCI_FLAGS_DEBUG        = 0
 530     HAL_MCI_BT_MCI_FLAGS_SCHED_MSG    = 1
 531     HAL_MCI_BT_MCI_FLAGS_CONT_MSG     = 1
 532     HAL_MCI_BT_MCI_FLAGS_COEX_GPM     = 1
 533     HAL_MCI_BT_MCI_FLAGS_CPU_INT_MSG  = 0
 534     HAL_MCI_BT_MCI_FLAGS_MCI_MODE     = 1
 535     HAL_MCI_BT_MCI_FLAGS_EGRET_MODE   = 1
 536     HAL_MCI_BT_MCI_FLAGS_JUPITER_MODE = 1
 537     HAL_MCI_BT_MCI_FLAGS_OTHER        = 1
 538 */
 539
 540 #define HAL_MCI_TOGGLE_BT_MCI_FLAGS \
 541     (   HAL_MCI_BT_MCI_FLAGS_UPDATE_CORR    |   \
 542         HAL_MCI_BT_MCI_FLAGS_UPDATE_HDR     |   \
 543         HAL_MCI_BT_MCI_FLAGS_UPDATE_PLD     |   \
 544         HAL_MCI_BT_MCI_FLAGS_MCI_MODE   )
 545
 546 #define HAL_MCI_2G_FLAGS_CLEAR_MASK         0x00000000
 547 #define HAL_MCI_2G_FLAGS_SET_MASK           HAL_MCI_TOGGLE_BT_MCI_FLAGS
 548 #define HAL_MCI_2G_FLAGS                    HAL_MCI_DEFAULT_BT_MCI_FLAGS
 549
 550 #define HAL_MCI_5G_FLAGS_CLEAR_MASK         HAL_MCI_TOGGLE_BT_MCI_FLAGS
 551 #define HAL_MCI_5G_FLAGS_SET_MASK           0x00000000
 552 #define HAL_MCI_5G_FLAGS                    (HAL_MCI_DEFAULT_BT_MCI_FLAGS & \
 553                                             ~HAL_MCI_TOGGLE_BT_MCI_FLAGS)
 554
 555 #define HAL_MCI_GPM_NOMORE  0
 556 #define HAL_MCI_GPM_MORE    1
 557 #define HAL_MCI_GPM_INVALID 0xffffffff
 558
 559 #define ATH_AIC_MAX_BT_CHANNEL          79
 560
 561 /*
 562  * Default value for Jupiter   is 0x00002201
 563  * Default value for Aphrodite is 0x00002282
 564  */
 565 #define ATH_MCI_CONFIG_CONCUR_TX            0x00000003
 566 #define ATH_MCI_CONFIG_MCI_OBS_MCI          0x00000004
 567 #define ATH_MCI_CONFIG_MCI_OBS_TXRX         0x00000008
 568 #define ATH_MCI_CONFIG_MCI_OBS_BT           0x00000010
 569 #define ATH_MCI_CONFIG_DISABLE_MCI_CAL      0x00000020
 570 #define ATH_MCI_CONFIG_DISABLE_OSLA         0x00000040
 571 #define ATH_MCI_CONFIG_DISABLE_FTP_STOMP    0x00000080
 572 #define ATH_MCI_CONFIG_AGGR_THRESH          0x00000700
 573 #define ATH_MCI_CONFIG_AGGR_THRESH_S        8
 574 #define ATH_MCI_CONFIG_DISABLE_AGGR_THRESH  0x00000800
 575 #define ATH_MCI_CONFIG_CLK_DIV              0x00003000
 576 #define ATH_MCI_CONFIG_CLK_DIV_S            12
 577 #define ATH_MCI_CONFIG_DISABLE_TUNING       0x00004000
 578 #define ATH_MCI_CONFIG_MCI_WEIGHT_DBG       0x40000000
 579 #define ATH_MCI_CONFIG_DISABLE_MCI          0x80000000
 580
 581 #define ATH_MCI_CONFIG_MCI_OBS_MASK     ( ATH_MCI_CONFIG_MCI_OBS_MCI | \
 582                                           ATH_MCI_CONFIG_MCI_OBS_TXRX | \
 583                                           ATH_MCI_CONFIG_MCI_OBS_BT )
 584 #define ATH_MCI_CONFIG_MCI_OBS_GPIO     0x0000002F
 585
 586 #define ATH_MCI_CONCUR_TX_SHARED_CHN    0x01
 587 #define ATH_MCI_CONCUR_TX_UNSHARED_CHN  0x02
 588 #define ATH_MCI_CONCUR_TX_DEBUG         0x03
 589
 590 /*
 591  * The values below come from the system team test result.
 592  * For Jupiter, BT tx power level is from 0(-20dBm) to 6(4dBm).
 593  * Lowest WLAN tx power would be in bit[23:16] of dword 1.
 594  */
 595 static const u_int32_t mci_concur_tx_max_pwr[4][8] =
 596     { /* No limit */
 597       {0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f,
 598        0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f, 0x7f7f7f7f},
 599       /* 11G */
 600       {0x16161616, 0x12121516, 0x12121212, 0x12121212,
 601        0x12121212, 0x12121212, 0x12121212, 0x7f121212},
 602       /* HT20 */
 603       {0x15151515, 0x14141515, 0x14141414, 0x14141414,
 604        0x14141414, 0x14141414, 0x14141414, 0x7f141414},
 605       /* HT40 */
 606       {0x10101010, 0x10101010, 0x10101010, 0x10101010,
 607        0x10101010, 0x10101010, 0x10101010, 0x7f101010}};
 608 #define ATH_MCI_CONCUR_TX_LOWEST_PWR_MASK     0x00ff0000
 609 #define ATH_MCI_CONCUR_TX_LOWEST_PWR_MASK_S   16
 610
 611 #endif  /* __AR9300_FREEBSD_INC_H__ */