sys/dev/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include <drm/drmP.h>
  30 #include <drm/i915_drm.h>
  31 #include "i915_drv.h"
  32 #include "intel_drv.h"
  33 #include "intel_ringbuffer.h"
  34 #include <linux/workqueue.h>
  35
  36 extern struct drm_i915_private *i915_mch_dev;
  37
  38 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
  39
  40 #define BEGIN_LP_RING(n) \
  41         intel_ring_begin(LP_RING(dev_priv), (n))
  42
  43 #define OUT_RING(x) \
  44         intel_ring_emit(LP_RING(dev_priv), x)
  45
  46 #define ADVANCE_LP_RING() \
  47         intel_ring_advance(LP_RING(dev_priv))
  48
  49 /**
  50  * Lock test for when it's just for synchronization of ring access.
  51  *
  52  * In that case, we don't need to do it when GEM is initialized as nobody else
  53  * has access to the ring.
  54  */
  55 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do {                      \
  56         if (LP_RING(dev->dev_private)->obj == NULL)                     \
  57                 LOCK_TEST_WITH_RETURN(dev, file);                       \
  58 } while (0)
  59
  60 static inline u32
  61 intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg)
  62 {
  63         if (I915_NEED_GFX_HWS(dev_priv->dev))
  64                 return ioread32(dev_priv->dri1.gfx_hws_cpu_addr + reg);
  65         else
  66                 return intel_read_status_page(LP_RING(dev_priv), reg);
  67 }
  68
  69 #define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg)
  70 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
  71 #define I915_BREADCRUMB_INDEX           0x21
  72
  73 void i915_update_dri1_breadcrumb(struct drm_device *dev)
  74 {
  75         /*
  76          * The dri breadcrumb update races against the drm master disappearing.
  77          * Instead of trying to fix this (this is by far not the only ums issue)
  78          * just don't do the update in kms mode.
  79          */
  80         if (drm_core_check_feature(dev, DRIVER_MODESET))
  81                 return;
  82
  83         /* XXX: don't do it at all actually */
  84         return;
  85 }
  86
  87 static void i915_write_hws_pga(struct drm_device *dev)
  88 {
  89         drm_i915_private_t *dev_priv = dev->dev_private;
  90         u32 addr;
  91
  92         addr = dev_priv->status_page_dmah->busaddr;
  93         if (INTEL_INFO(dev)->gen >= 4)
  94                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
  95         I915_WRITE(HWS_PGA, addr);
  96 }
  97
  98 /**
  99  * Sets up the hardware status page for devices that need a physical address
 100  * in the register.
 101  */
 102 static int i915_init_phys_hws(struct drm_device *dev)
 103 {
 104         drm_i915_private_t *dev_priv = dev->dev_private;
 105         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 106
 107         /*
 108          * Program Hardware Status Page
 109          * XXXKIB Keep 4GB limit for allocation for now.  This method
 110          * of allocation is used on <= 965 hardware, that has several
 111          * erratas regarding the use of physical memory > 4 GB.
 112          */
 113         DRM_UNLOCK(dev);
 114         dev_priv->status_page_dmah =
 115                 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
 116         DRM_LOCK(dev);
 117         if (!dev_priv->status_page_dmah) {
 118                 DRM_ERROR("Can not allocate hardware status page\n");
 119                 return -ENOMEM;
 120         }
 121         ring->status_page.page_addr = dev_priv->hw_status_page =
 122             dev_priv->status_page_dmah->vaddr;
 123         dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
 124
 125         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
 126
 127         i915_write_hws_pga(dev);
 128         DRM_DEBUG("Enabled hardware status page, phys %jx\n",
 129             (uintmax_t)dev_priv->dma_status_page);
 130         return 0;
 131 }
 132
 133 /**
 134  * Frees the hardware status page, whether it's a physical address or a virtual
 135  * address set up by the X Server.
 136  */
 137 static void i915_free_hws(struct drm_device *dev)
 138 {
 139         drm_i915_private_t *dev_priv = dev->dev_private;
 140         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 141
 142         if (dev_priv->status_page_dmah) {
 143                 drm_pci_free(dev, dev_priv->status_page_dmah);
 144                 dev_priv->status_page_dmah = NULL;
 145         }
 146
 147         if (dev_priv->status_gfx_addr) {
 148                 dev_priv->status_gfx_addr = 0;
 149                 ring->status_page.gfx_addr = 0;
 150                 drm_core_ioremapfree(&dev_priv->hws_map, dev);
 151         }
 152
 153         /* Need to rewrite hardware status page */
 154         I915_WRITE(HWS_PGA, 0x1ffff000);
 155 }
 156
 157 void i915_kernel_lost_context(struct drm_device * dev)
 158 {
 159         drm_i915_private_t *dev_priv = dev->dev_private;
 160         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 161
 162         /*
 163          * We should never lose context on the ring with modesetting
 164          * as we don't expose it to userspace
 165          */
 166         if (drm_core_check_feature(dev, DRIVER_MODESET))
 167                 return;
 168
 169         ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
 170         ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 171         ring->space = ring->head - (ring->tail + I915_RING_FREE_SPACE);
 172         if (ring->space < 0)
 173                 ring->space += ring->size;
 174
 175 #if 1
 176         KIB_NOTYET();
 177 #else
 178         if (!dev->primary->master)
 179                 return;
 180 #endif
 181
 182         if (ring->head == ring->tail && dev_priv->sarea_priv)
 183                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
 184 }
 185
 186 static int i915_dma_cleanup(struct drm_device * dev)
 187 {
 188         drm_i915_private_t *dev_priv = dev->dev_private;
 189         int i;
 190
 191
 192         /* Make sure interrupts are disabled here because the uninstall ioctl
 193          * may not have been called from userspace and after dev_private
 194          * is freed, it's too late.
 195          */
 196         if (dev->irq_enabled)
 197                 drm_irq_uninstall(dev);
 198
 199         DRM_LOCK(dev);
 200         for (i = 0; i < I915_NUM_RINGS; i++)
 201                 intel_cleanup_ring_buffer(&dev_priv->ring[i]);
 202         DRM_UNLOCK(dev);
 203
 204         /* Clear the HWS virtual address at teardown */
 205         if (I915_NEED_GFX_HWS(dev))
 206                 i915_free_hws(dev);
 207
 208         return 0;
 209 }
 210
 211 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
 212 {
 213         drm_i915_private_t *dev_priv = dev->dev_private;
 214         int ret;
 215
 216         dev_priv->sarea = drm_getsarea(dev);
 217         if (!dev_priv->sarea) {
 218                 DRM_ERROR("can not find sarea!\n");
 219                 i915_dma_cleanup(dev);
 220                 return -EINVAL;
 221         }
 222
 223         dev_priv->sarea_priv = (drm_i915_sarea_t *)
 224             ((u8 *) dev_priv->sarea->virtual + init->sarea_priv_offset);
 225
 226         if (init->ring_size != 0) {
 227                 if (LP_RING(dev_priv)->obj != NULL) {
 228                         i915_dma_cleanup(dev);
 229                         DRM_ERROR("Client tried to initialize ringbuffer in "
 230                                   "GEM mode\n");
 231                         return -EINVAL;
 232                 }
 233
 234                 ret = intel_render_ring_init_dri(dev,
 235                                                  init->ring_start,
 236                                                  init->ring_size);
 237                 if (ret) {
 238                         i915_dma_cleanup(dev);
 239                         return ret;
 240                 }
 241         }
 242
 243         dev_priv->cpp = init->cpp;
 244         dev_priv->back_offset = init->back_offset;
 245         dev_priv->front_offset = init->front_offset;
 246         dev_priv->current_page = 0;
 247         dev_priv->sarea_priv->pf_current_page = 0;
 248
 249         /* Allow hardware batchbuffers unless told otherwise.
 250          */
 251         dev_priv->dri1.allow_batchbuffer = 1;
 252
 253         return 0;
 254 }
 255
 256 static int i915_dma_resume(struct drm_device * dev)
 257 {
 258         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 259         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 260
 261         DRM_DEBUG_DRIVER("%s\n", __func__);
 262
 263         if (ring->virtual_start == NULL) {
 264                 DRM_ERROR("can not ioremap virtual address for"
 265                           " ring buffer\n");
 266                 return -ENOMEM;
 267         }
 268
 269         /* Program Hardware Status Page */
 270         if (!ring->status_page.page_addr) {
 271                 DRM_ERROR("Can not find hardware status page\n");
 272                 return -EINVAL;
 273         }
 274         DRM_DEBUG_DRIVER("hw status page @ %p\n",
 275                                 ring->status_page.page_addr);
 276         if (ring->status_page.gfx_addr != 0)
 277                 intel_ring_setup_status_page(ring);
 278         else
 279                 i915_write_hws_pga(dev);
 280
 281         DRM_DEBUG_DRIVER("Enabled hardware status page\n");
 282
 283         return 0;
 284 }
 285
 286 static int i915_dma_init(struct drm_device *dev, void *data,
 287                          struct drm_file *file_priv)
 288 {
 289         drm_i915_init_t *init = data;
 290         int retcode = 0;
 291
 292         if (drm_core_check_feature(dev, DRIVER_MODESET))
 293                 return -ENODEV;
 294
 295         switch (init->func) {
 296         case I915_INIT_DMA:
 297                 retcode = i915_initialize(dev, init);
 298                 break;
 299         case I915_CLEANUP_DMA:
 300                 retcode = i915_dma_cleanup(dev);
 301                 break;
 302         case I915_RESUME_DMA:
 303                 retcode = i915_dma_resume(dev);
 304                 break;
 305         default:
 306                 retcode = -EINVAL;
 307                 break;
 308         }
 309
 310         return retcode;
 311 }
 312
 313 /* Implement basically the same security restrictions as hardware does
 314  * for MI_BATCH_NON_SECURE.  These can be made stricter at any time.
 315  *
 316  * Most of the calculations below involve calculating the size of a
 317  * particular instruction.  It's important to get the size right as
 318  * that tells us where the next instruction to check is.  Any illegal
 319  * instruction detected will be given a size of zero, which is a
 320  * signal to abort the rest of the buffer.
 321  */
 322 static int validate_cmd(int cmd)
 323 {
 324         switch (((cmd >> 29) & 0x7)) {
 325         case 0x0:
 326                 switch ((cmd >> 23) & 0x3f) {
 327                 case 0x0:
 328                         return 1;       /* MI_NOOP */
 329                 case 0x4:
 330                         return 1;       /* MI_FLUSH */
 331                 default:
 332                         return 0;       /* disallow everything else */
 333                 }
 334                 break;
 335         case 0x1:
 336                 return 0;       /* reserved */
 337         case 0x2:
 338                 return (cmd & 0xff) + 2;        /* 2d commands */
 339         case 0x3:
 340                 if (((cmd >> 24) & 0x1f) <= 0x18)
 341                         return 1;
 342
 343                 switch ((cmd >> 24) & 0x1f) {
 344                 case 0x1c:
 345                         return 1;
 346                 case 0x1d:
 347                         switch ((cmd >> 16) & 0xff) {
 348                         case 0x3:
 349                                 return (cmd & 0x1f) + 2;
 350                         case 0x4:
 351                                 return (cmd & 0xf) + 2;
 352                         default:
 353                                 return (cmd & 0xffff) + 2;
 354                         }
 355                 case 0x1e:
 356                         if (cmd & (1 << 23))
 357                                 return (cmd & 0xffff) + 1;
 358                         else
 359                                 return 1;
 360                 case 0x1f:
 361                         if ((cmd & (1 << 23)) == 0)     /* inline vertices */
 362                                 return (cmd & 0x1ffff) + 2;
 363                         else if (cmd & (1 << 17))       /* indirect random */
 364                                 if ((cmd & 0xffff) == 0)
 365                                         return 0;       /* unknown length, too hard */
 366                                 else
 367                                         return (((cmd & 0xffff) + 1) / 2) + 1;
 368                         else
 369                                 return 2;       /* indirect sequential */
 370                 default:
 371                         return 0;
 372                 }
 373         default:
 374                 return 0;
 375         }
 376
 377         return 0;
 378 }
 379
 380 static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
 381 {
 382         drm_i915_private_t *dev_priv = dev->dev_private;
 383         int i, ret;
 384
 385         if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
 386                 return -EINVAL;
 387
 388         for (i = 0; i < dwords;) {
 389                 int sz = validate_cmd(buffer[i]);
 390                 if (sz == 0 || i + sz > dwords)
 391                         return -EINVAL;
 392                 i += sz;
 393         }
 394
 395         ret = BEGIN_LP_RING((dwords+1)&~1);
 396         if (ret)
 397                 return ret;
 398
 399         for (i = 0; i < dwords; i++)
 400                 OUT_RING(buffer[i]);
 401         if (dwords & 1)
 402                 OUT_RING(0);
 403
 404         ADVANCE_LP_RING();
 405
 406         return 0;
 407 }
 408
 409 int
 410 i915_emit_box(struct drm_device *dev,
 411               struct drm_clip_rect *box,
 412               int DR1, int DR4)
 413 {
 414         struct drm_i915_private *dev_priv = dev->dev_private;
 415         int ret;
 416
 417         if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
 418             box->y2 <= 0 || box->x2 <= 0) {
 419                 DRM_ERROR("Bad box %d,%d..%d,%d\n",
 420                           box->x1, box->y1, box->x2, box->y2);
 421                 return -EINVAL;
 422         }
 423
 424         if (INTEL_INFO(dev)->gen >= 4) {
 425                 ret = BEGIN_LP_RING(4);
 426                 if (ret)
 427                         return ret;
 428
 429                 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
 430                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 431                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 432                 OUT_RING(DR4);
 433         } else {
 434                 ret = BEGIN_LP_RING(6);
 435                 if (ret)
 436                         return ret;
 437
 438                 OUT_RING(GFX_OP_DRAWRECT_INFO);
 439                 OUT_RING(DR1);
 440                 OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
 441                 OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
 442                 OUT_RING(DR4);
 443                 OUT_RING(0);
 444         }
 445         ADVANCE_LP_RING();
 446
 447         return 0;
 448 }
 449
 450 /* XXX: Emitting the counter should really be moved to part of the IRQ
 451  * emit. For now, do it in both places:
 452  */
 453
 454 static void i915_emit_breadcrumb(struct drm_device *dev)
 455 {
 456         drm_i915_private_t *dev_priv = dev->dev_private;
 457
 458         dev_priv->dri1.counter++;
 459         if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
 460                 dev_priv->dri1.counter = 0;
 461         if (dev_priv->sarea_priv)
 462                 dev_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
 463
 464         if (BEGIN_LP_RING(4) == 0) {
 465                 OUT_RING(MI_STORE_DWORD_INDEX);
 466                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 467                 OUT_RING(dev_priv->dri1.counter);
 468                 OUT_RING(0);
 469                 ADVANCE_LP_RING();
 470         }
 471 }
 472
 473 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
 474                                    drm_i915_cmdbuffer_t *cmd,
 475                                    struct drm_clip_rect *cliprects,
 476                                    void *cmdbuf)
 477 {
 478         int nbox = cmd->num_cliprects;
 479         int i = 0, count, ret;
 480
 481         if (cmd->sz & 0x3) {
 482                 DRM_ERROR("alignment");
 483                 return -EINVAL;
 484         }
 485
 486         i915_kernel_lost_context(dev);
 487
 488         count = nbox ? nbox : 1;
 489
 490         for (i = 0; i < count; i++) {
 491                 if (i < nbox) {
 492                         ret = i915_emit_box(dev, &cliprects[i],
 493                                             cmd->DR1, cmd->DR4);
 494                         if (ret)
 495                                 return ret;
 496                 }
 497
 498                 ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
 499                 if (ret)
 500                         return ret;
 501         }
 502
 503         i915_emit_breadcrumb(dev);
 504         return 0;
 505 }
 506
 507 static int i915_dispatch_batchbuffer(struct drm_device * dev,
 508                                      drm_i915_batchbuffer_t * batch,
 509                                      struct drm_clip_rect *cliprects)
 510 {
 511         struct drm_i915_private *dev_priv = dev->dev_private;
 512         int nbox = batch->num_cliprects;
 513         int i, count, ret;
 514
 515         if ((batch->start | batch->used) & 0x7) {
 516                 DRM_ERROR("alignment");
 517                 return -EINVAL;
 518         }
 519
 520         i915_kernel_lost_context(dev);
 521
 522         count = nbox ? nbox : 1;
 523         for (i = 0; i < count; i++) {
 524                 if (i < nbox) {
 525                         ret = i915_emit_box(dev, &cliprects[i],
 526                                             batch->DR1, batch->DR4);
 527                         if (ret)
 528                                 return ret;
 529                 }
 530
 531                 if (!IS_I830(dev) && !IS_845G(dev)) {
 532                         ret = BEGIN_LP_RING(2);
 533                         if (ret)
 534                                 return ret;
 535
 536                         if (INTEL_INFO(dev)->gen >= 4) {
 537                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
 538                                 OUT_RING(batch->start);
 539                         } else {
 540                                 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
 541                                 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 542                         }
 543                 } else {
 544                         ret = BEGIN_LP_RING(4);
 545                         if (ret)
 546                                 return ret;
 547
 548                         OUT_RING(MI_BATCH_BUFFER);
 549                         OUT_RING(batch->start | MI_BATCH_NON_SECURE);
 550                         OUT_RING(batch->start + batch->used - 4);
 551                         OUT_RING(0);
 552                 }
 553                 ADVANCE_LP_RING();
 554         }
 555
 556
 557         if (IS_G4X(dev) || IS_GEN5(dev)) {
 558                 if (BEGIN_LP_RING(2) == 0) {
 559                         OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
 560                         OUT_RING(MI_NOOP);
 561                         ADVANCE_LP_RING();
 562                 }
 563         }
 564
 565         i915_emit_breadcrumb(dev);
 566         return 0;
 567 }
 568
 569 static int i915_dispatch_flip(struct drm_device * dev)
 570 {
 571         drm_i915_private_t *dev_priv = dev->dev_private;
 572         int ret;
 573
 574         if (!dev_priv->sarea_priv)
 575                 return -EINVAL;
 576
 577         DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
 578                           __func__,
 579                          dev_priv->dri1.current_page,
 580                          dev_priv->sarea_priv->pf_current_page);
 581
 582         i915_kernel_lost_context(dev);
 583
 584         ret = BEGIN_LP_RING(10);
 585         if (ret)
 586                 return ret;
 587
 588         OUT_RING(MI_FLUSH | MI_READ_FLUSH);
 589         OUT_RING(0);
 590
 591         OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
 592         OUT_RING(0);
 593         if (dev_priv->dri1.current_page == 0) {
 594                 OUT_RING(dev_priv->dri1.back_offset);
 595                 dev_priv->dri1.current_page = 1;
 596         } else {
 597                 OUT_RING(dev_priv->dri1.front_offset);
 598                 dev_priv->dri1.current_page = 0;
 599         }
 600         OUT_RING(0);
 601
 602         OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
 603         OUT_RING(0);
 604
 605         ADVANCE_LP_RING();
 606
 607         dev_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter++;
 608
 609         if (BEGIN_LP_RING(4) == 0) {
 610                 OUT_RING(MI_STORE_DWORD_INDEX);
 611                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 612                 OUT_RING(dev_priv->dri1.counter);
 613                 OUT_RING(0);
 614                 ADVANCE_LP_RING();
 615         }
 616
 617         dev_priv->sarea_priv->pf_current_page = dev_priv->dri1.current_page;
 618         return 0;
 619 }
 620
 621 static int i915_quiescent(struct drm_device *dev)
 622 {
 623         i915_kernel_lost_context(dev);
 624         return intel_ring_idle(LP_RING(dev->dev_private));
 625 }
 626
 627 static int i915_flush_ioctl(struct drm_device *dev, void *data,
 628                             struct drm_file *file_priv)
 629 {
 630         int ret;
 631
 632         if (drm_core_check_feature(dev, DRIVER_MODESET))
 633                 return -ENODEV;
 634
 635         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 636
 637         DRM_LOCK(dev);
 638         ret = i915_quiescent(dev);
 639         DRM_UNLOCK(dev);
 640
 641         return ret;
 642 }
 643
 644 static int i915_batchbuffer(struct drm_device *dev, void *data,
 645                             struct drm_file *file_priv)
 646 {
 647         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 648         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)dev_priv->sarea_priv;
 649         drm_i915_batchbuffer_t *batch = data;
 650         int ret;
 651         struct drm_clip_rect *cliprects = NULL;
 652
 653         if (drm_core_check_feature(dev, DRIVER_MODESET))
 654                 return -ENODEV;
 655
 656         if (!dev_priv->dri1.allow_batchbuffer) {
 657                 DRM_ERROR("Batchbuffer ioctl disabled\n");
 658                 return -EINVAL;
 659         }
 660
 661         DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
 662                         batch->start, batch->used, batch->num_cliprects);
 663
 664         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 665
 666         if (batch->num_cliprects < 0)
 667                 return -EINVAL;
 668
 669         if (batch->num_cliprects) {
 670                 cliprects = kmalloc(batch->num_cliprects *
 671                                     sizeof(struct drm_clip_rect), DRM_MEM_DMA,
 672                                     M_WAITOK | M_ZERO);
 673                 if (cliprects == NULL)
 674                         return -ENOMEM;
 675
 676                 ret = copy_from_user(cliprects, batch->cliprects,
 677                                      batch->num_cliprects *
 678                                      sizeof(struct drm_clip_rect));
 679                 if (ret != 0) {
 680                         ret = -EFAULT;
 681                         goto fail_free;
 682                 }
 683         }
 684
 685         DRM_LOCK(dev);
 686         ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
 687         DRM_UNLOCK(dev);
 688
 689         if (sarea_priv)
 690                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 691
 692 fail_free:
 693         kfree(cliprects, DRM_MEM_DMA);
 694         return ret;
 695 }
 696
 697 static int i915_cmdbuffer(struct drm_device *dev, void *data,
 698                           struct drm_file *file_priv)
 699 {
 700         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 701         drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)dev_priv->sarea_priv;
 702         drm_i915_cmdbuffer_t *cmdbuf = data;
 703         struct drm_clip_rect *cliprects = NULL;
 704         void *batch_data;
 705         int ret;
 706
 707         DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
 708                         cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
 709
 710         if (drm_core_check_feature(dev, DRIVER_MODESET))
 711                 return -ENODEV;
 712
 713         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 714
 715         if (cmdbuf->num_cliprects < 0)
 716                 return -EINVAL;
 717
 718         batch_data = kmalloc(cmdbuf->sz, DRM_MEM_DMA, M_WAITOK);
 719         if (batch_data == NULL)
 720                 return -ENOMEM;
 721
 722         ret = -copyin(cmdbuf->buf, batch_data, cmdbuf->sz);
 723         if (ret != 0) {
 724                 ret = -EFAULT;
 725                 goto fail_batch_free;
 726         }
 727
 728         if (cmdbuf->num_cliprects) {
 729                 cliprects = kmalloc(cmdbuf->num_cliprects *
 730                                     sizeof(struct drm_clip_rect), DRM_MEM_DMA,
 731                                     M_WAITOK | M_ZERO);
 732                 if (cliprects == NULL) {
 733                         ret = -ENOMEM;
 734                         goto fail_batch_free;
 735                 }
 736
 737                 ret = copy_from_user(cliprects, cmdbuf->cliprects,
 738                                      cmdbuf->num_cliprects *
 739                                      sizeof(struct drm_clip_rect));
 740                 if (ret != 0) {
 741                         ret = -EFAULT;
 742                         goto fail_clip_free;
 743                 }
 744         }
 745
 746         DRM_LOCK(dev);
 747         ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
 748         DRM_UNLOCK(dev);
 749         if (ret) {
 750                 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
 751                 goto fail_clip_free;
 752         }
 753
 754         if (sarea_priv)
 755                 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 756
 757 fail_clip_free:
 758         drm_free(cliprects, DRM_MEM_DMA);
 759 fail_batch_free:
 760         drm_free(batch_data, DRM_MEM_DMA);
 761         return ret;
 762 }
 763
 764 static int i915_emit_irq(struct drm_device * dev)
 765 {
 766         drm_i915_private_t *dev_priv = dev->dev_private;
 767 #if 0
 768         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 769 #endif
 770
 771         i915_kernel_lost_context(dev);
 772
 773         DRM_DEBUG_DRIVER("\n");
 774
 775         dev_priv->dri1.counter++;
 776         if (dev_priv->dri1.counter > 0x7FFFFFFFUL)
 777                 dev_priv->dri1.counter = 1;
 778         if (dev_priv->sarea_priv)
 779                 dev_priv->sarea_priv->last_enqueue = dev_priv->dri1.counter;
 780
 781         if (BEGIN_LP_RING(4) == 0) {
 782                 OUT_RING(MI_STORE_DWORD_INDEX);
 783                 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 784                 OUT_RING(dev_priv->dri1.counter);
 785                 OUT_RING(MI_USER_INTERRUPT);
 786                 ADVANCE_LP_RING();
 787         }
 788
 789         return dev_priv->dri1.counter;
 790 }
 791
 792 static int i915_wait_irq(struct drm_device * dev, int irq_nr)
 793 {
 794         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 795 #if 0
 796         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
 797 #endif
 798         int ret = 0;
 799         struct intel_ring_buffer *ring = LP_RING(dev_priv);
 800
 801         DRM_DEBUG_DRIVER("irq_nr=%d breadcrumb=%d\n", irq_nr,
 802                   READ_BREADCRUMB(dev_priv));
 803
 804 #if 0
 805         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
 806                 if (master_priv->sarea_priv)
 807                         master_priv->sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
 808                 return 0;
 809         }
 810
 811         if (master_priv->sarea_priv)
 812                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 813 #else
 814         if (READ_BREADCRUMB(dev_priv) >= irq_nr) {
 815                 if (dev_priv->sarea_priv) {
 816                         dev_priv->sarea_priv->last_dispatch =
 817                                 READ_BREADCRUMB(dev_priv);
 818                 }
 819                 return 0;
 820         }
 821
 822         if (dev_priv->sarea_priv)
 823                 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
 824 #endif
 825
 826         if (ring->irq_get(ring)) {
 827                 DRM_WAIT_ON(ret, ring->irq_queue, 3 * DRM_HZ,
 828                             READ_BREADCRUMB(dev_priv) >= irq_nr);
 829                 ring->irq_put(ring);
 830         } else if (wait_for(READ_BREADCRUMB(dev_priv) >= irq_nr, 3000))
 831                 ret = -EBUSY;
 832
 833         if (ret == -EBUSY) {
 834                 DRM_ERROR("EBUSY -- rec: %d emitted: %d\n",
 835                           READ_BREADCRUMB(dev_priv), (int)dev_priv->dri1.counter);
 836         }
 837
 838         return ret;
 839 }
 840
 841 /* Needs the lock as it touches the ring.
 842  */
 843 static int i915_irq_emit(struct drm_device *dev, void *data,
 844                          struct drm_file *file_priv)
 845 {
 846         drm_i915_private_t *dev_priv = dev->dev_private;
 847         drm_i915_irq_emit_t *emit = data;
 848         int result;
 849
 850         if (drm_core_check_feature(dev, DRIVER_MODESET))
 851                 return -ENODEV;
 852
 853         if (!dev_priv || !LP_RING(dev_priv)->virtual_start) {
 854                 DRM_ERROR("called with no initialization\n");
 855                 return -EINVAL;
 856         }
 857
 858         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 859
 860         DRM_LOCK(dev);
 861         result = i915_emit_irq(dev);
 862         DRM_UNLOCK(dev);
 863
 864         if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
 865                 DRM_ERROR("copy_to_user\n");
 866                 return -EFAULT;
 867         }
 868
 869         return 0;
 870 }
 871
 872 /* Doesn't need the hardware lock.
 873  */
 874 static int i915_irq_wait(struct drm_device *dev, void *data,
 875                          struct drm_file *file_priv)
 876 {
 877         drm_i915_private_t *dev_priv = dev->dev_private;
 878         drm_i915_irq_wait_t *irqwait = data;
 879
 880         if (drm_core_check_feature(dev, DRIVER_MODESET))
 881                 return -ENODEV;
 882
 883         if (!dev_priv) {
 884                 DRM_ERROR("called with no initialization\n");
 885                 return -EINVAL;
 886         }
 887
 888         return i915_wait_irq(dev, irqwait->irq_seq);
 889 }
 890
 891 static int i915_vblank_pipe_get(struct drm_device *dev, void *data,
 892                          struct drm_file *file_priv)
 893 {
 894         drm_i915_private_t *dev_priv = dev->dev_private;
 895         drm_i915_vblank_pipe_t *pipe = data;
 896
 897         if (drm_core_check_feature(dev, DRIVER_MODESET))
 898                 return -ENODEV;
 899
 900         if (!dev_priv) {
 901                 DRM_ERROR("called with no initialization\n");
 902                 return -EINVAL;
 903         }
 904
 905         pipe->pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
 906
 907         return 0;
 908 }
 909
 910 /**
 911  * Schedule buffer swap at given vertical blank.
 912  */
 913 static int i915_vblank_swap(struct drm_device *dev, void *data,
 914                      struct drm_file *file_priv)
 915 {
 916         /* The delayed swap mechanism was fundamentally racy, and has been
 917          * removed.  The model was that the client requested a delayed flip/swap
 918          * from the kernel, then waited for vblank before continuing to perform
 919          * rendering.  The problem was that the kernel might wake the client
 920          * up before it dispatched the vblank swap (since the lock has to be
 921          * held while touching the ringbuffer), in which case the client would
 922          * clear and start the next frame before the swap occurred, and
 923          * flicker would occur in addition to likely missing the vblank.
 924          *
 925          * In the absence of this ioctl, userland falls back to a correct path
 926          * of waiting for a vblank, then dispatching the swap on its own.
 927          * Context switching to userland and back is plenty fast enough for
 928          * meeting the requirements of vblank swapping.
 929          */
 930         return -EINVAL;
 931 }
 932
 933 static int i915_flip_bufs(struct drm_device *dev, void *data,
 934                           struct drm_file *file_priv)
 935 {
 936         int ret;
 937
 938         if (drm_core_check_feature(dev, DRIVER_MODESET))
 939                 return -ENODEV;
 940
 941         DRM_DEBUG_DRIVER("%s\n", __func__);
 942
 943         RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
 944
 945         DRM_LOCK(dev);
 946         ret = i915_dispatch_flip(dev);
 947         DRM_UNLOCK(dev);
 948
 949         return ret;
 950 }
 951
 952 static int i915_getparam(struct drm_device *dev, void *data,
 953                          struct drm_file *file_priv)
 954 {
 955         drm_i915_private_t *dev_priv = dev->dev_private;
 956         drm_i915_getparam_t *param = data;
 957         int value;
 958
 959         if (!dev_priv) {
 960                 DRM_ERROR("called with no initialization\n");
 961                 return -EINVAL;
 962         }
 963
 964         switch (param->param) {
 965         case I915_PARAM_IRQ_ACTIVE:
 966                 value = dev->irq_enabled ? 1 : 0;
 967                 break;
 968         case I915_PARAM_ALLOW_BATCHBUFFER:
 969                 value = dev_priv->dri1.allow_batchbuffer ? 1 : 0;
 970                 break;
 971         case I915_PARAM_LAST_DISPATCH:
 972                 value = READ_BREADCRUMB(dev_priv);
 973                 break;
 974         case I915_PARAM_CHIPSET_ID:
 975                 value = dev->pci_device;
 976                 break;
 977         case I915_PARAM_HAS_GEM:
 978                 value = 1;
 979                 break;
 980         case I915_PARAM_NUM_FENCES_AVAIL:
 981                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
 982                 break;
 983         case I915_PARAM_HAS_OVERLAY:
 984                 value = dev_priv->overlay ? 1 : 0;
 985                 break;
 986         case I915_PARAM_HAS_PAGEFLIPPING:
 987                 value = 1;
 988                 break;
 989         case I915_PARAM_HAS_EXECBUF2:
 990                 /* depends on GEM */
 991                 value = 1;
 992                 break;
 993         case I915_PARAM_HAS_BSD:
 994                 value = intel_ring_initialized(&dev_priv->ring[VCS]);
 995                 break;
 996         case I915_PARAM_HAS_BLT:
 997                 value = intel_ring_initialized(&dev_priv->ring[BCS]);
 998                 break;
 999         case I915_PARAM_HAS_RELAXED_FENCING:
1000                 value = 1;
1001                 break;
1002         case I915_PARAM_HAS_COHERENT_RINGS:
1003                 value = 1;
1004                 break;
1005         case I915_PARAM_HAS_EXEC_CONSTANTS:
1006                 value = INTEL_INFO(dev)->gen >= 4;
1007                 break;
1008         case I915_PARAM_HAS_RELAXED_DELTA:
1009                 value = 1;
1010                 break;
1011         case I915_PARAM_HAS_GEN7_SOL_RESET:
1012                 value = 1;
1013                 break;
1014         case I915_PARAM_HAS_LLC:
1015                 value = HAS_LLC(dev);
1016                 break;
1017         case I915_PARAM_HAS_ALIASING_PPGTT:
1018                 value = dev_priv->mm.aliasing_ppgtt ? 1 : 0;
1019                 break;
1020         case I915_PARAM_HAS_WAIT_TIMEOUT:
1021                 value = 1;
1022                 break;
1023         case I915_PARAM_HAS_PINNED_BATCHES:
1024                 value = 1;
1025                 break;
1026         default:
1027                 DRM_DEBUG_DRIVER("Unknown parameter %d\n",
1028                                  param->param);
1029                 return -EINVAL;
1030         }
1031
1032         if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
1033                 DRM_ERROR("DRM_COPY_TO_USER failed\n");
1034                 return -EFAULT;
1035         }
1036
1037         return 0;
1038 }
1039
1040 static int i915_setparam(struct drm_device *dev, void *data,
1041                          struct drm_file *file_priv)
1042 {
1043         drm_i915_private_t *dev_priv = dev->dev_private;
1044         drm_i915_setparam_t *param = data;
1045
1046         if (!dev_priv) {
1047                 DRM_ERROR("called with no initialization\n");
1048                 return -EINVAL;
1049         }
1050
1051         switch (param->param) {
1052         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
1053                 break;
1054         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
1055                 break;
1056         case I915_SETPARAM_ALLOW_BATCHBUFFER:
1057                 dev_priv->dri1.allow_batchbuffer = param->value;
1058                 break;
1059         case I915_SETPARAM_NUM_USED_FENCES:
1060                 if (param->value > dev_priv->num_fence_regs ||
1061                     param->value < 0)
1062                         return -EINVAL;
1063                 /* Userspace can use first N regs */
1064                 dev_priv->fence_reg_start = param->value;
1065                 break;
1066         default:
1067                 DRM_DEBUG_DRIVER("unknown parameter %d\n",
1068                                         param->param);
1069                 return -EINVAL;
1070         }
1071
1072         return 0;
1073 }
1074
1075 static int i915_set_status_page(struct drm_device *dev, void *data,
1076                                 struct drm_file *file_priv)
1077 {
1078         drm_i915_private_t *dev_priv = dev->dev_private;
1079         drm_i915_hws_addr_t *hws = data;
1080         struct intel_ring_buffer *ring = LP_RING(dev_priv);
1081
1082         if (drm_core_check_feature(dev, DRIVER_MODESET))
1083                 return -ENODEV;
1084
1085         if (!I915_NEED_GFX_HWS(dev))
1086                 return -EINVAL;
1087
1088         if (!dev_priv) {
1089                 DRM_ERROR("called with no initialization\n");
1090                 return -EINVAL;
1091         }
1092
1093         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1094                 WARN(1, "tried to set status page when mode setting active\n");
1095                 return 0;
1096         }
1097
1098         ring->status_page.gfx_addr = dev_priv->status_gfx_addr =
1099             hws->addr & (0x1ffff<<12);
1100
1101         dev_priv->hws_map.offset = dev->agp->base + hws->addr;
1102         dev_priv->hws_map.size = 4*1024;
1103         dev_priv->hws_map.type = 0;
1104         dev_priv->hws_map.flags = 0;
1105         dev_priv->hws_map.mtrr = 0;
1106
1107         drm_core_ioremap_wc(&dev_priv->hws_map, dev);
1108         if (dev_priv->hws_map.virtual == NULL) {
1109                 i915_dma_cleanup(dev);
1110                 ring->status_page.gfx_addr = dev_priv->status_gfx_addr = 0;
1111                 DRM_ERROR("can not ioremap virtual address for"
1112                                 " G33 hw status page\n");
1113                 return -ENOMEM;
1114         }
1115         ring->status_page.page_addr = dev_priv->hw_status_page =
1116             dev_priv->hws_map.virtual;
1117
1118         memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
1119         I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
1120
1121         DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
1122                          ring->status_page.gfx_addr);
1123         DRM_DEBUG_DRIVER("load hws at %p\n",
1124                          ring->status_page.page_addr);
1125         return 0;
1126 }
1127
1128 static int i915_get_bridge_dev(struct drm_device *dev)
1129 {
1130         struct drm_i915_private *dev_priv = dev->dev_private;
1131
1132         dev_priv->bridge_dev = pci_find_dbsf(0, 0, 0, 0);
1133         if (!dev_priv->bridge_dev) {
1134                 DRM_ERROR("bridge device not found\n");
1135                 return -1;
1136         }
1137         return 0;
1138 }
1139
1140 #define MCHBAR_I915 0x44
1141 #define MCHBAR_I965 0x48
1142 #define MCHBAR_SIZE (4*4096)
1143
1144 #define DEVEN_REG 0x54
1145 #define   DEVEN_MCHBAR_EN (1 << 28)
1146
1147 /* Allocate space for the MCH regs if needed, return nonzero on error */
1148 static int
1149 intel_alloc_mchbar_resource(struct drm_device *dev)
1150 {
1151         drm_i915_private_t *dev_priv = dev->dev_private;
1152         int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1153         device_t vga;
1154         u32 temp_lo, temp_hi;
1155         u64 mchbar_addr, temp;
1156
1157         if (INTEL_INFO(dev)->gen >= 4)
1158                 temp_hi = pci_read_config(dev_priv->bridge_dev, reg + 4, 4);
1159         else
1160                 temp_hi = 0;
1161         temp_lo = pci_read_config(dev_priv->bridge_dev, reg, 4);
1162         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
1163
1164         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
1165 #ifdef CONFIG_PNP
1166         if (mchbar_addr &&
1167             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
1168                 return 0;
1169 #endif
1170
1171         /* Get some space for it */
1172         vga = device_get_parent(dev->dev);
1173         dev_priv->mch_res_rid = 0x100;
1174         dev_priv->mch_res = BUS_ALLOC_RESOURCE(device_get_parent(vga),
1175             dev->dev, SYS_RES_MEMORY, &dev_priv->mch_res_rid, 0, ~0UL,
1176             MCHBAR_SIZE, RF_ACTIVE | RF_SHAREABLE, -1);
1177         if (dev_priv->mch_res == NULL) {
1178                 DRM_ERROR("failed mchbar resource alloc\n");
1179                 return (-ENOMEM);
1180         }
1181
1182         if (INTEL_INFO(dev)->gen >= 4) {
1183                 temp = rman_get_start(dev_priv->mch_res);
1184                 temp >>= 32;
1185                 pci_write_config(dev_priv->bridge_dev, reg + 4, temp, 4);
1186         }
1187         pci_write_config(dev_priv->bridge_dev, reg,
1188             rman_get_start(dev_priv->mch_res) & UINT32_MAX, 4);
1189         return 0;
1190 }
1191
1192 /* Setup MCHBAR if possible, return true if we should disable it again */
1193 static void
1194 intel_setup_mchbar(struct drm_device *dev)
1195 {
1196         drm_i915_private_t *dev_priv = dev->dev_private;
1197         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1198         u32 temp;
1199         bool enabled;
1200
1201         dev_priv->mchbar_need_disable = false;
1202
1203         if (IS_I915G(dev) || IS_I915GM(dev)) {
1204                 temp = pci_read_config(dev_priv->bridge_dev, DEVEN_REG, 4);
1205                 enabled = (temp & DEVEN_MCHBAR_EN) != 0;
1206         } else {
1207                 temp = pci_read_config(dev_priv->bridge_dev, mchbar_reg, 4);
1208                 enabled = temp & 1;
1209         }
1210
1211         /* If it's already enabled, don't have to do anything */
1212         if (enabled)
1213                 return;
1214
1215         if (intel_alloc_mchbar_resource(dev))
1216                 return;
1217
1218         dev_priv->mchbar_need_disable = true;
1219
1220         /* Space is allocated or reserved, so enable it. */
1221         if (IS_I915G(dev) || IS_I915GM(dev)) {
1222                 pci_write_config(dev_priv->bridge_dev, DEVEN_REG,
1223                     temp | DEVEN_MCHBAR_EN, 4);
1224         } else {
1225                 temp = pci_read_config(dev_priv->bridge_dev, mchbar_reg, 4);
1226                 pci_write_config(dev_priv->bridge_dev, mchbar_reg, temp | 1, 4);
1227         }
1228 }
1229
1230 static void
1231 intel_teardown_mchbar(struct drm_device *dev)
1232 {
1233         drm_i915_private_t *dev_priv = dev->dev_private;
1234         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
1235         device_t vga;
1236         u32 temp;
1237
1238         if (dev_priv->mchbar_need_disable) {
1239                 if (IS_I915G(dev) || IS_I915GM(dev)) {
1240                         temp = pci_read_config(dev_priv->bridge_dev,
1241                             DEVEN_REG, 4);
1242                         temp &= ~DEVEN_MCHBAR_EN;
1243                         pci_write_config(dev_priv->bridge_dev, DEVEN_REG,
1244                             temp, 4);
1245                 } else {
1246                         temp = pci_read_config(dev_priv->bridge_dev,
1247                             mchbar_reg, 4);
1248                         temp &= ~1;
1249                         pci_write_config(dev_priv->bridge_dev, mchbar_reg,
1250                             temp, 4);
1251                 }
1252         }
1253
1254         if (dev_priv->mch_res != NULL) {
1255                 vga = device_get_parent(dev->dev);
1256                 BUS_DEACTIVATE_RESOURCE(device_get_parent(vga), dev->dev,
1257                     SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1258                 BUS_RELEASE_RESOURCE(device_get_parent(vga), dev->dev,
1259                     SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
1260                 dev_priv->mch_res = NULL;
1261         }
1262 }
1263
1264 static int i915_load_modeset_init(struct drm_device *dev)
1265 {
1266         struct drm_i915_private *dev_priv = dev->dev_private;
1267         int ret;
1268
1269         ret = intel_parse_bios(dev);
1270         if (ret)
1271                 DRM_INFO("failed to find VBIOS tables\n");
1272
1273 #if 0
1274         /* If we have > 1 VGA cards, then we need to arbitrate access
1275          * to the common VGA resources.
1276          *
1277          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
1278          * then we do not take part in VGA arbitration and the
1279          * vga_client_register() fails with -ENODEV.
1280          */
1281         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
1282         if (ret && ret != -ENODEV)
1283                 goto out;
1284
1285         intel_register_dsm_handler();
1286
1287         ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops);
1288         if (ret)
1289                 goto cleanup_vga_client;
1290
1291         /* Initialise stolen first so that we may reserve preallocated
1292          * objects for the BIOS to KMS transition.
1293          */
1294         ret = i915_gem_init_stolen(dev);
1295         if (ret)
1296                 goto cleanup_vga_switcheroo;
1297 #endif
1298
1299         intel_modeset_init(dev);
1300
1301         ret = i915_gem_init(dev);
1302         if (ret)
1303                 goto cleanup_gem_stolen;
1304
1305         intel_modeset_gem_init(dev);
1306
1307         ret = drm_irq_install(dev);
1308         if (ret)
1309                 goto cleanup_gem;
1310
1311         /* Always safe in the mode setting case. */
1312         /* FIXME: do pre/post-mode set stuff in core KMS code */
1313         dev->vblank_disable_allowed = 1;
1314
1315         ret = intel_fbdev_init(dev);
1316         if (ret)
1317                 goto cleanup_irq;
1318
1319         drm_kms_helper_poll_init(dev);
1320
1321         /* We're off and running w/KMS */
1322         dev_priv->mm.suspended = 0;
1323
1324         return 0;
1325
1326 cleanup_irq:
1327         drm_irq_uninstall(dev);
1328 cleanup_gem:
1329         DRM_LOCK(dev);
1330         i915_gem_cleanup_ringbuffer(dev);
1331         DRM_UNLOCK(dev);
1332         i915_gem_cleanup_aliasing_ppgtt(dev);
1333 cleanup_gem_stolen:
1334 #if 0
1335         i915_gem_cleanup_stolen(dev);
1336 cleanup_vga_switcheroo:
1337         vga_switcheroo_unregister_client(dev->pdev);
1338 cleanup_vga_client:
1339         vga_client_register(dev->pdev, NULL, NULL, NULL);
1340 out:
1341 #endif
1342         return ret;
1343 }
1344
1345 /**
1346  * i915_driver_load - setup chip and create an initial config
1347  * @dev: DRM device
1348  * @flags: startup flags
1349  *
1350  * The driver load routine has to do several things:
1351  *   - drive output discovery via intel_modeset_init()
1352  *   - initialize the memory manager
1353  *   - allocate initial config memory
1354  *   - setup the DRM framebuffer with the allocated memory
1355  */
1356 int i915_driver_load(struct drm_device *dev, unsigned long flags)
1357 {
1358         struct drm_i915_private *dev_priv = dev->dev_private;
1359         unsigned long base, size;
1360         int mmio_bar, ret;
1361
1362         ret = 0;
1363
1364         /* i915 has 4 more counters */
1365         dev->counters += 4;
1366         dev->types[6] = _DRM_STAT_IRQ;
1367         dev->types[7] = _DRM_STAT_PRIMARY;
1368         dev->types[8] = _DRM_STAT_SECONDARY;
1369         dev->types[9] = _DRM_STAT_DMA;
1370
1371         dev_priv = kmalloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER,
1372             M_ZERO | M_WAITOK);
1373         if (dev_priv == NULL)
1374                 return -ENOMEM;
1375
1376         dev->dev_private = (void *)dev_priv;
1377         dev_priv->dev = dev;
1378         dev_priv->info = i915_get_device_id(dev->pci_device);
1379
1380         if (i915_get_bridge_dev(dev)) {
1381                 drm_free(dev_priv, DRM_MEM_DRIVER);
1382                 return (-EIO);
1383         }
1384         dev_priv->mm.gtt = intel_gtt_get();
1385
1386         /* Add register map (needed for suspend/resume) */
1387         mmio_bar = IS_GEN2(dev) ? 1 : 0;
1388         base = drm_get_resource_start(dev, mmio_bar);
1389         size = drm_get_resource_len(dev, mmio_bar);
1390
1391         ret = drm_addmap(dev, base, size, _DRM_REGISTERS,
1392             _DRM_KERNEL | _DRM_DRIVER, &dev_priv->mmio_map);
1393
1394         /* The i915 workqueue is primarily used for batched retirement of
1395          * requests (and thus managing bo) once the task has been completed
1396          * by the GPU. i915_gem_retire_requests() is called directly when we
1397          * need high-priority retirement, such as waiting for an explicit
1398          * bo.
1399          *
1400          * It is also used for periodic low-priority events, such as
1401          * idle-timers and recording error state.
1402          *
1403          * All tasks on the workqueue are expected to acquire the dev mutex
1404          * so there is no point in running more than one instance of the
1405          * workqueue at any time.  Use an ordered one.
1406          */
1407         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
1408         if (dev_priv->wq == NULL) {
1409                 DRM_ERROR("Failed to create our workqueue.\n");
1410                 ret = -ENOMEM;
1411                 goto out_mtrrfree;
1412         }
1413
1414         /* This must be called before any calls to HAS_PCH_* */
1415         intel_detect_pch(dev);
1416
1417         intel_irq_init(dev);
1418         intel_gt_init(dev);
1419
1420         /* Try to make sure MCHBAR is enabled before poking at it */
1421         intel_setup_mchbar(dev);
1422         intel_setup_gmbus(dev);
1423         intel_opregion_setup(dev);
1424
1425         intel_setup_bios(dev);
1426
1427         i915_gem_load(dev);
1428
1429         /* On the 945G/GM, the chipset reports the MSI capability on the
1430          * integrated graphics even though the support isn't actually there
1431          * according to the published specs.  It doesn't appear to function
1432          * correctly in testing on 945G.
1433          * This may be a side effect of MSI having been made available for PEG
1434          * and the registers being closely associated.
1435          *
1436          * According to chipset errata, on the 965GM, MSI interrupts may
1437          * be lost or delayed, but we use them anyways to avoid
1438          * stuck interrupts on some machines.
1439          */
1440
1441         lockinit(&dev_priv->irq_lock, "userirq", 0, LK_CANRECURSE);
1442         lockinit(&dev_priv->error_lock, "915err", 0, LK_CANRECURSE);
1443         spin_init(&dev_priv->rps.lock, "i915initrps");
1444         spin_init(&dev_priv->dpio_lock, "i915initdpio");
1445
1446         lockinit(&dev_priv->rps.hw_lock, "i915 rps.hw_lock", 0, LK_CANRECURSE);
1447
1448         /* Init HWS */
1449         if (!I915_NEED_GFX_HWS(dev)) {
1450                 ret = i915_init_phys_hws(dev);
1451                 if (ret != 0) {
1452                         drm_rmmap(dev, dev_priv->mmio_map);
1453                         drm_free(dev_priv, DRM_MEM_DRIVER);
1454                         return ret;
1455                 }
1456         }
1457
1458         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1459                 dev_priv->num_pipe = 3;
1460         else if (IS_MOBILE(dev) || !IS_GEN2(dev))
1461                 dev_priv->num_pipe = 2;
1462         else
1463                 dev_priv->num_pipe = 1;
1464
1465         ret = drm_vblank_init(dev, dev_priv->num_pipe);
1466         if (ret)
1467                 goto out_gem_unload;
1468
1469         /* Start out suspended */
1470         dev_priv->mm.suspended = 1;
1471
1472         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1473                 ret = i915_load_modeset_init(dev);
1474                 if (ret < 0) {
1475                         DRM_ERROR("failed to init modeset\n");
1476                         goto out_gem_unload;
1477                 }
1478         }
1479
1480         /* Must be done after probing outputs */
1481         intel_opregion_init(dev);
1482
1483         setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
1484                     (unsigned long) dev);
1485
1486         if (IS_GEN5(dev))
1487                 intel_gpu_ips_init(dev_priv);
1488
1489         return 0;
1490
1491 out_gem_unload:
1492         intel_teardown_gmbus(dev);
1493         intel_teardown_mchbar(dev);
1494         destroy_workqueue(dev_priv->wq);
1495 out_mtrrfree:
1496         return ret;
1497 }
1498
1499 int i915_driver_unload(struct drm_device *dev)
1500 {
1501         struct drm_i915_private *dev_priv = dev->dev_private;
1502         int ret;
1503
1504         intel_gpu_ips_teardown();
1505
1506         DRM_LOCK(dev);
1507         ret = i915_gpu_idle(dev);
1508         if (ret)
1509                 DRM_ERROR("failed to idle hardware: %d\n", ret);
1510         i915_gem_retire_requests(dev);
1511         DRM_UNLOCK(dev);
1512
1513         /* Cancel the retire work handler, which should be idle now. */
1514         cancel_delayed_work_sync(&dev_priv->mm.retire_work);
1515
1516         i915_free_hws(dev);
1517
1518         intel_teardown_mchbar(dev);
1519
1520         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1521                 intel_fbdev_fini(dev);
1522                 intel_modeset_cleanup(dev);
1523         }
1524
1525         /* Free error state after interrupts are fully disabled. */
1526         del_timer_sync(&dev_priv->hangcheck_timer);
1527         cancel_work_sync(&dev_priv->error_work);
1528         i915_destroy_error_state(dev);
1529
1530         intel_opregion_fini(dev);
1531
1532         if (drm_core_check_feature(dev, DRIVER_MODESET)) {
1533                 /* Flush any outstanding unpin_work. */
1534                 flush_workqueue(dev_priv->wq);
1535
1536                 DRM_LOCK(dev);
1537                 i915_gem_free_all_phys_object(dev);
1538                 i915_gem_cleanup_ringbuffer(dev);
1539                 DRM_UNLOCK(dev);
1540                 i915_gem_cleanup_aliasing_ppgtt(dev);
1541                 drm_mm_takedown(&dev_priv->mm.stolen);
1542
1543                 intel_cleanup_overlay(dev);
1544
1545                 if (!I915_NEED_GFX_HWS(dev))
1546                         i915_free_hws(dev);
1547         }
1548
1549         i915_gem_unload(dev);
1550
1551         bus_generic_detach(dev->dev);
1552         drm_rmmap(dev, dev_priv->mmio_map);
1553         intel_teardown_gmbus(dev);
1554
1555         destroy_workqueue(dev_priv->wq);
1556
1557         drm_free(dev->dev_private, DRM_MEM_DRIVER);
1558
1559         return 0;
1560 }
1561
1562 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1563 {
1564         struct drm_i915_file_private *file_priv;
1565
1566         DRM_DEBUG_DRIVER("\n");
1567         file_priv = kmalloc(sizeof(*file_priv), DRM_MEM_FILES,
1568             M_WAITOK | M_ZERO);
1569         if (!file_priv)
1570                 return -ENOMEM;
1571
1572         file->driver_priv = file_priv;
1573
1574         spin_init(&file_priv->mm.lock, "i915_priv");
1575         INIT_LIST_HEAD(&file_priv->mm.request_list);
1576
1577         idr_init(&file_priv->context_idr);
1578
1579         return 0;
1580 }
1581
1582 /**
1583  * i915_driver_lastclose - clean up after all DRM clients have exited
1584  * @dev: DRM device
1585  *
1586  * Take care of cleaning up after all DRM clients have exited.  In the
1587  * mode setting case, we want to restore the kernel's initial mode (just
1588  * in case the last client left us in a bad state).
1589  *
1590  * Additionally, in the non-mode setting case, we'll tear down the GTT
1591  * and DMA structures, since the kernel won't be using them, and clea
1592  * up any GEM state.
1593  */
1594 void i915_driver_lastclose(struct drm_device * dev)
1595 {
1596         drm_i915_private_t *dev_priv = dev->dev_private;
1597
1598         if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
1599 #if 1
1600                 KIB_NOTYET();
1601 #else
1602                 drm_fb_helper_restore();
1603                 vga_switcheroo_process_delayed_switch();
1604 #endif
1605                 return;
1606         }
1607         i915_gem_lastclose(dev);
1608         i915_dma_cleanup(dev);
1609 }
1610
1611 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
1612 {
1613
1614         i915_gem_release(dev, file_priv);
1615 }
1616
1617 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
1618 {
1619         struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
1620
1621         spin_uninit(&i915_file_priv->mm.lock);
1622         drm_free(i915_file_priv, DRM_MEM_FILES);
1623 }
1624
1625 struct drm_ioctl_desc i915_ioctls[] = {
1626         DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1627         DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
1628         DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
1629         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
1630         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
1631         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
1632         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH),
1633         DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1634         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1635         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1636         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1637         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1638         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1639         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1640         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  i915_vblank_pipe_get, DRM_AUTH),
1641         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1642         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1643         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1644         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
1645         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
1646         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1647         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1648         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
1649         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED),
1650         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED),
1651         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
1652         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1653         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1654         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
1655         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
1656         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
1657         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
1658         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
1659         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
1660         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
1661         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
1662         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
1663         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
1664         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
1665         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
1666         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1667         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1668         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1669         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, intel_sprite_get_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1670         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED),
1671 };
1672
1673 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1674
1675 /*
1676  * This is really ugly: Because old userspace abused the linux agp interface to
1677  * manage the gtt, we need to claim that all intel devices are agp.  For
1678  * otherwise the drm core refuses to initialize the agp support code.
1679  */
1680 int i915_driver_device_is_agp(struct drm_device * dev)
1681 {
1682         return 1;
1683 }