sys/dev/agp/agp_i810.c

   1 /*
   2  * Copyright (c) 2000 Doug Rabson
   3  * Copyright (c) 2000 Ruslan Ermilov
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  *
  27  *      $FreeBSD: src/sys/dev/agp/agp_i810.c,v 1.43 2007/11/12 21:51:36 jhb Exp $
  28  *      $DragonFly: src/sys/dev/agp/agp_i810.c,v 1.19 2008/10/03 08:56:58 hasso Exp $
  29  */
  30
  31 /*
  32  * Fixes for 830/845G support: David Dawes <dawes@xfree86.org>
  33  * 852GM/855GM/865G support added by David Dawes <dawes@xfree86.org>
  34  */
  35
  36 #include "opt_bus.h"
  37
  38 #include <sys/param.h>
  39 #include <sys/systm.h>
  40 #include <sys/malloc.h>
  41 #include <sys/kernel.h>
  42 #include <sys/bus.h>
  43 #include <sys/lock.h>
  44 #include <sys/rman.h>
  45
  46 #include <bus/pci/pcivar.h>
  47 #include <bus/pci/pcireg.h>
  48 #include "agppriv.h"
  49 #include "agpreg.h"
  50
  51 #include <vm/vm.h>
  52 #include <vm/vm_object.h>
  53 #include <vm/vm_page.h>
  54 #include <vm/vm_pageout.h>
  55 #include <vm/pmap.h>
  56
  57 #include <machine/md_var.h>
  58
  59 #define bus_read_1(r, o) \
  60                    bus_space_read_1((r)->r_bustag, (r)->r_bushandle, (o))
  61 #define bus_read_4(r, o) \
  62                    bus_space_read_4((r)->r_bustag, (r)->r_bushandle, (o))
  63 #define bus_write_4(r, o, v) \
  64                     bus_space_write_4((r)->r_bustag, (r)->r_bushandle, (o), (v))
  65
  66 MALLOC_DECLARE(M_AGP);
  67
  68 enum {
  69         CHIP_I810,      /* i810/i815 */
  70         CHIP_I830,      /* 830M/845G */
  71         CHIP_I855,      /* 852GM/855GM/865G */
  72         CHIP_I915,      /* 915G/915GM */
  73         CHIP_I965,      /* G965 */
  74         CHIP_G33,       /* G33/Q33/Q35 */
  75         CHIP_G4X,       /* G45/Q45 */
  76 };
  77
  78 /* The i810 through i855 have the registers at BAR 1, and the GATT gets
  79  * allocated by us.  The i915 has registers in BAR 0 and the GATT is at the
  80  * start of the stolen memory, and should only be accessed by the OS through
  81  * BAR 3.  The G965 has registers and GATT in the same BAR (0) -- first 512KB
  82  * is registers, second 512KB is GATT.
  83  */
  84 static struct resource_spec agp_i810_res_spec[] = {
  85         { SYS_RES_MEMORY, AGP_I810_MMADR, RF_ACTIVE | RF_SHAREABLE },
  86         { -1, 0 }
  87 };
  88
  89 static struct resource_spec agp_i915_res_spec[] = {
  90         { SYS_RES_MEMORY, AGP_I915_MMADR, RF_ACTIVE | RF_SHAREABLE },
  91         { SYS_RES_MEMORY, AGP_I915_GTTADR, RF_ACTIVE | RF_SHAREABLE },
  92         { -1, 0 }
  93 };
  94
  95 static struct resource_spec agp_i965_res_spec[] = {
  96         { SYS_RES_MEMORY, AGP_I965_GTTMMADR, RF_ACTIVE | RF_SHAREABLE },
  97         { -1, 0 }
  98 };
  99
 100 struct agp_i810_softc {
 101         struct agp_softc agp;
 102         u_int32_t initial_aperture;     /* aperture size at startup */
 103         struct agp_gatt *gatt;
 104         int chiptype;                   /* i810-like or i830 */
 105         u_int32_t dcache_size;          /* i810 only */
 106         u_int32_t stolen;               /* number of i830/845 gtt entries for stolen memory */
 107         device_t bdev;                  /* bridge device */
 108
 109         void *argb_cursor;              /* contigmalloc area for ARGB cursor */
 110
 111         struct resource_spec * sc_res_spec;
 112         struct resource *sc_res[2];
 113 };
 114
 115 /* For adding new devices, devid is the id of the graphics controller
 116  * (pci:0:2:0, for example).  The placeholder (usually at pci:0:2:1) for the
 117  * second head should never be added.  The bridge_offset is the offset to
 118  * subtract from devid to get the id of the hostb that the device is on.
 119  */
 120 static const struct agp_i810_match {
 121         int devid;
 122         int chiptype;
 123         int bridge_offset;
 124         char *name;
 125 } agp_i810_matches[] = {
 126         {0x71218086, CHIP_I810, 0x00010000,
 127             "Intel 82810 (i810 GMCH) SVGA controller"},
 128         {0x71238086, CHIP_I810, 0x00010000,
 129             "Intel 82810-DC100 (i810-DC100 GMCH) SVGA controller"},
 130         {0x71258086, CHIP_I810, 0x00010000,
 131             "Intel 82810E (i810E GMCH) SVGA controller"},
 132         {0x11328086, CHIP_I810, 0x00020000,
 133             "Intel 82815 (i815 GMCH) SVGA controller"},
 134         {0x35778086, CHIP_I830, 0x00020000,
 135             "Intel 82830M (830M GMCH) SVGA controller"},
 136         {0x25628086, CHIP_I830, 0x00020000,
 137             "Intel 82845M (845M GMCH) SVGA controller"},
 138         {0x35828086, CHIP_I855, 0x00020000,
 139             "Intel 82852/855GM SVGA controller"},
 140         {0x25728086, CHIP_I855, 0x00020000,
 141             "Intel 82865G (865G GMCH) SVGA controller"},
 142         {0x25828086, CHIP_I915, 0x00020000,
 143             "Intel 82915G (915G GMCH) SVGA controller"},
 144         {0x258A8086, CHIP_I915, 0x00020000,
 145             "Intel E7221 SVGA controller"},
 146         {0x25928086, CHIP_I915, 0x00020000,
 147             "Intel 82915GM (915GM GMCH) SVGA controller"},
 148         {0x27728086, CHIP_I915, 0x00020000,
 149             "Intel 82945G (945G GMCH) SVGA controller"},
 150         {0x27A28086, CHIP_I915, 0x00020000,
 151             "Intel 82945GM (945GM GMCH) SVGA controller"},
 152         {0x27AE8086, CHIP_I915, 0x00020000,
 153             "Intel 945GME SVGA controller"},
 154         {0x29728086, CHIP_I965, 0x00020000,
 155             "Intel 946GZ SVGA controller"},
 156         {0x29828086, CHIP_I965, 0x00020000,
 157             "Intel G965 SVGA controller"},
 158         {0x29928086, CHIP_I965, 0x00020000,
 159             "Intel Q965 SVGA controller"},
 160         {0x29A28086, CHIP_I965, 0x00020000,
 161             "Intel G965 SVGA controller"},
 162         {0x29B28086, CHIP_G33, 0x00020000,
 163             "Intel Q35 SVGA controller"},
 164         {0x29C28086, CHIP_G33, 0x00020000,
 165             "Intel G33 SVGA controller"},
 166         {0x29D28086, CHIP_G33, 0x00020000,
 167             "Intel Q33 SVGA controller"},
 168         {0x2A028086, CHIP_I965, 0x00020000,
 169             "Intel GM965 SVGA controller"},
 170         {0x2A128086, CHIP_I965, 0x00020000,
 171             "Intel GME965 SVGA controller"},
 172         {0x2A428086, CHIP_G4X, 0x00020000,
 173             "Intel GM45 SVGA controller"},
 174         {0x2E028086, CHIP_G4X, 0x00020000,
 175             "Intel 4 Series SVGA controller"},
 176         {0x2E128086, CHIP_G4X, 0x00020000,
 177             "Intel Q45 SVGA controller"},
 178         {0x2E228086, CHIP_G4X, 0x00020000,
 179             "Intel G45 SVGA controller"},
 180         {0, 0, 0, NULL}
 181 };
 182
 183 static const struct agp_i810_match*
 184 agp_i810_match(device_t dev)
 185 {
 186         int i, devid;
 187
 188         if (pci_get_class(dev) != PCIC_DISPLAY
 189             || pci_get_subclass(dev) != PCIS_DISPLAY_VGA)
 190                 return NULL;
 191
 192         devid = pci_get_devid(dev);
 193         for (i = 0; agp_i810_matches[i].devid != 0; i++) {
 194                 if (agp_i810_matches[i].devid == devid)
 195                     break;
 196         }
 197         if (agp_i810_matches[i].devid == 0)
 198                 return NULL;
 199         else
 200                 return &agp_i810_matches[i];
 201 }
 202
 203 /*
 204  * Find bridge device.
 205  */
 206 static device_t
 207 agp_i810_find_bridge(device_t dev)
 208 {
 209         device_t *children, child;
 210         int nchildren, i;
 211         u_int32_t devid;
 212         const struct agp_i810_match *match;
 213
 214         match = agp_i810_match(dev);
 215         devid = match->devid - match->bridge_offset;
 216
 217         if (device_get_children(device_get_parent(dev), &children, &nchildren))
 218                 return 0;
 219
 220         for (i = 0; i < nchildren; i++) {
 221                 child = children[i];
 222
 223                 if (pci_get_devid(child) == devid) {
 224                         kfree(children, M_TEMP);
 225                         return child;
 226                 }
 227         }
 228         kfree(children, M_TEMP);
 229         return 0;
 230 }
 231
 232 static void
 233 agp_i810_identify(driver_t *driver, device_t parent)
 234 {
 235
 236         if (device_find_child(parent, "agp", -1) == NULL &&
 237             agp_i810_match(parent))
 238                 device_add_child(parent, "agp", -1);
 239 }
 240
 241 static int
 242 agp_i810_probe(device_t dev)
 243 {
 244         device_t bdev;
 245         const struct agp_i810_match *match;
 246         u_int8_t smram;
 247         int gcc1, deven;
 248
 249         if (resource_disabled("agp", device_get_unit(dev)))
 250                 return (ENXIO);
 251         match = agp_i810_match(dev);
 252         if (match == NULL)
 253                 return ENXIO;
 254
 255         bdev = agp_i810_find_bridge(dev);
 256         if (!bdev) {
 257                 if (bootverbose)
 258                         kprintf("I810: can't find bridge device\n");
 259                 return ENXIO;
 260         }
 261
 262         /*
 263          * checking whether internal graphics device has been activated.
 264          */
 265         switch (match->chiptype) {
 266         case CHIP_I810:
 267                 smram = pci_read_config(bdev, AGP_I810_SMRAM, 1);
 268                 if ((smram & AGP_I810_SMRAM_GMS) ==
 269                     AGP_I810_SMRAM_GMS_DISABLED) {
 270                         if (bootverbose)
 271                                 kprintf("I810: disabled, not probing\n");
 272                         return ENXIO;
 273                 }
 274                 break;
 275         case CHIP_I830:
 276         case CHIP_I855:
 277                 gcc1 = pci_read_config(bdev, AGP_I830_GCC1, 1);
 278                 if ((gcc1 & AGP_I830_GCC1_DEV2) ==
 279                     AGP_I830_GCC1_DEV2_DISABLED) {
 280                         if (bootverbose)
 281                                 kprintf("I830: disabled, not probing\n");
 282                         return ENXIO;
 283                 }
 284                 break;
 285         case CHIP_I915:
 286         case CHIP_I965:
 287         case CHIP_G33:
 288         case CHIP_G4X:
 289                 deven = pci_read_config(bdev, AGP_I915_DEVEN, 4);
 290                 if ((deven & AGP_I915_DEVEN_D2F0) ==
 291                     AGP_I915_DEVEN_D2F0_DISABLED) {
 292                         if (bootverbose)
 293                                 kprintf("I915: disabled, not probing\n");
 294                         return ENXIO;
 295                 }
 296                 break;
 297         }
 298
 299         device_verbose(dev);
 300         if (match->devid == 0x35828086) {
 301                 switch (pci_read_config(dev, AGP_I85X_CAPID, 1)) {
 302                 case AGP_I855_GME:
 303                         device_set_desc(dev,
 304                             "Intel 82855GME (855GME GMCH) SVGA controller");
 305                         break;
 306                 case AGP_I855_GM:
 307                         device_set_desc(dev,
 308                             "Intel 82855GM (855GM GMCH) SVGA controller");
 309                         break;
 310                 case AGP_I852_GME:
 311                         device_set_desc(dev,
 312                             "Intel 82852GME (852GME GMCH) SVGA controller");
 313                         break;
 314                 case AGP_I852_GM:
 315                         device_set_desc(dev,
 316                             "Intel 82852GM (852GM GMCH) SVGA controller");
 317                         break;
 318                 default:
 319                         device_set_desc(dev,
 320                             "Intel 8285xM (85xGM GMCH) SVGA controller");
 321                         break;
 322                 }
 323         } else {
 324                 device_set_desc(dev, match->name);
 325         }
 326
 327         return BUS_PROBE_DEFAULT;
 328 }
 329
 330 static void
 331 agp_i810_dump_regs(device_t dev)
 332 {
 333         struct agp_i810_softc *sc = device_get_softc(dev);
 334
 335         device_printf(dev, "AGP_I810_PGTBL_CTL: %08x\n",
 336             bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL));
 337
 338         switch (sc->chiptype) {
 339         case CHIP_I810:
 340                 device_printf(dev, "AGP_I810_MISCC: 0x%04x\n",
 341                     pci_read_config(sc->bdev, AGP_I810_MISCC, 2));
 342                 break;
 343         case CHIP_I830:
 344                 device_printf(dev, "AGP_I830_GCC1: 0x%02x\n",
 345                     pci_read_config(sc->bdev, AGP_I830_GCC1, 1));
 346                 break;
 347         case CHIP_I855:
 348                 device_printf(dev, "AGP_I855_GCC1: 0x%02x\n",
 349                     pci_read_config(sc->bdev, AGP_I855_GCC1, 1));
 350                 break;
 351         case CHIP_I915:
 352         case CHIP_I965:
 353         case CHIP_G33:
 354         case CHIP_G4X:
 355                 device_printf(dev, "AGP_I855_GCC1: 0x%02x\n",
 356                     pci_read_config(sc->bdev, AGP_I855_GCC1, 1));
 357                 device_printf(dev, "AGP_I915_MSAC: 0x%02x\n",
 358                     pci_read_config(sc->bdev, AGP_I915_MSAC, 1));
 359                 break;
 360         }
 361         device_printf(dev, "Aperture resource size: %d bytes\n",
 362             AGP_GET_APERTURE(dev));
 363 }
 364
 365 static int
 366 agp_i810_attach(device_t dev)
 367 {
 368         struct agp_i810_softc *sc = device_get_softc(dev);
 369         struct agp_gatt *gatt;
 370         const struct agp_i810_match *match;
 371         int error;
 372
 373         sc->bdev = agp_i810_find_bridge(dev);
 374         if (!sc->bdev)
 375                 return ENOENT;
 376
 377         match = agp_i810_match(dev);
 378         sc->chiptype = match->chiptype;
 379
 380         switch (sc->chiptype) {
 381         case CHIP_I810:
 382         case CHIP_I830:
 383         case CHIP_I855:
 384                 sc->sc_res_spec = agp_i810_res_spec;
 385                 agp_set_aperture_resource(dev, AGP_APBASE);
 386                 break;
 387         case CHIP_I915:
 388         case CHIP_G33:
 389                 sc->sc_res_spec = agp_i915_res_spec;
 390                 agp_set_aperture_resource(dev, AGP_I915_GMADR);
 391                 break;
 392         case CHIP_I965:
 393         case CHIP_G4X:
 394                 sc->sc_res_spec = agp_i965_res_spec;
 395                 agp_set_aperture_resource(dev, AGP_I915_GMADR);
 396                 break;
 397         }
 398
 399         error = agp_generic_attach(dev);
 400         if (error)
 401                 return error;
 402
 403         if (sc->chiptype != CHIP_I965 && sc->chiptype != CHIP_G33 &&
 404             sc->chiptype != CHIP_G4X && ptoa((vm_paddr_t)Maxmem) > 0xfffffffful)
 405         {
 406                 device_printf(dev, "agp_i810.c does not support physical "
 407                     "memory above 4GB.\n");
 408                 return ENOENT;
 409         }
 410
 411         if (bus_alloc_resources(dev, sc->sc_res_spec, sc->sc_res)) {
 412                 agp_generic_detach(dev);
 413                 return ENODEV;
 414         }
 415
 416         sc->initial_aperture = AGP_GET_APERTURE(dev);
 417         if (sc->initial_aperture == 0) {
 418                 device_printf(dev, "bad initial aperture size, disabling\n");
 419                 return ENXIO;
 420         }
 421
 422         gatt = kmalloc( sizeof(struct agp_gatt), M_AGP, M_INTWAIT);
 423         sc->gatt = gatt;
 424
 425         gatt->ag_entries = AGP_GET_APERTURE(dev) >> AGP_PAGE_SHIFT;
 426
 427         if ( sc->chiptype == CHIP_I810 ) {
 428                 /* Some i810s have on-chip memory called dcache */
 429                 if (bus_read_1(sc->sc_res[0], AGP_I810_DRT) &
 430                     AGP_I810_DRT_POPULATED)
 431                         sc->dcache_size = 4 * 1024 * 1024;
 432                 else
 433                         sc->dcache_size = 0;
 434
 435                 /* According to the specs the gatt on the i810 must be 64k */
 436                 gatt->ag_virtual = contigmalloc( 64 * 1024, M_AGP, 0,
 437                                         0, ~0, PAGE_SIZE, 0);
 438                 if (!gatt->ag_virtual) {
 439                         if (bootverbose)
 440                                 device_printf(dev, "contiguous allocation failed\n");
 441                         bus_release_resources(dev, sc->sc_res_spec,
 442                             sc->sc_res);
 443                         kfree(gatt, M_AGP);
 444                         agp_generic_detach(dev);
 445                         return ENOMEM;
 446                 }
 447                 bzero(gatt->ag_virtual, gatt->ag_entries * sizeof(u_int32_t));
 448
 449                 gatt->ag_physical = vtophys((vm_offset_t) gatt->ag_virtual);
 450                 agp_flush_cache();
 451                 /* Install the GATT. */
 452                 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL,
 453                     gatt->ag_physical | 1);
 454         } else if ( sc->chiptype == CHIP_I830 ) {
 455                 /* The i830 automatically initializes the 128k gatt on boot. */
 456                 unsigned int gcc1, pgtblctl;
 457
 458                 gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 1);
 459                 switch (gcc1 & AGP_I830_GCC1_GMS) {
 460                         case AGP_I830_GCC1_GMS_STOLEN_512:
 461                                 sc->stolen = (512 - 132) * 1024 / 4096;
 462                                 break;
 463                         case AGP_I830_GCC1_GMS_STOLEN_1024:
 464                                 sc->stolen = (1024 - 132) * 1024 / 4096;
 465                                 break;
 466                         case AGP_I830_GCC1_GMS_STOLEN_8192:
 467                                 sc->stolen = (8192 - 132) * 1024 / 4096;
 468                                 break;
 469                         default:
 470                                 sc->stolen = 0;
 471                                 device_printf(dev, "unknown memory configuration, disabling\n");
 472                                 bus_release_resources(dev, sc->sc_res_spec,
 473                                     sc->sc_res);
 474                                 kfree(gatt, M_AGP);
 475                                 agp_generic_detach(dev);
 476                                 return EINVAL;
 477                 }
 478                 if (sc->stolen > 0) {
 479                         device_printf(dev, "detected %dk stolen memory\n",
 480                             sc->stolen * 4);
 481                 }
 482                 device_printf(dev, "aperture size is %dM\n",
 483                     sc->initial_aperture / 1024 / 1024);
 484
 485                 /* GATT address is already in there, make sure it's enabled */
 486                 pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
 487                 pgtblctl |= 1;
 488                 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl);
 489
 490                 gatt->ag_physical = pgtblctl & ~1;
 491         } else if (sc->chiptype == CHIP_I855 || sc->chiptype == CHIP_I915 ||
 492             sc->chiptype == CHIP_I965 || sc->chiptype == CHIP_G33 ||
 493             sc->chiptype == CHIP_G4X) {
 494                 unsigned int gcc1, pgtblctl, stolen, gtt_size;
 495
 496                 /* Stolen memory is set up at the beginning of the aperture by
 497                  * the BIOS, consisting of the GATT followed by 4kb for the
 498                  * BIOS display.
 499                  */
 500                 switch (sc->chiptype) {
 501                 case CHIP_I855:
 502                         gtt_size = 128;
 503                         break;
 504                 case CHIP_I915:
 505                         gtt_size = 256;
 506                         break;
 507                 case CHIP_I965:
 508                         switch (bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL) &
 509                             AGP_I810_PGTBL_SIZE_MASK) {
 510                         case AGP_I810_PGTBL_SIZE_128KB:
 511                                 gtt_size = 128;
 512                                 break;
 513                         case AGP_I810_PGTBL_SIZE_256KB:
 514                                 gtt_size = 256;
 515                                 break;
 516                         case AGP_I810_PGTBL_SIZE_512KB:
 517                                 gtt_size = 512;
 518                                 break;
 519                         case AGP_I965_PGTBL_SIZE_1MB:
 520                                 gtt_size = 1024;
 521                                 break;
 522                         case AGP_I965_PGTBL_SIZE_2MB:
 523                                 gtt_size = 2048;
 524                                 break;
 525                         case AGP_I965_PGTBL_SIZE_1_5MB:
 526                                 gtt_size = 1024 + 512;
 527                                 break;
 528                         default:
 529                                 device_printf(dev, "Bad PGTBL size\n");
 530                                 bus_release_resources(dev, sc->sc_res_spec,
 531                                     sc->sc_res);
 532                                 kfree(gatt, M_AGP);
 533                                 agp_generic_detach(dev);
 534                                 return EINVAL;
 535                         }
 536                         break;
 537                 case CHIP_G33:
 538                         gcc1 = pci_read_config(sc->bdev, AGP_I855_GCC1, 2);
 539                         switch (gcc1 & AGP_G33_MGGC_GGMS_MASK) {
 540                         case AGP_G33_MGGC_GGMS_SIZE_1M:
 541                                 gtt_size = 1024;
 542                                 break;
 543                         case AGP_G33_MGGC_GGMS_SIZE_2M:
 544                                 gtt_size = 2048;
 545                                 break;
 546                         default:
 547                                 device_printf(dev, "Bad PGTBL size\n");
 548                                 bus_release_resources(dev, sc->sc_res_spec,
 549                                     sc->sc_res);
 550                                 kfree(gatt, M_AGP);
 551                                 agp_generic_detach(dev);
 552                                 return EINVAL;
 553                         }
 554                         break;
 555                 case CHIP_G4X:
 556                         gtt_size = 0;
 557                         break;
 558                 default:
 559                         device_printf(dev, "Bad chiptype\n");
 560                         bus_release_resources(dev, sc->sc_res_spec,
 561                             sc->sc_res);
 562                         kfree(gatt, M_AGP);
 563                         agp_generic_detach(dev);
 564                         return EINVAL;
 565                 }
 566
 567                 /* GCC1 is called MGGC on i915+ */
 568                 gcc1 = pci_read_config(sc->bdev, AGP_I855_GCC1, 1);
 569                 switch (gcc1 & AGP_I855_GCC1_GMS) {
 570                 case AGP_I855_GCC1_GMS_STOLEN_1M:
 571                         stolen = 1024;
 572                         break;
 573                 case AGP_I855_GCC1_GMS_STOLEN_4M:
 574                         stolen = 4 * 1024;
 575                         break;
 576                 case AGP_I855_GCC1_GMS_STOLEN_8M:
 577                         stolen = 8 * 1024;
 578                         break;
 579                 case AGP_I855_GCC1_GMS_STOLEN_16M:
 580                         stolen = 16 * 1024;
 581                         break;
 582                 case AGP_I855_GCC1_GMS_STOLEN_32M:
 583                         stolen = 32 * 1024;
 584                         break;
 585                 case AGP_I915_GCC1_GMS_STOLEN_48M:
 586                         if (sc->chiptype == CHIP_I915 ||
 587                             sc->chiptype == CHIP_I965 ||
 588                             sc->chiptype == CHIP_G33 ||
 589                             sc->chiptype == CHIP_G4X) {
 590                                 stolen = 48 * 1024;
 591                         } else {
 592                                 stolen = 0;
 593                         }
 594                         break;
 595                 case AGP_I915_GCC1_GMS_STOLEN_64M:
 596                         if (sc->chiptype == CHIP_I915 ||
 597                             sc->chiptype == CHIP_I965 ||
 598                             sc->chiptype == CHIP_G33 ||
 599                             sc->chiptype == CHIP_G4X) {
 600                                 stolen = 64 * 1024;
 601                         } else {
 602                                 stolen = 0;
 603                         }
 604                         break;
 605                 case AGP_G33_GCC1_GMS_STOLEN_128M:
 606                         if (sc->chiptype == CHIP_I965 ||
 607                             sc->chiptype == CHIP_G33 ||
 608                             sc->chiptype == CHIP_G4X) {
 609                                 stolen = 128 * 1024;
 610                         } else {
 611                                 stolen = 0;
 612                         }
 613                         break;
 614                 case AGP_G33_GCC1_GMS_STOLEN_256M:
 615                         if (sc->chiptype == CHIP_I965 ||
 616                             sc->chiptype == CHIP_G33 ||
 617                             sc->chiptype == CHIP_G4X) {
 618                                 stolen = 256 * 1024;
 619                         } else {
 620                                 stolen = 0;
 621                         }
 622                         break;
 623                 case AGP_G4X_GCC1_GMS_STOLEN_96M:
 624                         if (sc->chiptype == CHIP_I965 ||
 625                             sc->chiptype == CHIP_G4X) {
 626                                 stolen = 96 * 1024;
 627                         } else {
 628                                 stolen = 0;
 629                         }
 630                         break;
 631                 case AGP_G4X_GCC1_GMS_STOLEN_160M:
 632                         if (sc->chiptype == CHIP_I965 ||
 633                             sc->chiptype == CHIP_G4X) {
 634                                 stolen = 160 * 1024;
 635                         } else {
 636                                 stolen = 0;
 637                         }
 638                         break;
 639                 case AGP_G4X_GCC1_GMS_STOLEN_224M:
 640                         if (sc->chiptype == CHIP_I965 ||
 641                             sc->chiptype == CHIP_G4X) {
 642                                 stolen = 224 * 1024;
 643                         } else {
 644                                 stolen = 0;
 645                         }
 646                         break;
 647                 case AGP_G4X_GCC1_GMS_STOLEN_352M:
 648                         if (sc->chiptype == CHIP_I965 ||
 649                             sc->chiptype == CHIP_G4X) {
 650                                 stolen = 352 * 1024;
 651                         } else {
 652                                 stolen = 0;
 653                         }
 654                         break;
 655                 default:
 656                         device_printf(dev, "unknown memory configuration, "
 657                             "disabling\n");
 658                         bus_release_resources(dev, sc->sc_res_spec,
 659                             sc->sc_res);
 660                         kfree(gatt, M_AGP);
 661                         agp_generic_detach(dev);
 662                         return EINVAL;
 663                 }
 664
 665                 gtt_size += 4;
 666
 667                 sc->stolen = (stolen - gtt_size) * 1024 / 4096;
 668                 if (sc->stolen > 0)
 669                         device_printf(dev, "detected %dk stolen memory\n", sc->stolen * 4);
 670                 device_printf(dev, "aperture size is %dM\n", sc->initial_aperture / 1024 / 1024);
 671
 672                 /* GATT address is already in there, make sure it's enabled */
 673                 pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
 674                 pgtblctl |= 1;
 675                 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl);
 676
 677                 gatt->ag_physical = pgtblctl & ~1;
 678         }
 679
 680         /* Add a device for the drm to attach to */
 681         /* XXX This will go away once we have vgapci */
 682         if (!device_add_child(dev, "drmsub", -1))
 683                 device_printf(dev, "could not add drm subdevice\n");
 684
 685         if (0)
 686                 agp_i810_dump_regs(dev);
 687
 688         return 0;
 689 }
 690
 691 static int
 692 agp_i810_detach(device_t dev)
 693 {
 694         struct agp_i810_softc *sc = device_get_softc(dev);
 695         device_t child;
 696
 697         agp_free_cdev(dev);
 698
 699         /* Clear the GATT base. */
 700         if ( sc->chiptype == CHIP_I810 ) {
 701                 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, 0);
 702         } else {
 703                 unsigned int pgtblctl;
 704                 pgtblctl = bus_read_4(sc->sc_res[0], AGP_I810_PGTBL_CTL);
 705                 pgtblctl &= ~1;
 706                 bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL, pgtblctl);
 707         }
 708
 709         /* Put the aperture back the way it started. */
 710         AGP_SET_APERTURE(dev, sc->initial_aperture);
 711
 712         if ( sc->chiptype == CHIP_I810 ) {
 713                 contigfree(sc->gatt->ag_virtual, 64 * 1024, M_AGP);
 714         }
 715         kfree(sc->gatt, M_AGP);
 716
 717         bus_release_resources(dev, sc->sc_res_spec, sc->sc_res);
 718         agp_free_res(dev);
 719
 720         /* XXX This will go away once we have vgapci */
 721         child = device_find_child(dev, "drmsub", 0);
 722         if (child != NULL)
 723                 device_delete_child(dev, child);
 724
 725         return 0;
 726 }
 727
 728 static int
 729 agp_i810_resume(device_t dev)
 730 {
 731         struct agp_i810_softc *sc;
 732         sc = device_get_softc(dev);
 733
 734         AGP_SET_APERTURE(dev, sc->initial_aperture);
 735
 736         /* Install the GATT. */
 737         bus_write_4(sc->sc_res[0], AGP_I810_PGTBL_CTL,
 738         sc->gatt->ag_physical | 1);
 739
 740         return (bus_generic_resume(dev));
 741 }
 742
 743 /**
 744  * Sets the PCI resource size of the aperture on i830-class and below chipsets,
 745  * while returning failure on later chipsets when an actual change is
 746  * requested.
 747  *
 748  * This whole function is likely bogus, as the kernel would probably need to
 749  * reconfigure the placement of the AGP aperture if a larger size is requested,
 750  * which doesn't happen currently.
 751  */
 752 static int
 753 agp_i810_set_aperture(device_t dev, u_int32_t aperture)
 754 {
 755         struct agp_i810_softc *sc = device_get_softc(dev);
 756         u_int16_t miscc, gcc1;
 757
 758         switch (sc->chiptype) {
 759         case CHIP_I810:
 760                 /*
 761                  * Double check for sanity.
 762                  */
 763                 if (aperture != 32 * 1024 * 1024 && aperture != 64 * 1024 * 1024) {
 764                         device_printf(dev, "bad aperture size %d\n", aperture);
 765                         return EINVAL;
 766                 }
 767
 768                 miscc = pci_read_config(sc->bdev, AGP_I810_MISCC, 2);
 769                 miscc &= ~AGP_I810_MISCC_WINSIZE;
 770                 if (aperture == 32 * 1024 * 1024)
 771                         miscc |= AGP_I810_MISCC_WINSIZE_32;
 772                 else
 773                         miscc |= AGP_I810_MISCC_WINSIZE_64;
 774
 775                 pci_write_config(sc->bdev, AGP_I810_MISCC, miscc, 2);
 776                 break;
 777         case CHIP_I830:
 778                 if (aperture != 64 * 1024 * 1024 &&
 779                     aperture != 128 * 1024 * 1024) {
 780                         device_printf(dev, "bad aperture size %d\n", aperture);
 781                         return EINVAL;
 782                 }
 783                 gcc1 = pci_read_config(sc->bdev, AGP_I830_GCC1, 2);
 784                 gcc1 &= ~AGP_I830_GCC1_GMASIZE;
 785                 if (aperture == 64 * 1024 * 1024)
 786                         gcc1 |= AGP_I830_GCC1_GMASIZE_64;
 787                 else
 788                         gcc1 |= AGP_I830_GCC1_GMASIZE_128;
 789
 790                 pci_write_config(sc->bdev, AGP_I830_GCC1, gcc1, 2);
 791                 break;
 792         case CHIP_I855:
 793         case CHIP_I915:
 794         case CHIP_I965:
 795         case CHIP_G33:
 796         case CHIP_G4X:
 797                 return agp_generic_set_aperture(dev, aperture);
 798         }
 799
 800         return 0;
 801 }
 802
 803 /**
 804  * Writes a GTT entry mapping the page at the given offset from the beginning
 805  * of the aperture to the given physical address.
 806  */
 807 static void
 808 agp_i810_write_gtt_entry(device_t dev, int offset, vm_offset_t physical,
 809     int enabled)
 810 {
 811         struct agp_i810_softc *sc = device_get_softc(dev);
 812         u_int32_t pte;
 813
 814         pte = (u_int32_t)physical | 1;
 815         if (sc->chiptype == CHIP_I965 || sc->chiptype == CHIP_G33 ||
 816             sc->chiptype == CHIP_G4X) {
 817                 pte |= (physical & 0x0000000f00000000ull) >> 28;
 818         } else {
 819                 /* If we do actually have memory above 4GB on an older system,
 820                  * crash cleanly rather than scribble on system memory,
 821                  * so we know we need to fix it.
 822                  */
 823                 KASSERT((pte & 0x0000000f00000000ull) == 0,
 824                     (">4GB physical address in agp"));
 825         }
 826
 827         switch (sc->chiptype) {
 828         case CHIP_I810:
 829         case CHIP_I830:
 830         case CHIP_I855:
 831                 bus_write_4(sc->sc_res[0],
 832                     AGP_I810_GTT + (offset >> AGP_PAGE_SHIFT) * 4, pte);
 833                 break;
 834         case CHIP_I915:
 835         case CHIP_G33:
 836                 bus_write_4(sc->sc_res[1],
 837                     (offset >> AGP_PAGE_SHIFT) * 4, pte);
 838                 break;
 839         case CHIP_I965:
 840                 bus_write_4(sc->sc_res[0],
 841                     (offset >> AGP_PAGE_SHIFT) * 4 + (512 * 1024), pte);
 842                 break;
 843         case CHIP_G4X:
 844                 bus_write_4(sc->sc_res[0],
 845                     (offset >> AGP_PAGE_SHIFT) * 4 + (2 * 1024 * 1024), pte);
 846                 break;
 847         }
 848 }
 849
 850 static int
 851 agp_i810_bind_page(device_t dev, int offset, vm_offset_t physical)
 852 {
 853         struct agp_i810_softc *sc = device_get_softc(dev);
 854
 855         if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT)) {
 856                 device_printf(dev, "failed: offset is 0x%08x, shift is %d, entries is %d\n", offset, AGP_PAGE_SHIFT, sc->gatt->ag_entries);
 857                 return EINVAL;
 858         }
 859
 860         if ( sc->chiptype != CHIP_I810 ) {
 861                 if ( (offset >> AGP_PAGE_SHIFT) < sc->stolen ) {
 862                         device_printf(dev, "trying to bind into stolen memory");
 863                         return EINVAL;
 864                 }
 865         }
 866
 867         agp_i810_write_gtt_entry(dev, offset, physical, 1);
 868
 869         return 0;
 870 }
 871
 872 static int
 873 agp_i810_unbind_page(device_t dev, int offset)
 874 {
 875         struct agp_i810_softc *sc = device_get_softc(dev);
 876
 877         if (offset < 0 || offset >= (sc->gatt->ag_entries << AGP_PAGE_SHIFT))
 878                 return EINVAL;
 879
 880         if ( sc->chiptype != CHIP_I810 ) {
 881                 if ( (offset >> AGP_PAGE_SHIFT) < sc->stolen ) {
 882                         device_printf(dev, "trying to unbind from stolen memory");
 883                         return EINVAL;
 884                 }
 885         }
 886
 887         agp_i810_write_gtt_entry(dev, offset, 0, 0);
 888
 889         return 0;
 890 }
 891
 892 /*
 893  * Writing via memory mapped registers already flushes all TLBs.
 894  */
 895 static void
 896 agp_i810_flush_tlb(device_t dev)
 897 {
 898 }
 899
 900 static int
 901 agp_i810_enable(device_t dev, u_int32_t mode)
 902 {
 903
 904         return 0;
 905 }
 906
 907 static struct agp_memory *
 908 agp_i810_alloc_memory(device_t dev, int type, vm_size_t size)
 909 {
 910         struct agp_i810_softc *sc = device_get_softc(dev);
 911         struct agp_memory *mem;
 912
 913         if ((size & (AGP_PAGE_SIZE - 1)) != 0)
 914                 return 0;
 915
 916         if (sc->agp.as_allocated + size > sc->agp.as_maxmem)
 917                 return 0;
 918
 919         if (type == 1) {
 920                 /*
 921                  * Mapping local DRAM into GATT.
 922                  */
 923                 if ( sc->chiptype != CHIP_I810 )
 924                         return 0;
 925                 if (size != sc->dcache_size)
 926                         return 0;
 927         } else if (type == 2) {
 928                 /*
 929                  * Type 2 is the contiguous physical memory type, that hands
 930                  * back a physical address.  This is used for cursors on i810.
 931                  * Hand back as many single pages with physical as the user
 932                  * wants, but only allow one larger allocation (ARGB cursor)
 933                  * for simplicity.
 934                  */
 935                 if (size != AGP_PAGE_SIZE) {
 936                         if (sc->argb_cursor != NULL)
 937                                 return 0;
 938
 939                         /* Allocate memory for ARGB cursor, if we can. */
 940                         sc->argb_cursor = contigmalloc(size, M_AGP,
 941                            0, 0, ~0, PAGE_SIZE, 0);
 942                         if (sc->argb_cursor == NULL)
 943                                 return 0;
 944                 }
 945         }
 946
 947         mem = kmalloc(sizeof *mem, M_AGP, M_INTWAIT);
 948         mem->am_id = sc->agp.as_nextid++;
 949         mem->am_size = size;
 950         mem->am_type = type;
 951         if (type != 1 && (type != 2 || size == AGP_PAGE_SIZE))
 952                 mem->am_obj = vm_object_allocate(OBJT_DEFAULT,
 953                                                  atop(round_page(size)));
 954         else
 955                 mem->am_obj = 0;
 956
 957         if (type == 2) {
 958                 if (size == AGP_PAGE_SIZE) {
 959                         /*
 960                          * Allocate and wire down the page now so that we can
 961                          * get its physical address.
 962                          */
 963                         vm_page_t m;
 964
 965                         m = vm_page_grab(mem->am_obj, 0,
 966                                          VM_ALLOC_NORMAL|VM_ALLOC_ZERO|VM_ALLOC_RETRY);
 967                         if ((m->flags & PG_ZERO) == 0)
 968                                 vm_page_zero_fill(m);
 969                         vm_page_wire(m);
 970                         mem->am_physical = VM_PAGE_TO_PHYS(m);
 971                         vm_page_wakeup(m);
 972                 } else {
 973                         /* Our allocation is already nicely wired down for us.
 974                          * Just grab the physical address.
 975                          */
 976                         mem->am_physical = vtophys(sc->argb_cursor);
 977                 }
 978         } else {
 979                 mem->am_physical = 0;
 980         }
 981
 982         mem->am_offset = 0;
 983         mem->am_is_bound = 0;
 984         TAILQ_INSERT_TAIL(&sc->agp.as_memory, mem, am_link);
 985         sc->agp.as_allocated += size;
 986
 987         return mem;
 988 }
 989
 990 static int
 991 agp_i810_free_memory(device_t dev, struct agp_memory *mem)
 992 {
 993         struct agp_i810_softc *sc = device_get_softc(dev);
 994
 995         if (mem->am_is_bound)
 996                 return EBUSY;
 997
 998         if (mem->am_type == 2) {
 999                 if (mem->am_size == AGP_PAGE_SIZE) {
1000                         /*
1001                          * Unwire the page which we wired in alloc_memory.
1002                          */
1003                         vm_page_t m = vm_page_lookup(mem->am_obj, 0);
1004                         vm_page_unwire(m, 0);
1005                 } else {
1006                         contigfree(sc->argb_cursor, mem->am_size, M_AGP);
1007                         sc->argb_cursor = NULL;
1008                 }
1009         }
1010
1011         sc->agp.as_allocated -= mem->am_size;
1012         TAILQ_REMOVE(&sc->agp.as_memory, mem, am_link);
1013         if (mem->am_obj)
1014                 vm_object_deallocate(mem->am_obj);
1015         kfree(mem, M_AGP);
1016         return 0;
1017 }
1018
1019 static int
1020 agp_i810_bind_memory(device_t dev, struct agp_memory *mem,
1021                      vm_offset_t offset)
1022 {
1023         struct agp_i810_softc *sc = device_get_softc(dev);
1024         vm_offset_t i;
1025
1026         /* Do some sanity checks first. */
1027         if (offset < 0 || (offset & (AGP_PAGE_SIZE - 1)) != 0 ||
1028             offset + mem->am_size > AGP_GET_APERTURE(dev)) {
1029                 device_printf(dev, "binding memory at bad offset %#x\n",
1030                     (int)offset);
1031                 return EINVAL;
1032         }
1033
1034         if (mem->am_type == 2 && mem->am_size != AGP_PAGE_SIZE) {
1035                 lockmgr(&sc->agp.as_lock, LK_EXCLUSIVE);
1036                 if (mem->am_is_bound) {
1037                         lockmgr(&sc->agp.as_lock, LK_RELEASE);
1038                         return EINVAL;
1039                 }
1040                 /* The memory's already wired down, just stick it in the GTT. */
1041                 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
1042                         agp_i810_write_gtt_entry(dev, offset + i,
1043                             mem->am_physical + i, 1);
1044                 }
1045                 agp_flush_cache();
1046                 mem->am_offset = offset;
1047                 mem->am_is_bound = 1;
1048                 lockmgr(&sc->agp.as_lock, LK_RELEASE);
1049                 return 0;
1050         }
1051
1052         if (mem->am_type != 1)
1053                 return agp_generic_bind_memory(dev, mem, offset);
1054
1055         if ( sc->chiptype != CHIP_I810 )
1056                 return EINVAL;
1057
1058         for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
1059                 bus_write_4(sc->sc_res[0],
1060                     AGP_I810_GTT + (i >> AGP_PAGE_SHIFT) * 4, i | 3);
1061         }
1062
1063         return 0;
1064 }
1065
1066 static int
1067 agp_i810_unbind_memory(device_t dev, struct agp_memory *mem)
1068 {
1069         struct agp_i810_softc *sc = device_get_softc(dev);
1070         vm_offset_t i;
1071
1072         if (mem->am_type == 2 && mem->am_size != AGP_PAGE_SIZE) {
1073                 lockmgr(&sc->agp.as_lock, LK_EXCLUSIVE);
1074                 if (!mem->am_is_bound) {
1075                         lockmgr(&sc->agp.as_lock, LK_RELEASE);
1076                         return EINVAL;
1077                 }
1078
1079                 for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
1080                         agp_i810_write_gtt_entry(dev, mem->am_offset + i,
1081                             0, 0);
1082                 }
1083                 agp_flush_cache();
1084                 mem->am_is_bound = 0;
1085                 lockmgr(&sc->agp.as_lock, LK_RELEASE);
1086                 return 0;
1087         }
1088
1089         if (mem->am_type != 1)
1090                 return agp_generic_unbind_memory(dev, mem);
1091
1092         if ( sc->chiptype != CHIP_I810 )
1093                 return EINVAL;
1094
1095         for (i = 0; i < mem->am_size; i += AGP_PAGE_SIZE) {
1096                 bus_write_4(sc->sc_res[0],
1097                     AGP_I810_GTT + (i >> AGP_PAGE_SHIFT) * 4, 0);
1098         }
1099
1100         return 0;
1101 }
1102
1103 static device_method_t agp_i810_methods[] = {
1104         /* Device interface */
1105         DEVMETHOD(device_identify,      agp_i810_identify),
1106         DEVMETHOD(device_probe,         agp_i810_probe),
1107         DEVMETHOD(device_attach,        agp_i810_attach),
1108         DEVMETHOD(device_detach,        agp_i810_detach),
1109         DEVMETHOD(device_suspend,       bus_generic_suspend),
1110         DEVMETHOD(device_resume,        agp_i810_resume),
1111
1112         /* AGP interface */
1113         DEVMETHOD(agp_get_aperture,     agp_generic_get_aperture),
1114         DEVMETHOD(agp_set_aperture,     agp_i810_set_aperture),
1115         DEVMETHOD(agp_bind_page,        agp_i810_bind_page),
1116         DEVMETHOD(agp_unbind_page,      agp_i810_unbind_page),
1117         DEVMETHOD(agp_flush_tlb,        agp_i810_flush_tlb),
1118         DEVMETHOD(agp_enable,           agp_i810_enable),
1119         DEVMETHOD(agp_alloc_memory,     agp_i810_alloc_memory),
1120         DEVMETHOD(agp_free_memory,      agp_i810_free_memory),
1121         DEVMETHOD(agp_bind_memory,      agp_i810_bind_memory),
1122         DEVMETHOD(agp_unbind_memory,    agp_i810_unbind_memory),
1123
1124         { 0, 0 }
1125 };
1126
1127 static driver_t agp_i810_driver = {
1128         "agp",
1129         agp_i810_methods,
1130         sizeof(struct agp_i810_softc),
1131 };
1132
1133 static devclass_t agp_devclass;
1134
1135 DRIVER_MODULE(agp_i810, pci, agp_i810_driver, agp_devclass, 0, 0);
1136 MODULE_DEPEND(agp_i810, agp, 1, 1, 1);
1137 MODULE_DEPEND(agp_i810, pci, 1, 1, 1);