2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Keith Packard <keithp@keithp.com>
28 #include <linux/i2c.h>
29 #include <linux/export.h>
31 #include <drm/drm_crtc.h>
32 #include <drm/drm_crtc_helper.h>
33 #include <drm/drm_edid.h>
34 #include "intel_drv.h"
35 #include <drm/i915_drm.h>
38 #define DP_LINK_CHECK_TIMEOUT (10 * 1000)
41 * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
42 * @intel_dp: DP struct
44 * If a CPU or PCH DP output is attached to an eDP panel, this function
45 * will return true, and false otherwise.
47 static bool is_edp(struct intel_dp *intel_dp)
49 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
51 return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
55 * is_pch_edp - is the port on the PCH and attached to an eDP panel?
56 * @intel_dp: DP struct
58 * Returns true if the given DP struct corresponds to a PCH DP port attached
59 * to an eDP panel, false otherwise. Helpful for determining whether we
60 * may need FDI resources for a given DP output or not.
62 static bool is_pch_edp(struct intel_dp *intel_dp)
64 return intel_dp->is_pch_edp;
68 * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
69 * @intel_dp: DP struct
71 * Returns true if the given DP struct corresponds to a CPU eDP port.
73 static bool is_cpu_edp(struct intel_dp *intel_dp)
75 return is_edp(intel_dp) && !is_pch_edp(intel_dp);
78 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
80 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
82 return intel_dig_port->base.base.dev;
85 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
87 return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
91 * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
92 * @encoder: DRM encoder
94 * Return true if @encoder corresponds to a PCH attached eDP panel. Needed
97 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
99 struct intel_dp *intel_dp;
104 intel_dp = enc_to_intel_dp(encoder);
106 return is_pch_edp(intel_dp);
109 static void intel_dp_link_down(struct intel_dp *intel_dp);
112 intel_edp_link_config(struct intel_encoder *intel_encoder,
113 int *lane_num, int *link_bw)
115 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
117 *lane_num = intel_dp->lane_count;
118 *link_bw = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
122 intel_edp_target_clock(struct intel_encoder *intel_encoder,
123 struct drm_display_mode *mode)
125 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
126 struct intel_connector *intel_connector = intel_dp->attached_connector;
128 if (intel_connector->panel.fixed_mode)
129 return intel_connector->panel.fixed_mode->clock;
135 intel_dp_max_link_bw(struct intel_dp *intel_dp)
137 int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
139 switch (max_link_bw) {
140 case DP_LINK_BW_1_62:
144 max_link_bw = DP_LINK_BW_1_62;
151 * The units on the numbers in the next two are... bizarre. Examples will
152 * make it clearer; this one parallels an example in the eDP spec.
154 * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
156 * 270000 * 1 * 8 / 10 == 216000
158 * The actual data capacity of that configuration is 2.16Gbit/s, so the
159 * units are decakilobits. ->clock in a drm_display_mode is in kilohertz -
160 * or equivalently, kilopixels per second - so for 1680x1050R it'd be
161 * 119000. At 18bpp that's 2142000 kilobits per second.
163 * Thus the strange-looking division by 10 in intel_dp_link_required, to
164 * get the result in decakilobits instead of kilobits.
168 intel_dp_link_required(int pixel_clock, int bpp)
170 return (pixel_clock * bpp + 9) / 10;
174 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
176 return (max_link_clock * max_lanes * 8) / 10;
180 intel_dp_adjust_dithering(struct intel_dp *intel_dp,
181 struct drm_display_mode *mode,
185 drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
186 int max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
187 int max_rate, mode_rate;
189 mode_rate = intel_dp_link_required(mode->clock, 24);
190 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
192 if (mode_rate > max_rate) {
193 mode_rate = intel_dp_link_required(mode->clock, 18);
194 if (mode_rate > max_rate)
199 |= INTEL_MODE_DP_FORCE_6BPC;
208 intel_dp_mode_valid(struct drm_connector *connector,
209 struct drm_display_mode *mode)
211 struct intel_dp *intel_dp = intel_attached_dp(connector);
212 struct intel_connector *intel_connector = to_intel_connector(connector);
213 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
215 if (is_edp(intel_dp) && fixed_mode) {
216 if (mode->hdisplay > fixed_mode->hdisplay)
219 if (mode->vdisplay > fixed_mode->vdisplay)
223 if (!intel_dp_adjust_dithering(intel_dp, mode, false))
224 return MODE_CLOCK_HIGH;
226 if (mode->clock < 10000)
227 return MODE_CLOCK_LOW;
229 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
230 return MODE_H_ILLEGAL;
236 pack_aux(uint8_t *src, int src_bytes)
243 for (i = 0; i < src_bytes; i++)
244 v |= ((uint32_t) src[i]) << ((3-i) * 8);
249 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
254 for (i = 0; i < dst_bytes; i++)
255 dst[i] = src >> ((3-i) * 8);
258 /* hrawclock is 1/4 the FSB frequency */
260 intel_hrawclk(struct drm_device *dev)
262 struct drm_i915_private *dev_priv = dev->dev_private;
265 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
266 if (IS_VALLEYVIEW(dev))
269 clkcfg = I915_READ(CLKCFG);
270 switch (clkcfg & CLKCFG_FSB_MASK) {
279 case CLKCFG_FSB_1067:
281 case CLKCFG_FSB_1333:
283 /* these two are just a guess; one of them might be right */
284 case CLKCFG_FSB_1600:
285 case CLKCFG_FSB_1600_ALT:
292 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
294 struct drm_device *dev = intel_dp_to_dev(intel_dp);
295 struct drm_i915_private *dev_priv = dev->dev_private;
297 return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
300 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
302 struct drm_device *dev = intel_dp_to_dev(intel_dp);
303 struct drm_i915_private *dev_priv = dev->dev_private;
305 return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
309 intel_dp_check_edp(struct intel_dp *intel_dp)
311 struct drm_device *dev = intel_dp_to_dev(intel_dp);
312 struct drm_i915_private *dev_priv = dev->dev_private;
314 if (!is_edp(intel_dp))
316 if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
317 WARN(1, "eDP powered off while attempting aux channel communication.\n");
318 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
319 I915_READ(PCH_PP_STATUS),
320 I915_READ(PCH_PP_CONTROL));
325 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
327 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
328 struct drm_device *dev = intel_dig_port->base.base.dev;
329 struct drm_i915_private *dev_priv = dev->dev_private;
330 uint32_t ch_ctl = intel_dp->output_reg + 0x10;
334 if (IS_HASWELL(dev)) {
335 switch (intel_dig_port->port) {
337 ch_ctl = DPA_AUX_CH_CTL;
340 ch_ctl = PCH_DPB_AUX_CH_CTL;
343 ch_ctl = PCH_DPC_AUX_CH_CTL;
346 ch_ctl = PCH_DPD_AUX_CH_CTL;
353 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
355 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
356 msecs_to_jiffies(10));
358 done = wait_for_atomic(C, 10) == 0;
360 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
368 intel_dp_aux_ch(struct intel_dp *intel_dp,
369 uint8_t *send, int send_bytes,
370 uint8_t *recv, int recv_size)
372 uint32_t output_reg = intel_dp->output_reg;
373 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
374 struct drm_device *dev = intel_dig_port->base.base.dev;
375 struct drm_i915_private *dev_priv = dev->dev_private;
376 uint32_t ch_ctl = output_reg + 0x10;
377 uint32_t ch_data = ch_ctl + 4;
378 int i, ret, recv_bytes;
380 uint32_t aux_clock_divider;
382 bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
384 /* dp aux is extremely sensitive to irq latency, hence request the
385 * lowest possible wakeup latency and so prevent the cpu from going into
388 pm_qos_update_request(&dev_priv->pm_qos, 0);
390 if (IS_HASWELL(dev)) {
391 switch (intel_dig_port->port) {
393 ch_ctl = DPA_AUX_CH_CTL;
394 ch_data = DPA_AUX_CH_DATA1;
397 ch_ctl = PCH_DPB_AUX_CH_CTL;
398 ch_data = PCH_DPB_AUX_CH_DATA1;
401 ch_ctl = PCH_DPC_AUX_CH_CTL;
402 ch_data = PCH_DPC_AUX_CH_DATA1;
405 ch_ctl = PCH_DPD_AUX_CH_CTL;
406 ch_data = PCH_DPD_AUX_CH_DATA1;
413 intel_dp_check_edp(intel_dp);
414 /* The clock divider is based off the hrawclk,
415 * and would like to run at 2MHz. So, take the
416 * hrawclk value and divide by 2 and use that
418 * Note that PCH attached eDP panels should use a 125MHz input
421 if (is_cpu_edp(intel_dp)) {
423 aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
424 else if (IS_VALLEYVIEW(dev))
425 aux_clock_divider = 100;
426 else if (IS_GEN6(dev) || IS_GEN7(dev))
427 aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
429 aux_clock_divider = 225; /* eDP input clock at 450Mhz */
430 } else if (HAS_PCH_SPLIT(dev))
431 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
433 aux_clock_divider = intel_hrawclk(dev) / 2;
440 /* Try to wait for any previous AUX channel activity */
441 for (try = 0; try < 3; try++) {
442 status = I915_READ_NOTRACE(ch_ctl);
443 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
449 WARN(1, "dp_aux_ch not started status 0x%08x\n",
455 /* Must try at least 3 times according to DP spec */
456 for (try = 0; try < 5; try++) {
457 /* Load the send data into the aux channel data registers */
458 for (i = 0; i < send_bytes; i += 4)
459 I915_WRITE(ch_data + i,
460 pack_aux(send + i, send_bytes - i));
462 /* Send the command and wait for it to complete */
464 DP_AUX_CH_CTL_SEND_BUSY |
465 (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
466 DP_AUX_CH_CTL_TIME_OUT_400us |
467 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
468 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
469 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
471 DP_AUX_CH_CTL_TIME_OUT_ERROR |
472 DP_AUX_CH_CTL_RECEIVE_ERROR);
474 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
476 /* Clear done status and any errors */
480 DP_AUX_CH_CTL_TIME_OUT_ERROR |
481 DP_AUX_CH_CTL_RECEIVE_ERROR);
483 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
484 DP_AUX_CH_CTL_RECEIVE_ERROR))
486 if (status & DP_AUX_CH_CTL_DONE)
490 if ((status & DP_AUX_CH_CTL_DONE) == 0) {
491 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
496 /* Check for timeout or receive error.
497 * Timeouts occur when the sink is not connected
499 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
500 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
505 /* Timeouts occur when the device isn't connected, so they're
506 * "normal" -- don't fill the kernel log with these */
507 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
508 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
513 /* Unload any bytes sent back from the other side */
514 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
515 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
516 if (recv_bytes > recv_size)
517 recv_bytes = recv_size;
519 for (i = 0; i < recv_bytes; i += 4)
520 unpack_aux(I915_READ(ch_data + i),
521 recv + i, recv_bytes - i);
525 pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
530 /* Write data to the aux channel in native mode */
532 intel_dp_aux_native_write(struct intel_dp *intel_dp,
533 uint16_t address, uint8_t *send, int send_bytes)
540 intel_dp_check_edp(intel_dp);
543 msg[0] = AUX_NATIVE_WRITE << 4;
544 msg[1] = address >> 8;
545 msg[2] = address & 0xff;
546 msg[3] = send_bytes - 1;
547 memcpy(&msg[4], send, send_bytes);
548 msg_bytes = send_bytes + 4;
550 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
553 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
555 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
563 /* Write a single byte to the aux channel in native mode */
565 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
566 uint16_t address, uint8_t byte)
568 return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
571 /* read bytes from a native aux channel */
573 intel_dp_aux_native_read(struct intel_dp *intel_dp,
574 uint16_t address, uint8_t *recv, int recv_bytes)
583 intel_dp_check_edp(intel_dp);
584 msg[0] = AUX_NATIVE_READ << 4;
585 msg[1] = address >> 8;
586 msg[2] = address & 0xff;
587 msg[3] = recv_bytes - 1;
590 reply_bytes = recv_bytes + 1;
593 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
600 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
601 memcpy(recv, reply + 1, ret - 1);
604 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
612 intel_dp_i2c_aux_ch(struct device *adapter, int mode,
613 uint8_t write_byte, uint8_t *read_byte)
615 struct iic_dp_aux_data *data = device_get_softc(adapter);
616 struct intel_dp *intel_dp = data->priv;
617 uint16_t address = data->address;
625 intel_dp_check_edp(intel_dp);
626 /* Set up the command byte */
627 if (mode & MODE_I2C_READ)
628 msg[0] = AUX_I2C_READ << 4;
630 msg[0] = AUX_I2C_WRITE << 4;
632 if (!(mode & MODE_I2C_STOP))
633 msg[0] |= AUX_I2C_MOT << 4;
635 msg[1] = address >> 8;
656 for (retry = 0; retry < 5; retry++) {
657 ret = intel_dp_aux_ch(intel_dp,
661 DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
665 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
666 case AUX_NATIVE_REPLY_ACK:
667 /* I2C-over-AUX Reply field is only valid
668 * when paired with AUX ACK.
671 case AUX_NATIVE_REPLY_NACK:
672 DRM_DEBUG_KMS("aux_ch native nack\n");
674 case AUX_NATIVE_REPLY_DEFER:
678 DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
683 switch (reply[0] & AUX_I2C_REPLY_MASK) {
684 case AUX_I2C_REPLY_ACK:
685 if (mode == MODE_I2C_READ) {
686 *read_byte = reply[1];
688 return (0/*reply_bytes - 1*/);
689 case AUX_I2C_REPLY_NACK:
690 DRM_DEBUG_KMS("aux_i2c nack\n");
692 case AUX_I2C_REPLY_DEFER:
693 DRM_DEBUG_KMS("aux_i2c defer\n");
697 DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
702 DRM_ERROR("too many retries, giving up\n");
707 intel_dp_i2c_init(struct intel_dp *intel_dp,
708 struct intel_connector *intel_connector, const char *name)
712 DRM_DEBUG_KMS("i2c_init %s\n", name);
714 ironlake_edp_panel_vdd_on(intel_dp);
715 ret = iic_dp_aux_add_bus(intel_connector->base.dev->dev, name,
716 intel_dp_i2c_aux_ch, intel_dp, &intel_dp->dp_iic_bus,
718 ironlake_edp_panel_vdd_off(intel_dp, false);
723 intel_dp_mode_fixup(struct drm_encoder *encoder,
724 const struct drm_display_mode *mode,
725 struct drm_display_mode *adjusted_mode)
727 struct drm_device *dev = encoder->dev;
728 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
729 struct intel_connector *intel_connector = intel_dp->attached_connector;
730 int lane_count, clock;
731 int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
732 int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
734 static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
736 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
737 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
739 intel_pch_panel_fitting(dev,
740 intel_connector->panel.fitting_mode,
741 mode, adjusted_mode);
744 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
747 DRM_DEBUG_KMS("DP link computation with max lane count %i "
748 "max bw %02x pixel clock %iKHz\n",
749 max_lane_count, bws[max_clock], adjusted_mode->clock);
751 if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true))
754 bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
756 if (intel_dp->color_range_auto) {
759 * CEA-861-E - 5.1 Default Encoding Parameters
760 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
762 if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1)
763 intel_dp->color_range = DP_COLOR_RANGE_16_235;
765 intel_dp->color_range = 0;
768 if (intel_dp->color_range)
769 adjusted_mode->private_flags |= INTEL_MODE_LIMITED_COLOR_RANGE;
771 mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
773 for (clock = 0; clock <= max_clock; clock++) {
774 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
776 drm_dp_bw_code_to_link_rate(bws[clock]);
777 int link_avail = intel_dp_max_data_rate(link_bw_clock,
780 if (mode_rate <= link_avail) {
781 intel_dp->link_bw = bws[clock];
782 intel_dp->lane_count = lane_count;
783 adjusted_mode->clock = link_bw_clock;
784 DRM_DEBUG_KMS("DP link bw %02x lane "
785 "count %d clock %d bpp %d\n",
786 intel_dp->link_bw, intel_dp->lane_count,
787 adjusted_mode->clock, bpp);
788 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
789 mode_rate, link_avail);
799 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
800 struct drm_display_mode *adjusted_mode)
802 struct drm_device *dev = crtc->dev;
803 struct intel_encoder *intel_encoder;
804 struct intel_dp *intel_dp;
805 struct drm_i915_private *dev_priv = dev->dev_private;
806 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
808 struct intel_link_m_n m_n;
809 int pipe = intel_crtc->pipe;
810 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
814 * Find the lane count in the intel_encoder private
816 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
817 intel_dp = enc_to_intel_dp(&intel_encoder->base);
819 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
820 intel_encoder->type == INTEL_OUTPUT_EDP)
822 lane_count = intel_dp->lane_count;
827 target_clock = mode->clock;
828 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
829 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
830 target_clock = intel_edp_target_clock(intel_encoder,
837 * Compute the GMCH and Link ratios. The '3' here is
838 * the number of bytes_per_pixel post-LUT, which we always
839 * set up for 8-bits of R/G/B, or 3 bytes total.
841 intel_link_compute_m_n(intel_crtc->bpp, lane_count,
842 target_clock, adjusted_mode->clock, &m_n);
844 if (IS_HASWELL(dev)) {
845 I915_WRITE(PIPE_DATA_M1(cpu_transcoder),
846 TU_SIZE(m_n.tu) | m_n.gmch_m);
847 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
848 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
849 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
850 } else if (HAS_PCH_SPLIT(dev)) {
851 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
852 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
853 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
854 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
855 } else if (IS_VALLEYVIEW(dev)) {
856 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
857 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
858 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
859 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
861 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
862 TU_SIZE(m_n.tu) | m_n.gmch_m);
863 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
864 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
865 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
869 void intel_dp_init_link_config(struct intel_dp *intel_dp)
871 memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
872 intel_dp->link_configuration[0] = intel_dp->link_bw;
873 intel_dp->link_configuration[1] = intel_dp->lane_count;
874 intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
876 * Check for DPCD version > 1.1 and enhanced framing support
878 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
879 (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
880 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
884 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
886 struct drm_device *dev = crtc->dev;
887 struct drm_i915_private *dev_priv = dev->dev_private;
890 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
891 dpa_ctl = I915_READ(DP_A);
892 dpa_ctl &= ~DP_PLL_FREQ_MASK;
894 if (clock < 200000) {
895 /* For a long time we've carried around a ILK-DevA w/a for the
896 * 160MHz clock. If we're really unlucky, it's still required.
898 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
899 dpa_ctl |= DP_PLL_FREQ_160MHZ;
901 dpa_ctl |= DP_PLL_FREQ_270MHZ;
904 I915_WRITE(DP_A, dpa_ctl);
911 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
912 struct drm_display_mode *adjusted_mode)
914 struct drm_device *dev = encoder->dev;
915 struct drm_i915_private *dev_priv = dev->dev_private;
916 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
917 struct drm_crtc *crtc = encoder->crtc;
918 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
921 * There are four kinds of DP registers:
928 * IBX PCH and CPU are the same for almost everything,
929 * except that the CPU DP PLL is configured in this
932 * CPT PCH is quite different, having many bits moved
933 * to the TRANS_DP_CTL register instead. That
934 * configuration happens (oddly) in ironlake_pch_enable
937 /* Preserve the BIOS-computed detected bit. This is
938 * supposed to be read-only.
940 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
942 /* Handle DP bits in common between all three register formats */
943 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
945 switch (intel_dp->lane_count) {
947 intel_dp->DP |= DP_PORT_WIDTH_1;
950 intel_dp->DP |= DP_PORT_WIDTH_2;
953 intel_dp->DP |= DP_PORT_WIDTH_4;
956 if (intel_dp->has_audio) {
957 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
958 pipe_name(intel_crtc->pipe));
959 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
960 intel_write_eld(encoder, adjusted_mode);
963 intel_dp_init_link_config(intel_dp);
965 /* Split out the IBX/CPU vs CPT settings */
967 if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
968 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
969 intel_dp->DP |= DP_SYNC_HS_HIGH;
970 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
971 intel_dp->DP |= DP_SYNC_VS_HIGH;
972 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
974 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
975 intel_dp->DP |= DP_ENHANCED_FRAMING;
977 intel_dp->DP |= intel_crtc->pipe << 29;
979 /* don't miss out required setting for eDP */
980 if (adjusted_mode->clock < 200000)
981 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
983 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
984 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
985 if (!HAS_PCH_SPLIT(dev))
986 intel_dp->DP |= intel_dp->color_range;
988 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
989 intel_dp->DP |= DP_SYNC_HS_HIGH;
990 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
991 intel_dp->DP |= DP_SYNC_VS_HIGH;
992 intel_dp->DP |= DP_LINK_TRAIN_OFF;
994 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
995 intel_dp->DP |= DP_ENHANCED_FRAMING;
997 if (intel_crtc->pipe == 1)
998 intel_dp->DP |= DP_PIPEB_SELECT;
1000 if (is_cpu_edp(intel_dp)) {
1001 /* don't miss out required setting for eDP */
1002 if (adjusted_mode->clock < 200000)
1003 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
1005 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
1008 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1011 if (is_cpu_edp(intel_dp))
1012 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
1015 #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1016 #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE)
1018 #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK)
1019 #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1021 #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1022 #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE)
1024 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
1028 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1029 struct drm_i915_private *dev_priv = dev->dev_private;
1031 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1033 I915_READ(PCH_PP_STATUS),
1034 I915_READ(PCH_PP_CONTROL));
1036 if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
1037 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1038 I915_READ(PCH_PP_STATUS),
1039 I915_READ(PCH_PP_CONTROL));
1043 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
1045 DRM_DEBUG_KMS("Wait for panel power on\n");
1046 ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1049 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
1051 DRM_DEBUG_KMS("Wait for panel power off time\n");
1052 ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1055 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
1057 DRM_DEBUG_KMS("Wait for panel power cycle\n");
1058 ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1062 /* Read the current pp_control value, unlocking the register if it
1066 static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
1068 u32 control = I915_READ(PCH_PP_CONTROL);
1070 control &= ~PANEL_UNLOCK_MASK;
1071 control |= PANEL_UNLOCK_REGS;
1075 void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1077 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1078 struct drm_i915_private *dev_priv = dev->dev_private;
1081 if (!is_edp(intel_dp))
1083 DRM_DEBUG_KMS("Turn eDP VDD on\n");
1085 WARN(intel_dp->want_panel_vdd,
1086 "eDP VDD already requested on\n");
1088 intel_dp->want_panel_vdd = true;
1090 if (ironlake_edp_have_panel_vdd(intel_dp)) {
1091 DRM_DEBUG_KMS("eDP VDD already on\n");
1095 if (!ironlake_edp_have_panel_power(intel_dp))
1096 ironlake_wait_panel_power_cycle(intel_dp);
1098 pp = ironlake_get_pp_control(dev_priv);
1099 pp |= EDP_FORCE_VDD;
1100 I915_WRITE(PCH_PP_CONTROL, pp);
1101 POSTING_READ(PCH_PP_CONTROL);
1102 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1103 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1106 * If the panel wasn't on, delay before accessing aux channel
1108 if (!ironlake_edp_have_panel_power(intel_dp)) {
1109 DRM_DEBUG_KMS("eDP was not running\n");
1110 msleep(intel_dp->panel_power_up_delay);
1114 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1116 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1117 struct drm_i915_private *dev_priv = dev->dev_private;
1120 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1122 if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1123 pp = ironlake_get_pp_control(dev_priv);
1124 pp &= ~EDP_FORCE_VDD;
1125 I915_WRITE(PCH_PP_CONTROL, pp);
1126 POSTING_READ(PCH_PP_CONTROL);
1128 /* Make sure sequencer is idle before allowing subsequent activity */
1129 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1130 I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1132 msleep(intel_dp->panel_power_down_delay);
1136 static void ironlake_panel_vdd_work(struct work_struct *__work)
1138 struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1139 struct intel_dp, panel_vdd_work);
1140 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1142 mutex_lock(&dev->mode_config.mutex);
1143 ironlake_panel_vdd_off_sync(intel_dp);
1144 mutex_unlock(&dev->mode_config.mutex);
1147 void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1149 if (!is_edp(intel_dp))
1152 DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1153 WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1155 intel_dp->want_panel_vdd = false;
1158 ironlake_panel_vdd_off_sync(intel_dp);
1161 * Queue the timer to fire a long
1162 * time from now (relative to the power down delay)
1163 * to keep the panel power up across a sequence of operations
1165 schedule_delayed_work(&intel_dp->panel_vdd_work,
1166 msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1170 void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1172 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1173 struct drm_i915_private *dev_priv = dev->dev_private;
1176 if (!is_edp(intel_dp))
1179 DRM_DEBUG_KMS("Turn eDP power on\n");
1181 if (ironlake_edp_have_panel_power(intel_dp)) {
1182 DRM_DEBUG_KMS("eDP power already on\n");
1186 ironlake_wait_panel_power_cycle(intel_dp);
1188 pp = ironlake_get_pp_control(dev_priv);
1190 /* ILK workaround: disable reset around power sequence */
1191 pp &= ~PANEL_POWER_RESET;
1192 I915_WRITE(PCH_PP_CONTROL, pp);
1193 POSTING_READ(PCH_PP_CONTROL);
1196 pp |= POWER_TARGET_ON;
1198 pp |= PANEL_POWER_RESET;
1200 I915_WRITE(PCH_PP_CONTROL, pp);
1201 POSTING_READ(PCH_PP_CONTROL);
1203 ironlake_wait_panel_on(intel_dp);
1206 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1207 I915_WRITE(PCH_PP_CONTROL, pp);
1208 POSTING_READ(PCH_PP_CONTROL);
1212 void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1214 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1215 struct drm_i915_private *dev_priv = dev->dev_private;
1218 if (!is_edp(intel_dp))
1221 DRM_DEBUG_KMS("Turn eDP power off\n");
1223 WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1225 pp = ironlake_get_pp_control(dev_priv);
1226 /* We need to switch off panel power _and_ force vdd, for otherwise some
1227 * panels get very unhappy and cease to work. */
1228 pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1229 I915_WRITE(PCH_PP_CONTROL, pp);
1230 POSTING_READ(PCH_PP_CONTROL);
1232 intel_dp->want_panel_vdd = false;
1234 ironlake_wait_panel_off(intel_dp);
1237 void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1239 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1240 struct drm_device *dev = intel_dig_port->base.base.dev;
1241 struct drm_i915_private *dev_priv = dev->dev_private;
1242 int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
1245 if (!is_edp(intel_dp))
1248 DRM_DEBUG_KMS("\n");
1250 * If we enable the backlight right away following a panel power
1251 * on, we may see slight flicker as the panel syncs with the eDP
1252 * link. So delay a bit to make sure the image is solid before
1253 * allowing it to appear.
1255 msleep(intel_dp->backlight_on_delay);
1256 pp = ironlake_get_pp_control(dev_priv);
1257 pp |= EDP_BLC_ENABLE;
1258 I915_WRITE(PCH_PP_CONTROL, pp);
1259 POSTING_READ(PCH_PP_CONTROL);
1261 intel_panel_enable_backlight(dev, pipe);
1264 void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1266 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1267 struct drm_i915_private *dev_priv = dev->dev_private;
1270 if (!is_edp(intel_dp))
1273 intel_panel_disable_backlight(dev);
1275 DRM_DEBUG_KMS("\n");
1276 pp = ironlake_get_pp_control(dev_priv);
1277 pp &= ~EDP_BLC_ENABLE;
1278 I915_WRITE(PCH_PP_CONTROL, pp);
1279 POSTING_READ(PCH_PP_CONTROL);
1280 msleep(intel_dp->backlight_off_delay);
1283 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1285 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1286 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1287 struct drm_device *dev = crtc->dev;
1288 struct drm_i915_private *dev_priv = dev->dev_private;
1291 assert_pipe_disabled(dev_priv,
1292 to_intel_crtc(crtc)->pipe);
1294 DRM_DEBUG_KMS("\n");
1295 dpa_ctl = I915_READ(DP_A);
1296 WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1297 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1299 /* We don't adjust intel_dp->DP while tearing down the link, to
1300 * facilitate link retraining (e.g. after hotplug). Hence clear all
1301 * enable bits here to ensure that we don't enable too much. */
1302 intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1303 intel_dp->DP |= DP_PLL_ENABLE;
1304 I915_WRITE(DP_A, intel_dp->DP);
1309 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1311 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1312 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1313 struct drm_device *dev = crtc->dev;
1314 struct drm_i915_private *dev_priv = dev->dev_private;
1317 assert_pipe_disabled(dev_priv,
1318 to_intel_crtc(crtc)->pipe);
1320 dpa_ctl = I915_READ(DP_A);
1321 WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1322 "dp pll off, should be on\n");
1323 WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1325 /* We can't rely on the value tracked for the DP register in
1326 * intel_dp->DP because link_down must not change that (otherwise link
1327 * re-training will fail. */
1328 dpa_ctl &= ~DP_PLL_ENABLE;
1329 I915_WRITE(DP_A, dpa_ctl);
1334 /* If the sink supports it, try to set the power state appropriately */
1335 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1339 /* Should have a valid DPCD by this point */
1340 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1343 if (mode != DRM_MODE_DPMS_ON) {
1344 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1347 DRM_DEBUG_DRIVER("failed to write sink power state\n");
1350 * When turning on, we need to retry for 1ms to give the sink
1353 for (i = 0; i < 3; i++) {
1354 ret = intel_dp_aux_native_write_1(intel_dp,
1364 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1365 enum i915_pipe *pipe)
1367 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1368 struct drm_device *dev = encoder->base.dev;
1369 struct drm_i915_private *dev_priv = dev->dev_private;
1370 u32 tmp = I915_READ(intel_dp->output_reg);
1372 if (!(tmp & DP_PORT_EN))
1375 if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
1376 *pipe = PORT_TO_PIPE_CPT(tmp);
1377 } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1378 *pipe = PORT_TO_PIPE(tmp);
1384 switch (intel_dp->output_reg) {
1386 trans_sel = TRANS_DP_PORT_SEL_B;
1389 trans_sel = TRANS_DP_PORT_SEL_C;
1392 trans_sel = TRANS_DP_PORT_SEL_D;
1399 trans_dp = I915_READ(TRANS_DP_CTL(i));
1400 if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1406 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1407 intel_dp->output_reg);
1413 static void intel_disable_dp(struct intel_encoder *encoder)
1415 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1417 /* Make sure the panel is off before trying to change the mode. But also
1418 * ensure that we have vdd while we switch off the panel. */
1419 ironlake_edp_panel_vdd_on(intel_dp);
1420 ironlake_edp_backlight_off(intel_dp);
1421 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1422 ironlake_edp_panel_off(intel_dp);
1424 /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1425 if (!is_cpu_edp(intel_dp))
1426 intel_dp_link_down(intel_dp);
1429 static void intel_post_disable_dp(struct intel_encoder *encoder)
1431 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1433 if (is_cpu_edp(intel_dp)) {
1434 intel_dp_link_down(intel_dp);
1435 ironlake_edp_pll_off(intel_dp);
1439 static void intel_enable_dp(struct intel_encoder *encoder)
1441 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1442 struct drm_device *dev = encoder->base.dev;
1443 struct drm_i915_private *dev_priv = dev->dev_private;
1444 uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1446 if (WARN_ON(dp_reg & DP_PORT_EN))
1449 ironlake_edp_panel_vdd_on(intel_dp);
1450 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1451 intel_dp_start_link_train(intel_dp);
1452 ironlake_edp_panel_on(intel_dp);
1453 ironlake_edp_panel_vdd_off(intel_dp, true);
1454 intel_dp_complete_link_train(intel_dp);
1455 ironlake_edp_backlight_on(intel_dp);
1458 static void intel_pre_enable_dp(struct intel_encoder *encoder)
1460 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1462 if (is_cpu_edp(intel_dp))
1463 ironlake_edp_pll_on(intel_dp);
1467 * Native read with retry for link status and receiver capability reads for
1468 * cases where the sink may still be asleep.
1471 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1472 uint8_t *recv, int recv_bytes)
1477 * Sinks are *supposed* to come up within 1ms from an off state,
1478 * but we're also supposed to retry 3 times per the spec.
1480 for (i = 0; i < 3; i++) {
1481 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1483 if (ret == recv_bytes)
1492 * Fetch AUX CH registers 0x202 - 0x207 which contain
1493 * link status information
1496 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1498 return intel_dp_aux_native_read_retry(intel_dp,
1501 DP_LINK_STATUS_SIZE);
1505 static char *voltage_names[] = {
1506 "0.4V", "0.6V", "0.8V", "1.2V"
1508 static char *pre_emph_names[] = {
1509 "0dB", "3.5dB", "6dB", "9.5dB"
1511 static char *link_train_names[] = {
1512 "pattern 1", "pattern 2", "idle", "off"
1517 * These are source-specific values; current Intel hardware supports
1518 * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1522 intel_dp_voltage_max(struct intel_dp *intel_dp)
1524 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1526 if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1527 return DP_TRAIN_VOLTAGE_SWING_800;
1528 else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1529 return DP_TRAIN_VOLTAGE_SWING_1200;
1531 return DP_TRAIN_VOLTAGE_SWING_800;
1535 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1537 struct drm_device *dev = intel_dp_to_dev(intel_dp);
1539 if (IS_HASWELL(dev)) {
1540 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1541 case DP_TRAIN_VOLTAGE_SWING_400:
1542 return DP_TRAIN_PRE_EMPHASIS_9_5;
1543 case DP_TRAIN_VOLTAGE_SWING_600:
1544 return DP_TRAIN_PRE_EMPHASIS_6;
1545 case DP_TRAIN_VOLTAGE_SWING_800:
1546 return DP_TRAIN_PRE_EMPHASIS_3_5;
1547 case DP_TRAIN_VOLTAGE_SWING_1200:
1549 return DP_TRAIN_PRE_EMPHASIS_0;
1551 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1552 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1553 case DP_TRAIN_VOLTAGE_SWING_400:
1554 return DP_TRAIN_PRE_EMPHASIS_6;
1555 case DP_TRAIN_VOLTAGE_SWING_600:
1556 case DP_TRAIN_VOLTAGE_SWING_800:
1557 return DP_TRAIN_PRE_EMPHASIS_3_5;
1559 return DP_TRAIN_PRE_EMPHASIS_0;
1562 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1563 case DP_TRAIN_VOLTAGE_SWING_400:
1564 return DP_TRAIN_PRE_EMPHASIS_6;
1565 case DP_TRAIN_VOLTAGE_SWING_600:
1566 return DP_TRAIN_PRE_EMPHASIS_6;
1567 case DP_TRAIN_VOLTAGE_SWING_800:
1568 return DP_TRAIN_PRE_EMPHASIS_3_5;
1569 case DP_TRAIN_VOLTAGE_SWING_1200:
1571 return DP_TRAIN_PRE_EMPHASIS_0;
1577 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1582 uint8_t voltage_max;
1583 uint8_t preemph_max;
1585 for (lane = 0; lane < intel_dp->lane_count; lane++) {
1586 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1587 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
1595 voltage_max = intel_dp_voltage_max(intel_dp);
1596 if (v >= voltage_max)
1597 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1599 preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1600 if (p >= preemph_max)
1601 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1603 for (lane = 0; lane < 4; lane++)
1604 intel_dp->train_set[lane] = v | p;
1608 intel_gen4_signal_levels(uint8_t train_set)
1610 uint32_t signal_levels = 0;
1612 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1613 case DP_TRAIN_VOLTAGE_SWING_400:
1615 signal_levels |= DP_VOLTAGE_0_4;
1617 case DP_TRAIN_VOLTAGE_SWING_600:
1618 signal_levels |= DP_VOLTAGE_0_6;
1620 case DP_TRAIN_VOLTAGE_SWING_800:
1621 signal_levels |= DP_VOLTAGE_0_8;
1623 case DP_TRAIN_VOLTAGE_SWING_1200:
1624 signal_levels |= DP_VOLTAGE_1_2;
1627 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1628 case DP_TRAIN_PRE_EMPHASIS_0:
1630 signal_levels |= DP_PRE_EMPHASIS_0;
1632 case DP_TRAIN_PRE_EMPHASIS_3_5:
1633 signal_levels |= DP_PRE_EMPHASIS_3_5;
1635 case DP_TRAIN_PRE_EMPHASIS_6:
1636 signal_levels |= DP_PRE_EMPHASIS_6;
1638 case DP_TRAIN_PRE_EMPHASIS_9_5:
1639 signal_levels |= DP_PRE_EMPHASIS_9_5;
1642 return signal_levels;
1645 /* Gen6's DP voltage swing and pre-emphasis control */
1647 intel_gen6_edp_signal_levels(uint8_t train_set)
1649 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1650 DP_TRAIN_PRE_EMPHASIS_MASK);
1651 switch (signal_levels) {
1652 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1653 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1654 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1655 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1656 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1657 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1658 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1659 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1660 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1661 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1662 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1663 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1664 case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1665 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1667 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1668 "0x%x\n", signal_levels);
1669 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1673 /* Gen7's DP voltage swing and pre-emphasis control */
1675 intel_gen7_edp_signal_levels(uint8_t train_set)
1677 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1678 DP_TRAIN_PRE_EMPHASIS_MASK);
1679 switch (signal_levels) {
1680 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1681 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1682 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1683 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1684 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1685 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1687 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1688 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1689 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1690 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1692 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1693 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1694 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1695 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1698 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1699 "0x%x\n", signal_levels);
1700 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1704 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1706 intel_hsw_signal_levels(uint8_t train_set)
1708 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1709 DP_TRAIN_PRE_EMPHASIS_MASK);
1710 switch (signal_levels) {
1711 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1712 return DDI_BUF_EMP_400MV_0DB_HSW;
1713 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1714 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1715 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1716 return DDI_BUF_EMP_400MV_6DB_HSW;
1717 case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1718 return DDI_BUF_EMP_400MV_9_5DB_HSW;
1720 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1721 return DDI_BUF_EMP_600MV_0DB_HSW;
1722 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1723 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1724 case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1725 return DDI_BUF_EMP_600MV_6DB_HSW;
1727 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1728 return DDI_BUF_EMP_800MV_0DB_HSW;
1729 case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1730 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1732 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1733 "0x%x\n", signal_levels);
1734 return DDI_BUF_EMP_400MV_0DB_HSW;
1738 /* Properly updates "DP" with the correct signal levels. */
1740 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
1742 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1743 struct drm_device *dev = intel_dig_port->base.base.dev;
1744 uint32_t signal_levels, mask;
1745 uint8_t train_set = intel_dp->train_set[0];
1747 if (IS_HASWELL(dev)) {
1748 signal_levels = intel_hsw_signal_levels(train_set);
1749 mask = DDI_BUF_EMP_MASK;
1750 } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1751 signal_levels = intel_gen7_edp_signal_levels(train_set);
1752 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
1753 } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1754 signal_levels = intel_gen6_edp_signal_levels(train_set);
1755 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
1757 signal_levels = intel_gen4_signal_levels(train_set);
1758 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
1761 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
1763 *DP = (*DP & ~mask) | signal_levels;
1767 intel_dp_set_link_train(struct intel_dp *intel_dp,
1768 uint32_t dp_reg_value,
1769 uint8_t dp_train_pat)
1771 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1772 struct drm_device *dev = intel_dig_port->base.base.dev;
1773 struct drm_i915_private *dev_priv = dev->dev_private;
1774 enum port port = intel_dig_port->port;
1778 if (IS_HASWELL(dev)) {
1779 temp = I915_READ(DP_TP_CTL(port));
1781 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1782 temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1784 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1786 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1787 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1788 case DP_TRAINING_PATTERN_DISABLE:
1790 if (port != PORT_A) {
1791 temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
1792 I915_WRITE(DP_TP_CTL(port), temp);
1794 if (wait_for((I915_READ(DP_TP_STATUS(port)) &
1795 DP_TP_STATUS_IDLE_DONE), 1))
1796 DRM_ERROR("Timed out waiting for DP idle patterns\n");
1798 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1801 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1804 case DP_TRAINING_PATTERN_1:
1805 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1807 case DP_TRAINING_PATTERN_2:
1808 temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1810 case DP_TRAINING_PATTERN_3:
1811 temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1814 I915_WRITE(DP_TP_CTL(port), temp);
1816 } else if (HAS_PCH_CPT(dev) &&
1817 (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1818 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1820 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1821 case DP_TRAINING_PATTERN_DISABLE:
1822 dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1824 case DP_TRAINING_PATTERN_1:
1825 dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1827 case DP_TRAINING_PATTERN_2:
1828 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1830 case DP_TRAINING_PATTERN_3:
1831 DRM_ERROR("DP training pattern 3 not supported\n");
1832 dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1837 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1839 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1840 case DP_TRAINING_PATTERN_DISABLE:
1841 dp_reg_value |= DP_LINK_TRAIN_OFF;
1843 case DP_TRAINING_PATTERN_1:
1844 dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1846 case DP_TRAINING_PATTERN_2:
1847 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1849 case DP_TRAINING_PATTERN_3:
1850 DRM_ERROR("DP training pattern 3 not supported\n");
1851 dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1856 I915_WRITE(intel_dp->output_reg, dp_reg_value);
1857 POSTING_READ(intel_dp->output_reg);
1859 intel_dp_aux_native_write_1(intel_dp,
1860 DP_TRAINING_PATTERN_SET,
1863 if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1864 DP_TRAINING_PATTERN_DISABLE) {
1865 ret = intel_dp_aux_native_write(intel_dp,
1866 DP_TRAINING_LANE0_SET,
1867 intel_dp->train_set,
1868 intel_dp->lane_count);
1869 if (ret != intel_dp->lane_count)
1876 /* Enable corresponding port and start training pattern 1 */
1878 intel_dp_start_link_train(struct intel_dp *intel_dp)
1880 struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
1881 struct drm_device *dev = encoder->dev;
1884 bool clock_recovery = false;
1885 int voltage_tries, loop_tries;
1886 uint32_t DP = intel_dp->DP;
1889 intel_ddi_prepare_link_retrain(encoder);
1891 /* Write the link configuration data */
1892 intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1893 intel_dp->link_configuration,
1894 DP_LINK_CONFIGURATION_SIZE);
1898 memset(intel_dp->train_set, 0, 4);
1902 clock_recovery = false;
1904 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1905 uint8_t link_status[DP_LINK_STATUS_SIZE];
1907 intel_dp_set_signal_levels(intel_dp, &DP);
1909 /* Set training pattern 1 */
1910 if (!intel_dp_set_link_train(intel_dp, DP,
1911 DP_TRAINING_PATTERN_1 |
1912 DP_LINK_SCRAMBLING_DISABLE))
1915 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
1916 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1917 DRM_ERROR("failed to get link status\n");
1921 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1922 DRM_DEBUG_KMS("clock recovery OK\n");
1923 clock_recovery = true;
1927 /* Check to see if we've tried the max voltage */
1928 for (i = 0; i < intel_dp->lane_count; i++)
1929 if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1931 if (i == intel_dp->lane_count) {
1933 if (loop_tries == 5) {
1934 DRM_DEBUG_KMS("too many full retries, give up\n");
1937 memset(intel_dp->train_set, 0, 4);
1942 /* Check to see if we've tried the same voltage 5 times */
1943 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1945 if (voltage_tries == 5) {
1946 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1951 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1953 /* Compute new intel_dp->train_set as requested by target */
1954 intel_get_adjust_train(intel_dp, link_status);
1961 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1963 bool channel_eq = false;
1964 int tries, cr_tries;
1965 uint32_t DP = intel_dp->DP;
1967 /* channel equalization */
1972 uint8_t link_status[DP_LINK_STATUS_SIZE];
1975 DRM_ERROR("failed to train DP, aborting\n");
1976 intel_dp_link_down(intel_dp);
1980 intel_dp_set_signal_levels(intel_dp, &DP);
1982 /* channel eq pattern */
1983 if (!intel_dp_set_link_train(intel_dp, DP,
1984 DP_TRAINING_PATTERN_2 |
1985 DP_LINK_SCRAMBLING_DISABLE))
1988 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
1989 if (!intel_dp_get_link_status(intel_dp, link_status))
1992 /* Make sure clock is still ok */
1993 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1994 intel_dp_start_link_train(intel_dp);
1999 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2004 /* Try 5 times, then try clock recovery if that fails */
2006 intel_dp_link_down(intel_dp);
2007 intel_dp_start_link_train(intel_dp);
2013 /* Compute new intel_dp->train_set as requested by target */
2014 intel_get_adjust_train(intel_dp, link_status);
2019 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
2021 intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
2025 intel_dp_link_down(struct intel_dp *intel_dp)
2027 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2028 struct drm_device *dev = intel_dig_port->base.base.dev;
2029 struct drm_i915_private *dev_priv = dev->dev_private;
2030 struct intel_crtc *intel_crtc =
2031 to_intel_crtc(intel_dig_port->base.base.crtc);
2032 uint32_t DP = intel_dp->DP;
2035 * DDI code has a strict mode set sequence and we should try to respect
2036 * it, otherwise we might hang the machine in many different ways. So we
2037 * really should be disabling the port only on a complete crtc_disable
2038 * sequence. This function is just called under two conditions on DDI
2040 * - Link train failed while doing crtc_enable, and on this case we
2041 * really should respect the mode set sequence and wait for a
2043 * - Someone turned the monitor off and intel_dp_check_link_status
2044 * called us. We don't need to disable the whole port on this case, so
2045 * when someone turns the monitor on again,
2046 * intel_ddi_prepare_link_retrain will take care of redoing the link
2052 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2055 DRM_DEBUG_KMS("\n");
2057 if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
2058 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2059 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2061 DP &= ~DP_LINK_TRAIN_MASK;
2062 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2064 POSTING_READ(intel_dp->output_reg);
2066 /* We don't really know why we're doing this */
2067 intel_wait_for_vblank(dev, intel_crtc->pipe);
2069 if (HAS_PCH_IBX(dev) &&
2070 I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2071 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2073 /* Hardware workaround: leaving our transcoder select
2074 * set to transcoder B while it's off will prevent the
2075 * corresponding HDMI output on transcoder A.
2077 * Combine this with another hardware workaround:
2078 * transcoder select bit can only be cleared while the
2081 DP &= ~DP_PIPEB_SELECT;
2082 I915_WRITE(intel_dp->output_reg, DP);
2084 /* Changes to enable or select take place the vblank
2085 * after being written.
2087 if (WARN_ON(crtc == NULL)) {
2088 /* We should never try to disable a port without a crtc
2089 * attached. For paranoia keep the code around for a
2091 POSTING_READ(intel_dp->output_reg);
2094 intel_wait_for_vblank(dev, intel_crtc->pipe);
2097 DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2098 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2099 POSTING_READ(intel_dp->output_reg);
2100 msleep(intel_dp->panel_power_down_delay);
2104 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2106 char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2108 if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2109 sizeof(intel_dp->dpcd)) == 0)
2110 return false; /* aux transfer failed */
2112 ksnprintf(dpcd_hex_dump,
2113 sizeof(dpcd_hex_dump),
2114 "%02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n",
2115 intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2],
2116 intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5],
2117 intel_dp->dpcd[6], intel_dp->dpcd[7]);
2118 DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2120 if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2121 return false; /* DPCD not present */
2123 if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2124 DP_DWN_STRM_PORT_PRESENT))
2125 return true; /* native DP sink */
2127 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2128 return true; /* no per-port downstream info */
2130 if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2131 intel_dp->downstream_ports,
2132 DP_MAX_DOWNSTREAM_PORTS) == 0)
2133 return false; /* downstream port status fetch failed */
2139 intel_dp_probe_oui(struct intel_dp *intel_dp)
2143 if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2146 ironlake_edp_panel_vdd_on(intel_dp);
2148 if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2149 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2150 buf[0], buf[1], buf[2]);
2152 if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2153 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2154 buf[0], buf[1], buf[2]);
2156 ironlake_edp_panel_vdd_off(intel_dp, false);
2160 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2164 ret = intel_dp_aux_native_read_retry(intel_dp,
2165 DP_DEVICE_SERVICE_IRQ_VECTOR,
2166 sink_irq_vector, 1);
2174 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2176 /* NAK by default */
2177 intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2181 * According to DP spec
2184 * 2. Configure link according to Receiver Capabilities
2185 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3
2186 * 4. Check link status on receipt of hot-plug interrupt
2190 intel_dp_check_link_status(struct intel_dp *intel_dp)
2192 struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2194 u8 link_status[DP_LINK_STATUS_SIZE];
2196 if (!intel_encoder->connectors_active)
2199 if (WARN_ON(!intel_encoder->base.crtc))
2202 /* Try to read receiver status if the link appears to be up */
2203 if (!intel_dp_get_link_status(intel_dp, link_status)) {
2204 intel_dp_link_down(intel_dp);
2208 /* Now read the DPCD to see if it's actually running */
2209 if (!intel_dp_get_dpcd(intel_dp)) {
2210 intel_dp_link_down(intel_dp);
2214 /* Try to read the source of the interrupt */
2215 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2216 intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2217 /* Clear interrupt source */
2218 intel_dp_aux_native_write_1(intel_dp,
2219 DP_DEVICE_SERVICE_IRQ_VECTOR,
2222 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2223 intel_dp_handle_test_request(intel_dp);
2224 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2225 DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2228 if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2229 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2230 drm_get_encoder_name(&intel_encoder->base));
2231 intel_dp_start_link_train(intel_dp);
2232 intel_dp_complete_link_train(intel_dp);
2236 /* XXX this is probably wrong for multiple downstream ports */
2237 static enum drm_connector_status
2238 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2240 uint8_t *dpcd = intel_dp->dpcd;
2244 if (!intel_dp_get_dpcd(intel_dp))
2245 return connector_status_disconnected;
2247 /* if there's no downstream port, we're done */
2248 if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2249 return connector_status_connected;
2251 /* If we're HPD-aware, SINK_COUNT changes dynamically */
2252 hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2255 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2257 return connector_status_unknown;
2258 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2259 : connector_status_disconnected;
2262 /* If no HPD, poke DDC gently */
2263 if (drm_probe_ddc(intel_dp->adapter))
2264 return connector_status_connected;
2266 /* Well we tried, say unknown for unreliable port types */
2267 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2268 if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2269 return connector_status_unknown;
2271 /* Anything else is out of spec, warn and ignore */
2272 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2273 return connector_status_disconnected;
2276 static enum drm_connector_status
2277 ironlake_dp_detect(struct intel_dp *intel_dp)
2279 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2280 struct drm_i915_private *dev_priv = dev->dev_private;
2281 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2282 enum drm_connector_status status;
2284 /* Can't disconnect eDP, but you can close the lid... */
2285 if (is_edp(intel_dp)) {
2286 status = intel_panel_detect(dev);
2287 if (status == connector_status_unknown)
2288 status = connector_status_connected;
2292 if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2293 return connector_status_disconnected;
2295 return intel_dp_detect_dpcd(intel_dp);
2298 static enum drm_connector_status
2299 g4x_dp_detect(struct intel_dp *intel_dp)
2301 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2302 struct drm_i915_private *dev_priv = dev->dev_private;
2303 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2306 switch (intel_dig_port->port) {
2308 bit = PORTB_HOTPLUG_LIVE_STATUS;
2311 bit = PORTC_HOTPLUG_LIVE_STATUS;
2314 bit = PORTD_HOTPLUG_LIVE_STATUS;
2317 return connector_status_unknown;
2320 if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2321 return connector_status_disconnected;
2323 return intel_dp_detect_dpcd(intel_dp);
2326 static struct edid *
2327 intel_dp_get_edid(struct drm_connector *connector, struct device *adapter)
2329 struct intel_connector *intel_connector = to_intel_connector(connector);
2331 /* use cached edid if we have one */
2332 if (intel_connector->edid) {
2337 if (IS_ERR(intel_connector->edid))
2340 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
2341 edid = kmalloc(size, M_DRM, M_WAITOK);
2345 memcpy(edid, intel_connector->edid, size);
2349 return drm_get_edid(connector, adapter);
2353 intel_dp_get_edid_modes(struct drm_connector *connector, struct device *adapter)
2355 struct intel_connector *intel_connector = to_intel_connector(connector);
2357 /* use cached edid if we have one */
2358 if (intel_connector->edid) {
2360 if (IS_ERR(intel_connector->edid))
2363 return intel_connector_update_modes(connector,
2364 intel_connector->edid);
2367 return intel_ddc_get_modes(connector, adapter);
2370 static enum drm_connector_status
2371 intel_dp_detect(struct drm_connector *connector, bool force)
2373 struct intel_dp *intel_dp = intel_attached_dp(connector);
2374 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2375 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2376 struct drm_device *dev = connector->dev;
2377 enum drm_connector_status status;
2378 struct edid *edid = NULL;
2380 intel_dp->has_audio = false;
2382 if (HAS_PCH_SPLIT(dev))
2383 status = ironlake_dp_detect(intel_dp);
2385 status = g4x_dp_detect(intel_dp);
2387 if (status != connector_status_connected)
2390 intel_dp_probe_oui(intel_dp);
2392 if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2393 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2395 edid = intel_dp_get_edid(connector, intel_dp->adapter);
2397 intel_dp->has_audio = drm_detect_monitor_audio(edid);
2402 if (intel_encoder->type != INTEL_OUTPUT_EDP)
2403 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2404 return connector_status_connected;
2407 static int intel_dp_get_modes(struct drm_connector *connector)
2409 struct intel_dp *intel_dp = intel_attached_dp(connector);
2410 struct intel_connector *intel_connector = to_intel_connector(connector);
2411 struct drm_device *dev = connector->dev;
2414 /* We should parse the EDID data and find out if it has an audio sink
2417 ret = intel_dp_get_edid_modes(connector, intel_dp->adapter);
2421 /* if eDP has no EDID, fall back to fixed mode */
2422 if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2423 struct drm_display_mode *mode;
2424 mode = drm_mode_duplicate(dev,
2425 intel_connector->panel.fixed_mode);
2427 drm_mode_probed_add(connector, mode);
2435 intel_dp_detect_audio(struct drm_connector *connector)
2437 struct intel_dp *intel_dp = intel_attached_dp(connector);
2439 bool has_audio = false;
2441 edid = intel_dp_get_edid(connector, intel_dp->adapter);
2443 has_audio = drm_detect_monitor_audio(edid);
2451 intel_dp_set_property(struct drm_connector *connector,
2452 struct drm_property *property,
2455 struct drm_i915_private *dev_priv = connector->dev->dev_private;
2456 struct intel_connector *intel_connector = to_intel_connector(connector);
2457 struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2458 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2461 ret = drm_object_property_set_value(&connector->base, property, val);
2465 if (property == dev_priv->force_audio_property) {
2469 if (i == intel_dp->force_audio)
2472 intel_dp->force_audio = i;
2474 if (i == HDMI_AUDIO_AUTO)
2475 has_audio = intel_dp_detect_audio(connector);
2477 has_audio = (i == HDMI_AUDIO_ON);
2479 if (has_audio == intel_dp->has_audio)
2482 intel_dp->has_audio = has_audio;
2486 if (property == dev_priv->broadcast_rgb_property) {
2488 case INTEL_BROADCAST_RGB_AUTO:
2489 intel_dp->color_range_auto = true;
2491 case INTEL_BROADCAST_RGB_FULL:
2492 intel_dp->color_range_auto = false;
2493 intel_dp->color_range = 0;
2495 case INTEL_BROADCAST_RGB_LIMITED:
2496 intel_dp->color_range_auto = false;
2497 intel_dp->color_range = DP_COLOR_RANGE_16_235;
2505 if (is_edp(intel_dp) &&
2506 property == connector->dev->mode_config.scaling_mode_property) {
2507 if (val == DRM_MODE_SCALE_NONE) {
2508 DRM_DEBUG_KMS("no scaling not supported\n");
2512 if (intel_connector->panel.fitting_mode == val) {
2513 /* the eDP scaling property is not changed */
2516 intel_connector->panel.fitting_mode = val;
2524 if (intel_encoder->base.crtc)
2525 intel_crtc_restore_mode(intel_encoder->base.crtc);
2531 intel_dp_destroy(struct drm_connector *connector)
2533 struct intel_dp *intel_dp = intel_attached_dp(connector);
2534 struct intel_connector *intel_connector = to_intel_connector(connector);
2536 if (!IS_ERR_OR_NULL(intel_connector->edid))
2537 kfree(intel_connector->edid, M_DRM);
2539 if (is_edp(intel_dp))
2540 intel_panel_fini(&intel_connector->panel);
2543 drm_sysfs_connector_remove(connector);
2545 drm_connector_cleanup(connector);
2546 kfree(connector, M_DRM);
2549 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2551 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2552 struct intel_dp *intel_dp = &intel_dig_port->dp;
2553 struct drm_device *dev = intel_dp_to_dev(intel_dp);
2555 if (intel_dp->dp_iic_bus != NULL) {
2556 if (intel_dp->adapter != NULL) {
2557 device_delete_child(intel_dp->dp_iic_bus,
2560 device_delete_child(dev->dev, intel_dp->dp_iic_bus);
2562 drm_encoder_cleanup(encoder);
2563 if (is_edp(intel_dp)) {
2564 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2565 mutex_lock(&dev->mode_config.mutex);
2566 ironlake_panel_vdd_off_sync(intel_dp);
2567 mutex_unlock(&dev->mode_config.mutex);
2569 kfree(intel_dig_port, M_DRM);
2572 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2573 .mode_fixup = intel_dp_mode_fixup,
2574 .mode_set = intel_dp_mode_set,
2575 .disable = intel_encoder_noop,
2578 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2579 .dpms = intel_connector_dpms,
2580 .detect = intel_dp_detect,
2581 .fill_modes = drm_helper_probe_single_connector_modes,
2582 .set_property = intel_dp_set_property,
2583 .destroy = intel_dp_destroy,
2586 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2587 .get_modes = intel_dp_get_modes,
2588 .mode_valid = intel_dp_mode_valid,
2589 .best_encoder = intel_best_encoder,
2592 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2593 .destroy = intel_dp_encoder_destroy,
2597 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2599 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2601 intel_dp_check_link_status(intel_dp);
2604 /* Return which DP Port should be selected for Transcoder DP control */
2606 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2608 struct drm_device *dev = crtc->dev;
2609 struct intel_encoder *intel_encoder;
2610 struct intel_dp *intel_dp;
2612 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2613 intel_dp = enc_to_intel_dp(&intel_encoder->base);
2615 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2616 intel_encoder->type == INTEL_OUTPUT_EDP)
2617 return intel_dp->output_reg;
2623 /* check the VBT to see whether the eDP is on DP-D port */
2624 bool intel_dpd_is_edp(struct drm_device *dev)
2626 struct drm_i915_private *dev_priv = dev->dev_private;
2627 struct child_device_config *p_child;
2630 if (!dev_priv->child_dev_num)
2633 for (i = 0; i < dev_priv->child_dev_num; i++) {
2634 p_child = dev_priv->child_dev + i;
2636 if (p_child->dvo_port == PORT_IDPD &&
2637 p_child->device_type == DEVICE_TYPE_eDP)
2644 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2646 struct intel_connector *intel_connector = to_intel_connector(connector);
2648 intel_attach_force_audio_property(connector);
2649 intel_attach_broadcast_rgb_property(connector);
2650 intel_dp->color_range_auto = true;
2652 if (is_edp(intel_dp)) {
2653 drm_mode_create_scaling_mode_property(connector->dev);
2654 drm_object_attach_property(
2656 connector->dev->mode_config.scaling_mode_property,
2657 DRM_MODE_SCALE_ASPECT);
2658 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
2663 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
2664 struct intel_dp *intel_dp,
2665 struct edp_power_seq *out)
2667 struct drm_i915_private *dev_priv = dev->dev_private;
2668 struct edp_power_seq cur, vbt, spec, final;
2669 u32 pp_on, pp_off, pp_div, pp;
2671 /* Workaround: Need to write PP_CONTROL with the unlock key as
2672 * the very first thing. */
2673 pp = ironlake_get_pp_control(dev_priv);
2674 I915_WRITE(PCH_PP_CONTROL, pp);
2676 pp_on = I915_READ(PCH_PP_ON_DELAYS);
2677 pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2678 pp_div = I915_READ(PCH_PP_DIVISOR);
2680 /* Pull timing values out of registers */
2681 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2682 PANEL_POWER_UP_DELAY_SHIFT;
2684 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2685 PANEL_LIGHT_ON_DELAY_SHIFT;
2687 cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2688 PANEL_LIGHT_OFF_DELAY_SHIFT;
2690 cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2691 PANEL_POWER_DOWN_DELAY_SHIFT;
2693 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2694 PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2696 DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2697 cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2699 vbt = dev_priv->edp.pps;
2701 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2702 * our hw here, which are all in 100usec. */
2703 spec.t1_t3 = 210 * 10;
2704 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
2705 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
2706 spec.t10 = 500 * 10;
2707 /* This one is special and actually in units of 100ms, but zero
2708 * based in the hw (so we need to add 100 ms). But the sw vbt
2709 * table multiplies it with 1000 to make it in units of 100usec,
2711 spec.t11_t12 = (510 + 100) * 10;
2713 DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2714 vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2716 /* Use the max of the register settings and vbt. If both are
2717 * unset, fall back to the spec limits. */
2718 #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \
2720 max(cur.field, vbt.field))
2721 assign_final(t1_t3);
2725 assign_final(t11_t12);
2728 #define get_delay(field) (DIV_ROUND_UP(final.field, 10))
2729 intel_dp->panel_power_up_delay = get_delay(t1_t3);
2730 intel_dp->backlight_on_delay = get_delay(t8);
2731 intel_dp->backlight_off_delay = get_delay(t9);
2732 intel_dp->panel_power_down_delay = get_delay(t10);
2733 intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2736 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2737 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2738 intel_dp->panel_power_cycle_delay);
2740 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2741 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2748 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
2749 struct intel_dp *intel_dp,
2750 struct edp_power_seq *seq)
2752 struct drm_i915_private *dev_priv = dev->dev_private;
2753 u32 pp_on, pp_off, pp_div;
2755 /* And finally store the new values in the power sequencer. */
2756 pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
2757 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
2758 pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
2759 (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
2760 /* Compute the divisor for the pp clock, simply match the Bspec
2762 pp_div = ((100 * intel_pch_rawclk(dev))/2 - 1)
2763 << PP_REFERENCE_DIVIDER_SHIFT;
2764 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
2765 << PANEL_POWER_CYCLE_DELAY_SHIFT);
2767 /* Haswell doesn't have any port selection bits for the panel
2768 * power sequencer any more. */
2769 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2770 if (is_cpu_edp(intel_dp))
2771 pp_on |= PANEL_POWER_PORT_DP_A;
2773 pp_on |= PANEL_POWER_PORT_DP_D;
2776 I915_WRITE(PCH_PP_ON_DELAYS, pp_on);
2777 I915_WRITE(PCH_PP_OFF_DELAYS, pp_off);
2778 I915_WRITE(PCH_PP_DIVISOR, pp_div);
2780 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
2781 I915_READ(PCH_PP_ON_DELAYS),
2782 I915_READ(PCH_PP_OFF_DELAYS),
2783 I915_READ(PCH_PP_DIVISOR));
2787 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
2788 struct intel_connector *intel_connector)
2790 struct drm_connector *connector = &intel_connector->base;
2791 struct intel_dp *intel_dp = &intel_dig_port->dp;
2792 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2793 struct drm_device *dev = intel_encoder->base.dev;
2794 struct drm_i915_private *dev_priv = dev->dev_private;
2795 struct drm_display_mode *fixed_mode = NULL;
2796 struct edp_power_seq power_seq = { 0 };
2797 enum port port = intel_dig_port->port;
2798 const char *name = NULL;
2801 /* Preserve the current hw state. */
2802 intel_dp->DP = I915_READ(intel_dp->output_reg);
2803 intel_dp->attached_connector = intel_connector;
2805 if (HAS_PCH_SPLIT(dev) && port == PORT_D)
2806 if (intel_dpd_is_edp(dev))
2807 intel_dp->is_pch_edp = true;
2810 * FIXME : We need to initialize built-in panels before external panels.
2811 * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2813 if (IS_VALLEYVIEW(dev) && port == PORT_C) {
2814 type = DRM_MODE_CONNECTOR_eDP;
2815 intel_encoder->type = INTEL_OUTPUT_EDP;
2816 } else if (port == PORT_A || is_pch_edp(intel_dp)) {
2817 type = DRM_MODE_CONNECTOR_eDP;
2818 intel_encoder->type = INTEL_OUTPUT_EDP;
2820 /* The intel_encoder->type value may be INTEL_OUTPUT_UNKNOWN for
2821 * DDI or INTEL_OUTPUT_DISPLAYPORT for the older gens, so don't
2824 type = DRM_MODE_CONNECTOR_DisplayPort;
2827 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2828 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2830 connector->polled = DRM_CONNECTOR_POLL_HPD;
2831 connector->interlace_allowed = true;
2832 connector->doublescan_allowed = 0;
2834 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2835 ironlake_panel_vdd_work);
2837 intel_connector_attach_encoder(intel_connector, intel_encoder);
2839 drm_sysfs_connector_add(connector);
2843 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2845 intel_connector->get_hw_state = intel_connector_get_hw_state;
2848 /* Set up the DDC bus. */
2854 dev_priv->hotplug_supported_mask |= PORTB_HOTPLUG_INT_STATUS;
2858 dev_priv->hotplug_supported_mask |= PORTC_HOTPLUG_INT_STATUS;
2862 dev_priv->hotplug_supported_mask |= PORTD_HOTPLUG_INT_STATUS;
2866 WARN(1, "Invalid port %c\n", port_name(port));
2870 if (is_edp(intel_dp))
2871 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2873 intel_dp_i2c_init(intel_dp, intel_connector, name);
2875 /* Cache DPCD and EDID for edp. */
2876 if (is_edp(intel_dp)) {
2878 struct drm_display_mode *scan;
2881 ironlake_edp_panel_vdd_on(intel_dp);
2882 ret = intel_dp_get_dpcd(intel_dp);
2883 ironlake_edp_panel_vdd_off(intel_dp, false);
2886 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2887 dev_priv->no_aux_handshake =
2888 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2889 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2891 /* if this fails, presume the device is a ghost */
2892 DRM_INFO("failed to retrieve link info, disabling eDP\n");
2893 intel_dp_encoder_destroy(&intel_encoder->base);
2894 intel_dp_destroy(connector);
2898 /* We now know it's not a ghost, init power sequence regs. */
2899 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2902 ironlake_edp_panel_vdd_on(intel_dp);
2903 edid = drm_get_edid(connector, intel_dp->adapter);
2905 if (drm_add_edid_modes(connector, edid)) {
2906 drm_mode_connector_update_edid_property(connector, edid);
2907 drm_edid_to_eld(connector, edid);
2910 edid = ERR_PTR(-EINVAL);
2913 edid = ERR_PTR(-ENOENT);
2915 intel_connector->edid = edid;
2917 /* prefer fixed mode from EDID if available */
2918 list_for_each_entry(scan, &connector->probed_modes, head) {
2919 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
2920 fixed_mode = drm_mode_duplicate(dev, scan);
2925 /* fallback to VBT if available for eDP */
2926 if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
2927 fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2929 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
2932 ironlake_edp_panel_vdd_off(intel_dp, false);
2935 if (is_edp(intel_dp)) {
2936 intel_panel_init(&intel_connector->panel, fixed_mode);
2937 intel_panel_setup_backlight(connector);
2940 intel_dp_add_properties(intel_dp, connector);
2942 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2943 * 0xd. Failure to do so will result in spurious interrupts being
2944 * generated on the port when a cable is not attached.
2946 if (IS_G4X(dev) && !IS_GM45(dev)) {
2947 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2948 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2953 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
2955 struct intel_digital_port *intel_dig_port;
2956 struct intel_encoder *intel_encoder;
2957 struct drm_encoder *encoder;
2958 struct intel_connector *intel_connector;
2960 intel_dig_port = kmalloc(sizeof(struct intel_digital_port), M_DRM,
2962 if (!intel_dig_port)
2965 intel_connector = kmalloc(sizeof(struct intel_connector), M_DRM,
2967 if (!intel_connector) {
2968 kfree(intel_dig_port, M_DRM);
2972 intel_encoder = &intel_dig_port->base;
2973 encoder = &intel_encoder->base;
2975 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2976 DRM_MODE_ENCODER_TMDS);
2977 drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
2979 intel_encoder->enable = intel_enable_dp;
2980 intel_encoder->pre_enable = intel_pre_enable_dp;
2981 intel_encoder->disable = intel_disable_dp;
2982 intel_encoder->post_disable = intel_post_disable_dp;
2983 intel_encoder->get_hw_state = intel_dp_get_hw_state;
2985 intel_dig_port->port = port;
2986 intel_dig_port->dp.output_reg = output_reg;
2988 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2989 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2990 intel_encoder->cloneable = false;
2991 intel_encoder->hot_plug = intel_dp_hot_plug;
2993 intel_dp_init_connector(intel_dig_port, intel_connector);