a352a3464f3ac9f5fa877b4f6383752b58c6339b
[dragonfly.git] / sys / dev / netif / bce / if_bce.c
1 /*-
2  * Copyright (c) 2006-2007 Broadcom Corporation
3  *      David Christensen <davidch@broadcom.com>.  All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  *
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  * 3. Neither the name of Broadcom Corporation nor the name of its contributors
15  *    may be used to endorse or promote products derived from this software
16  *    without specific prior written consent.
17  *
18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
19  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
22  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
28  * THE POSSIBILITY OF SUCH DAMAGE.
29  *
30  * $FreeBSD: src/sys/dev/bce/if_bce.c,v 1.31 2007/05/16 23:34:11 davidch Exp $
31  */
32
33 /*
34  * The following controllers are supported by this driver:
35  *   BCM5706C A2, A3
36  *   BCM5706S A2, A3
37  *   BCM5708C B1, B2
38  *   BCM5708S B1, B2
39  *   BCM5709C A1, C0
40  *   BCM5716  C0
41  *
42  * The following controllers are not supported by this driver:
43  *   BCM5706C A0, A1
44  *   BCM5706S A0, A1
45  *   BCM5708C A0, B0
46  *   BCM5708S A0, B0
47  *   BCM5709C A0, B0, B1
48  *   BCM5709S A0, A1, B0, B1, B2, C0
49  */
50
51 #include "opt_bce.h"
52 #include "opt_polling.h"
53
54 #include <sys/param.h>
55 #include <sys/bus.h>
56 #include <sys/endian.h>
57 #include <sys/kernel.h>
58 #include <sys/interrupt.h>
59 #include <sys/mbuf.h>
60 #include <sys/malloc.h>
61 #include <sys/queue.h>
62 #ifdef BCE_DEBUG
63 #include <sys/random.h>
64 #endif
65 #include <sys/rman.h>
66 #include <sys/serialize.h>
67 #include <sys/socket.h>
68 #include <sys/sockio.h>
69 #include <sys/sysctl.h>
70
71 #include <netinet/ip.h>
72 #include <netinet/tcp.h>
73
74 #include <net/bpf.h>
75 #include <net/ethernet.h>
76 #include <net/if.h>
77 #include <net/if_arp.h>
78 #include <net/if_dl.h>
79 #include <net/if_media.h>
80 #include <net/if_types.h>
81 #include <net/ifq_var.h>
82 #include <net/vlan/if_vlan_var.h>
83 #include <net/vlan/if_vlan_ether.h>
84
85 #include <dev/netif/mii_layer/mii.h>
86 #include <dev/netif/mii_layer/miivar.h>
87 #include <dev/netif/mii_layer/brgphyreg.h>
88
89 #include <bus/pci/pcireg.h>
90 #include <bus/pci/pcivar.h>
91
92 #include "miibus_if.h"
93
94 #include <dev/netif/bce/if_bcereg.h>
95 #include <dev/netif/bce/if_bcefw.h>
96
97 /****************************************************************************/
98 /* BCE Debug Options                                                        */
99 /****************************************************************************/
100 #ifdef BCE_DEBUG
101
102 static uint32_t bce_debug = BCE_WARN;
103
104 /*
105  *          0 = Never             
106  *          1 = 1 in 2,147,483,648
107  *        256 = 1 in     8,388,608
108  *       2048 = 1 in     1,048,576
109  *      65536 = 1 in        32,768
110  *    1048576 = 1 in         2,048
111  *  268435456 = 1 in             8
112  *  536870912 = 1 in             4
113  * 1073741824 = 1 in             2
114  *
115  * bce_debug_mbuf_allocation_failure:
116  *     How often to simulate an mbuf allocation failure.
117  *
118  * bce_debug_dma_map_addr_failure:
119  *     How often to simulate a DMA mapping failure.
120  *
121  * bce_debug_bootcode_running_failure:
122  *     How often to simulate a bootcode failure.
123  */
124 static int      bce_debug_mbuf_allocation_failure = 0;
125 static int      bce_debug_dma_map_addr_failure = 0;
126 static int      bce_debug_bootcode_running_failure = 0;
127
128 #endif  /* BCE_DEBUG */
129
130
131 /****************************************************************************/
132 /* PCI Device ID Table                                                      */
133 /*                                                                          */
134 /* Used by bce_probe() to identify the devices supported by this driver.    */
135 /****************************************************************************/
136 #define BCE_DEVDESC_MAX         64
137
138 static struct bce_type bce_devs[] = {
139         /* BCM5706C Controllers and OEM boards. */
140         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3101,
141                 "HP NC370T Multifunction Gigabit Server Adapter" },
142         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3106,
143                 "HP NC370i Multifunction Gigabit Server Adapter" },
144         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3070,
145                 "HP NC380T PCIe DP Multifunc Gig Server Adapter" },
146         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x1709,
147                 "HP NC371i Multifunction Gigabit Server Adapter" },
148         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  PCI_ANY_ID,  PCI_ANY_ID,
149                 "Broadcom NetXtreme II BCM5706 1000Base-T" },
150
151         /* BCM5706S controllers and OEM boards. */
152         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102,
153                 "HP NC370F Multifunction Gigabit Server Adapter" },
154         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID,  PCI_ANY_ID,
155                 "Broadcom NetXtreme II BCM5706 1000Base-SX" },
156
157         /* BCM5708C controllers and OEM boards. */
158         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7037,
159                 "HP NC373T PCIe Multifunction Gig Server Adapter" },
160         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7038,
161                 "HP NC373i Multifunction Gigabit Server Adapter" },
162         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7045,
163                 "HP NC374m PCIe Multifunction Adapter" },
164         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  PCI_ANY_ID,  PCI_ANY_ID,
165                 "Broadcom NetXtreme II BCM5708 1000Base-T" },
166
167         /* BCM5708S controllers and OEM boards. */
168         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x1706,
169                 "HP NC373m Multifunction Gigabit Server Adapter" },
170         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x703b,
171                 "HP NC373i Multifunction Gigabit Server Adapter" },
172         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x703d,
173                 "HP NC373F PCIe Multifunc Giga Server Adapter" },
174         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  PCI_ANY_ID,  PCI_ANY_ID,
175                 "Broadcom NetXtreme II BCM5708S 1000Base-T" },
176
177         /* BCM5709C controllers and OEM boards. */
178         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  HP_VENDORID, 0x7055,
179                 "HP NC382i DP Multifunction Gigabit Server Adapter" },
180         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  HP_VENDORID, 0x7059,
181                 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" },
182         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  PCI_ANY_ID,  PCI_ANY_ID,
183                 "Broadcom NetXtreme II BCM5709 1000Base-T" },
184
185         /* BCM5709S controllers and OEM boards. */
186         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  HP_VENDORID, 0x171d,
187                 "HP NC382m DP 1GbE Multifunction BL-c Adapter" },
188         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  HP_VENDORID, 0x7056,
189                 "HP NC382i DP Multifunction Gigabit Server Adapter" },
190         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  PCI_ANY_ID,  PCI_ANY_ID,
191                 "Broadcom NetXtreme II BCM5709 1000Base-SX" },
192
193         /* BCM5716 controllers and OEM boards. */
194         { BRCM_VENDORID, BRCM_DEVICEID_BCM5716,   PCI_ANY_ID,  PCI_ANY_ID,
195                 "Broadcom NetXtreme II BCM5716 1000Base-T" },
196
197         { 0, 0, 0, 0, NULL }
198 };
199
200
201 /****************************************************************************/
202 /* Supported Flash NVRAM device data.                                       */
203 /****************************************************************************/
204 static const struct flash_spec flash_table[] =
205 {
206 #define BUFFERED_FLAGS          (BCE_NV_BUFFERED | BCE_NV_TRANSLATE)
207 #define NONBUFFERED_FLAGS       (BCE_NV_WREN)
208
209         /* Slow EEPROM */
210         {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
211          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
212          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
213          "EEPROM - slow"},
214         /* Expansion entry 0001 */
215         {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
216          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
217          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
218          "Entry 0001"},
219         /* Saifun SA25F010 (non-buffered flash) */
220         /* strap, cfg1, & write1 need updates */
221         {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
222          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
223          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
224          "Non-buffered flash (128kB)"},
225         /* Saifun SA25F020 (non-buffered flash) */
226         /* strap, cfg1, & write1 need updates */
227         {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
228          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
229          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
230          "Non-buffered flash (256kB)"},
231         /* Expansion entry 0100 */
232         {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
233          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
234          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
235          "Entry 0100"},
236         /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
237         {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
238          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
239          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
240          "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
241         /* Entry 0110: ST M45PE20 (non-buffered flash)*/
242         {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
243          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
244          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
245          "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
246         /* Saifun SA25F005 (non-buffered flash) */
247         /* strap, cfg1, & write1 need updates */
248         {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
249          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
250          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
251          "Non-buffered flash (64kB)"},
252         /* Fast EEPROM */
253         {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
254          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
255          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
256          "EEPROM - fast"},
257         /* Expansion entry 1001 */
258         {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
259          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
260          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
261          "Entry 1001"},
262         /* Expansion entry 1010 */
263         {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
264          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
265          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
266          "Entry 1010"},
267         /* ATMEL AT45DB011B (buffered flash) */
268         {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
269          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
270          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
271          "Buffered flash (128kB)"},
272         /* Expansion entry 1100 */
273         {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
274          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
275          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
276          "Entry 1100"},
277         /* Expansion entry 1101 */
278         {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
279          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
280          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
281          "Entry 1101"},
282         /* Ateml Expansion entry 1110 */
283         {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
284          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
285          BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
286          "Entry 1110 (Atmel)"},
287         /* ATMEL AT45DB021B (buffered flash) */
288         {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
289          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
290          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
291          "Buffered flash (256kB)"},
292 };
293
294 /*
295  * The BCM5709 controllers transparently handle the
296  * differences between Atmel 264 byte pages and all
297  * flash devices which use 256 byte pages, so no
298  * logical-to-physical mapping is required in the
299  * driver.
300  */
301 static struct flash_spec flash_5709 = {
302         .flags          = BCE_NV_BUFFERED,
303         .page_bits      = BCM5709_FLASH_PAGE_BITS,
304         .page_size      = BCM5709_FLASH_PAGE_SIZE,
305         .addr_mask      = BCM5709_FLASH_BYTE_ADDR_MASK,
306         .total_size     = BUFFERED_FLASH_TOTAL_SIZE * 2,
307         .name           = "5709/5716 buffered flash (256kB)",
308 };
309
310
311 /****************************************************************************/
312 /* DragonFly device entry points.                                           */
313 /****************************************************************************/
314 static int      bce_probe(device_t);
315 static int      bce_attach(device_t);
316 static int      bce_detach(device_t);
317 static void     bce_shutdown(device_t);
318
319 /****************************************************************************/
320 /* BCE Debug Data Structure Dump Routines                                   */
321 /****************************************************************************/
322 #ifdef BCE_DEBUG
323 static void     bce_dump_mbuf(struct bce_softc *, struct mbuf *);
324 static void     bce_dump_rx_mbuf_chain(struct bce_softc *, int, int);
325 static void     bce_dump_txbd(struct bce_softc *, int, struct tx_bd *);
326 static void     bce_dump_rxbd(struct bce_softc *, int, struct rx_bd *);
327 static void     bce_dump_l2fhdr(struct bce_softc *, int,
328                                 struct l2_fhdr *) __unused;
329 static void     bce_dump_tx_chain(struct bce_softc *, int, int);
330 static void     bce_dump_rx_chain(struct bce_softc *, int, int);
331 static void     bce_dump_status_block(struct bce_softc *);
332 static void     bce_dump_driver_state(struct bce_softc *);
333 static void     bce_dump_stats_block(struct bce_softc *) __unused;
334 static void     bce_dump_hw_state(struct bce_softc *);
335 static void     bce_dump_txp_state(struct bce_softc *);
336 static void     bce_dump_rxp_state(struct bce_softc *) __unused;
337 static void     bce_dump_tpat_state(struct bce_softc *) __unused;
338 static void     bce_freeze_controller(struct bce_softc *) __unused;
339 static void     bce_unfreeze_controller(struct bce_softc *) __unused;
340 static void     bce_breakpoint(struct bce_softc *);
341 #endif  /* BCE_DEBUG */
342
343
344 /****************************************************************************/
345 /* BCE Register/Memory Access Routines                                      */
346 /****************************************************************************/
347 static uint32_t bce_reg_rd_ind(struct bce_softc *, uint32_t);
348 static void     bce_reg_wr_ind(struct bce_softc *, uint32_t, uint32_t);
349 static void     bce_shmem_wr(struct bce_softc *, uint32_t, uint32_t);
350 static uint32_t bce_shmem_rd(struct bce_softc *, u32);
351 static void     bce_ctx_wr(struct bce_softc *, uint32_t, uint32_t, uint32_t);
352 static int      bce_miibus_read_reg(device_t, int, int);
353 static int      bce_miibus_write_reg(device_t, int, int, int);
354 static void     bce_miibus_statchg(device_t);
355
356
357 /****************************************************************************/
358 /* BCE NVRAM Access Routines                                                */
359 /****************************************************************************/
360 static int      bce_acquire_nvram_lock(struct bce_softc *);
361 static int      bce_release_nvram_lock(struct bce_softc *);
362 static void     bce_enable_nvram_access(struct bce_softc *);
363 static void     bce_disable_nvram_access(struct bce_softc *);
364 static int      bce_nvram_read_dword(struct bce_softc *, uint32_t, uint8_t *,
365                                      uint32_t);
366 static int      bce_init_nvram(struct bce_softc *);
367 static int      bce_nvram_read(struct bce_softc *, uint32_t, uint8_t *, int);
368 static int      bce_nvram_test(struct bce_softc *);
369
370 /****************************************************************************/
371 /* BCE DMA Allocate/Free Routines                                           */
372 /****************************************************************************/
373 static int      bce_dma_alloc(struct bce_softc *);
374 static void     bce_dma_free(struct bce_softc *);
375 static void     bce_dma_map_addr(void *, bus_dma_segment_t *, int, int);
376
377 /****************************************************************************/
378 /* BCE Firmware Synchronization and Load                                    */
379 /****************************************************************************/
380 static int      bce_fw_sync(struct bce_softc *, uint32_t);
381 static void     bce_load_rv2p_fw(struct bce_softc *, uint32_t *,
382                                  uint32_t, uint32_t);
383 static void     bce_load_cpu_fw(struct bce_softc *, struct cpu_reg *,
384                                 struct fw_info *);
385 static void     bce_start_cpu(struct bce_softc *, struct cpu_reg *);
386 static void     bce_halt_cpu(struct bce_softc *, struct cpu_reg *);
387 static void     bce_start_rxp_cpu(struct bce_softc *);
388 static void     bce_init_rxp_cpu(struct bce_softc *);
389 static void     bce_init_txp_cpu(struct bce_softc *);
390 static void     bce_init_tpat_cpu(struct bce_softc *);
391 static void     bce_init_cp_cpu(struct bce_softc *);
392 static void     bce_init_com_cpu(struct bce_softc *);
393 static void     bce_init_cpus(struct bce_softc *);
394
395 static void     bce_stop(struct bce_softc *);
396 static int      bce_reset(struct bce_softc *, uint32_t);
397 static int      bce_chipinit(struct bce_softc *);
398 static int      bce_blockinit(struct bce_softc *);
399 static int      bce_newbuf_std(struct bce_softc *, uint16_t *, uint16_t *,
400                                uint32_t *, int);
401 static void     bce_setup_rxdesc_std(struct bce_softc *, uint16_t, uint32_t *);
402 static void     bce_probe_pci_caps(struct bce_softc *);
403 static void     bce_print_adapter_info(struct bce_softc *);
404 static void     bce_get_media(struct bce_softc *);
405
406 static void     bce_init_tx_context(struct bce_softc *);
407 static int      bce_init_tx_chain(struct bce_softc *);
408 static void     bce_init_rx_context(struct bce_softc *);
409 static int      bce_init_rx_chain(struct bce_softc *);
410 static void     bce_free_rx_chain(struct bce_softc *);
411 static void     bce_free_tx_chain(struct bce_softc *);
412
413 static int      bce_encap(struct bce_softc *, struct mbuf **);
414 static int      bce_tso_setup(struct bce_softc *, struct mbuf **,
415                     uint16_t *, uint16_t *);
416 static void     bce_start(struct ifnet *);
417 static int      bce_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
418 static void     bce_watchdog(struct ifnet *);
419 static int      bce_ifmedia_upd(struct ifnet *);
420 static void     bce_ifmedia_sts(struct ifnet *, struct ifmediareq *);
421 static void     bce_init(void *);
422 static void     bce_mgmt_init(struct bce_softc *);
423
424 static int      bce_init_ctx(struct bce_softc *);
425 static void     bce_get_mac_addr(struct bce_softc *);
426 static void     bce_set_mac_addr(struct bce_softc *);
427 static void     bce_phy_intr(struct bce_softc *);
428 static void     bce_rx_intr(struct bce_softc *, int, uint16_t);
429 static void     bce_tx_intr(struct bce_softc *, uint16_t);
430 static void     bce_disable_intr(struct bce_softc *);
431 static void     bce_enable_intr(struct bce_softc *);
432 static void     bce_reenable_intr(struct bce_softc *);
433
434 #ifdef DEVICE_POLLING
435 static void     bce_poll(struct ifnet *, enum poll_cmd, int);
436 #endif
437 static void     bce_intr(struct bce_softc *);
438 static void     bce_intr_legacy(void *);
439 static void     bce_intr_msi(void *);
440 static void     bce_intr_msi_oneshot(void *);
441 static void     bce_set_rx_mode(struct bce_softc *);
442 static void     bce_stats_update(struct bce_softc *);
443 static void     bce_tick(void *);
444 static void     bce_tick_serialized(struct bce_softc *);
445 static void     bce_pulse(void *);
446 static void     bce_pulse_check_msi(struct bce_softc *);
447 static void     bce_add_sysctls(struct bce_softc *);
448
449 static void     bce_coal_change(struct bce_softc *);
450 static int      bce_sysctl_tx_bds_int(SYSCTL_HANDLER_ARGS);
451 static int      bce_sysctl_tx_bds(SYSCTL_HANDLER_ARGS);
452 static int      bce_sysctl_tx_ticks_int(SYSCTL_HANDLER_ARGS);
453 static int      bce_sysctl_tx_ticks(SYSCTL_HANDLER_ARGS);
454 static int      bce_sysctl_rx_bds_int(SYSCTL_HANDLER_ARGS);
455 static int      bce_sysctl_rx_bds(SYSCTL_HANDLER_ARGS);
456 static int      bce_sysctl_rx_ticks_int(SYSCTL_HANDLER_ARGS);
457 static int      bce_sysctl_rx_ticks(SYSCTL_HANDLER_ARGS);
458 static int      bce_sysctl_coal_change(SYSCTL_HANDLER_ARGS,
459                                        uint32_t *, uint32_t);
460
461 /*
462  * NOTE:
463  * Don't set bce_tx_ticks_int/bce_tx_ticks to 1023.  Linux's bnx2
464  * takes 1023 as the TX ticks limit.  However, using 1023 will
465  * cause 5708(B2) to generate extra interrupts (~2000/s) even when
466  * there is _no_ network activity on the NIC.
467  */
468 static uint32_t bce_tx_bds_int = 255;           /* bcm: 20 */
469 static uint32_t bce_tx_bds = 255;               /* bcm: 20 */
470 static uint32_t bce_tx_ticks_int = 1022;        /* bcm: 80 */
471 static uint32_t bce_tx_ticks = 1022;            /* bcm: 80 */
472 static uint32_t bce_rx_bds_int = 128;           /* bcm: 6 */
473 static uint32_t bce_rx_bds = 128;               /* bcm: 6 */
474 static uint32_t bce_rx_ticks_int = 150;         /* bcm: 18 */
475 static uint32_t bce_rx_ticks = 150;             /* bcm: 18 */
476
477 static int      bce_msi_enable = 1;
478
479 static int      bce_rx_pages = RX_PAGES_DEFAULT;
480 static int      bce_tx_pages = TX_PAGES_DEFAULT;
481
482 TUNABLE_INT("hw.bce.tx_bds_int", &bce_tx_bds_int);
483 TUNABLE_INT("hw.bce.tx_bds", &bce_tx_bds);
484 TUNABLE_INT("hw.bce.tx_ticks_int", &bce_tx_ticks_int);
485 TUNABLE_INT("hw.bce.tx_ticks", &bce_tx_ticks);
486 TUNABLE_INT("hw.bce.rx_bds_int", &bce_rx_bds_int);
487 TUNABLE_INT("hw.bce.rx_bds", &bce_rx_bds);
488 TUNABLE_INT("hw.bce.rx_ticks_int", &bce_rx_ticks_int);
489 TUNABLE_INT("hw.bce.rx_ticks", &bce_rx_ticks);
490 TUNABLE_INT("hw.bce.msi.enable", &bce_msi_enable);
491 TUNABLE_INT("hw.bce.rx_pages", &bce_rx_pages);
492 TUNABLE_INT("hw.bce.tx_pages", &bce_tx_pages);
493
494 /****************************************************************************/
495 /* DragonFly device dispatch table.                                         */
496 /****************************************************************************/
497 static device_method_t bce_methods[] = {
498         /* Device interface */
499         DEVMETHOD(device_probe,         bce_probe),
500         DEVMETHOD(device_attach,        bce_attach),
501         DEVMETHOD(device_detach,        bce_detach),
502         DEVMETHOD(device_shutdown,      bce_shutdown),
503
504         /* bus interface */
505         DEVMETHOD(bus_print_child,      bus_generic_print_child),
506         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
507
508         /* MII interface */
509         DEVMETHOD(miibus_readreg,       bce_miibus_read_reg),
510         DEVMETHOD(miibus_writereg,      bce_miibus_write_reg),
511         DEVMETHOD(miibus_statchg,       bce_miibus_statchg),
512
513         { 0, 0 }
514 };
515
516 static driver_t bce_driver = {
517         "bce",
518         bce_methods,
519         sizeof(struct bce_softc)
520 };
521
522 static devclass_t bce_devclass;
523
524
525 DECLARE_DUMMY_MODULE(if_bce);
526 MODULE_DEPEND(bce, miibus, 1, 1, 1);
527 DRIVER_MODULE(if_bce, pci, bce_driver, bce_devclass, NULL, NULL);
528 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, NULL, NULL);
529
530
531 /****************************************************************************/
532 /* Device probe function.                                                   */
533 /*                                                                          */
534 /* Compares the device to the driver's list of supported devices and        */
535 /* reports back to the OS whether this is the right driver for the device.  */
536 /*                                                                          */
537 /* Returns:                                                                 */
538 /*   BUS_PROBE_DEFAULT on success, positive value on failure.               */
539 /****************************************************************************/
540 static int
541 bce_probe(device_t dev)
542 {
543         struct bce_type *t;
544         uint16_t vid, did, svid, sdid;
545
546         /* Get the data for the device to be probed. */
547         vid  = pci_get_vendor(dev);
548         did  = pci_get_device(dev);
549         svid = pci_get_subvendor(dev);
550         sdid = pci_get_subdevice(dev);
551
552         /* Look through the list of known devices for a match. */
553         for (t = bce_devs; t->bce_name != NULL; ++t) {
554                 if (vid == t->bce_vid && did == t->bce_did && 
555                     (svid == t->bce_svid || t->bce_svid == PCI_ANY_ID) &&
556                     (sdid == t->bce_sdid || t->bce_sdid == PCI_ANY_ID)) {
557                         uint32_t revid = pci_read_config(dev, PCIR_REVID, 4);
558                         char *descbuf;
559
560                         descbuf = kmalloc(BCE_DEVDESC_MAX, M_TEMP, M_WAITOK);
561
562                         /* Print out the device identity. */
563                         ksnprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)",
564                                   t->bce_name,
565                                   ((revid & 0xf0) >> 4) + 'A', revid & 0xf);
566
567                         device_set_desc_copy(dev, descbuf);
568                         kfree(descbuf, M_TEMP);
569                         return 0;
570                 }
571         }
572         return ENXIO;
573 }
574
575
576 /****************************************************************************/
577 /* PCI Capabilities Probe Function.                                         */
578 /*                                                                          */
579 /* Walks the PCI capabiites list for the device to find what features are   */
580 /* supported.                                                               */
581 /*                                                                          */
582 /* Returns:                                                                 */
583 /*   None.                                                                  */
584 /****************************************************************************/
585 static void
586 bce_print_adapter_info(struct bce_softc *sc)
587 {
588         device_printf(sc->bce_dev, "ASIC (0x%08X); ", sc->bce_chipid);
589
590         kprintf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >> 12) + 'A',
591                 ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4));
592
593         /* Bus info. */
594         if (sc->bce_flags & BCE_PCIE_FLAG) {
595                 kprintf("Bus (PCIe x%d, ", sc->link_width);
596                 switch (sc->link_speed) {
597                 case 1:
598                         kprintf("2.5Gbps); ");
599                         break;
600                 case 2:
601                         kprintf("5Gbps); ");
602                         break;
603                 default:
604                         kprintf("Unknown link speed); ");
605                         break;
606                 }
607         } else {
608                 kprintf("Bus (PCI%s, %s, %dMHz); ",
609                     ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""),
610                     ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ? "32-bit" : "64-bit"),
611                     sc->bus_speed_mhz);
612         }
613
614         /* Firmware version and device features. */
615         kprintf("B/C (%s)", sc->bce_bc_ver);
616
617         if ((sc->bce_flags & BCE_MFW_ENABLE_FLAG) ||
618             (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)) {
619                 kprintf("; Flags(");
620                 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG)
621                         kprintf("MFW[%s]", sc->bce_mfw_ver);
622                 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
623                         kprintf(" 2.5G");
624                 kprintf(")");
625         }
626         kprintf("\n");
627 }
628
629
630 /****************************************************************************/
631 /* PCI Capabilities Probe Function.                                         */
632 /*                                                                          */
633 /* Walks the PCI capabiites list for the device to find what features are   */
634 /* supported.                                                               */
635 /*                                                                          */
636 /* Returns:                                                                 */
637 /*   None.                                                                  */
638 /****************************************************************************/
639 static void
640 bce_probe_pci_caps(struct bce_softc *sc)
641 {
642         device_t dev = sc->bce_dev;
643         uint8_t ptr;
644
645         if (pci_is_pcix(dev))
646                 sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG;
647
648         ptr = pci_get_pciecap_ptr(dev);
649         if (ptr) {
650                 uint16_t link_status = pci_read_config(dev, ptr + 0x12, 2);
651
652                 sc->link_speed = link_status & 0xf;
653                 sc->link_width = (link_status >> 4) & 0x3f;
654                 sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG;
655                 sc->bce_flags |= BCE_PCIE_FLAG;
656         }
657 }
658
659
660 /****************************************************************************/
661 /* Device attach function.                                                  */
662 /*                                                                          */
663 /* Allocates device resources, performs secondary chip identification,      */
664 /* resets and initializes the hardware, and initializes driver instance     */
665 /* variables.                                                               */
666 /*                                                                          */
667 /* Returns:                                                                 */
668 /*   0 on success, positive value on failure.                               */
669 /****************************************************************************/
670 static int
671 bce_attach(device_t dev)
672 {
673         struct bce_softc *sc = device_get_softc(dev);
674         struct ifnet *ifp = &sc->arpcom.ac_if;
675         uint32_t val;
676         u_int irq_flags;
677         void (*irq_handle)(void *);
678         int rid, rc = 0;
679         int i, j;
680         struct mii_probe_args mii_args;
681         uintptr_t mii_priv = 0;
682
683         sc->bce_dev = dev;
684         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
685
686         pci_enable_busmaster(dev);
687
688         bce_probe_pci_caps(sc);
689
690         /* Allocate PCI memory resources. */
691         rid = PCIR_BAR(0);
692         sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
693                                                  RF_ACTIVE | PCI_RF_DENSE);
694         if (sc->bce_res_mem == NULL) {
695                 device_printf(dev, "PCI memory allocation failed\n");
696                 return ENXIO;
697         }
698         sc->bce_btag = rman_get_bustag(sc->bce_res_mem);
699         sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem);
700
701         /* Allocate PCI IRQ resources. */
702         sc->bce_irq_type = pci_alloc_1intr(dev, bce_msi_enable,
703             &sc->bce_irq_rid, &irq_flags);
704
705         sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
706             &sc->bce_irq_rid, irq_flags);
707         if (sc->bce_res_irq == NULL) {
708                 device_printf(dev, "PCI map interrupt failed\n");
709                 rc = ENXIO;
710                 goto fail;
711         }
712
713         /*
714          * Configure byte swap and enable indirect register access.
715          * Rely on CPU to do target byte swapping on big endian systems.
716          * Access to registers outside of PCI configurtion space are not
717          * valid until this is done.
718          */
719         pci_write_config(dev, BCE_PCICFG_MISC_CONFIG,
720                          BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
721                          BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4);
722
723         /* Save ASIC revsion info. */
724         sc->bce_chipid =  REG_RD(sc, BCE_MISC_ID);
725
726         /* Weed out any non-production controller revisions. */
727         switch (BCE_CHIP_ID(sc)) {
728         case BCE_CHIP_ID_5706_A0:
729         case BCE_CHIP_ID_5706_A1:
730         case BCE_CHIP_ID_5708_A0:
731         case BCE_CHIP_ID_5708_B0:
732         case BCE_CHIP_ID_5709_A0:
733         case BCE_CHIP_ID_5709_B0:
734         case BCE_CHIP_ID_5709_B1:
735 #ifdef foo
736         /* 5709C B2 seems to work fine */
737         case BCE_CHIP_ID_5709_B2:
738 #endif
739                 device_printf(dev, "Unsupported chip id 0x%08x!\n",
740                               BCE_CHIP_ID(sc));
741                 rc = ENODEV;
742                 goto fail;
743         }
744
745         mii_priv |= BRGPHY_FLAG_WIRESPEED;
746         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
747                 if (BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax ||
748                     BCE_CHIP_REV(sc) == BCE_CHIP_REV_Bx)
749                         mii_priv |= BRGPHY_FLAG_NO_EARLYDAC;
750         } else {
751                 mii_priv |= BRGPHY_FLAG_BER_BUG;
752         }
753
754         if (sc->bce_irq_type == PCI_INTR_TYPE_LEGACY) {
755                 irq_handle = bce_intr_legacy;
756         } else if (sc->bce_irq_type == PCI_INTR_TYPE_MSI) {
757                 irq_handle = bce_intr_msi;
758                 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
759                         irq_handle = bce_intr_msi_oneshot;
760                         sc->bce_flags |= BCE_ONESHOT_MSI_FLAG;
761                 }
762         } else {
763                 panic("%s: unsupported intr type %d",
764                     device_get_nameunit(dev), sc->bce_irq_type);
765         }
766
767         /*
768          * Find the base address for shared memory access.
769          * Newer versions of bootcode use a signature and offset
770          * while older versions use a fixed address.
771          */
772         val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE);
773         if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) ==
774             BCE_SHM_HDR_SIGNATURE_SIG) {
775                 /* Multi-port devices use different offsets in shared memory. */
776                 sc->bce_shmem_base = REG_RD_IND(sc,
777                     BCE_SHM_HDR_ADDR_0 + (pci_get_function(sc->bce_dev) << 2));
778         } else {
779                 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE;
780         }
781         DBPRINT(sc, BCE_INFO, "bce_shmem_base = 0x%08X\n", sc->bce_shmem_base);
782
783         /* Fetch the bootcode revision. */
784         val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV);
785         for (i = 0, j = 0; i < 3; i++) {
786                 uint8_t num;
787                 int k, skip0;
788
789                 num = (uint8_t)(val >> (24 - (i * 8)));
790                 for (k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
791                         if (num >= k || !skip0 || k == 1) {
792                                 sc->bce_bc_ver[j++] = (num / k) + '0';
793                                 skip0 = 0;
794                         }
795                 }
796                 if (i != 2)
797                         sc->bce_bc_ver[j++] = '.';
798         }
799
800         /* Check if any management firwmare is running. */
801         val = bce_shmem_rd(sc, BCE_PORT_FEATURE);
802         if (val & BCE_PORT_FEATURE_ASF_ENABLED) {
803                 sc->bce_flags |= BCE_MFW_ENABLE_FLAG;
804
805                 /* Allow time for firmware to enter the running state. */
806                 for (i = 0; i < 30; i++) {
807                         val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
808                         if (val & BCE_CONDITION_MFW_RUN_MASK)
809                                 break;
810                         DELAY(10000);
811                 }
812         }
813
814         /* Check the current bootcode state. */
815         val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION) &
816             BCE_CONDITION_MFW_RUN_MASK;
817         if (val != BCE_CONDITION_MFW_RUN_UNKNOWN &&
818             val != BCE_CONDITION_MFW_RUN_NONE) {
819                 uint32_t addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR);
820
821                 for (i = 0, j = 0; j < 3; j++) {
822                         val = bce_reg_rd_ind(sc, addr + j * 4);
823                         val = bswap32(val);
824                         memcpy(&sc->bce_mfw_ver[i], &val, 4);
825                         i += 4;
826                 }
827         }
828
829         /* Get PCI bus information (speed and type). */
830         val = REG_RD(sc, BCE_PCICFG_MISC_STATUS);
831         if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) {
832                 uint32_t clkreg;
833
834                 sc->bce_flags |= BCE_PCIX_FLAG;
835
836                 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS) &
837                          BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
838                 switch (clkreg) {
839                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
840                         sc->bus_speed_mhz = 133;
841                         break;
842
843                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
844                         sc->bus_speed_mhz = 100;
845                         break;
846
847                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
848                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
849                         sc->bus_speed_mhz = 66;
850                         break;
851
852                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
853                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
854                         sc->bus_speed_mhz = 50;
855                         break;
856
857                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
858                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
859                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
860                         sc->bus_speed_mhz = 33;
861                         break;
862                 }
863         } else {
864                 if (val & BCE_PCICFG_MISC_STATUS_M66EN)
865                         sc->bus_speed_mhz = 66;
866                 else
867                         sc->bus_speed_mhz = 33;
868         }
869
870         if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET)
871                 sc->bce_flags |= BCE_PCI_32BIT_FLAG;
872
873         /* Reset the controller. */
874         rc = bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
875         if (rc != 0)
876                 goto fail;
877
878         /* Initialize the controller. */
879         rc = bce_chipinit(sc);
880         if (rc != 0) {
881                 device_printf(dev, "Controller initialization failed!\n");
882                 goto fail;
883         }
884
885         /* Perform NVRAM test. */
886         rc = bce_nvram_test(sc);
887         if (rc != 0) {
888                 device_printf(dev, "NVRAM test failed!\n");
889                 goto fail;
890         }
891
892         /* Fetch the permanent Ethernet MAC address. */
893         bce_get_mac_addr(sc);
894
895         /*
896          * Trip points control how many BDs
897          * should be ready before generating an
898          * interrupt while ticks control how long
899          * a BD can sit in the chain before
900          * generating an interrupt.  Set the default 
901          * values for the RX and TX rings.
902          */
903
904 #ifdef BCE_DRBUG
905         /* Force more frequent interrupts. */
906         sc->bce_tx_quick_cons_trip_int = 1;
907         sc->bce_tx_quick_cons_trip     = 1;
908         sc->bce_tx_ticks_int           = 0;
909         sc->bce_tx_ticks               = 0;
910
911         sc->bce_rx_quick_cons_trip_int = 1;
912         sc->bce_rx_quick_cons_trip     = 1;
913         sc->bce_rx_ticks_int           = 0;
914         sc->bce_rx_ticks               = 0;
915 #else
916         sc->bce_tx_quick_cons_trip_int = bce_tx_bds_int;
917         sc->bce_tx_quick_cons_trip     = bce_tx_bds;
918         sc->bce_tx_ticks_int           = bce_tx_ticks_int;
919         sc->bce_tx_ticks               = bce_tx_ticks;
920
921         sc->bce_rx_quick_cons_trip_int = bce_rx_bds_int;
922         sc->bce_rx_quick_cons_trip     = bce_rx_bds;
923         sc->bce_rx_ticks_int           = bce_rx_ticks_int;
924         sc->bce_rx_ticks               = bce_rx_ticks;
925 #endif
926
927         /* Update statistics once every second. */
928         sc->bce_stats_ticks = 1000000 & 0xffff00;
929
930         /* Find the media type for the adapter. */
931         bce_get_media(sc);
932
933         /* Allocate DMA memory resources. */
934         rc = bce_dma_alloc(sc);
935         if (rc != 0) {
936                 device_printf(dev, "DMA resource allocation failed!\n");
937                 goto fail;
938         }
939
940         /* Initialize the ifnet interface. */
941         ifp->if_softc = sc;
942         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
943         ifp->if_ioctl = bce_ioctl;
944         ifp->if_start = bce_start;
945         ifp->if_init = bce_init;
946         ifp->if_watchdog = bce_watchdog;
947 #ifdef DEVICE_POLLING
948         ifp->if_poll = bce_poll;
949 #endif
950         ifp->if_mtu = ETHERMTU;
951         ifp->if_hwassist = BCE_CSUM_FEATURES | CSUM_TSO;
952         ifp->if_capabilities = BCE_IF_CAPABILITIES;
953         ifp->if_capenable = ifp->if_capabilities;
954         ifq_set_maxlen(&ifp->if_snd, USABLE_TX_BD(sc));
955         ifq_set_ready(&ifp->if_snd);
956
957         if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
958                 ifp->if_baudrate = IF_Gbps(2.5);
959         else
960                 ifp->if_baudrate = IF_Gbps(1);
961
962         /* Assume a standard 1500 byte MTU size for mbuf allocations. */
963         sc->mbuf_alloc_size  = MCLBYTES;
964
965         /*
966          * Look for our PHY.
967          */
968         mii_probe_args_init(&mii_args, bce_ifmedia_upd, bce_ifmedia_sts);
969         mii_args.mii_probemask = 1 << sc->bce_phy_addr;
970         mii_args.mii_privtag = MII_PRIVTAG_BRGPHY;
971         mii_args.mii_priv = mii_priv;
972
973         rc = mii_probe(dev, &sc->bce_miibus, &mii_args);
974         if (rc != 0) {
975                 device_printf(dev, "PHY probe failed!\n");
976                 goto fail;
977         }
978
979         /* Attach to the Ethernet interface list. */
980         ether_ifattach(ifp, sc->eaddr, NULL);
981
982         callout_init_mp(&sc->bce_tick_callout);
983         callout_init_mp(&sc->bce_pulse_callout);
984
985         /* Hookup IRQ last. */
986         rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_MPSAFE, irq_handle, sc,
987                             &sc->bce_intrhand, ifp->if_serializer);
988         if (rc != 0) {
989                 device_printf(dev, "Failed to setup IRQ!\n");
990                 ether_ifdetach(ifp);
991                 goto fail;
992         }
993
994         ifp->if_cpuid = rman_get_cpuid(sc->bce_res_irq);
995         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
996
997         /* Print some important debugging info. */
998         DBRUN(BCE_INFO, bce_dump_driver_state(sc));
999
1000         /* Add the supported sysctls to the kernel. */
1001         bce_add_sysctls(sc);
1002
1003         /*
1004          * The chip reset earlier notified the bootcode that
1005          * a driver is present.  We now need to start our pulse
1006          * routine so that the bootcode is reminded that we're
1007          * still running.
1008          */
1009         bce_pulse(sc);
1010
1011         /* Get the firmware running so IPMI still works */
1012         bce_mgmt_init(sc);
1013
1014         if (bootverbose)
1015                 bce_print_adapter_info(sc);
1016
1017         return 0;
1018 fail:
1019         bce_detach(dev);
1020         return(rc);
1021 }
1022
1023
1024 /****************************************************************************/
1025 /* Device detach function.                                                  */
1026 /*                                                                          */
1027 /* Stops the controller, resets the controller, and releases resources.     */
1028 /*                                                                          */
1029 /* Returns:                                                                 */
1030 /*   0 on success, positive value on failure.                               */
1031 /****************************************************************************/
1032 static int
1033 bce_detach(device_t dev)
1034 {
1035         struct bce_softc *sc = device_get_softc(dev);
1036
1037         if (device_is_attached(dev)) {
1038                 struct ifnet *ifp = &sc->arpcom.ac_if;
1039                 uint32_t msg;
1040
1041                 /* Stop and reset the controller. */
1042                 lwkt_serialize_enter(ifp->if_serializer);
1043                 callout_stop(&sc->bce_pulse_callout);
1044                 bce_stop(sc);
1045                 if (sc->bce_flags & BCE_NO_WOL_FLAG)
1046                         msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1047                 else
1048                         msg = BCE_DRV_MSG_CODE_UNLOAD;
1049                 bce_reset(sc, msg);
1050                 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand);
1051                 lwkt_serialize_exit(ifp->if_serializer);
1052
1053                 ether_ifdetach(ifp);
1054         }
1055
1056         /* If we have a child device on the MII bus remove it too. */
1057         if (sc->bce_miibus)
1058                 device_delete_child(dev, sc->bce_miibus);
1059         bus_generic_detach(dev);
1060
1061         if (sc->bce_res_irq != NULL) {
1062                 bus_release_resource(dev, SYS_RES_IRQ, sc->bce_irq_rid,
1063                     sc->bce_res_irq);
1064         }
1065
1066         if (sc->bce_irq_type == PCI_INTR_TYPE_MSI)
1067                 pci_release_msi(dev);
1068
1069         if (sc->bce_res_mem != NULL) {
1070                 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
1071                                      sc->bce_res_mem);
1072         }
1073
1074         bce_dma_free(sc);
1075
1076         if (sc->bce_sysctl_tree != NULL)
1077                 sysctl_ctx_free(&sc->bce_sysctl_ctx);
1078
1079         return 0;
1080 }
1081
1082
1083 /****************************************************************************/
1084 /* Device shutdown function.                                                */
1085 /*                                                                          */
1086 /* Stops and resets the controller.                                         */
1087 /*                                                                          */
1088 /* Returns:                                                                 */
1089 /*   Nothing                                                                */
1090 /****************************************************************************/
1091 static void
1092 bce_shutdown(device_t dev)
1093 {
1094         struct bce_softc *sc = device_get_softc(dev);
1095         struct ifnet *ifp = &sc->arpcom.ac_if;
1096         uint32_t msg;
1097
1098         lwkt_serialize_enter(ifp->if_serializer);
1099         bce_stop(sc);
1100         if (sc->bce_flags & BCE_NO_WOL_FLAG)
1101                 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1102         else
1103                 msg = BCE_DRV_MSG_CODE_UNLOAD;
1104         bce_reset(sc, msg);
1105         lwkt_serialize_exit(ifp->if_serializer);
1106 }
1107
1108
1109 /****************************************************************************/
1110 /* Indirect register read.                                                  */
1111 /*                                                                          */
1112 /* Reads NetXtreme II registers using an index/data register pair in PCI    */
1113 /* configuration space.  Using this mechanism avoids issues with posted     */
1114 /* reads but is much slower than memory-mapped I/O.                         */
1115 /*                                                                          */
1116 /* Returns:                                                                 */
1117 /*   The value of the register.                                             */
1118 /****************************************************************************/
1119 static uint32_t
1120 bce_reg_rd_ind(struct bce_softc *sc, uint32_t offset)
1121 {
1122         device_t dev = sc->bce_dev;
1123
1124         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1125 #ifdef BCE_DEBUG
1126         {
1127                 uint32_t val;
1128                 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1129                 DBPRINT(sc, BCE_EXCESSIVE,
1130                         "%s(); offset = 0x%08X, val = 0x%08X\n",
1131                         __func__, offset, val);
1132                 return val;
1133         }
1134 #else
1135         return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1136 #endif
1137 }
1138
1139
1140 /****************************************************************************/
1141 /* Indirect register write.                                                 */
1142 /*                                                                          */
1143 /* Writes NetXtreme II registers using an index/data register pair in PCI   */
1144 /* configuration space.  Using this mechanism avoids issues with posted     */
1145 /* writes but is muchh slower than memory-mapped I/O.                       */
1146 /*                                                                          */
1147 /* Returns:                                                                 */
1148 /*   Nothing.                                                               */
1149 /****************************************************************************/
1150 static void
1151 bce_reg_wr_ind(struct bce_softc *sc, uint32_t offset, uint32_t val)
1152 {
1153         device_t dev = sc->bce_dev;
1154
1155         DBPRINT(sc, BCE_EXCESSIVE, "%s(); offset = 0x%08X, val = 0x%08X\n",
1156                 __func__, offset, val);
1157
1158         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1159         pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4);
1160 }
1161
1162
1163 /****************************************************************************/
1164 /* Shared memory write.                                                     */
1165 /*                                                                          */
1166 /* Writes NetXtreme II shared memory region.                                */
1167 /*                                                                          */
1168 /* Returns:                                                                 */
1169 /*   Nothing.                                                               */
1170 /****************************************************************************/
1171 static void
1172 bce_shmem_wr(struct bce_softc *sc, uint32_t offset, uint32_t val)
1173 {
1174         bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val);
1175 }
1176
1177
1178 /****************************************************************************/
1179 /* Shared memory read.                                                      */
1180 /*                                                                          */
1181 /* Reads NetXtreme II shared memory region.                                 */
1182 /*                                                                          */
1183 /* Returns:                                                                 */
1184 /*   The 32 bit value read.                                                 */
1185 /****************************************************************************/
1186 static u32
1187 bce_shmem_rd(struct bce_softc *sc, uint32_t offset)
1188 {
1189         return bce_reg_rd_ind(sc, sc->bce_shmem_base + offset);
1190 }
1191
1192
1193 /****************************************************************************/
1194 /* Context memory write.                                                    */
1195 /*                                                                          */
1196 /* The NetXtreme II controller uses context memory to track connection      */
1197 /* information for L2 and higher network protocols.                         */
1198 /*                                                                          */
1199 /* Returns:                                                                 */
1200 /*   Nothing.                                                               */
1201 /****************************************************************************/
1202 static void
1203 bce_ctx_wr(struct bce_softc *sc, uint32_t cid_addr, uint32_t ctx_offset,
1204     uint32_t ctx_val)
1205 {
1206         uint32_t idx, offset = ctx_offset + cid_addr;
1207         uint32_t val, retry_cnt = 5;
1208
1209         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1210             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1211                 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val);
1212                 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ));
1213
1214                 for (idx = 0; idx < retry_cnt; idx++) {
1215                         val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1216                         if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0)
1217                                 break;
1218                         DELAY(5);
1219                 }
1220
1221                 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ) {
1222                         device_printf(sc->bce_dev,
1223                             "Unable to write CTX memory: "
1224                             "cid_addr = 0x%08X, offset = 0x%08X!\n",
1225                             cid_addr, ctx_offset);
1226                 }
1227         } else {
1228                 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1229                 REG_WR(sc, BCE_CTX_DATA, ctx_val);
1230         }
1231 }
1232
1233
1234 /****************************************************************************/
1235 /* PHY register read.                                                       */
1236 /*                                                                          */
1237 /* Implements register reads on the MII bus.                                */
1238 /*                                                                          */
1239 /* Returns:                                                                 */
1240 /*   The value of the register.                                             */
1241 /****************************************************************************/
1242 static int
1243 bce_miibus_read_reg(device_t dev, int phy, int reg)
1244 {
1245         struct bce_softc *sc = device_get_softc(dev);
1246         uint32_t val;
1247         int i;
1248
1249         /* Make sure we are accessing the correct PHY address. */
1250         KASSERT(phy == sc->bce_phy_addr,
1251             ("invalid phyno %d, should be %d\n", phy, sc->bce_phy_addr));
1252
1253         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1254                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1255                 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1256
1257                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1258                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1259
1260                 DELAY(40);
1261         }
1262
1263         val = BCE_MIPHY(phy) | BCE_MIREG(reg) |
1264               BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT |
1265               BCE_EMAC_MDIO_COMM_START_BUSY;
1266         REG_WR(sc, BCE_EMAC_MDIO_COMM, val);
1267
1268         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1269                 DELAY(10);
1270
1271                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1272                 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1273                         DELAY(5);
1274
1275                         val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1276                         val &= BCE_EMAC_MDIO_COMM_DATA;
1277                         break;
1278                 }
1279         }
1280
1281         if (val & BCE_EMAC_MDIO_COMM_START_BUSY) {
1282                 if_printf(&sc->arpcom.ac_if,
1283                           "Error: PHY read timeout! phy = %d, reg = 0x%04X\n",
1284                           phy, reg);
1285                 val = 0x0;
1286         } else {
1287                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1288         }
1289
1290         DBPRINT(sc, BCE_EXCESSIVE,
1291                 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1292                 __func__, phy, (uint16_t)reg & 0xffff, (uint16_t) val & 0xffff);
1293
1294         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1295                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1296                 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1297
1298                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1299                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1300
1301                 DELAY(40);
1302         }
1303         return (val & 0xffff);
1304 }
1305
1306
1307 /****************************************************************************/
1308 /* PHY register write.                                                      */
1309 /*                                                                          */
1310 /* Implements register writes on the MII bus.                               */
1311 /*                                                                          */
1312 /* Returns:                                                                 */
1313 /*   The value of the register.                                             */
1314 /****************************************************************************/
1315 static int
1316 bce_miibus_write_reg(device_t dev, int phy, int reg, int val)
1317 {
1318         struct bce_softc *sc = device_get_softc(dev);
1319         uint32_t val1;
1320         int i;
1321
1322         /* Make sure we are accessing the correct PHY address. */
1323         KASSERT(phy == sc->bce_phy_addr,
1324             ("invalid phyno %d, should be %d\n", phy, sc->bce_phy_addr));
1325
1326         DBPRINT(sc, BCE_EXCESSIVE,
1327                 "%s(): phy = %d, reg = 0x%04X, val = 0x%04X\n",
1328                 __func__, phy, (uint16_t)(reg & 0xffff),
1329                 (uint16_t)(val & 0xffff));
1330
1331         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1332                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1333                 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1334
1335                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1336                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1337
1338                 DELAY(40);
1339         }
1340
1341         val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val |
1342                 BCE_EMAC_MDIO_COMM_COMMAND_WRITE |
1343                 BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT;
1344         REG_WR(sc, BCE_EMAC_MDIO_COMM, val1);
1345
1346         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1347                 DELAY(10);
1348
1349                 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1350                 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1351                         DELAY(5);
1352                         break;
1353                 }
1354         }
1355
1356         if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY)
1357                 if_printf(&sc->arpcom.ac_if, "PHY write timeout!\n");
1358
1359         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1360                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1361                 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1362
1363                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1364                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1365
1366                 DELAY(40);
1367         }
1368         return 0;
1369 }
1370
1371
1372 /****************************************************************************/
1373 /* MII bus status change.                                                   */
1374 /*                                                                          */
1375 /* Called by the MII bus driver when the PHY establishes link to set the    */
1376 /* MAC interface registers.                                                 */
1377 /*                                                                          */
1378 /* Returns:                                                                 */
1379 /*   Nothing.                                                               */
1380 /****************************************************************************/
1381 static void
1382 bce_miibus_statchg(device_t dev)
1383 {
1384         struct bce_softc *sc = device_get_softc(dev);
1385         struct mii_data *mii = device_get_softc(sc->bce_miibus);
1386
1387         DBPRINT(sc, BCE_INFO, "mii_media_active = 0x%08X\n",
1388                 mii->mii_media_active);
1389
1390 #ifdef BCE_DEBUG
1391         /* Decode the interface media flags. */
1392         if_printf(&sc->arpcom.ac_if, "Media: ( ");
1393         switch(IFM_TYPE(mii->mii_media_active)) {
1394         case IFM_ETHER:
1395                 kprintf("Ethernet )");
1396                 break;
1397         default:
1398                 kprintf("Unknown )");
1399                 break;
1400         }
1401
1402         kprintf(" Media Options: ( ");
1403         switch(IFM_SUBTYPE(mii->mii_media_active)) {
1404         case IFM_AUTO:
1405                 kprintf("Autoselect )");
1406                 break;
1407         case IFM_MANUAL:
1408                 kprintf("Manual )");
1409                 break;
1410         case IFM_NONE:
1411                 kprintf("None )");
1412                 break;
1413         case IFM_10_T:
1414                 kprintf("10Base-T )");
1415                 break;
1416         case IFM_100_TX:
1417                 kprintf("100Base-TX )");
1418                 break;
1419         case IFM_1000_SX:
1420                 kprintf("1000Base-SX )");
1421                 break;
1422         case IFM_1000_T:
1423                 kprintf("1000Base-T )");
1424                 break;
1425         default:
1426                 kprintf("Other )");
1427                 break;
1428         }
1429
1430         kprintf(" Global Options: (");
1431         if (mii->mii_media_active & IFM_FDX)
1432                 kprintf(" FullDuplex");
1433         if (mii->mii_media_active & IFM_HDX)
1434                 kprintf(" HalfDuplex");
1435         if (mii->mii_media_active & IFM_LOOP)
1436                 kprintf(" Loopback");
1437         if (mii->mii_media_active & IFM_FLAG0)
1438                 kprintf(" Flag0");
1439         if (mii->mii_media_active & IFM_FLAG1)
1440                 kprintf(" Flag1");
1441         if (mii->mii_media_active & IFM_FLAG2)
1442                 kprintf(" Flag2");
1443         kprintf(" )\n");
1444 #endif
1445
1446         BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT);
1447
1448         /*
1449          * Set MII or GMII interface based on the speed negotiated
1450          * by the PHY.
1451          */
1452         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T || 
1453             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX) {
1454                 DBPRINT(sc, BCE_INFO, "Setting GMII interface.\n");
1455                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_GMII);
1456         } else {
1457                 DBPRINT(sc, BCE_INFO, "Setting MII interface.\n");
1458                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_PORT_MII);
1459         }
1460
1461         /*
1462          * Set half or full duplex based on the duplicity negotiated
1463          * by the PHY.
1464          */
1465         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
1466                 DBPRINT(sc, BCE_INFO, "Setting Full-Duplex interface.\n");
1467                 BCE_CLRBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1468         } else {
1469                 DBPRINT(sc, BCE_INFO, "Setting Half-Duplex interface.\n");
1470                 BCE_SETBIT(sc, BCE_EMAC_MODE, BCE_EMAC_MODE_HALF_DUPLEX);
1471         }
1472 }
1473
1474
1475 /****************************************************************************/
1476 /* Acquire NVRAM lock.                                                      */
1477 /*                                                                          */
1478 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock.  */
1479 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
1480 /* for use by the driver.                                                   */
1481 /*                                                                          */
1482 /* Returns:                                                                 */
1483 /*   0 on success, positive value on failure.                               */
1484 /****************************************************************************/
1485 static int
1486 bce_acquire_nvram_lock(struct bce_softc *sc)
1487 {
1488         uint32_t val;
1489         int j;
1490
1491         DBPRINT(sc, BCE_VERBOSE, "Acquiring NVRAM lock.\n");
1492
1493         /* Request access to the flash interface. */
1494         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2);
1495         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1496                 val = REG_RD(sc, BCE_NVM_SW_ARB);
1497                 if (val & BCE_NVM_SW_ARB_ARB_ARB2)
1498                         break;
1499
1500                 DELAY(5);
1501         }
1502
1503         if (j >= NVRAM_TIMEOUT_COUNT) {
1504                 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n");
1505                 return EBUSY;
1506         }
1507         return 0;
1508 }
1509
1510
1511 /****************************************************************************/
1512 /* Release NVRAM lock.                                                      */
1513 /*                                                                          */
1514 /* When the caller is finished accessing NVRAM the lock must be released.   */
1515 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
1516 /* for use by the driver.                                                   */
1517 /*                                                                          */
1518 /* Returns:                                                                 */
1519 /*   0 on success, positive value on failure.                               */
1520 /****************************************************************************/
1521 static int
1522 bce_release_nvram_lock(struct bce_softc *sc)
1523 {
1524         int j;
1525         uint32_t val;
1526
1527         DBPRINT(sc, BCE_VERBOSE, "Releasing NVRAM lock.\n");
1528
1529         /*
1530          * Relinquish nvram interface.
1531          */
1532         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2);
1533
1534         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1535                 val = REG_RD(sc, BCE_NVM_SW_ARB);
1536                 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2))
1537                         break;
1538
1539                 DELAY(5);
1540         }
1541
1542         if (j >= NVRAM_TIMEOUT_COUNT) {
1543                 DBPRINT(sc, BCE_WARN, "Timeout reeasing NVRAM lock!\n");
1544                 return EBUSY;
1545         }
1546         return 0;
1547 }
1548
1549
1550 /****************************************************************************/
1551 /* Enable NVRAM access.                                                     */
1552 /*                                                                          */
1553 /* Before accessing NVRAM for read or write operations the caller must      */
1554 /* enabled NVRAM access.                                                    */
1555 /*                                                                          */
1556 /* Returns:                                                                 */
1557 /*   Nothing.                                                               */
1558 /****************************************************************************/
1559 static void
1560 bce_enable_nvram_access(struct bce_softc *sc)
1561 {
1562         uint32_t val;
1563
1564         DBPRINT(sc, BCE_VERBOSE, "Enabling NVRAM access.\n");
1565
1566         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1567         /* Enable both bits, even on read. */
1568         REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1569                val | BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN);
1570 }
1571
1572
1573 /****************************************************************************/
1574 /* Disable NVRAM access.                                                    */
1575 /*                                                                          */
1576 /* When the caller is finished accessing NVRAM access must be disabled.     */
1577 /*                                                                          */
1578 /* Returns:                                                                 */
1579 /*   Nothing.                                                               */
1580 /****************************************************************************/
1581 static void
1582 bce_disable_nvram_access(struct bce_softc *sc)
1583 {
1584         uint32_t val;
1585
1586         DBPRINT(sc, BCE_VERBOSE, "Disabling NVRAM access.\n");
1587
1588         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1589
1590         /* Disable both bits, even after read. */
1591         REG_WR(sc, BCE_NVM_ACCESS_ENABLE,
1592                val & ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN));
1593 }
1594
1595
1596 /****************************************************************************/
1597 /* Read a dword (32 bits) from NVRAM.                                       */
1598 /*                                                                          */
1599 /* Read a 32 bit word from NVRAM.  The caller is assumed to have already    */
1600 /* obtained the NVRAM lock and enabled the controller for NVRAM access.     */
1601 /*                                                                          */
1602 /* Returns:                                                                 */
1603 /*   0 on success and the 32 bit value read, positive value on failure.     */
1604 /****************************************************************************/
1605 static int
1606 bce_nvram_read_dword(struct bce_softc *sc, uint32_t offset, uint8_t *ret_val,
1607                      uint32_t cmd_flags)
1608 {
1609         uint32_t cmd;
1610         int i, rc = 0;
1611
1612         /* Build the command word. */
1613         cmd = BCE_NVM_COMMAND_DOIT | cmd_flags;
1614
1615         /* Calculate the offset for buffered flash. */
1616         if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
1617                 offset = ((offset / sc->bce_flash_info->page_size) <<
1618                           sc->bce_flash_info->page_bits) +
1619                          (offset % sc->bce_flash_info->page_size);
1620         }
1621
1622         /*
1623          * Clear the DONE bit separately, set the address to read,
1624          * and issue the read.
1625          */
1626         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1627         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
1628         REG_WR(sc, BCE_NVM_COMMAND, cmd);
1629
1630         /* Wait for completion. */
1631         for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) {
1632                 uint32_t val;
1633
1634                 DELAY(5);
1635
1636                 val = REG_RD(sc, BCE_NVM_COMMAND);
1637                 if (val & BCE_NVM_COMMAND_DONE) {
1638                         val = REG_RD(sc, BCE_NVM_READ);
1639
1640                         val = be32toh(val);
1641                         memcpy(ret_val, &val, 4);
1642                         break;
1643                 }
1644         }
1645
1646         /* Check for errors. */
1647         if (i >= NVRAM_TIMEOUT_COUNT) {
1648                 if_printf(&sc->arpcom.ac_if,
1649                           "Timeout error reading NVRAM at offset 0x%08X!\n",
1650                           offset);
1651                 rc = EBUSY;
1652         }
1653         return rc;
1654 }
1655
1656
1657 /****************************************************************************/
1658 /* Initialize NVRAM access.                                                 */
1659 /*                                                                          */
1660 /* Identify the NVRAM device in use and prepare the NVRAM interface to      */
1661 /* access that device.                                                      */
1662 /*                                                                          */
1663 /* Returns:                                                                 */
1664 /*   0 on success, positive value on failure.                               */
1665 /****************************************************************************/
1666 static int
1667 bce_init_nvram(struct bce_softc *sc)
1668 {
1669         uint32_t val;
1670         int j, entry_count, rc = 0;
1671         const struct flash_spec *flash;
1672
1673         DBPRINT(sc, BCE_VERBOSE_RESET, "Entering %s()\n", __func__);
1674
1675         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1676             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1677                 sc->bce_flash_info = &flash_5709;
1678                 goto bce_init_nvram_get_flash_size;
1679         }
1680
1681         /* Determine the selected interface. */
1682         val = REG_RD(sc, BCE_NVM_CFG1);
1683
1684         entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
1685
1686         /*
1687          * Flash reconfiguration is required to support additional
1688          * NVRAM devices not directly supported in hardware.
1689          * Check if the flash interface was reconfigured
1690          * by the bootcode.
1691          */
1692
1693         if (val & 0x40000000) {
1694                 /* Flash interface reconfigured by bootcode. */
1695
1696                 DBPRINT(sc, BCE_INFO_LOAD, 
1697                         "%s(): Flash WAS reconfigured.\n", __func__);
1698
1699                 for (j = 0, flash = flash_table; j < entry_count;
1700                      j++, flash++) {
1701                         if ((val & FLASH_BACKUP_STRAP_MASK) ==
1702                             (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
1703                                 sc->bce_flash_info = flash;
1704                                 break;
1705                         }
1706                 }
1707         } else {
1708                 /* Flash interface not yet reconfigured. */
1709                 uint32_t mask;
1710
1711                 DBPRINT(sc, BCE_INFO_LOAD, 
1712                         "%s(): Flash was NOT reconfigured.\n", __func__);
1713
1714                 if (val & (1 << 23))
1715                         mask = FLASH_BACKUP_STRAP_MASK;
1716                 else
1717                         mask = FLASH_STRAP_MASK;
1718
1719                 /* Look for the matching NVRAM device configuration data. */
1720                 for (j = 0, flash = flash_table; j < entry_count;
1721                      j++, flash++) {
1722                         /* Check if the device matches any of the known devices. */
1723                         if ((val & mask) == (flash->strapping & mask)) {
1724                                 /* Found a device match. */
1725                                 sc->bce_flash_info = flash;
1726
1727                                 /* Request access to the flash interface. */
1728                                 rc = bce_acquire_nvram_lock(sc);
1729                                 if (rc != 0)
1730                                         return rc;
1731
1732                                 /* Reconfigure the flash interface. */
1733                                 bce_enable_nvram_access(sc);
1734                                 REG_WR(sc, BCE_NVM_CFG1, flash->config1);
1735                                 REG_WR(sc, BCE_NVM_CFG2, flash->config2);
1736                                 REG_WR(sc, BCE_NVM_CFG3, flash->config3);
1737                                 REG_WR(sc, BCE_NVM_WRITE1, flash->write1);
1738                                 bce_disable_nvram_access(sc);
1739                                 bce_release_nvram_lock(sc);
1740                                 break;
1741                         }
1742                 }
1743         }
1744
1745         /* Check if a matching device was found. */
1746         if (j == entry_count) {
1747                 sc->bce_flash_info = NULL;
1748                 if_printf(&sc->arpcom.ac_if, "Unknown Flash NVRAM found!\n");
1749                 return ENODEV;
1750         }
1751
1752 bce_init_nvram_get_flash_size:
1753         /* Write the flash config data to the shared memory interface. */
1754         val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2) &
1755             BCE_SHARED_HW_CFG2_NVM_SIZE_MASK;
1756         if (val)
1757                 sc->bce_flash_size = val;
1758         else
1759                 sc->bce_flash_size = sc->bce_flash_info->total_size;
1760
1761         DBPRINT(sc, BCE_INFO_LOAD, "%s() flash->total_size = 0x%08X\n",
1762                 __func__, sc->bce_flash_info->total_size);
1763
1764         DBPRINT(sc, BCE_VERBOSE_RESET, "Exiting %s()\n", __func__);
1765
1766         return rc;
1767 }
1768
1769
1770 /****************************************************************************/
1771 /* Read an arbitrary range of data from NVRAM.                              */
1772 /*                                                                          */
1773 /* Prepares the NVRAM interface for access and reads the requested data     */
1774 /* into the supplied buffer.                                                */
1775 /*                                                                          */
1776 /* Returns:                                                                 */
1777 /*   0 on success and the data read, positive value on failure.             */
1778 /****************************************************************************/
1779 static int
1780 bce_nvram_read(struct bce_softc *sc, uint32_t offset, uint8_t *ret_buf,
1781                int buf_size)
1782 {
1783         uint32_t cmd_flags, offset32, len32, extra;
1784         int rc = 0;
1785
1786         if (buf_size == 0)
1787                 return 0;
1788
1789         /* Request access to the flash interface. */
1790         rc = bce_acquire_nvram_lock(sc);
1791         if (rc != 0)
1792                 return rc;
1793
1794         /* Enable access to flash interface */
1795         bce_enable_nvram_access(sc);
1796
1797         len32 = buf_size;
1798         offset32 = offset;
1799         extra = 0;
1800
1801         cmd_flags = 0;
1802
1803         /* XXX should we release nvram lock if read_dword() fails? */
1804         if (offset32 & 3) {
1805                 uint8_t buf[4];
1806                 uint32_t pre_len;
1807
1808                 offset32 &= ~3;
1809                 pre_len = 4 - (offset & 3);
1810
1811                 if (pre_len >= len32) {
1812                         pre_len = len32;
1813                         cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST;
1814                 } else {
1815                         cmd_flags = BCE_NVM_COMMAND_FIRST;
1816                 }
1817
1818                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1819                 if (rc)
1820                         return rc;
1821
1822                 memcpy(ret_buf, buf + (offset & 3), pre_len);
1823
1824                 offset32 += 4;
1825                 ret_buf += pre_len;
1826                 len32 -= pre_len;
1827         }
1828
1829         if (len32 & 3) {
1830                 extra = 4 - (len32 & 3);
1831                 len32 = (len32 + 4) & ~3;
1832         }
1833
1834         if (len32 == 4) {
1835                 uint8_t buf[4];
1836
1837                 if (cmd_flags)
1838                         cmd_flags = BCE_NVM_COMMAND_LAST;
1839                 else
1840                         cmd_flags = BCE_NVM_COMMAND_FIRST |
1841                                     BCE_NVM_COMMAND_LAST;
1842
1843                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1844
1845                 memcpy(ret_buf, buf, 4 - extra);
1846         } else if (len32 > 0) {
1847                 uint8_t buf[4];
1848
1849                 /* Read the first word. */
1850                 if (cmd_flags)
1851                         cmd_flags = 0;
1852                 else
1853                         cmd_flags = BCE_NVM_COMMAND_FIRST;
1854
1855                 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags);
1856
1857                 /* Advance to the next dword. */
1858                 offset32 += 4;
1859                 ret_buf += 4;
1860                 len32 -= 4;
1861
1862                 while (len32 > 4 && rc == 0) {
1863                         rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0);
1864
1865                         /* Advance to the next dword. */
1866                         offset32 += 4;
1867                         ret_buf += 4;
1868                         len32 -= 4;
1869                 }
1870
1871                 if (rc)
1872                         goto bce_nvram_read_locked_exit;
1873
1874                 cmd_flags = BCE_NVM_COMMAND_LAST;
1875                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
1876
1877                 memcpy(ret_buf, buf, 4 - extra);
1878         }
1879
1880 bce_nvram_read_locked_exit:
1881         /* Disable access to flash interface and release the lock. */
1882         bce_disable_nvram_access(sc);
1883         bce_release_nvram_lock(sc);
1884
1885         return rc;
1886 }
1887
1888
1889 /****************************************************************************/
1890 /* Verifies that NVRAM is accessible and contains valid data.               */
1891 /*                                                                          */
1892 /* Reads the configuration data from NVRAM and verifies that the CRC is     */
1893 /* correct.                                                                 */
1894 /*                                                                          */
1895 /* Returns:                                                                 */
1896 /*   0 on success, positive value on failure.                               */
1897 /****************************************************************************/
1898 static int
1899 bce_nvram_test(struct bce_softc *sc)
1900 {
1901         uint32_t buf[BCE_NVRAM_SIZE / 4];
1902         uint32_t magic, csum;
1903         uint8_t *data = (uint8_t *)buf;
1904         int rc = 0;
1905
1906         /*
1907          * Check that the device NVRAM is valid by reading
1908          * the magic value at offset 0.
1909          */
1910         rc = bce_nvram_read(sc, 0, data, 4);
1911         if (rc != 0)
1912                 return rc;
1913
1914         magic = be32toh(buf[0]);
1915         if (magic != BCE_NVRAM_MAGIC) {
1916                 if_printf(&sc->arpcom.ac_if,
1917                           "Invalid NVRAM magic value! Expected: 0x%08X, "
1918                           "Found: 0x%08X\n", BCE_NVRAM_MAGIC, magic);
1919                 return ENODEV;
1920         }
1921
1922         /*
1923          * Verify that the device NVRAM includes valid
1924          * configuration data.
1925          */
1926         rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE);
1927         if (rc != 0)
1928                 return rc;
1929
1930         csum = ether_crc32_le(data, 0x100);
1931         if (csum != BCE_CRC32_RESIDUAL) {
1932                 if_printf(&sc->arpcom.ac_if,
1933                           "Invalid Manufacturing Information NVRAM CRC! "
1934                           "Expected: 0x%08X, Found: 0x%08X\n",
1935                           BCE_CRC32_RESIDUAL, csum);
1936                 return ENODEV;
1937         }
1938
1939         csum = ether_crc32_le(data + 0x100, 0x100);
1940         if (csum != BCE_CRC32_RESIDUAL) {
1941                 if_printf(&sc->arpcom.ac_if,
1942                           "Invalid Feature Configuration Information "
1943                           "NVRAM CRC! Expected: 0x%08X, Found: 08%08X\n",
1944                           BCE_CRC32_RESIDUAL, csum);
1945                 rc = ENODEV;
1946         }
1947         return rc;
1948 }
1949
1950
1951 /****************************************************************************/
1952 /* Identifies the current media type of the controller and sets the PHY     */
1953 /* address.                                                                 */
1954 /*                                                                          */
1955 /* Returns:                                                                 */
1956 /*   Nothing.                                                               */
1957 /****************************************************************************/
1958 static void
1959 bce_get_media(struct bce_softc *sc)
1960 {
1961         uint32_t val;
1962
1963         sc->bce_phy_addr = 1;
1964
1965         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
1966             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
1967                 uint32_t val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL);
1968                 uint32_t bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID;
1969                 uint32_t strap;
1970
1971                 /*
1972                  * The BCM5709S is software configurable
1973                  * for Copper or SerDes operation.
1974                  */
1975                 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) {
1976                         return;
1977                 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
1978                         sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1979                         return;
1980                 }
1981
1982                 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE) {
1983                         strap = (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
1984                 } else {
1985                         strap =
1986                         (val & BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
1987                 }
1988
1989                 if (pci_get_function(sc->bce_dev) == 0) {
1990                         switch (strap) {
1991                         case 0x4:
1992                         case 0x5:
1993                         case 0x6:
1994                                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
1995                                 break;
1996                         }
1997                 } else {
1998                         switch (strap) {
1999                         case 0x1:
2000                         case 0x2:
2001                         case 0x4:
2002                                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
2003                                 break;
2004                         }
2005                 }
2006         } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT) {
2007                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
2008         }
2009
2010         if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) {
2011                 sc->bce_flags |= BCE_NO_WOL_FLAG;
2012                 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
2013                         sc->bce_phy_addr = 2;
2014                         val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG);
2015                         if (val & BCE_SHARED_HW_CFG_PHY_2_5G)
2016                                 sc->bce_phy_flags |= BCE_PHY_2_5G_CAPABLE_FLAG;
2017                 }
2018         } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) ||
2019             (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)) {
2020                 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG;
2021         }
2022 }
2023
2024
2025 /****************************************************************************/
2026 /* Free any DMA memory owned by the driver.                                 */
2027 /*                                                                          */
2028 /* Scans through each data structre that requires DMA memory and frees      */
2029 /* the memory if allocated.                                                 */
2030 /*                                                                          */
2031 /* Returns:                                                                 */
2032 /*   Nothing.                                                               */
2033 /****************************************************************************/
2034 static void
2035 bce_dma_free(struct bce_softc *sc)
2036 {
2037         int i;
2038
2039         /* Destroy the status block. */
2040         if (sc->status_tag != NULL) {
2041                 if (sc->status_block != NULL) {
2042                         bus_dmamap_unload(sc->status_tag, sc->status_map);
2043                         bus_dmamem_free(sc->status_tag, sc->status_block,
2044                                         sc->status_map);
2045                 }
2046                 bus_dma_tag_destroy(sc->status_tag);
2047         }
2048
2049         /* Destroy the statistics block. */
2050         if (sc->stats_tag != NULL) {
2051                 if (sc->stats_block != NULL) {
2052                         bus_dmamap_unload(sc->stats_tag, sc->stats_map);
2053                         bus_dmamem_free(sc->stats_tag, sc->stats_block,
2054                                         sc->stats_map);
2055                 }
2056                 bus_dma_tag_destroy(sc->stats_tag);
2057         }
2058
2059         /* Destroy the CTX DMA stuffs. */
2060         if (sc->ctx_tag != NULL) {
2061                 for (i = 0; i < sc->ctx_pages; i++) {
2062                         if (sc->ctx_block[i] != NULL) {
2063                                 bus_dmamap_unload(sc->ctx_tag, sc->ctx_map[i]);
2064                                 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
2065                                                 sc->ctx_map[i]);
2066                         }
2067                 }
2068                 bus_dma_tag_destroy(sc->ctx_tag);
2069         }
2070
2071         /* Destroy the TX buffer descriptor DMA stuffs. */
2072         if (sc->tx_bd_chain_tag != NULL) {
2073                 for (i = 0; i < sc->tx_pages; i++) {
2074                         if (sc->tx_bd_chain[i] != NULL) {
2075                                 bus_dmamap_unload(sc->tx_bd_chain_tag,
2076                                                   sc->tx_bd_chain_map[i]);
2077                                 bus_dmamem_free(sc->tx_bd_chain_tag,
2078                                                 sc->tx_bd_chain[i],
2079                                                 sc->tx_bd_chain_map[i]);
2080                         }
2081                 }
2082                 bus_dma_tag_destroy(sc->tx_bd_chain_tag);
2083         }
2084
2085         /* Destroy the RX buffer descriptor DMA stuffs. */
2086         if (sc->rx_bd_chain_tag != NULL) {
2087                 for (i = 0; i < sc->rx_pages; i++) {
2088                         if (sc->rx_bd_chain[i] != NULL) {
2089                                 bus_dmamap_unload(sc->rx_bd_chain_tag,
2090                                                   sc->rx_bd_chain_map[i]);
2091                                 bus_dmamem_free(sc->rx_bd_chain_tag,
2092                                                 sc->rx_bd_chain[i],
2093                                                 sc->rx_bd_chain_map[i]);
2094                         }
2095                 }
2096                 bus_dma_tag_destroy(sc->rx_bd_chain_tag);
2097         }
2098
2099         /* Destroy the TX mbuf DMA stuffs. */
2100         if (sc->tx_mbuf_tag != NULL) {
2101                 for (i = 0; i < TOTAL_TX_BD(sc); i++) {
2102                         /* Must have been unloaded in bce_stop() */
2103                         KKASSERT(sc->tx_mbuf_ptr[i] == NULL);
2104                         bus_dmamap_destroy(sc->tx_mbuf_tag,
2105                                            sc->tx_mbuf_map[i]);
2106                 }
2107                 bus_dma_tag_destroy(sc->tx_mbuf_tag);
2108         }
2109
2110         /* Destroy the RX mbuf DMA stuffs. */
2111         if (sc->rx_mbuf_tag != NULL) {
2112                 for (i = 0; i < TOTAL_RX_BD(sc); i++) {
2113                         /* Must have been unloaded in bce_stop() */
2114                         KKASSERT(sc->rx_mbuf_ptr[i] == NULL);
2115                         bus_dmamap_destroy(sc->rx_mbuf_tag,
2116                                            sc->rx_mbuf_map[i]);
2117                 }
2118                 bus_dmamap_destroy(sc->rx_mbuf_tag, sc->rx_mbuf_tmpmap);
2119                 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2120         }
2121
2122         /* Destroy the parent tag */
2123         if (sc->parent_tag != NULL)
2124                 bus_dma_tag_destroy(sc->parent_tag);
2125
2126         if (sc->tx_bd_chain_map != NULL)
2127                 kfree(sc->tx_bd_chain_map, M_DEVBUF);
2128         if (sc->tx_bd_chain != NULL)
2129                 kfree(sc->tx_bd_chain, M_DEVBUF);
2130         if (sc->tx_bd_chain_paddr != NULL)
2131                 kfree(sc->tx_bd_chain_paddr, M_DEVBUF);
2132
2133         if (sc->rx_bd_chain_map != NULL)
2134                 kfree(sc->rx_bd_chain_map, M_DEVBUF);
2135         if (sc->rx_bd_chain != NULL)
2136                 kfree(sc->rx_bd_chain, M_DEVBUF);
2137         if (sc->rx_bd_chain_paddr != NULL)
2138                 kfree(sc->rx_bd_chain_paddr, M_DEVBUF);
2139
2140         if (sc->tx_mbuf_map != NULL)
2141                 kfree(sc->tx_mbuf_map, M_DEVBUF);
2142         if (sc->tx_mbuf_ptr != NULL)
2143                 kfree(sc->tx_mbuf_ptr, M_DEVBUF);
2144
2145         if (sc->rx_mbuf_map != NULL)
2146                 kfree(sc->rx_mbuf_map, M_DEVBUF);
2147         if (sc->rx_mbuf_ptr != NULL)
2148                 kfree(sc->rx_mbuf_ptr, M_DEVBUF);
2149         if (sc->rx_mbuf_paddr != NULL)
2150                 kfree(sc->rx_mbuf_paddr, M_DEVBUF);
2151 }
2152
2153
2154 /****************************************************************************/
2155 /* Get DMA memory from the OS.                                              */
2156 /*                                                                          */
2157 /* Validates that the OS has provided DMA buffers in response to a          */
2158 /* bus_dmamap_load() call and saves the physical address of those buffers.  */
2159 /* When the callback is used the OS will return 0 for the mapping function  */
2160 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any  */
2161 /* failures back to the caller.                                             */
2162 /*                                                                          */
2163 /* Returns:                                                                 */
2164 /*   Nothing.                                                               */
2165 /****************************************************************************/
2166 static void
2167 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
2168 {
2169         bus_addr_t *busaddr = arg;
2170
2171         /*
2172          * Simulate a mapping failure.
2173          * XXX not correct.
2174          */
2175         DBRUNIF(DB_RANDOMTRUE(bce_debug_dma_map_addr_failure),
2176                 kprintf("bce: %s(%d): Simulating DMA mapping error.\n",
2177                         __FILE__, __LINE__);
2178                 error = ENOMEM);
2179                 
2180         /* Check for an error and signal the caller that an error occurred. */
2181         if (error)
2182                 return;
2183
2184         KASSERT(nseg == 1, ("only one segment is allowed"));
2185         *busaddr = segs->ds_addr;
2186 }
2187
2188
2189 /****************************************************************************/
2190 /* Allocate any DMA memory needed by the driver.                            */
2191 /*                                                                          */
2192 /* Allocates DMA memory needed for the various global structures needed by  */
2193 /* hardware.                                                                */
2194 /*                                                                          */
2195 /* Memory alignment requirements:                                           */
2196 /* -----------------+----------+----------+----------+----------+           */
2197 /*  Data Structure  |   5706   |   5708   |   5709   |   5716   |           */
2198 /* -----------------+----------+----------+----------+----------+           */
2199 /* Status Block     | 8 bytes  | 8 bytes  | 16 bytes | 16 bytes |           */
2200 /* Statistics Block | 8 bytes  | 8 bytes  | 16 bytes | 16 bytes |           */
2201 /* RX Buffers       | 16 bytes | 16 bytes | 16 bytes | 16 bytes |           */
2202 /* PG Buffers       |   none   |   none   |   none   |   none   |           */
2203 /* TX Buffers       |   none   |   none   |   none   |   none   |           */
2204 /* Chain Pages(1)   |   4KiB   |   4KiB   |   4KiB   |   4KiB   |           */
2205 /* Context Pages(1) |   N/A    |   N/A    |   4KiB   |   4KiB   |           */
2206 /* -----------------+----------+----------+----------+----------+           */
2207 /*                                                                          */
2208 /* (1) Must align with CPU page size (BCM_PAGE_SZIE).                       */
2209 /*                                                                          */
2210 /* Returns:                                                                 */
2211 /*   0 for success, positive value for failure.                             */
2212 /****************************************************************************/
2213 static int
2214 bce_dma_alloc(struct bce_softc *sc)
2215 {
2216         struct ifnet *ifp = &sc->arpcom.ac_if;
2217         int i, j, rc = 0, pages;
2218         bus_addr_t busaddr, max_busaddr;
2219         bus_size_t status_align, stats_align;
2220
2221         pages = device_getenv_int(sc->bce_dev, "rx_pages", bce_rx_pages);
2222         if (pages <= 0 || pages > RX_PAGES_MAX || !powerof2(pages)) {
2223                 device_printf(sc->bce_dev, "invalid # of RX pages\n");
2224                 pages = RX_PAGES_DEFAULT;
2225         }
2226         sc->rx_pages = pages;
2227
2228         pages = device_getenv_int(sc->bce_dev, "tx_pages", bce_tx_pages);
2229         if (pages <= 0 || pages > TX_PAGES_MAX || !powerof2(pages)) {
2230                 device_printf(sc->bce_dev, "invalid # of TX pages\n");
2231                 pages = TX_PAGES_DEFAULT;
2232         }
2233         sc->tx_pages = pages;
2234
2235         sc->tx_bd_chain_map = kmalloc(sizeof(bus_dmamap_t) * sc->tx_pages,
2236             M_DEVBUF, M_WAITOK | M_ZERO);
2237         sc->tx_bd_chain = kmalloc(sizeof(struct tx_bd *) * sc->tx_pages,
2238             M_DEVBUF, M_WAITOK | M_ZERO);
2239         sc->tx_bd_chain_paddr = kmalloc(sizeof(bus_addr_t) * sc->tx_pages,
2240             M_DEVBUF, M_WAITOK | M_ZERO);
2241
2242         sc->rx_bd_chain_map = kmalloc(sizeof(bus_dmamap_t) * sc->rx_pages,
2243             M_DEVBUF, M_WAITOK | M_ZERO);
2244         sc->rx_bd_chain = kmalloc(sizeof(struct rx_bd *) * sc->rx_pages,
2245             M_DEVBUF, M_WAITOK | M_ZERO);
2246         sc->rx_bd_chain_paddr = kmalloc(sizeof(bus_addr_t) * sc->rx_pages,
2247             M_DEVBUF, M_WAITOK | M_ZERO);
2248
2249         sc->tx_mbuf_map = kmalloc(sizeof(bus_dmamap_t) * TOTAL_TX_BD(sc),
2250             M_DEVBUF, M_WAITOK | M_ZERO);
2251         sc->tx_mbuf_ptr = kmalloc(sizeof(struct mbuf *) * TOTAL_TX_BD(sc),
2252             M_DEVBUF, M_WAITOK | M_ZERO);
2253
2254         sc->rx_mbuf_map = kmalloc(sizeof(bus_dmamap_t) * TOTAL_RX_BD(sc),
2255             M_DEVBUF, M_WAITOK | M_ZERO);
2256         sc->rx_mbuf_ptr = kmalloc(sizeof(struct mbuf *) * TOTAL_RX_BD(sc),
2257             M_DEVBUF, M_WAITOK | M_ZERO);
2258         sc->rx_mbuf_paddr = kmalloc(sizeof(bus_addr_t) * TOTAL_RX_BD(sc),
2259             M_DEVBUF, M_WAITOK | M_ZERO);
2260
2261         /*
2262          * The embedded PCIe to PCI-X bridge (EPB) 
2263          * in the 5708 cannot address memory above 
2264          * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043). 
2265          */
2266         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)
2267                 max_busaddr = BCE_BUS_SPACE_MAXADDR;
2268         else
2269                 max_busaddr = BUS_SPACE_MAXADDR;
2270
2271         /*
2272          * BCM5709 and BCM5716 uses host memory as cache for context memory.
2273          */
2274         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2275             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2276                 sc->ctx_pages = BCE_CTX_BLK_SZ / BCM_PAGE_SIZE;
2277                 if (sc->ctx_pages == 0)
2278                         sc->ctx_pages = 1;
2279                 if (sc->ctx_pages > BCE_CTX_PAGES) {
2280                         device_printf(sc->bce_dev, "excessive ctx pages %d\n",
2281                             sc->ctx_pages);
2282                         return ENOMEM;
2283                 }
2284                 status_align = 16;
2285                 stats_align = 16;
2286         } else {
2287                 status_align = 8;
2288                 stats_align = 8;
2289         }
2290
2291         /*
2292          * Allocate the parent bus DMA tag appropriate for PCI.
2293          */
2294         rc = bus_dma_tag_create(NULL, 1, BCE_DMA_BOUNDARY,
2295                                 max_busaddr, BUS_SPACE_MAXADDR,
2296                                 NULL, NULL,
2297                                 BUS_SPACE_MAXSIZE_32BIT, 0,
2298                                 BUS_SPACE_MAXSIZE_32BIT,
2299                                 0, &sc->parent_tag);
2300         if (rc != 0) {
2301                 if_printf(ifp, "Could not allocate parent DMA tag!\n");
2302                 return rc;
2303         }
2304
2305         /*
2306          * Allocate status block.
2307          */
2308         sc->status_block = bus_dmamem_coherent_any(sc->parent_tag,
2309                                 status_align, BCE_STATUS_BLK_SZ,
2310                                 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2311                                 &sc->status_tag, &sc->status_map,
2312                                 &sc->status_block_paddr);
2313         if (sc->status_block == NULL) {
2314                 if_printf(ifp, "Could not allocate status block!\n");
2315                 return ENOMEM;
2316         }
2317
2318         /*
2319          * Allocate statistics block.
2320          */
2321         sc->stats_block = bus_dmamem_coherent_any(sc->parent_tag,
2322                                 stats_align, BCE_STATS_BLK_SZ,
2323                                 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2324                                 &sc->stats_tag, &sc->stats_map,
2325                                 &sc->stats_block_paddr);
2326         if (sc->stats_block == NULL) {
2327                 if_printf(ifp, "Could not allocate statistics block!\n");
2328                 return ENOMEM;
2329         }
2330
2331         /*
2332          * Allocate context block, if needed
2333          */
2334         if (sc->ctx_pages != 0) {
2335                 rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2336                                         BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2337                                         NULL, NULL,
2338                                         BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE,
2339                                         0, &sc->ctx_tag);
2340                 if (rc != 0) {
2341                         if_printf(ifp, "Could not allocate "
2342                                   "context block DMA tag!\n");
2343                         return rc;
2344                 }
2345
2346                 for (i = 0; i < sc->ctx_pages; i++) {
2347                         rc = bus_dmamem_alloc(sc->ctx_tag,
2348                                               (void **)&sc->ctx_block[i],
2349                                               BUS_DMA_WAITOK | BUS_DMA_ZERO |
2350                                               BUS_DMA_COHERENT,
2351                                               &sc->ctx_map[i]);
2352                         if (rc != 0) {
2353                                 if_printf(ifp, "Could not allocate %dth context "
2354                                           "DMA memory!\n", i);
2355                                 return rc;
2356                         }
2357
2358                         rc = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i],
2359                                              sc->ctx_block[i], BCM_PAGE_SIZE,
2360                                              bce_dma_map_addr, &busaddr,
2361                                              BUS_DMA_WAITOK);
2362                         if (rc != 0) {
2363                                 if (rc == EINPROGRESS) {
2364                                         panic("%s coherent memory loading "
2365                                               "is still in progress!", ifp->if_xname);
2366                                 }
2367                                 if_printf(ifp, "Could not map %dth context "
2368                                           "DMA memory!\n", i);
2369                                 bus_dmamem_free(sc->ctx_tag, sc->ctx_block[i],
2370                                                 sc->ctx_map[i]);
2371                                 sc->ctx_block[i] = NULL;
2372                                 return rc;
2373                         }
2374                         sc->ctx_paddr[i] = busaddr;
2375                 }
2376         }
2377
2378         /*
2379          * Create a DMA tag for the TX buffer descriptor chain,
2380          * allocate and clear the  memory, and fetch the
2381          * physical address of the block.
2382          */
2383         rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2384                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2385                                 NULL, NULL,
2386                                 BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ,
2387                                 0, &sc->tx_bd_chain_tag);
2388         if (rc != 0) {
2389                 if_printf(ifp, "Could not allocate "
2390                           "TX descriptor chain DMA tag!\n");
2391                 return rc;
2392         }
2393
2394         for (i = 0; i < sc->tx_pages; i++) {
2395                 rc = bus_dmamem_alloc(sc->tx_bd_chain_tag,
2396                                       (void **)&sc->tx_bd_chain[i],
2397                                       BUS_DMA_WAITOK | BUS_DMA_ZERO |
2398                                       BUS_DMA_COHERENT,
2399                                       &sc->tx_bd_chain_map[i]);
2400                 if (rc != 0) {
2401                         if_printf(ifp, "Could not allocate %dth TX descriptor "
2402                                   "chain DMA memory!\n", i);
2403                         return rc;
2404                 }
2405
2406                 rc = bus_dmamap_load(sc->tx_bd_chain_tag,
2407                                      sc->tx_bd_chain_map[i],
2408                                      sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ,
2409                                      bce_dma_map_addr, &busaddr,
2410                                      BUS_DMA_WAITOK);
2411                 if (rc != 0) {
2412                         if (rc == EINPROGRESS) {
2413                                 panic("%s coherent memory loading "
2414                                       "is still in progress!", ifp->if_xname);
2415                         }
2416                         if_printf(ifp, "Could not map %dth TX descriptor "
2417                                   "chain DMA memory!\n", i);
2418                         bus_dmamem_free(sc->tx_bd_chain_tag,
2419                                         sc->tx_bd_chain[i],
2420                                         sc->tx_bd_chain_map[i]);
2421                         sc->tx_bd_chain[i] = NULL;
2422                         return rc;
2423                 }
2424
2425                 sc->tx_bd_chain_paddr[i] = busaddr;
2426                 /* DRC - Fix for 64 bit systems. */
2427                 DBPRINT(sc, BCE_INFO, "tx_bd_chain_paddr[%d] = 0x%08X\n", 
2428                         i, (uint32_t)sc->tx_bd_chain_paddr[i]);
2429         }
2430
2431         /* Create a DMA tag for TX mbufs. */
2432         rc = bus_dma_tag_create(sc->parent_tag, 1, 0,
2433                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2434                                 NULL, NULL,
2435                                 IP_MAXPACKET + sizeof(struct ether_vlan_header),
2436                                 BCE_MAX_SEGMENTS, PAGE_SIZE,
2437                                 BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK |
2438                                 BUS_DMA_ONEBPAGE,
2439                                 &sc->tx_mbuf_tag);
2440         if (rc != 0) {
2441                 if_printf(ifp, "Could not allocate TX mbuf DMA tag!\n");
2442                 return rc;
2443         }
2444
2445         /* Create DMA maps for the TX mbufs clusters. */
2446         for (i = 0; i < TOTAL_TX_BD(sc); i++) {
2447                 rc = bus_dmamap_create(sc->tx_mbuf_tag,
2448                                        BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2449                                        &sc->tx_mbuf_map[i]);
2450                 if (rc != 0) {
2451                         for (j = 0; j < i; ++j) {
2452                                 bus_dmamap_destroy(sc->tx_mbuf_tag,
2453                                                    sc->tx_mbuf_map[i]);
2454                         }
2455                         bus_dma_tag_destroy(sc->tx_mbuf_tag);
2456                         sc->tx_mbuf_tag = NULL;
2457
2458                         if_printf(ifp, "Unable to create "
2459                                   "%dth TX mbuf DMA map!\n", i);
2460                         return rc;
2461                 }
2462         }
2463
2464         /*
2465          * Create a DMA tag for the RX buffer descriptor chain,
2466          * allocate and clear the  memory, and fetch the physical
2467          * address of the blocks.
2468          */
2469         rc = bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, 0,
2470                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2471                                 NULL, NULL,
2472                                 BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ,
2473                                 0, &sc->rx_bd_chain_tag);
2474         if (rc != 0) {
2475                 if_printf(ifp, "Could not allocate "
2476                           "RX descriptor chain DMA tag!\n");
2477                 return rc;
2478         }
2479
2480         for (i = 0; i < sc->rx_pages; i++) {
2481                 rc = bus_dmamem_alloc(sc->rx_bd_chain_tag,
2482                                       (void **)&sc->rx_bd_chain[i],
2483                                       BUS_DMA_WAITOK | BUS_DMA_ZERO |
2484                                       BUS_DMA_COHERENT,
2485                                       &sc->rx_bd_chain_map[i]);
2486                 if (rc != 0) {
2487                         if_printf(ifp, "Could not allocate %dth RX descriptor "
2488                                   "chain DMA memory!\n", i);
2489                         return rc;
2490                 }
2491
2492                 rc = bus_dmamap_load(sc->rx_bd_chain_tag,
2493                                      sc->rx_bd_chain_map[i],
2494                                      sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ,
2495                                      bce_dma_map_addr, &busaddr,
2496                                      BUS_DMA_WAITOK);
2497                 if (rc != 0) {
2498                         if (rc == EINPROGRESS) {
2499                                 panic("%s coherent memory loading "
2500                                       "is still in progress!", ifp->if_xname);
2501                         }
2502                         if_printf(ifp, "Could not map %dth RX descriptor "
2503                                   "chain DMA memory!\n", i);
2504                         bus_dmamem_free(sc->rx_bd_chain_tag,
2505                                         sc->rx_bd_chain[i],
2506                                         sc->rx_bd_chain_map[i]);
2507                         sc->rx_bd_chain[i] = NULL;
2508                         return rc;
2509                 }
2510
2511                 sc->rx_bd_chain_paddr[i] = busaddr;
2512                 /* DRC - Fix for 64 bit systems. */
2513                 DBPRINT(sc, BCE_INFO, "rx_bd_chain_paddr[%d] = 0x%08X\n",
2514                         i, (uint32_t)sc->rx_bd_chain_paddr[i]);
2515         }
2516
2517         /* Create a DMA tag for RX mbufs. */
2518         rc = bus_dma_tag_create(sc->parent_tag, BCE_DMA_RX_ALIGN, 0,
2519                                 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
2520                                 NULL, NULL,
2521                                 MCLBYTES, 1, MCLBYTES,
2522                                 BUS_DMA_ALLOCNOW | BUS_DMA_ALIGNED |
2523                                 BUS_DMA_WAITOK,
2524                                 &sc->rx_mbuf_tag);
2525         if (rc != 0) {
2526                 if_printf(ifp, "Could not allocate RX mbuf DMA tag!\n");
2527                 return rc;
2528         }
2529
2530         /* Create tmp DMA map for RX mbuf clusters. */
2531         rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2532                                &sc->rx_mbuf_tmpmap);
2533         if (rc != 0) {
2534                 bus_dma_tag_destroy(sc->rx_mbuf_tag);
2535                 sc->rx_mbuf_tag = NULL;
2536
2537                 if_printf(ifp, "Could not create RX mbuf tmp DMA map!\n");
2538                 return rc;
2539         }
2540
2541         /* Create DMA maps for the RX mbuf clusters. */
2542         for (i = 0; i < TOTAL_RX_BD(sc); i++) {
2543                 rc = bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_WAITOK,
2544                                        &sc->rx_mbuf_map[i]);
2545                 if (rc != 0) {
2546                         for (j = 0; j < i; ++j) {
2547                                 bus_dmamap_destroy(sc->rx_mbuf_tag,
2548                                                    sc->rx_mbuf_map[j]);
2549                         }
2550                         bus_dma_tag_destroy(sc->rx_mbuf_tag);
2551                         sc->rx_mbuf_tag = NULL;
2552
2553                         if_printf(ifp, "Unable to create "
2554                                   "%dth RX mbuf DMA map!\n", i);
2555                         return rc;
2556                 }
2557         }
2558         return 0;
2559 }
2560
2561
2562 /****************************************************************************/
2563 /* Firmware synchronization.                                                */
2564 /*                                                                          */
2565 /* Before performing certain events such as a chip reset, synchronize with  */
2566 /* the firmware first.                                                      */
2567 /*                                                                          */
2568 /* Returns:                                                                 */
2569 /*   0 for success, positive value for failure.                             */
2570 /****************************************************************************/
2571 static int
2572 bce_fw_sync(struct bce_softc *sc, uint32_t msg_data)
2573 {
2574         int i, rc = 0;
2575         uint32_t val;
2576
2577         /* Don't waste any time if we've timed out before. */
2578         if (sc->bce_fw_timed_out)
2579                 return EBUSY;
2580
2581         /* Increment the message sequence number. */
2582         sc->bce_fw_wr_seq++;
2583         msg_data |= sc->bce_fw_wr_seq;
2584
2585         DBPRINT(sc, BCE_VERBOSE, "bce_fw_sync(): msg_data = 0x%08X\n", msg_data);
2586
2587         /* Send the message to the bootcode driver mailbox. */
2588         bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
2589
2590         /* Wait for the bootcode to acknowledge the message. */
2591         for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) {
2592                 /* Check for a response in the bootcode firmware mailbox. */
2593                 val = bce_shmem_rd(sc, BCE_FW_MB);
2594                 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ))
2595                         break;
2596                 DELAY(1000);
2597         }
2598
2599         /* If we've timed out, tell the bootcode that we've stopped waiting. */
2600         if ((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ) &&
2601             (msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0) {
2602                 if_printf(&sc->arpcom.ac_if,
2603                           "Firmware synchronization timeout! "
2604                           "msg_data = 0x%08X\n", msg_data);
2605
2606                 msg_data &= ~BCE_DRV_MSG_CODE;
2607                 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT;
2608
2609                 bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
2610
2611                 sc->bce_fw_timed_out = 1;
2612                 rc = EBUSY;
2613         }
2614         return rc;
2615 }
2616
2617
2618 /****************************************************************************/
2619 /* Load Receive Virtual 2 Physical (RV2P) processor firmware.               */
2620 /*                                                                          */
2621 /* Returns:                                                                 */
2622 /*   Nothing.                                                               */
2623 /****************************************************************************/
2624 static void
2625 bce_load_rv2p_fw(struct bce_softc *sc, uint32_t *rv2p_code,
2626                  uint32_t rv2p_code_len, uint32_t rv2p_proc)
2627 {
2628         int i;
2629         uint32_t val;
2630
2631         for (i = 0; i < rv2p_code_len; i += 8) {
2632                 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code);
2633                 rv2p_code++;
2634                 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code);
2635                 rv2p_code++;
2636
2637                 if (rv2p_proc == RV2P_PROC1) {
2638                         val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR;
2639                         REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
2640                 } else {
2641                         val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR;
2642                         REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
2643                 }
2644         }
2645
2646         /* Reset the processor, un-stall is done later. */
2647         if (rv2p_proc == RV2P_PROC1)
2648                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET);
2649         else
2650                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET);
2651 }
2652
2653
2654 /****************************************************************************/
2655 /* Load RISC processor firmware.                                            */
2656 /*                                                                          */
2657 /* Loads firmware from the file if_bcefw.h into the scratchpad memory       */
2658 /* associated with a particular processor.                                  */
2659 /*                                                                          */
2660 /* Returns:                                                                 */
2661 /*   Nothing.                                                               */
2662 /****************************************************************************/
2663 static void
2664 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg,
2665                 struct fw_info *fw)
2666 {
2667         uint32_t offset;
2668         int j;
2669
2670         bce_halt_cpu(sc, cpu_reg);
2671
2672         /* Load the Text area. */
2673         offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
2674         if (fw->text) {
2675                 for (j = 0; j < (fw->text_len / 4); j++, offset += 4)
2676                         REG_WR_IND(sc, offset, fw->text[j]);
2677         }
2678
2679         /* Load the Data area. */
2680         offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
2681         if (fw->data) {
2682                 for (j = 0; j < (fw->data_len / 4); j++, offset += 4)
2683                         REG_WR_IND(sc, offset, fw->data[j]);
2684         }
2685
2686         /* Load the SBSS area. */
2687         offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
2688         if (fw->sbss) {
2689                 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4)
2690                         REG_WR_IND(sc, offset, fw->sbss[j]);
2691         }
2692
2693         /* Load the BSS area. */
2694         offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
2695         if (fw->bss) {
2696                 for (j = 0; j < (fw->bss_len/4); j++, offset += 4)
2697                         REG_WR_IND(sc, offset, fw->bss[j]);
2698         }
2699
2700         /* Load the Read-Only area. */
2701         offset = cpu_reg->spad_base +
2702                 (fw->rodata_addr - cpu_reg->mips_view_base);
2703         if (fw->rodata) {
2704                 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4)
2705                         REG_WR_IND(sc, offset, fw->rodata[j]);
2706         }
2707
2708         /* Clear the pre-fetch instruction and set the FW start address. */
2709         REG_WR_IND(sc, cpu_reg->inst, 0);
2710         REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
2711 }
2712
2713
2714 /****************************************************************************/
2715 /* Starts the RISC processor.                                               */
2716 /*                                                                          */
2717 /* Assumes the CPU starting address has already been set.                   */
2718 /*                                                                          */
2719 /* Returns:                                                                 */
2720 /*   Nothing.                                                               */
2721 /****************************************************************************/
2722 static void
2723 bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
2724 {
2725         uint32_t val;
2726
2727         /* Start the CPU. */
2728         val = REG_RD_IND(sc, cpu_reg->mode);
2729         val &= ~cpu_reg->mode_value_halt;
2730         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2731         REG_WR_IND(sc, cpu_reg->mode, val);
2732 }
2733
2734
2735 /****************************************************************************/
2736 /* Halts the RISC processor.                                                */
2737 /*                                                                          */
2738 /* Returns:                                                                 */
2739 /*   Nothing.                                                               */
2740 /****************************************************************************/
2741 static void
2742 bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
2743 {
2744         uint32_t val;
2745
2746         /* Halt the CPU. */
2747         val = REG_RD_IND(sc, cpu_reg->mode);
2748         val |= cpu_reg->mode_value_halt;
2749         REG_WR_IND(sc, cpu_reg->mode, val);
2750         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
2751 }
2752
2753
2754 /****************************************************************************/
2755 /* Start the RX CPU.                                                        */
2756 /*                                                                          */
2757 /* Returns:                                                                 */
2758 /*   Nothing.                                                               */
2759 /****************************************************************************/
2760 static void
2761 bce_start_rxp_cpu(struct bce_softc *sc)
2762 {
2763         struct cpu_reg cpu_reg;
2764
2765         cpu_reg.mode = BCE_RXP_CPU_MODE;
2766         cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2767         cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2768         cpu_reg.state = BCE_RXP_CPU_STATE;
2769         cpu_reg.state_value_clear = 0xffffff;
2770         cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2771         cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2772         cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2773         cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2774         cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2775         cpu_reg.spad_base = BCE_RXP_SCRATCH;
2776         cpu_reg.mips_view_base = 0x8000000;
2777
2778         bce_start_cpu(sc, &cpu_reg);
2779 }
2780
2781
2782 /****************************************************************************/
2783 /* Initialize the RX CPU.                                                   */
2784 /*                                                                          */
2785 /* Returns:                                                                 */
2786 /*   Nothing.                                                               */
2787 /****************************************************************************/
2788 static void
2789 bce_init_rxp_cpu(struct bce_softc *sc)
2790 {
2791         struct cpu_reg cpu_reg;
2792         struct fw_info fw;
2793
2794         cpu_reg.mode = BCE_RXP_CPU_MODE;
2795         cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
2796         cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
2797         cpu_reg.state = BCE_RXP_CPU_STATE;
2798         cpu_reg.state_value_clear = 0xffffff;
2799         cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
2800         cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
2801         cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
2802         cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
2803         cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
2804         cpu_reg.spad_base = BCE_RXP_SCRATCH;
2805         cpu_reg.mips_view_base = 0x8000000;
2806
2807         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2808             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2809                 fw.ver_major = bce_RXP_b09FwReleaseMajor;
2810                 fw.ver_minor = bce_RXP_b09FwReleaseMinor;
2811                 fw.ver_fix = bce_RXP_b09FwReleaseFix;
2812                 fw.start_addr = bce_RXP_b09FwStartAddr;
2813
2814                 fw.text_addr = bce_RXP_b09FwTextAddr;
2815                 fw.text_len = bce_RXP_b09FwTextLen;
2816                 fw.text_index = 0;
2817                 fw.text = bce_RXP_b09FwText;
2818
2819                 fw.data_addr = bce_RXP_b09FwDataAddr;
2820                 fw.data_len = bce_RXP_b09FwDataLen;
2821                 fw.data_index = 0;
2822                 fw.data = bce_RXP_b09FwData;
2823
2824                 fw.sbss_addr = bce_RXP_b09FwSbssAddr;
2825                 fw.sbss_len = bce_RXP_b09FwSbssLen;
2826                 fw.sbss_index = 0;
2827                 fw.sbss = bce_RXP_b09FwSbss;
2828
2829                 fw.bss_addr = bce_RXP_b09FwBssAddr;
2830                 fw.bss_len = bce_RXP_b09FwBssLen;
2831                 fw.bss_index = 0;
2832                 fw.bss = bce_RXP_b09FwBss;
2833
2834                 fw.rodata_addr = bce_RXP_b09FwRodataAddr;
2835                 fw.rodata_len = bce_RXP_b09FwRodataLen;
2836                 fw.rodata_index = 0;
2837                 fw.rodata = bce_RXP_b09FwRodata;
2838         } else {
2839                 fw.ver_major = bce_RXP_b06FwReleaseMajor;
2840                 fw.ver_minor = bce_RXP_b06FwReleaseMinor;
2841                 fw.ver_fix = bce_RXP_b06FwReleaseFix;
2842                 fw.start_addr = bce_RXP_b06FwStartAddr;
2843
2844                 fw.text_addr = bce_RXP_b06FwTextAddr;
2845                 fw.text_len = bce_RXP_b06FwTextLen;
2846                 fw.text_index = 0;
2847                 fw.text = bce_RXP_b06FwText;
2848
2849                 fw.data_addr = bce_RXP_b06FwDataAddr;
2850                 fw.data_len = bce_RXP_b06FwDataLen;
2851                 fw.data_index = 0;
2852                 fw.data = bce_RXP_b06FwData;
2853
2854                 fw.sbss_addr = bce_RXP_b06FwSbssAddr;
2855                 fw.sbss_len = bce_RXP_b06FwSbssLen;
2856                 fw.sbss_index = 0;
2857                 fw.sbss = bce_RXP_b06FwSbss;
2858
2859                 fw.bss_addr = bce_RXP_b06FwBssAddr;
2860                 fw.bss_len = bce_RXP_b06FwBssLen;
2861                 fw.bss_index = 0;
2862                 fw.bss = bce_RXP_b06FwBss;
2863
2864                 fw.rodata_addr = bce_RXP_b06FwRodataAddr;
2865                 fw.rodata_len = bce_RXP_b06FwRodataLen;
2866                 fw.rodata_index = 0;
2867                 fw.rodata = bce_RXP_b06FwRodata;
2868         }
2869
2870         DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n");
2871         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2872         /* Delay RXP start until initialization is complete. */
2873 }
2874
2875
2876 /****************************************************************************/
2877 /* Initialize the TX CPU.                                                   */
2878 /*                                                                          */
2879 /* Returns:                                                                 */
2880 /*   Nothing.                                                               */
2881 /****************************************************************************/
2882 static void
2883 bce_init_txp_cpu(struct bce_softc *sc)
2884 {
2885         struct cpu_reg cpu_reg;
2886         struct fw_info fw;
2887
2888         cpu_reg.mode = BCE_TXP_CPU_MODE;
2889         cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT;
2890         cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA;
2891         cpu_reg.state = BCE_TXP_CPU_STATE;
2892         cpu_reg.state_value_clear = 0xffffff;
2893         cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE;
2894         cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK;
2895         cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER;
2896         cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION;
2897         cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT;
2898         cpu_reg.spad_base = BCE_TXP_SCRATCH;
2899         cpu_reg.mips_view_base = 0x8000000;
2900
2901         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2902             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2903                 fw.ver_major = bce_TXP_b09FwReleaseMajor;
2904                 fw.ver_minor = bce_TXP_b09FwReleaseMinor;
2905                 fw.ver_fix = bce_TXP_b09FwReleaseFix;
2906                 fw.start_addr = bce_TXP_b09FwStartAddr;
2907
2908                 fw.text_addr = bce_TXP_b09FwTextAddr;
2909                 fw.text_len = bce_TXP_b09FwTextLen;
2910                 fw.text_index = 0;
2911                 fw.text = bce_TXP_b09FwText;
2912
2913                 fw.data_addr = bce_TXP_b09FwDataAddr;
2914                 fw.data_len = bce_TXP_b09FwDataLen;
2915                 fw.data_index = 0;
2916                 fw.data = bce_TXP_b09FwData;
2917
2918                 fw.sbss_addr = bce_TXP_b09FwSbssAddr;
2919                 fw.sbss_len = bce_TXP_b09FwSbssLen;
2920                 fw.sbss_index = 0;
2921                 fw.sbss = bce_TXP_b09FwSbss;
2922
2923                 fw.bss_addr = bce_TXP_b09FwBssAddr;
2924                 fw.bss_len = bce_TXP_b09FwBssLen;
2925                 fw.bss_index = 0;
2926                 fw.bss = bce_TXP_b09FwBss;
2927
2928                 fw.rodata_addr = bce_TXP_b09FwRodataAddr;
2929                 fw.rodata_len = bce_TXP_b09FwRodataLen;
2930                 fw.rodata_index = 0;
2931                 fw.rodata = bce_TXP_b09FwRodata;
2932         } else {
2933                 fw.ver_major = bce_TXP_b06FwReleaseMajor;
2934                 fw.ver_minor = bce_TXP_b06FwReleaseMinor;
2935                 fw.ver_fix = bce_TXP_b06FwReleaseFix;
2936                 fw.start_addr = bce_TXP_b06FwStartAddr;
2937
2938                 fw.text_addr = bce_TXP_b06FwTextAddr;
2939                 fw.text_len = bce_TXP_b06FwTextLen;
2940                 fw.text_index = 0;
2941                 fw.text = bce_TXP_b06FwText;
2942
2943                 fw.data_addr = bce_TXP_b06FwDataAddr;
2944                 fw.data_len = bce_TXP_b06FwDataLen;
2945                 fw.data_index = 0;
2946                 fw.data = bce_TXP_b06FwData;
2947
2948                 fw.sbss_addr = bce_TXP_b06FwSbssAddr;
2949                 fw.sbss_len = bce_TXP_b06FwSbssLen;
2950                 fw.sbss_index = 0;
2951                 fw.sbss = bce_TXP_b06FwSbss;
2952
2953                 fw.bss_addr = bce_TXP_b06FwBssAddr;
2954                 fw.bss_len = bce_TXP_b06FwBssLen;
2955                 fw.bss_index = 0;
2956                 fw.bss = bce_TXP_b06FwBss;
2957
2958                 fw.rodata_addr = bce_TXP_b06FwRodataAddr;
2959                 fw.rodata_len = bce_TXP_b06FwRodataLen;
2960                 fw.rodata_index = 0;
2961                 fw.rodata = bce_TXP_b06FwRodata;
2962         }
2963
2964         DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n");
2965         bce_load_cpu_fw(sc, &cpu_reg, &fw);
2966         bce_start_cpu(sc, &cpu_reg);
2967 }
2968
2969
2970 /****************************************************************************/
2971 /* Initialize the TPAT CPU.                                                 */
2972 /*                                                                          */
2973 /* Returns:                                                                 */
2974 /*   Nothing.                                                               */
2975 /****************************************************************************/
2976 static void
2977 bce_init_tpat_cpu(struct bce_softc *sc)
2978 {
2979         struct cpu_reg cpu_reg;
2980         struct fw_info fw;
2981
2982         cpu_reg.mode = BCE_TPAT_CPU_MODE;
2983         cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT;
2984         cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA;
2985         cpu_reg.state = BCE_TPAT_CPU_STATE;
2986         cpu_reg.state_value_clear = 0xffffff;
2987         cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE;
2988         cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK;
2989         cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER;
2990         cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION;
2991         cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT;
2992         cpu_reg.spad_base = BCE_TPAT_SCRATCH;
2993         cpu_reg.mips_view_base = 0x8000000;
2994
2995         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
2996             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
2997                 fw.ver_major = bce_TPAT_b09FwReleaseMajor;
2998                 fw.ver_minor = bce_TPAT_b09FwReleaseMinor;
2999                 fw.ver_fix = bce_TPAT_b09FwReleaseFix;
3000                 fw.start_addr = bce_TPAT_b09FwStartAddr;
3001
3002                 fw.text_addr = bce_TPAT_b09FwTextAddr;
3003                 fw.text_len = bce_TPAT_b09FwTextLen;
3004                 fw.text_index = 0;
3005                 fw.text = bce_TPAT_b09FwText;
3006
3007                 fw.data_addr = bce_TPAT_b09FwDataAddr;
3008                 fw.data_len = bce_TPAT_b09FwDataLen;
3009                 fw.data_index = 0;
3010                 fw.data = bce_TPAT_b09FwData;
3011
3012                 fw.sbss_addr = bce_TPAT_b09FwSbssAddr;
3013                 fw.sbss_len = bce_TPAT_b09FwSbssLen;
3014                 fw.sbss_index = 0;
3015                 fw.sbss = bce_TPAT_b09FwSbss;
3016
3017                 fw.bss_addr = bce_TPAT_b09FwBssAddr;
3018                 fw.bss_len = bce_TPAT_b09FwBssLen;
3019                 fw.bss_index = 0;
3020                 fw.bss = bce_TPAT_b09FwBss;
3021
3022                 fw.rodata_addr = bce_TPAT_b09FwRodataAddr;
3023                 fw.rodata_len = bce_TPAT_b09FwRodataLen;
3024                 fw.rodata_index = 0;
3025                 fw.rodata = bce_TPAT_b09FwRodata;
3026         } else {
3027                 fw.ver_major = bce_TPAT_b06FwReleaseMajor;
3028                 fw.ver_minor = bce_TPAT_b06FwReleaseMinor;
3029                 fw.ver_fix = bce_TPAT_b06FwReleaseFix;
3030                 fw.start_addr = bce_TPAT_b06FwStartAddr;
3031
3032                 fw.text_addr = bce_TPAT_b06FwTextAddr;
3033                 fw.text_len = bce_TPAT_b06FwTextLen;
3034                 fw.text_index = 0;
3035                 fw.text = bce_TPAT_b06FwText;
3036
3037                 fw.data_addr = bce_TPAT_b06FwDataAddr;
3038                 fw.data_len = bce_TPAT_b06FwDataLen;
3039                 fw.data_index = 0;
3040                 fw.data = bce_TPAT_b06FwData;
3041
3042                 fw.sbss_addr = bce_TPAT_b06FwSbssAddr;
3043                 fw.sbss_len = bce_TPAT_b06FwSbssLen;
3044                 fw.sbss_index = 0;
3045                 fw.sbss = bce_TPAT_b06FwSbss;
3046
3047                 fw.bss_addr = bce_TPAT_b06FwBssAddr;
3048                 fw.bss_len = bce_TPAT_b06FwBssLen;
3049                 fw.bss_index = 0;
3050                 fw.bss = bce_TPAT_b06FwBss;
3051
3052                 fw.rodata_addr = bce_TPAT_b06FwRodataAddr;
3053                 fw.rodata_len = bce_TPAT_b06FwRodataLen;
3054                 fw.rodata_index = 0;
3055                 fw.rodata = bce_TPAT_b06FwRodata;
3056         }
3057
3058         DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n");
3059         bce_load_cpu_fw(sc, &cpu_reg, &fw);
3060         bce_start_cpu(sc, &cpu_reg);
3061 }
3062
3063
3064 /****************************************************************************/
3065 /* Initialize the CP CPU.                                                   */
3066 /*                                                                          */
3067 /* Returns:                                                                 */
3068 /*   Nothing.                                                               */
3069 /****************************************************************************/
3070 static void
3071 bce_init_cp_cpu(struct bce_softc *sc)
3072 {
3073         struct cpu_reg cpu_reg;
3074         struct fw_info fw;
3075
3076         cpu_reg.mode = BCE_CP_CPU_MODE;
3077         cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT;
3078         cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA;
3079         cpu_reg.state = BCE_CP_CPU_STATE;
3080         cpu_reg.state_value_clear = 0xffffff;
3081         cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE;
3082         cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK;
3083         cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER;
3084         cpu_reg.inst = BCE_CP_CPU_INSTRUCTION;
3085         cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT;
3086         cpu_reg.spad_base = BCE_CP_SCRATCH;
3087         cpu_reg.mips_view_base = 0x8000000;
3088
3089         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3090             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3091                 fw.ver_major = bce_CP_b09FwReleaseMajor;
3092                 fw.ver_minor = bce_CP_b09FwReleaseMinor;
3093                 fw.ver_fix = bce_CP_b09FwReleaseFix;
3094                 fw.start_addr = bce_CP_b09FwStartAddr;
3095
3096                 fw.text_addr = bce_CP_b09FwTextAddr;
3097                 fw.text_len = bce_CP_b09FwTextLen;
3098                 fw.text_index = 0;
3099                 fw.text = bce_CP_b09FwText;
3100
3101                 fw.data_addr = bce_CP_b09FwDataAddr;
3102                 fw.data_len = bce_CP_b09FwDataLen;
3103                 fw.data_index = 0;
3104                 fw.data = bce_CP_b09FwData;
3105
3106                 fw.sbss_addr = bce_CP_b09FwSbssAddr;
3107                 fw.sbss_len = bce_CP_b09FwSbssLen;
3108                 fw.sbss_index = 0;
3109                 fw.sbss = bce_CP_b09FwSbss;
3110
3111                 fw.bss_addr = bce_CP_b09FwBssAddr;
3112                 fw.bss_len = bce_CP_b09FwBssLen;
3113                 fw.bss_index = 0;
3114                 fw.bss = bce_CP_b09FwBss;
3115
3116                 fw.rodata_addr = bce_CP_b09FwRodataAddr;
3117                 fw.rodata_len = bce_CP_b09FwRodataLen;
3118                 fw.rodata_index = 0;
3119                 fw.rodata = bce_CP_b09FwRodata;
3120         } else {
3121                 fw.ver_major = bce_CP_b06FwReleaseMajor;
3122                 fw.ver_minor = bce_CP_b06FwReleaseMinor;
3123                 fw.ver_fix = bce_CP_b06FwReleaseFix;
3124                 fw.start_addr = bce_CP_b06FwStartAddr;
3125
3126                 fw.text_addr = bce_CP_b06FwTextAddr;
3127                 fw.text_len = bce_CP_b06FwTextLen;
3128                 fw.text_index = 0;
3129                 fw.text = bce_CP_b06FwText;
3130
3131                 fw.data_addr = bce_CP_b06FwDataAddr;
3132                 fw.data_len = bce_CP_b06FwDataLen;
3133                 fw.data_index = 0;
3134                 fw.data = bce_CP_b06FwData;
3135
3136                 fw.sbss_addr = bce_CP_b06FwSbssAddr;
3137                 fw.sbss_len = bce_CP_b06FwSbssLen;
3138                 fw.sbss_index = 0;
3139                 fw.sbss = bce_CP_b06FwSbss;
3140
3141                 fw.bss_addr = bce_CP_b06FwBssAddr;
3142                 fw.bss_len = bce_CP_b06FwBssLen;
3143                 fw.bss_index = 0;
3144                 fw.bss = bce_CP_b06FwBss;
3145
3146                 fw.rodata_addr = bce_CP_b06FwRodataAddr;
3147                 fw.rodata_len = bce_CP_b06FwRodataLen;
3148                 fw.rodata_index = 0;
3149                 fw.rodata = bce_CP_b06FwRodata;
3150         }
3151
3152         DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n");
3153         bce_load_cpu_fw(sc, &cpu_reg, &fw);
3154         bce_start_cpu(sc, &cpu_reg);
3155 }
3156
3157
3158 /****************************************************************************/
3159 /* Initialize the COM CPU.                                                 */
3160 /*                                                                          */
3161 /* Returns:                                                                 */
3162 /*   Nothing.                                                               */
3163 /****************************************************************************/
3164 static void
3165 bce_init_com_cpu(struct bce_softc *sc)
3166 {
3167         struct cpu_reg cpu_reg;
3168         struct fw_info fw;
3169
3170         cpu_reg.mode = BCE_COM_CPU_MODE;
3171         cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT;
3172         cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA;
3173         cpu_reg.state = BCE_COM_CPU_STATE;
3174         cpu_reg.state_value_clear = 0xffffff;
3175         cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE;
3176         cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK;
3177         cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER;
3178         cpu_reg.inst = BCE_COM_CPU_INSTRUCTION;
3179         cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT;
3180         cpu_reg.spad_base = BCE_COM_SCRATCH;
3181         cpu_reg.mips_view_base = 0x8000000;
3182
3183         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3184             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3185                 fw.ver_major = bce_COM_b09FwReleaseMajor;
3186                 fw.ver_minor = bce_COM_b09FwReleaseMinor;
3187                 fw.ver_fix = bce_COM_b09FwReleaseFix;
3188                 fw.start_addr = bce_COM_b09FwStartAddr;
3189
3190                 fw.text_addr = bce_COM_b09FwTextAddr;
3191                 fw.text_len = bce_COM_b09FwTextLen;
3192                 fw.text_index = 0;
3193                 fw.text = bce_COM_b09FwText;
3194
3195                 fw.data_addr = bce_COM_b09FwDataAddr;
3196                 fw.data_len = bce_COM_b09FwDataLen;
3197                 fw.data_index = 0;
3198                 fw.data = bce_COM_b09FwData;
3199
3200                 fw.sbss_addr = bce_COM_b09FwSbssAddr;
3201                 fw.sbss_len = bce_COM_b09FwSbssLen;
3202                 fw.sbss_index = 0;
3203                 fw.sbss = bce_COM_b09FwSbss;
3204
3205                 fw.bss_addr = bce_COM_b09FwBssAddr;
3206                 fw.bss_len = bce_COM_b09FwBssLen;
3207                 fw.bss_index = 0;
3208                 fw.bss = bce_COM_b09FwBss;
3209
3210                 fw.rodata_addr = bce_COM_b09FwRodataAddr;
3211                 fw.rodata_len = bce_COM_b09FwRodataLen;
3212                 fw.rodata_index = 0;
3213                 fw.rodata = bce_COM_b09FwRodata;
3214         } else {
3215                 fw.ver_major = bce_COM_b06FwReleaseMajor;
3216                 fw.ver_minor = bce_COM_b06FwReleaseMinor;
3217                 fw.ver_fix = bce_COM_b06FwReleaseFix;
3218                 fw.start_addr = bce_COM_b06FwStartAddr;
3219
3220                 fw.text_addr = bce_COM_b06FwTextAddr;
3221                 fw.text_len = bce_COM_b06FwTextLen;
3222                 fw.text_index = 0;
3223                 fw.text = bce_COM_b06FwText;
3224
3225                 fw.data_addr = bce_COM_b06FwDataAddr;
3226                 fw.data_len = bce_COM_b06FwDataLen;
3227                 fw.data_index = 0;
3228                 fw.data = bce_COM_b06FwData;
3229
3230                 fw.sbss_addr = bce_COM_b06FwSbssAddr;
3231                 fw.sbss_len = bce_COM_b06FwSbssLen;
3232                 fw.sbss_index = 0;
3233                 fw.sbss = bce_COM_b06FwSbss;
3234
3235                 fw.bss_addr = bce_COM_b06FwBssAddr;
3236                 fw.bss_len = bce_COM_b06FwBssLen;
3237                 fw.bss_index = 0;
3238                 fw.bss = bce_COM_b06FwBss;
3239
3240                 fw.rodata_addr = bce_COM_b06FwRodataAddr;
3241                 fw.rodata_len = bce_COM_b06FwRodataLen;
3242                 fw.rodata_index = 0;
3243                 fw.rodata = bce_COM_b06FwRodata;
3244         }
3245
3246         DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n");
3247         bce_load_cpu_fw(sc, &cpu_reg, &fw);
3248         bce_start_cpu(sc, &cpu_reg);
3249 }
3250
3251
3252 /****************************************************************************/
3253 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs.                     */
3254 /*                                                                          */
3255 /* Loads the firmware for each CPU and starts the CPU.                      */
3256 /*                                                                          */
3257 /* Returns:                                                                 */
3258 /*   Nothing.                                                               */
3259 /****************************************************************************/
3260 static void
3261 bce_init_cpus(struct bce_softc *sc)
3262 {
3263         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3264             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3265                 if (BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax) {
3266                         bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1,
3267                             sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1);
3268                         bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2,
3269                             sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2);
3270                 } else {
3271                         bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1,
3272                             sizeof(bce_xi_rv2p_proc1), RV2P_PROC1);
3273                         bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2,
3274                             sizeof(bce_xi_rv2p_proc2), RV2P_PROC2);
3275                 }
3276         } else {
3277                 bce_load_rv2p_fw(sc, bce_rv2p_proc1,
3278                     sizeof(bce_rv2p_proc1), RV2P_PROC1);
3279                 bce_load_rv2p_fw(sc, bce_rv2p_proc2,
3280                     sizeof(bce_rv2p_proc2), RV2P_PROC2);
3281         }
3282
3283         bce_init_rxp_cpu(sc);
3284         bce_init_txp_cpu(sc);
3285         bce_init_tpat_cpu(sc);
3286         bce_init_com_cpu(sc);
3287         bce_init_cp_cpu(sc);
3288 }
3289
3290
3291 /****************************************************************************/
3292 /* Initialize context memory.                                               */
3293 /*                                                                          */
3294 /* Clears the memory associated with each Context ID (CID).                 */
3295 /*                                                                          */
3296 /* Returns:                                                                 */
3297 /*   Nothing.                                                               */
3298 /****************************************************************************/
3299 static int
3300 bce_init_ctx(struct bce_softc *sc)
3301 {
3302         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3303             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3304                 /* DRC: Replace this constant value with a #define. */
3305                 int i, retry_cnt = 10;
3306                 uint32_t val;
3307
3308                 /*
3309                  * BCM5709 context memory may be cached
3310                  * in host memory so prepare the host memory
3311                  * for access.
3312                  */
3313                 val = BCE_CTX_COMMAND_ENABLED | BCE_CTX_COMMAND_MEM_INIT |
3314                     (1 << 12);
3315                 val |= (BCM_PAGE_BITS - 8) << 16;
3316                 REG_WR(sc, BCE_CTX_COMMAND, val);
3317
3318                 /* Wait for mem init command to complete. */
3319                 for (i = 0; i < retry_cnt; i++) {
3320                         val = REG_RD(sc, BCE_CTX_COMMAND);
3321                         if (!(val & BCE_CTX_COMMAND_MEM_INIT))
3322                                 break;
3323                         DELAY(2);
3324                 }
3325                 if (i == retry_cnt) {
3326                         device_printf(sc->bce_dev,
3327                             "Context memory initialization failed!\n");
3328                         return ETIMEDOUT;
3329                 }
3330
3331                 for (i = 0; i < sc->ctx_pages; i++) {
3332                         int j;
3333
3334                         /*
3335                          * Set the physical address of the context
3336                          * memory cache.
3337                          */
3338                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0,
3339                             BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) |
3340                             BCE_CTX_HOST_PAGE_TBL_DATA0_VALID);
3341                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1,
3342                             BCE_ADDR_HI(sc->ctx_paddr[i]));
3343                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL,
3344                             i | BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
3345
3346                         /*
3347                          * Verify that the context memory write was successful.
3348                          */
3349                         for (j = 0; j < retry_cnt; j++) {
3350                                 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL);
3351                                 if ((val &
3352                                     BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0)
3353                                         break;
3354                                 DELAY(5);
3355                         }
3356                         if (j == retry_cnt) {
3357                                 device_printf(sc->bce_dev,
3358                                     "Failed to initialize context page!\n");
3359                                 return ETIMEDOUT;
3360                         }
3361                 }
3362         } else {
3363                 uint32_t vcid_addr, offset;
3364
3365                 /*
3366                  * For the 5706/5708, context memory is local to
3367                  * the controller, so initialize the controller
3368                  * context memory.
3369                  */
3370
3371                 vcid_addr = GET_CID_ADDR(96);
3372                 while (vcid_addr) {
3373                         vcid_addr -= PHY_CTX_SIZE;
3374
3375                         REG_WR(sc, BCE_CTX_VIRT_ADDR, 0);
3376                         REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
3377
3378                         for (offset = 0; offset < PHY_CTX_SIZE; offset += 4)
3379                                 CTX_WR(sc, 0x00, offset, 0);
3380
3381                         REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr);
3382                         REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
3383                 }
3384         }
3385         return 0;
3386 }
3387
3388
3389 /****************************************************************************/
3390 /* Fetch the permanent MAC address of the controller.                       */
3391 /*                                                                          */
3392 /* Returns:                                                                 */
3393 /*   Nothing.                                                               */
3394 /****************************************************************************/
3395 static void
3396 bce_get_mac_addr(struct bce_softc *sc)
3397 {
3398         uint32_t mac_lo = 0, mac_hi = 0;
3399
3400         /*
3401          * The NetXtreme II bootcode populates various NIC
3402          * power-on and runtime configuration items in a
3403          * shared memory area.  The factory configured MAC
3404          * address is available from both NVRAM and the
3405          * shared memory area so we'll read the value from
3406          * shared memory for speed.
3407          */
3408
3409         mac_hi = bce_shmem_rd(sc,  BCE_PORT_HW_CFG_MAC_UPPER);
3410         mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER);
3411
3412         if (mac_lo == 0 && mac_hi == 0) {
3413                 if_printf(&sc->arpcom.ac_if, "Invalid Ethernet address!\n");
3414         } else {
3415                 sc->eaddr[0] = (u_char)(mac_hi >> 8);
3416                 sc->eaddr[1] = (u_char)(mac_hi >> 0);
3417                 sc->eaddr[2] = (u_char)(mac_lo >> 24);
3418                 sc->eaddr[3] = (u_char)(mac_lo >> 16);
3419                 sc->eaddr[4] = (u_char)(mac_lo >> 8);
3420                 sc->eaddr[5] = (u_char)(mac_lo >> 0);
3421         }
3422
3423         DBPRINT(sc, BCE_INFO, "Permanent Ethernet address = %6D\n", sc->eaddr, ":");
3424 }
3425
3426
3427 /****************************************************************************/
3428 /* Program the MAC address.                                                 */
3429 /*                                                                          */
3430 /* Returns:                                                                 */
3431 /*   Nothing.                                                               */
3432 /****************************************************************************/
3433 static void
3434 bce_set_mac_addr(struct bce_softc *sc)
3435 {
3436         const uint8_t *mac_addr = sc->eaddr;
3437         uint32_t val;
3438
3439         DBPRINT(sc, BCE_INFO, "Setting Ethernet address = %6D\n",
3440                 sc->eaddr, ":");
3441
3442         val = (mac_addr[0] << 8) | mac_addr[1];
3443         REG_WR(sc, BCE_EMAC_MAC_MATCH0, val);
3444
3445         val = (mac_addr[2] << 24) |
3446               (mac_addr[3] << 16) |
3447               (mac_addr[4] << 8) |
3448               mac_addr[5];
3449         REG_WR(sc, BCE_EMAC_MAC_MATCH1, val);
3450 }
3451
3452
3453 /****************************************************************************/
3454 /* Stop the controller.                                                     */
3455 /*                                                                          */
3456 /* Returns:                                                                 */
3457 /*   Nothing.                                                               */
3458 /****************************************************************************/
3459 static void
3460 bce_stop(struct bce_softc *sc)
3461 {
3462         struct ifnet *ifp = &sc->arpcom.ac_if;
3463
3464         ASSERT_SERIALIZED(ifp->if_serializer);
3465
3466         callout_stop(&sc->bce_tick_callout);
3467
3468         /* Disable the transmit/receive blocks. */
3469         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT);
3470         REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3471         DELAY(20);
3472
3473         bce_disable_intr(sc);
3474
3475         /* Free the RX lists. */
3476         bce_free_rx_chain(sc);
3477
3478         /* Free TX buffers. */
3479         bce_free_tx_chain(sc);
3480
3481         sc->bce_link = 0;
3482         sc->bce_coalchg_mask = 0;
3483
3484         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
3485         ifp->if_timer = 0;
3486 }
3487
3488
3489 static int
3490 bce_reset(struct bce_softc *sc, uint32_t reset_code)
3491 {
3492         uint32_t val;
3493         int i, rc = 0;
3494
3495         /* Wait for pending PCI transactions to complete. */
3496         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS,
3497                BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
3498                BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
3499                BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
3500                BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
3501         val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
3502         DELAY(5);
3503
3504         /* Disable DMA */
3505         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3506             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3507                 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
3508                 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
3509                 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
3510         }
3511
3512         /* Assume bootcode is running. */
3513         sc->bce_fw_timed_out = 0;
3514         sc->bce_drv_cardiac_arrest = 0;
3515
3516         /* Give the firmware a chance to prepare for the reset. */
3517         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code);
3518         if (rc) {
3519                 if_printf(&sc->arpcom.ac_if,
3520                           "Firmware is not ready for reset\n");
3521                 return rc;
3522         }
3523
3524         /* Set a firmware reminder that this is a soft reset. */
3525         bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE,
3526             BCE_DRV_RESET_SIGNATURE_MAGIC);
3527
3528         /* Dummy read to force the chip to complete all current transactions. */
3529         val = REG_RD(sc, BCE_MISC_ID);
3530
3531         /* Chip reset. */
3532         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3533             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3534                 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET);
3535                 REG_RD(sc, BCE_MISC_COMMAND);
3536                 DELAY(5);
3537
3538                 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3539                     BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3540
3541                 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4);
3542         } else {
3543                 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3544                     BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
3545                     BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
3546                 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val);
3547
3548                 /* Allow up to 30us for reset to complete. */
3549                 for (i = 0; i < 10; i++) {
3550                         val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG);
3551                         if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3552                             BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0)
3553                                 break;
3554                         DELAY(10);
3555                 }
3556
3557                 /* Check that reset completed successfully. */
3558                 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
3559                     BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
3560                         if_printf(&sc->arpcom.ac_if, "Reset failed!\n");
3561                         return EBUSY;
3562                 }
3563         }
3564
3565         /* Make sure byte swapping is properly configured. */
3566         val = REG_RD(sc, BCE_PCI_SWAP_DIAG0);
3567         if (val != 0x01020304) {
3568                 if_printf(&sc->arpcom.ac_if, "Byte swap is incorrect!\n");
3569                 return ENODEV;
3570         }
3571
3572         /* Just completed a reset, assume that firmware is running again. */
3573         sc->bce_fw_timed_out = 0;
3574         sc->bce_drv_cardiac_arrest = 0;
3575
3576         /* Wait for the firmware to finish its initialization. */
3577         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code);
3578         if (rc) {
3579                 if_printf(&sc->arpcom.ac_if,
3580                           "Firmware did not complete initialization!\n");
3581         }
3582         return rc;
3583 }
3584
3585
3586 static int
3587 bce_chipinit(struct bce_softc *sc)
3588 {
3589         uint32_t val;
3590         int rc = 0;
3591
3592         /* Make sure the interrupt is not active. */
3593         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
3594         REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
3595
3596         /*
3597          * Initialize DMA byte/word swapping, configure the number of DMA
3598          * channels and PCI clock compensation delay.
3599          */
3600         val = BCE_DMA_CONFIG_DATA_BYTE_SWAP |
3601               BCE_DMA_CONFIG_DATA_WORD_SWAP |
3602 #if BYTE_ORDER == BIG_ENDIAN
3603               BCE_DMA_CONFIG_CNTL_BYTE_SWAP |
3604 #endif
3605               BCE_DMA_CONFIG_CNTL_WORD_SWAP |
3606               DMA_READ_CHANS << 12 |
3607               DMA_WRITE_CHANS << 16;
3608
3609         val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY;
3610
3611         if ((sc->bce_flags & BCE_PCIX_FLAG) && sc->bus_speed_mhz == 133)
3612                 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP;
3613
3614         /*
3615          * This setting resolves a problem observed on certain Intel PCI
3616          * chipsets that cannot handle multiple outstanding DMA operations.
3617          * See errata E9_5706A1_65.
3618          */
3619         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706 &&
3620             BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0 &&
3621             !(sc->bce_flags & BCE_PCIX_FLAG))
3622                 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA;
3623
3624         REG_WR(sc, BCE_DMA_CONFIG, val);
3625
3626         /* Enable the RX_V2P and Context state machines before access. */
3627         REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
3628                BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
3629                BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
3630                BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
3631
3632         /* Initialize context mapping and zero out the quick contexts. */
3633         rc = bce_init_ctx(sc);
3634         if (rc != 0)
3635                 return rc;
3636
3637         /* Initialize the on-boards CPUs */
3638         bce_init_cpus(sc);
3639
3640         /* Enable management frames (NC-SI) to flow to the MCP. */
3641         if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
3642                 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) |
3643                     BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
3644                 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
3645         }
3646
3647         /* Prepare NVRAM for access. */
3648         rc = bce_init_nvram(sc);
3649         if (rc != 0)
3650                 return rc;
3651
3652         /* Set the kernel bypass block size */
3653         val = REG_RD(sc, BCE_MQ_CONFIG);
3654         val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE;
3655         val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
3656
3657         /* Enable bins used on the 5709/5716. */
3658         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709 ||
3659             BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716) {
3660                 val |= BCE_MQ_CONFIG_BIN_MQ_MODE;
3661                 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1)
3662                         val |= BCE_MQ_CONFIG_HALT_DIS;
3663         }
3664
3665         REG_WR(sc, BCE_MQ_CONFIG, val);
3666
3667         val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
3668         REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val);
3669         REG_WR(sc, BCE_MQ_KNL_WIND_END, val);
3670
3671         /* Set the page size and clear the RV2P processor stall bits. */
3672         val = (BCM_PAGE_BITS - 8) << 24;
3673         REG_WR(sc, BCE_RV2P_CONFIG, val);
3674 <