2 * Copyright (c) 1991 The Regents of the University of California.
3 * Copyright (c) 2008 The DragonFly Project.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 4. Neither the name of the University nor the names of its contributors
15 * may be used to endorse or promote products derived from this software
16 * without specific prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * from: @(#)specialreg.h 7.1 (Berkeley) 5/9/91
31 * $FreeBSD: src/sys/amd64/include/specialreg.h,v 1.39 2007/05/31 11:26:44 des Exp $
34 #ifndef _CPU_SPECIALREG_H_
35 #define _CPU_SPECIALREG_H_
38 * Bits in 386 special registers:
40 #define CR0_PE 0x00000001 /* Protected mode Enable */
41 #define CR0_MP 0x00000002 /* "Math" (fpu) Present */
42 #define CR0_EM 0x00000004 /* EMulate FPU instructions. (trap ESC only) */
43 #define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */
44 #define CR0_PG 0x80000000 /* Paging enable */
47 * Bits in 486 special registers:
49 #define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */
50 #define CR0_WP 0x00010000 /* Write Protect (honor page protect in all modes) */
51 #define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */
52 #define CR0_NW 0x20000000 /* Not Write-through */
53 #define CR0_CD 0x40000000 /* Cache Disable */
56 * Bits in CR4 special register
58 #define CR4_VME 0x00000001 /* Virtual 8086 mode extensions */
59 #define CR4_PVI 0x00000002 /* Protected-mode virtual interrupts */
60 #define CR4_TSD 0x00000004 /* Time stamp disable */
61 #define CR4_DE 0x00000008 /* Debugging extensions */
62 #define CR4_PSE 0x00000010 /* Page size extensions */
63 #define CR4_PAE 0x00000020 /* Physical address extension */
64 #define CR4_MCE 0x00000040 /* Machine check enable */
65 #define CR4_PGE 0x00000080 /* Page global enable */
66 #define CR4_PCE 0x00000100 /* Performance monitoring counter enable */
67 #define CR4_FXSR 0x00000200 /* Fast FPU save/restore used by OS */
68 #define CR4_XMM 0x00000400 /* Enable SIMD/MMX2 to use except 16 */
69 #define CR4_VMXE 0x00002000 /* Enables VMX - Intel specific */
70 #define CR4_XSAVE 0x00040000 /* Enable XSave (for AVX Instructions)*/
73 * Bits in x86_64 special registers. EFER is 64 bits wide.
75 #define EFER_SCE 0x000000001 /* System Call Extensions (R/W) */
76 #define EFER_LME 0x000000100 /* Long mode enable (R/W) */
77 #define EFER_LMA 0x000000400 /* Long mode active (R) */
78 #define EFER_NXE 0x000000800 /* PTE No-Execute bit enable (R/W) */
79 #define EFER_SVME 0x000001000 /* SVM Enable (R/W) */
82 * CPUID instruction features register
84 #define CPUID_FPU 0x00000001
85 #define CPUID_VME 0x00000002
86 #define CPUID_DE 0x00000004
87 #define CPUID_PSE 0x00000008
88 #define CPUID_TSC 0x00000010
89 #define CPUID_MSR 0x00000020
90 #define CPUID_PAE 0x00000040
91 #define CPUID_MCE 0x00000080
92 #define CPUID_CX8 0x00000100
93 #define CPUID_APIC 0x00000200
94 #define CPUID_B10 0x00000400
95 #define CPUID_SEP 0x00000800
96 #define CPUID_MTRR 0x00001000
97 #define CPUID_PGE 0x00002000
98 #define CPUID_MCA 0x00004000
99 #define CPUID_CMOV 0x00008000
100 #define CPUID_PAT 0x00010000
101 #define CPUID_PSE36 0x00020000
102 #define CPUID_PSN 0x00040000
103 #define CPUID_CLFSH 0x00080000
104 #define CPUID_B20 0x00100000
105 #define CPUID_DS 0x00200000
106 #define CPUID_ACPI 0x00400000
107 #define CPUID_MMX 0x00800000
108 #define CPUID_FXSR 0x01000000
109 #define CPUID_SSE 0x02000000
110 #define CPUID_XMM 0x02000000
111 #define CPUID_SSE2 0x04000000
112 #define CPUID_SS 0x08000000
113 #define CPUID_HTT 0x10000000
114 #define CPUID_TM 0x20000000
115 #define CPUID_IA64 0x40000000
116 #define CPUID_PBE 0x80000000
118 #define CPUID2_SSE3 0x00000001
119 #define CPUID2_PCLMULQDQ 0x00000002
120 #define CPUID2_DTES64 0x00000004
121 #define CPUID2_MON 0x00000008
122 #define CPUID2_DS_CPL 0x00000010
123 #define CPUID2_VMX 0x00000020
124 #define CPUID2_SMX 0x00000040
125 #define CPUID2_EST 0x00000080
126 #define CPUID2_TM2 0x00000100
127 #define CPUID2_SSSE3 0x00000200
128 #define CPUID2_CNXTID 0x00000400
129 #define CPUID2_CX16 0x00002000
130 #define CPUID2_XTPR 0x00004000
131 #define CPUID2_PDCM 0x00008000
132 #define CPUID2_DCA 0x00040000
133 #define CPUID2_SSE41 0x00080000
134 #define CPUID2_SSE42 0x00100000
135 #define CPUID2_X2APIC 0x00200000
136 #define CPUID2_POPCNT 0x00800000
137 #define CPUID2_AESNI 0x02000000 /* AES Instruction Set */
138 #define CPUID2_XSAVE 0x04000000 /* XSave supported by CPU */
139 #define CPUID2_OSXSAVE 0x08000000 /* XSave and AVX supported by OS */
140 #define CPUID2_AVX 0x10000000 /* AVX instruction set support */
141 #define CPUID2_F16C 0x20000000 /* CVT16 instruction set support */
142 #define CPUID2_RDRAND 0x40000000 /* RdRand. On chip random numbers */
143 #define CPUID2_VMM 0x80000000 /* AMD 25481 2.34 page 11 */
145 /*Bits related to the XFEATURE_ENABLED_MASK control register*/
146 #define CPU_XFEATURE_X87 0x00000001
147 #define CPU_XFEATURE_SSE 0x00000002
148 #define CPU_XFEATURE_YMM 0x00000004
151 * Important bits in the AMD extended cpuid flags
153 #define AMDID_SYSCALL 0x00000800
154 #define AMDID_MP 0x00080000
155 #define AMDID_NX 0x00100000
156 #define AMDID_EXT_MMX 0x00400000
157 #define AMDID_FFXSR 0x01000000
158 #define AMDID_PAGE1GB 0x04000000
159 #define AMDID_RDTSCP 0x08000000
160 #define AMDID_LM 0x20000000
161 #define AMDID_EXT_3DNOW 0x40000000
162 #define AMDID_3DNOW 0x80000000
164 #define AMDID2_LAHF 0x00000001
165 #define AMDID2_CMP 0x00000002
166 #define AMDID2_SVM 0x00000004
167 #define AMDID2_EXT_APIC 0x00000008
168 #define AMDID2_CR8 0x00000010
169 #define AMDID2_ABM 0x00000020
170 #define AMDID2_SSE4A 0x00000040
171 #define AMDID2_MAS 0x00000080
172 #define AMDID2_PREFETCH 0x00000100
173 #define AMDID2_OSVW 0x00000200
174 #define AMDID2_IBS 0x00000400
175 #define AMDID2_SSE5 0x00000800
176 #define AMDID2_SKINIT 0x00001000
177 #define AMDID2_WDT 0x00002000
180 * CPUID instruction 1 eax info
182 #define CPUID_STEPPING 0x0000000f
183 #define CPUID_MODEL 0x000000f0
184 #define CPUID_FAMILY 0x00000f00
185 #define CPUID_EXT_MODEL 0x000f0000
186 #define CPUID_EXT_FAMILY 0x0ff00000
187 #define CPUID_TO_MODEL(id) \
188 ((((id) & CPUID_MODEL) >> 4) | \
189 (((id) & CPUID_EXT_MODEL) >> 12))
190 #define CPUID_TO_FAMILY(id) \
191 ((((id) & CPUID_FAMILY) >> 8) + \
192 (((id) & CPUID_EXT_FAMILY) >> 20))
195 * CPUID instruction 1 ebx info
197 #define CPUID_BRAND_INDEX 0x000000ff
198 #define CPUID_CLFUSH_SIZE 0x0000ff00
199 #define CPUID_HTT_CORES 0x00ff0000
200 #define CPUID_HTT_CORE_SHIFT 16
201 #define CPUID_LOCAL_APIC_ID 0xff000000
204 * AMD extended function 8000_0008h ecx info
206 #define AMDID_CMP_CORES 0x000000ff
207 #define AMDID_COREID_SIZE 0x0000f000
208 #define AMDID_COREID_SIZE_SHIFT 12
211 * INTEL Deterministic Cache Parameters
214 #define FUNC_4_MAX_CORE_NO(eax) ((((eax) >> 26) & 0x3f))
217 * INTEL x2APIC Features / Processor topology
220 #define FUNC_B_THREAD_LEVEL 0
222 #define FUNC_B_INVALID_TYPE 0
223 #define FUNC_B_THREAD_TYPE 1
224 #define FUNC_B_CORE_TYPE 2
226 #define FUNC_B_TYPE(ecx) (((ecx) >> 8) & 0xff)
227 #define FUNC_B_BITS_SHIFT_NEXT_LEVEL(eax) ((eax) & 0x1f)
228 #define FUNC_B_LEVEL_MAX_SIBLINGS(ebx) ((ebx) & 0xffff)
231 * Structured Extended Features
233 #define CPUID_STDEXT_FSGSBASE 0x00000001
234 #define CPUID_STDEXT_TSC_ADJUST 0x00000002
235 #define CPUID_STDEXT_BMI1 0x00000008
236 #define CPUID_STDEXT_HLE 0x00000010
237 #define CPUID_STDEXT_AVX2 0x00000020
238 #define CPUID_STDEXT_SMEP 0x00000080
239 #define CPUID_STDEXT_BMI2 0x00000100
240 #define CPUID_STDEXT_ENH_MOVSB 0x00000200
241 #define CPUID_STDEXT_RTM 0x00000800
242 #define CPUID_STDEXT_INVPCID 0x00000400
243 #define CPUID_STDEXT_RDSEED 0x00040000
244 #define CPUID_STDEXT_ADX 0x00080000
245 #define CPUID_STDEXT_SMAP 0x00100000
248 * Thermal and PM Features
250 #define CPUID_THERMAL_SENSOR 0x00000001
251 #define CPUID_THERMAL_TURBO 0x00000002
252 #define CPUID_THERMAL_ARAT 0x00000004
253 #define CPUID_THERMAL_PLN 0x00000010
254 #define CPUID_THERMAL_ECMD 0x00000020
255 #define CPUID_THERMAL_PTM 0x00000040
257 #define CPUID_THERMAL2_SETBH 0x00000008
262 #define CPUID_MWAIT_EXT 0x00000001
263 #define CPUID_MWAIT_INTBRK 0x00000002
264 #define CPUID_MWAIT_CX_SUBCNT(emu, i) (((emu) >> ((i) * 4)) & 0xf)
266 /* MWAIT EAX to Cx and its sub state */
267 #define MWAIT_EAX_TO_CX(x) ((((x) >> 4) + 1) & 0xf)
268 #define MWAIT_EAX_TO_CX_SUB(x) ((x) & 0xf)
270 /* MWAIT EAX hint and ECX extension */
271 #define MWAIT_EAX_HINT(cx, sub) \
272 (((((uint32_t)(cx) - 1) & 0xf) << 4) | ((sub) & 0xf))
273 #define MWAIT_ECX_INTBRK 0x1
276 * CPUID manufacturers identifiers
278 #define AMD_VENDOR_ID "AuthenticAMD"
279 #define CENTAUR_VENDOR_ID "CentaurHauls"
280 #define INTEL_VENDOR_ID "GenuineIntel"
283 * Model-specific registers for the i386 family
285 #define MSR_P5_MC_ADDR 0x000
286 #define MSR_P5_MC_TYPE 0x001
287 #define MSR_TSC 0x010
288 #define MSR_P5_CESR 0x011
289 #define MSR_P5_CTR0 0x012
290 #define MSR_P5_CTR1 0x013
291 #define MSR_IA32_PLATFORM_ID 0x017
292 #define MSR_APICBASE 0x01b
293 #define MSR_EBL_CR_POWERON 0x02a
294 #define MSR_TEST_CTL 0x033
295 #define MSR_BIOS_UPDT_TRIG 0x079
296 #define MSR_BBL_CR_D0 0x088
297 #define MSR_BBL_CR_D1 0x089
298 #define MSR_BBL_CR_D2 0x08a
299 #define MSR_BIOS_SIGN 0x08b
300 #define MSR_PERFCTR0 0x0c1
301 #define MSR_PERFCTR1 0x0c2
302 #define MSR_IA32_EXT_CONFIG 0x0ee /* Undocumented. Core Solo/Duo only */
303 #define MSR_MTRRcap 0x0fe
304 #define MSR_BBL_CR_ADDR 0x116
305 #define MSR_BBL_CR_DECC 0x118
306 #define MSR_BBL_CR_CTL 0x119
307 #define MSR_BBL_CR_TRIG 0x11a
308 #define MSR_BBL_CR_BUSY 0x11b
309 #define MSR_BBL_CR_CTL3 0x11e
310 #define MSR_SYSENTER_CS_MSR 0x174
311 #define MSR_SYSENTER_ESP_MSR 0x175
312 #define MSR_SYSENTER_EIP_MSR 0x176
313 #define MSR_MCG_CAP 0x179
314 #define MSR_MCG_STATUS 0x17a
315 #define MSR_MCG_CTL 0x17b
316 #define MSR_EVNTSEL0 0x186
317 #define MSR_EVNTSEL1 0x187
318 #define MSR_THERM_CONTROL 0x19a
319 #define MSR_THERM_INTERRUPT 0x19b
320 #define MSR_THERM_STATUS 0x19c
321 #define MSR_IA32_MISC_ENABLE 0x1a0
322 #define MSR_IA32_TEMPERATURE_TARGET 0x1a2
323 #define MSR_DEBUGCTLMSR 0x1d9
324 #define MSR_LASTBRANCHFROMIP 0x1db
325 #define MSR_LASTBRANCHTOIP 0x1dc
326 #define MSR_LASTINTFROMIP 0x1dd
327 #define MSR_LASTINTTOIP 0x1de
328 #define MSR_ROB_CR_BKUPTMPDR6 0x1e0
329 #define MSR_MTRRVarBase 0x200
330 #define MSR_MTRR64kBase 0x250
331 #define MSR_MTRR16kBase 0x258
332 #define MSR_MTRR4kBase 0x268
333 #define MSR_PAT 0x277
334 #define MSR_MTRRdefType 0x2ff
335 #define MSR_MC0_CTL 0x400
336 #define MSR_MC0_STATUS 0x401
337 #define MSR_MC0_ADDR 0x402
338 #define MSR_MC0_MISC 0x403
339 #define MSR_MC1_CTL 0x404
340 #define MSR_MC1_STATUS 0x405
341 #define MSR_MC1_ADDR 0x406
342 #define MSR_MC1_MISC 0x407
343 #define MSR_MC2_CTL 0x408
344 #define MSR_MC2_STATUS 0x409
345 #define MSR_MC2_ADDR 0x40a
346 #define MSR_MC2_MISC 0x40b
347 #define MSR_MC3_CTL 0x40c
348 #define MSR_MC3_STATUS 0x40d
349 #define MSR_MC3_ADDR 0x40e
350 #define MSR_MC3_MISC 0x40f
351 #define MSR_MC4_CTL 0x410
352 #define MSR_MC4_STATUS 0x411
353 #define MSR_MC4_ADDR 0x412
354 #define MSR_MC4_MISC 0x413
357 * Constants related to MSR's.
359 #define APICBASE_RESERVED 0x000006ff
360 #define APICBASE_BSP 0x00000100
361 #define APICBASE_ENABLED 0x00000800
362 #define APICBASE_ADDRESS 0xfffff000
367 #define PAT_UNCACHEABLE 0x00
368 #define PAT_WRITE_COMBINING 0x01
369 #define PAT_WRITE_THROUGH 0x04
370 #define PAT_WRITE_PROTECTED 0x05
371 #define PAT_WRITE_BACK 0x06
372 #define PAT_UNCACHED 0x07
373 #define PAT_VALUE(i, m) ((long)(m) << (8 * (i)))
374 #define PAT_MASK(i) PAT_VALUE(i, 0xff)
377 * Constants related to MTRRs
379 #define MTRR_UNCACHEABLE 0x00
380 #define MTRR_WRITE_COMBINING 0x01
381 #define MTRR_WRITE_THROUGH 0x04
382 #define MTRR_WRITE_PROTECTED 0x05
383 #define MTRR_WRITE_BACK 0x06
384 #define MTRR_N64K 8 /* numbers of fixed-size entries */
387 #define MTRR_CAP_WC 0x0000000000000400UL
388 #define MTRR_CAP_FIXED 0x0000000000000100UL
389 #define MTRR_CAP_VCNT 0x00000000000000ffUL
390 #define MTRR_DEF_ENABLE 0x0000000000000800UL
391 #define MTRR_DEF_FIXED_ENABLE 0x0000000000000400UL
392 #define MTRR_DEF_TYPE 0x00000000000000ffUL
393 #define MTRR_PHYSBASE_PHYSBASE 0x000ffffffffff000UL
394 #define MTRR_PHYSBASE_TYPE 0x00000000000000ffUL
395 #define MTRR_PHYSMASK_PHYSMASK 0x000ffffffffff000UL
396 #define MTRR_PHYSMASK_VALID 0x0000000000000800UL
398 /* Performance Control Register (5x86 only). */
400 #define PCR0_RSTK 0x01 /* Enables return stack */
401 #define PCR0_BTB 0x02 /* Enables branch target buffer */
402 #define PCR0_LOOP 0x04 /* Enables loop */
403 #define PCR0_AIS 0x08 /* Enables all instrcutions stalled to
405 #define PCR0_MLR 0x10 /* Enables reordering of misaligned loads */
406 #define PCR0_BTBRT 0x40 /* Enables BTB test register. */
407 #define PCR0_LSSER 0x80 /* Disable reorder */
409 /* Device Identification Registers */
414 * Machine Check register constants.
416 #define MCG_CAP_COUNT 0x000000ff
417 #define MCG_CAP_CTL_P 0x00000100
418 #define MCG_CAP_EXT_P 0x00000200
419 #define MCG_CAP_TES_P 0x00000800
420 #define MCG_CAP_EXT_CNT 0x00ff0000
421 #define MCG_STATUS_RIPV 0x00000001
422 #define MCG_STATUS_EIPV 0x00000002
423 #define MCG_STATUS_MCIP 0x00000004
424 #define MCG_CTL_ENABLE 0xffffffffffffffffUL
425 #define MCG_CTL_DISABLE 0x0000000000000000UL
426 #define MSR_MC_CTL(x) (MSR_MC0_CTL + (x) * 4)
427 #define MSR_MC_STATUS(x) (MSR_MC0_STATUS + (x) * 4)
428 #define MSR_MC_ADDR(x) (MSR_MC0_ADDR + (x) * 4)
429 #define MSR_MC_MISC(x) (MSR_MC0_MISC + (x) * 4)
430 #define MC_STATUS_MCA_ERROR 0x000000000000ffffUL
431 #define MC_STATUS_MODEL_ERROR 0x00000000ffff0000UL
432 #define MC_STATUS_OTHER_INFO 0x01ffffff00000000UL
433 #define MC_STATUS_PCC 0x0200000000000000UL
434 #define MC_STATUS_ADDRV 0x0400000000000000UL
435 #define MC_STATUS_MISCV 0x0800000000000000UL
436 #define MC_STATUS_EN 0x1000000000000000UL
437 #define MC_STATUS_UC 0x2000000000000000UL
438 #define MC_STATUS_OVER 0x4000000000000000UL
439 #define MC_STATUS_VAL 0x8000000000000000UL
442 * The following four 3-byte registers control the non-cacheable regions.
443 * These registers must be written as three separate bytes.
445 * NCRx+0: A31-A24 of starting address
446 * NCRx+1: A23-A16 of starting address
447 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
449 * The non-cacheable region's starting address must be aligned to the
450 * size indicated by the NCR_SIZE_xx field.
457 #define NCR_SIZE_0K 0
458 #define NCR_SIZE_4K 1
459 #define NCR_SIZE_8K 2
460 #define NCR_SIZE_16K 3
461 #define NCR_SIZE_32K 4
462 #define NCR_SIZE_64K 5
463 #define NCR_SIZE_128K 6
464 #define NCR_SIZE_256K 7
465 #define NCR_SIZE_512K 8
466 #define NCR_SIZE_1M 9
467 #define NCR_SIZE_2M 10
468 #define NCR_SIZE_4M 11
469 #define NCR_SIZE_8M 12
470 #define NCR_SIZE_16M 13
471 #define NCR_SIZE_32M 14
472 #define NCR_SIZE_4G 15
475 * The address region registers are used to specify the location and
476 * size for the eight address regions.
478 * ARRx + 0: A31-A24 of start address
479 * ARRx + 1: A23-A16 of start address
480 * ARRx + 2: A15-A12 of start address | ARR_SIZE_xx
491 #define ARR_SIZE_0K 0
492 #define ARR_SIZE_4K 1
493 #define ARR_SIZE_8K 2
494 #define ARR_SIZE_16K 3
495 #define ARR_SIZE_32K 4
496 #define ARR_SIZE_64K 5
497 #define ARR_SIZE_128K 6
498 #define ARR_SIZE_256K 7
499 #define ARR_SIZE_512K 8
500 #define ARR_SIZE_1M 9
501 #define ARR_SIZE_2M 10
502 #define ARR_SIZE_4M 11
503 #define ARR_SIZE_8M 12
504 #define ARR_SIZE_16M 13
505 #define ARR_SIZE_32M 14
506 #define ARR_SIZE_4G 15
509 * The region control registers specify the attributes associated with
510 * the ARRx addres regions.
521 #define RCR_RCD 0x01 /* Disables caching for ARRx (x = 0-6). */
522 #define RCR_RCE 0x01 /* Enables caching for ARR7. */
523 #define RCR_WWO 0x02 /* Weak write ordering. */
524 #define RCR_WL 0x04 /* Weak locking. */
525 #define RCR_WG 0x08 /* Write gathering. */
526 #define RCR_WT 0x10 /* Write-through. */
527 #define RCR_NLB 0x20 /* LBA# pin is not asserted. */
529 /* AMD Write Allocate Top-Of-Memory and Control Register */
530 #define AMD_WT_ALLOC_TME 0x40000 /* top-of-memory enable */
531 #define AMD_WT_ALLOC_PRE 0x20000 /* programmable range enable */
532 #define AMD_WT_ALLOC_FRE 0x10000 /* fixed (A0000-FFFFF) range enable */
535 #define MSR_EFER 0xc0000080 /* extended features */
536 #define MSR_STAR 0xc0000081 /* legacy mode SYSCALL target/cs/ss */
537 #define MSR_LSTAR 0xc0000082 /* long mode SYSCALL target rip */
538 #define MSR_CSTAR 0xc0000083 /* compat mode SYSCALL target rip */
539 #define MSR_SF_MASK 0xc0000084 /* syscall flags mask */
540 #define MSR_FSBASE 0xc0000100 /* base address of the %fs "segment" */
541 #define MSR_GSBASE 0xc0000101 /* base address of the %gs "segment" */
542 #define MSR_KGSBASE 0xc0000102 /* base address of the kernel %gs */
543 #define MSR_PERFEVSEL0 0xc0010000
544 #define MSR_PERFEVSEL1 0xc0010001
545 #define MSR_PERFEVSEL2 0xc0010002
546 #define MSR_PERFEVSEL3 0xc0010003
549 #define MSR_PERFCTR0 0xc0010004
550 #define MSR_PERFCTR1 0xc0010005
551 #define MSR_PERFCTR2 0xc0010006
552 #define MSR_PERFCTR3 0xc0010007
553 #define MSR_SYSCFG 0xc0010010
554 #define MSR_IORRBASE0 0xc0010016
555 #define MSR_IORRMASK0 0xc0010017
556 #define MSR_IORRBASE1 0xc0010018
557 #define MSR_IORRMASK1 0xc0010019
558 #define MSR_TOP_MEM 0xc001001a /* boundary for ram below 4G */
559 #define MSR_TOP_MEM2 0xc001001d /* boundary for ram above 4G */
560 #define MSR_K8_UCODE_UPDATE 0xc0010020 /* update microcode */
563 #define MSR_AMD_DE_CFG 0xc0011029
566 #define MSR_AMD_VM_CR 0xc0010114
567 #define MSR_AMD_VM_HSAVE_PA 0xc0010117
569 /* AMD MSR_AMD_VM_CR fields */
570 #define MSR_AMD_VM_CR_SVMDIS 0x00000010 /* SVM Disabled */
572 /* VIA ACE crypto featureset: for via_feature_rng */
573 #define VIA_HAS_RNG 1 /* cpu has RNG */
575 /* VIA ACE crypto featureset: for via_feature_xcrypt */
576 #define VIA_HAS_AES 1 /* cpu has AES */
577 #define VIA_HAS_SHA 2 /* cpu has SHA1 & SHA256 */
578 #define VIA_HAS_MM 4 /* cpu has RSA instructions */
579 #define VIA_HAS_AESCTR 8 /* cpu has AES-CTR instructions */
581 /* Centaur Extended Feature flags */
582 #define VIA_CPUID_HAS_RNG 0x000004
583 #define VIA_CPUID_DO_RNG 0x000008
584 #define VIA_CPUID_HAS_ACE 0x000040
585 #define VIA_CPUID_DO_ACE 0x000080
586 #define VIA_CPUID_HAS_ACE2 0x000100
587 #define VIA_CPUID_DO_ACE2 0x000200
588 #define VIA_CPUID_HAS_PHE 0x000400
589 #define VIA_CPUID_DO_PHE 0x000800
590 #define VIA_CPUID_HAS_PMM 0x001000
591 #define VIA_CPUID_DO_PMM 0x002000
593 #endif /* !_CPU_SPECIALREG_H_ */