2 * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
3 * VA Linux Systems Inc., Fremont, California.
4 * Copyright 2008 Red Hat Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
25 * Kevin E. Martin, Rickard E. Faith, Alan Hourihane
27 * Kernel port Author: Dave Airlie
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drm_dp_helper.h>
36 #include <drm/drm_fixed.h>
37 #include <drm/drm_crtc_helper.h>
42 #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
43 #define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
44 #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
45 #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)
47 #define RADEON_MAX_HPD_PINS 7
48 #define RADEON_MAX_CRTCS 6
49 #define RADEON_MAX_AFMT_BLOCKS 7
51 enum radeon_rmx_type {
70 enum radeon_underscan_type {
83 RADEON_HPD_NONE = 0xff,
86 #define RADEON_MAX_I2C_BUS 16
88 /* radeon gpio-based i2c
89 * 1. "mask" reg and bits
90 * grabs the gpio pins for software use
95 * 3. "en" reg and bits
96 * sets the pin direction
102 struct radeon_i2c_bus_rec {
104 /* id used by atom */
106 /* id used by atom */
107 enum radeon_hpd_id hpd;
108 /* can be used with hw i2c engine */
110 /* uses multi-media i2c engine */
113 uint32_t mask_clk_reg;
114 uint32_t mask_data_reg;
118 uint32_t en_data_reg;
121 uint32_t mask_clk_mask;
122 uint32_t mask_data_mask;
124 uint32_t a_data_mask;
125 uint32_t en_clk_mask;
126 uint32_t en_data_mask;
128 uint32_t y_data_mask;
131 struct radeon_tmds_pll {
136 #define RADEON_MAX_BIOS_CONNECTOR 16
139 #define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
140 #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
141 #define RADEON_PLL_USE_REF_DIV (1 << 2)
142 #define RADEON_PLL_LEGACY (1 << 3)
143 #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4)
144 #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5)
145 #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6)
146 #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7)
147 #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8)
148 #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
149 #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10)
150 #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
151 #define RADEON_PLL_USE_POST_DIV (1 << 12)
152 #define RADEON_PLL_IS_LCD (1 << 13)
153 #define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
156 /* reference frequency */
157 uint32_t reference_freq;
160 uint32_t reference_div;
163 /* pll in/out limits */
166 uint32_t pll_out_min;
167 uint32_t pll_out_max;
168 uint32_t lcd_pll_out_min;
169 uint32_t lcd_pll_out_max;
173 uint32_t min_ref_div;
174 uint32_t max_ref_div;
175 uint32_t min_post_div;
176 uint32_t max_post_div;
177 uint32_t min_feedback_div;
178 uint32_t max_feedback_div;
179 uint32_t min_frac_feedback_div;
180 uint32_t max_frac_feedback_div;
182 /* flags for the current clock */
189 struct radeon_i2c_chan {
192 struct drm_device *dev;
193 struct radeon_i2c_bus_rec rec;
194 struct drm_dp_aux aux;
199 /* mostly for macs, but really any system without connector tables */
200 enum radeon_connector_table {
204 CT_POWERBOOK_EXTERNAL,
205 CT_POWERBOOK_INTERNAL,
218 enum radeon_dvo_chip {
228 bool last_buffer_filled_status;
230 struct r600_audio_pin *pin;
233 struct radeon_mode_info {
234 struct atom_context *atom_context;
235 struct card_info *atom_card_info;
236 enum radeon_connector_table connector_table;
237 bool mode_config_initialized;
238 struct radeon_crtc *crtcs[RADEON_MAX_CRTCS];
239 struct radeon_afmt *afmt[RADEON_MAX_AFMT_BLOCKS];
240 /* DVI-I properties */
241 struct drm_property *coherent_mode_property;
242 /* DAC enable load detect */
243 struct drm_property *load_detect_property;
245 struct drm_property *tv_std_property;
246 /* legacy TMDS PLL detect */
247 struct drm_property *tmds_pll_property;
249 struct drm_property *underscan_property;
250 struct drm_property *underscan_hborder_property;
251 struct drm_property *underscan_vborder_property;
253 struct drm_property *audio_property;
255 struct drm_property *dither_property;
256 /* hardcoded DFP edid from BIOS */
257 struct edid *bios_hardcoded_edid;
258 int bios_hardcoded_edid_size;
260 /* pointer to fbdev info structure */
261 struct radeon_fbdev *rfbdev;
264 /* pointer to backlight encoder */
265 struct radeon_encoder *bl_encoder;
268 #define RADEON_MAX_BL_LEVEL 0xFF
270 #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
272 struct radeon_backlight_privdata {
273 struct radeon_encoder *encoder;
279 #define MAX_H_CODE_TIMING_LEN 32
280 #define MAX_V_CODE_TIMING_LEN 32
282 /* need to store these as reading
283 back code tables is excessive */
284 struct radeon_tv_regs {
286 uint32_t timing_cntl;
290 uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
291 uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
294 struct radeon_atom_ss {
296 uint16_t percentage_divider;
307 enum radeon_flip_status {
310 RADEON_FLIP_SUBMITTED
314 struct drm_crtc base;
316 u16 lut_r[256], lut_g[256], lut_b[256];
319 uint32_t crtc_offset;
320 struct drm_gem_object *cursor_bo;
321 uint64_t cursor_addr;
324 int max_cursor_width;
325 int max_cursor_height;
326 uint32_t legacy_display_base_addr;
327 uint32_t legacy_cursor_offset;
328 enum radeon_rmx_type rmx_type;
333 struct drm_display_mode native_mode;
336 struct workqueue_struct *flip_queue;
337 struct radeon_flip_work *flip_work;
338 enum radeon_flip_status flip_status;
340 struct radeon_atom_ss ss;
344 u32 pll_reference_div;
347 struct drm_encoder *encoder;
348 struct drm_connector *connector;
353 struct drm_display_mode hw_mode;
356 struct radeon_encoder_primary_dac {
357 /* legacy primary dac */
358 uint32_t ps2_pdac_adj;
361 struct radeon_encoder_lvds {
363 uint16_t panel_vcc_delay;
364 uint8_t panel_pwr_delay;
365 uint8_t panel_digon_delay;
366 uint8_t panel_blon_delay;
367 uint16_t panel_ref_divider;
368 uint8_t panel_post_divider;
369 uint16_t panel_fb_divider;
370 bool use_bios_dividers;
371 uint32_t lvds_gen_cntl;
373 struct drm_display_mode native_mode;
374 struct backlight_device *bl_dev;
376 uint8_t backlight_level;
379 struct radeon_encoder_tv_dac {
381 uint32_t ps2_tvdac_adj;
382 uint32_t ntsc_tvdac_adj;
383 uint32_t pal_tvdac_adj;
388 int supported_tv_stds;
390 enum radeon_tv_std tv_std;
391 struct radeon_tv_regs tv;
394 struct radeon_encoder_int_tmds {
395 /* legacy int tmds */
396 struct radeon_tmds_pll tmds_pll[4];
399 struct radeon_encoder_ext_tmds {
401 struct radeon_i2c_chan *i2c_bus;
403 enum radeon_dvo_chip dvo_chip;
406 /* spread spectrum */
407 struct radeon_encoder_atom_dig {
411 int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
414 uint16_t panel_pwr_delay;
417 struct drm_display_mode native_mode;
418 struct backlight_device *bl_dev;
420 uint8_t backlight_level;
422 struct radeon_afmt *afmt;
425 struct radeon_encoder_atom_dac {
426 enum radeon_tv_std tv_std;
429 struct radeon_encoder {
430 struct drm_encoder base;
431 uint32_t encoder_enum;
434 uint32_t active_device;
436 uint32_t pixel_clock;
437 enum radeon_rmx_type rmx_type;
438 enum radeon_underscan_type underscan_type;
439 uint32_t underscan_hborder;
440 uint32_t underscan_vborder;
441 struct drm_display_mode native_mode;
443 int audio_polling_active;
448 struct radeon_connector_atom_dig {
449 uint32_t igp_lane_info;
451 struct radeon_i2c_chan *dp_i2c_bus;
452 u8 dpcd[DP_RECEIVER_CAP_SIZE];
459 struct radeon_gpio_rec {
467 enum radeon_hpd_id hpd;
469 struct radeon_gpio_rec gpio;
472 struct radeon_router {
474 struct radeon_i2c_bus_rec i2c_info;
479 u8 ddc_mux_control_pin;
484 u8 cd_mux_control_pin;
488 enum radeon_connector_audio {
489 RADEON_AUDIO_DISABLE = 0,
490 RADEON_AUDIO_ENABLE = 1,
491 RADEON_AUDIO_AUTO = 2
494 enum radeon_connector_dither {
495 RADEON_FMT_DITHER_DISABLE = 0,
496 RADEON_FMT_DITHER_ENABLE = 1,
499 struct radeon_connector {
500 struct drm_connector base;
501 uint32_t connector_id;
503 struct radeon_i2c_chan *ddc_bus;
504 /* some systems have an hdmi and vga port with a shared ddc line */
507 /* we need to mind the EDID between detect
508 and get modes due to analog/digital/tvencoder */
511 bool dac_load_detect;
512 bool detected_by_load; /* if the connection status was determined by load */
513 uint16_t connector_object_id;
514 struct radeon_hpd hpd;
515 struct radeon_router router;
516 struct radeon_i2c_chan *router_bus;
517 enum radeon_connector_audio audio;
518 enum radeon_connector_dither dither;
519 int pixelclock_for_modeset;
522 struct radeon_framebuffer {
523 struct drm_framebuffer base;
524 struct drm_gem_object *obj;
527 #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
528 ((em) == ATOM_ENCODER_MODE_DP_MST))
530 struct atom_clock_dividers {
536 u32 whole_fb_div : 12;
537 u32 frac_fb_div : 14;
539 u32 frac_fb_div : 14;
540 u32 whole_fb_div : 12;
547 bool enable_post_div;
556 struct atom_mpll_param {
580 #define MEM_TYPE_GDDR5 0x50
581 #define MEM_TYPE_GDDR4 0x40
582 #define MEM_TYPE_GDDR3 0x30
583 #define MEM_TYPE_DDR2 0x20
584 #define MEM_TYPE_GDDR1 0x10
585 #define MEM_TYPE_DDR3 0xb0
586 #define MEM_TYPE_MASK 0xf0
588 struct atom_memory_info {
593 #define MAX_AC_TIMING_ENTRIES 16
595 struct atom_memory_clock_range_table
599 u32 mclk[MAX_AC_TIMING_ENTRIES];
602 #define VBIOS_MC_REGISTER_ARRAY_SIZE 32
603 #define VBIOS_MAX_AC_TIMING_ENTRIES 20
605 struct atom_mc_reg_entry {
607 u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE];
610 struct atom_mc_register_address {
615 struct atom_mc_reg_table {
618 struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES];
619 struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE];
622 #define MAX_VOLTAGE_ENTRIES 32
624 struct atom_voltage_table_entry
630 struct atom_voltage_table
635 struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES];
638 /* Driver internal use only flags of radeon_get_crtc_scanoutpos() */
639 #define USE_REAL_VBLANKSTART (1 << 30)
640 #define GET_DISTANCE_TO_VBLANKSTART (1 << 31)
643 radeon_add_atom_connector(struct drm_device *dev,
644 uint32_t connector_id,
645 uint32_t supported_device,
647 struct radeon_i2c_bus_rec *i2c_bus,
648 uint32_t igp_lane_info,
649 uint16_t connector_object_id,
650 struct radeon_hpd *hpd,
651 struct radeon_router *router);
653 radeon_add_legacy_connector(struct drm_device *dev,
654 uint32_t connector_id,
655 uint32_t supported_device,
657 struct radeon_i2c_bus_rec *i2c_bus,
658 uint16_t connector_object_id,
659 struct radeon_hpd *hpd);
661 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
663 extern void radeon_link_encoder_connector(struct drm_device *dev);
665 extern enum radeon_tv_std
666 radeon_combios_get_tv_info(struct radeon_device *rdev);
667 extern enum radeon_tv_std
668 radeon_atombios_get_tv_info(struct radeon_device *rdev);
669 extern void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
670 u16 *vddc, u16 *vddci, u16 *mvdd);
673 radeon_combios_connected_scratch_regs(struct drm_connector *connector,
674 struct drm_encoder *encoder,
677 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
678 struct drm_encoder *encoder,
681 extern struct drm_connector *
682 radeon_get_connector_for_encoder(struct drm_encoder *encoder);
683 extern struct drm_connector *
684 radeon_get_connector_for_encoder_init(struct drm_encoder *encoder);
685 extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder,
688 extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
689 extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector);
690 extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector);
691 extern int radeon_get_monitor_bpc(struct drm_connector *connector);
693 extern struct edid *radeon_connector_edid(struct drm_connector *connector);
695 extern void radeon_connector_hotplug(struct drm_connector *connector);
696 extern int radeon_dp_mode_valid_helper(struct drm_connector *connector,
697 struct drm_display_mode *mode);
698 extern void radeon_dp_set_link_config(struct drm_connector *connector,
699 const struct drm_display_mode *mode);
700 extern void radeon_dp_link_train(struct drm_encoder *encoder,
701 struct drm_connector *connector);
702 extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
703 extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
704 extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
705 extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
706 struct drm_connector *connector);
707 extern void radeon_dp_set_rx_power_state(struct drm_connector *connector,
709 extern void radeon_dp_aux_init(struct radeon_connector *radeon_connector);
710 extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode);
711 extern void radeon_atom_encoder_init(struct radeon_device *rdev);
712 extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev);
713 extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
714 int action, uint8_t lane_num,
716 extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder);
717 extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder);
718 extern int radeon_dp_i2c_aux_ch(device_t dev, int mode,
719 u8 write_byte, u8 *read_byte);
720 void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le);
722 extern void radeon_i2c_init(struct radeon_device *rdev);
723 extern void radeon_i2c_fini(struct radeon_device *rdev);
724 extern void radeon_combios_i2c_init(struct radeon_device *rdev);
725 extern void radeon_atombios_i2c_init(struct radeon_device *rdev);
726 extern void radeon_i2c_add(struct radeon_device *rdev,
727 struct radeon_i2c_bus_rec *rec,
729 extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
730 struct radeon_i2c_bus_rec *i2c_bus);
731 extern struct radeon_i2c_chan *radeon_i2c_create_dp(struct drm_device *dev,
732 struct radeon_i2c_bus_rec *rec,
734 extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
735 struct radeon_i2c_bus_rec *rec,
737 extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
738 extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
742 extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c,
746 extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector);
747 extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector);
748 extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux);
750 extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
751 struct radeon_atom_ss *ss,
753 extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
754 struct radeon_atom_ss *ss,
757 extern void radeon_compute_pll_legacy(struct radeon_pll *pll,
759 uint32_t *dot_clock_p,
761 uint32_t *frac_fb_div_p,
763 uint32_t *post_div_p);
765 extern void radeon_compute_pll_avivo(struct radeon_pll *pll,
773 extern void radeon_setup_encoder_clones(struct drm_device *dev);
775 struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
776 struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
777 struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
778 struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
779 struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
780 extern void atombios_dvo_setup(struct drm_encoder *encoder, int action);
781 extern void atombios_digital_setup(struct drm_encoder *encoder, int action);
782 extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
783 extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action);
784 extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
785 extern bool radeon_encoder_is_digital(struct drm_encoder *encoder);
787 extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
788 extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
789 struct drm_framebuffer *old_fb);
790 extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
791 struct drm_framebuffer *fb,
793 enum mode_set_atomic state);
794 extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
795 struct drm_display_mode *mode,
796 struct drm_display_mode *adjusted_mode,
798 struct drm_framebuffer *old_fb);
799 extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
801 extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
802 struct drm_framebuffer *old_fb);
803 extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc,
804 struct drm_framebuffer *fb,
806 enum mode_set_atomic state);
807 extern int radeon_crtc_do_set_base(struct drm_crtc *crtc,
808 struct drm_framebuffer *fb,
809 int x, int y, int atomic);
810 extern int radeon_crtc_cursor_set(struct drm_crtc *crtc,
811 struct drm_file *file_priv,
815 extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
818 extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc,
820 int *vpos, int *hpos,
821 ktime_t *stime, ktime_t *etime,
822 const struct drm_display_mode *mode);
824 extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev);
826 radeon_bios_get_hardcoded_edid(struct radeon_device *rdev);
827 extern bool radeon_atom_get_clock_info(struct drm_device *dev);
828 extern bool radeon_combios_get_clock_info(struct drm_device *dev);
829 extern struct radeon_encoder_atom_dig *
830 radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
831 extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
832 struct radeon_encoder_int_tmds *tmds);
833 extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
834 struct radeon_encoder_int_tmds *tmds);
835 extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
836 struct radeon_encoder_int_tmds *tmds);
837 extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
838 struct radeon_encoder_ext_tmds *tmds);
839 extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
840 struct radeon_encoder_ext_tmds *tmds);
841 extern struct radeon_encoder_primary_dac *
842 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
843 extern struct radeon_encoder_tv_dac *
844 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
845 extern struct radeon_encoder_lvds *
846 radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
847 extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
848 extern struct radeon_encoder_tv_dac *
849 radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
850 extern struct radeon_encoder_primary_dac *
851 radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
852 extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder);
853 extern void radeon_external_tmds_setup(struct drm_encoder *encoder);
854 extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
855 extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
856 extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
857 extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
858 extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
859 extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
861 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
863 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
865 radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
867 radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
868 extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
869 u16 blue, int regno);
870 extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
871 u16 *blue, int regno);
872 int radeon_framebuffer_init(struct drm_device *dev,
873 struct radeon_framebuffer *rfb,
874 struct drm_mode_fb_cmd2 *mode_cmd,
875 struct drm_gem_object *obj);
877 int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
878 bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
879 bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
880 void radeon_atombios_init_crtc(struct drm_device *dev,
881 struct radeon_crtc *radeon_crtc);
882 void radeon_legacy_init_crtc(struct drm_device *dev,
883 struct radeon_crtc *radeon_crtc);
885 void radeon_get_clock_info(struct drm_device *dev);
887 extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
888 extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);
890 void radeon_enc_destroy(struct drm_encoder *encoder);
891 void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
892 void radeon_combios_asic_init(struct drm_device *dev);
893 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
894 const struct drm_display_mode *mode,
895 struct drm_display_mode *adjusted_mode);
896 void radeon_panel_mode_fixup(struct drm_encoder *encoder,
897 struct drm_display_mode *adjusted_mode);
898 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
901 void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
902 uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
903 uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
904 void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
905 uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
906 uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
907 void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
908 uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
909 uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);
910 void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
911 struct drm_display_mode *mode,
912 struct drm_display_mode *adjusted_mode);
915 void avivo_program_fmt(struct drm_encoder *encoder);
916 void dce3_program_fmt(struct drm_encoder *encoder);
917 void dce4_program_fmt(struct drm_encoder *encoder);
918 void dce8_program_fmt(struct drm_encoder *encoder);
921 int radeon_fbdev_init(struct radeon_device *rdev);
922 void radeon_fbdev_fini(struct radeon_device *rdev);
923 void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state);
924 bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj);
926 void radeon_fb_output_poll_changed(struct radeon_device *rdev);
928 void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id);
929 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id);
931 int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled);