sys/dev/netif/jme/if_jme.c

   1 /*-
   2  * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice unmodified, this list of conditions, and the following
  10  *    disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  *
  27  * $FreeBSD: src/sys/dev/jme/if_jme.c,v 1.2 2008/07/18 04:20:48 yongari Exp $
  28  */
  29
  30 #include "opt_polling.h"
  31 #include "opt_jme.h"
  32
  33 #include <sys/param.h>
  34 #include <sys/endian.h>
  35 #include <sys/kernel.h>
  36 #include <sys/bus.h>
  37 #include <sys/interrupt.h>
  38 #include <sys/malloc.h>
  39 #include <sys/proc.h>
  40 #include <sys/rman.h>
  41 #include <sys/serialize.h>
  42 #include <sys/serialize2.h>
  43 #include <sys/socket.h>
  44 #include <sys/sockio.h>
  45 #include <sys/sysctl.h>
  46
  47 #include <net/ethernet.h>
  48 #include <net/if.h>
  49 #include <net/bpf.h>
  50 #include <net/if_arp.h>
  51 #include <net/if_dl.h>
  52 #include <net/if_media.h>
  53 #include <net/ifq_var.h>
  54 #include <net/toeplitz.h>
  55 #include <net/toeplitz2.h>
  56 #include <net/vlan/if_vlan_var.h>
  57 #include <net/vlan/if_vlan_ether.h>
  58
  59 #include <netinet/in.h>
  60
  61 #include <dev/netif/mii_layer/miivar.h>
  62 #include <dev/netif/mii_layer/jmphyreg.h>
  63
  64 #include <bus/pci/pcireg.h>
  65 #include <bus/pci/pcivar.h>
  66 #include <bus/pci/pcidevs.h>
  67
  68 #include <dev/netif/jme/if_jmereg.h>
  69 #include <dev/netif/jme/if_jmevar.h>
  70
  71 #include "miibus_if.h"
  72
  73 /* Define the following to disable printing Rx errors. */
  74 #undef  JME_SHOW_ERRORS
  75
  76 #define JME_CSUM_FEATURES       (CSUM_IP | CSUM_TCP | CSUM_UDP)
  77
  78 #ifdef JME_RSS_DEBUG
  79 #define JME_RSS_DPRINTF(sc, lvl, fmt, ...) \
  80 do { \
  81         if ((sc)->jme_rss_debug >= (lvl)) \
  82                 if_printf(&(sc)->arpcom.ac_if, fmt, __VA_ARGS__); \
  83 } while (0)
  84 #else   /* !JME_RSS_DEBUG */
  85 #define JME_RSS_DPRINTF(sc, lvl, fmt, ...)      ((void)0)
  86 #endif  /* JME_RSS_DEBUG */
  87
  88 static int      jme_probe(device_t);
  89 static int      jme_attach(device_t);
  90 static int      jme_detach(device_t);
  91 static int      jme_shutdown(device_t);
  92 static int      jme_suspend(device_t);
  93 static int      jme_resume(device_t);
  94
  95 static int      jme_miibus_readreg(device_t, int, int);
  96 static int      jme_miibus_writereg(device_t, int, int, int);
  97 static void     jme_miibus_statchg(device_t);
  98
  99 static void     jme_init(void *);
 100 static int      jme_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 101 static void     jme_start(struct ifnet *);
 102 static void     jme_watchdog(struct ifnet *);
 103 static void     jme_mediastatus(struct ifnet *, struct ifmediareq *);
 104 static int      jme_mediachange(struct ifnet *);
 105 #ifdef DEVICE_POLLING
 106 static void     jme_poll(struct ifnet *, enum poll_cmd, int);
 107 #endif
 108 static void     jme_serialize(struct ifnet *, enum ifnet_serialize);
 109 static void     jme_deserialize(struct ifnet *, enum ifnet_serialize);
 110 static int      jme_tryserialize(struct ifnet *, enum ifnet_serialize);
 111 #ifdef INVARIANTS
 112 static void     jme_serialize_assert(struct ifnet *, enum ifnet_serialize,
 113                     boolean_t);
 114 #endif
 115
 116 static void     jme_intr(void *);
 117 static void     jme_msix_tx(void *);
 118 static void     jme_msix_rx(void *);
 119 static void     jme_txeof(struct jme_softc *);
 120 static void     jme_rxeof(struct jme_rxdata *, int);
 121 static void     jme_rx_intr(struct jme_softc *, uint32_t);
 122
 123 static int      jme_msix_setup(device_t);
 124 static void     jme_msix_teardown(device_t, int);
 125 static int      jme_intr_setup(device_t);
 126 static void     jme_intr_teardown(device_t);
 127 static void     jme_msix_try_alloc(device_t);
 128 static void     jme_msix_free(device_t);
 129 static int      jme_intr_alloc(device_t);
 130 static void     jme_intr_free(device_t);
 131 static int      jme_dma_alloc(struct jme_softc *);
 132 static void     jme_dma_free(struct jme_softc *);
 133 static int      jme_init_rx_ring(struct jme_rxdata *);
 134 static void     jme_init_tx_ring(struct jme_softc *);
 135 static void     jme_init_ssb(struct jme_softc *);
 136 static int      jme_newbuf(struct jme_rxdata *, struct jme_rxdesc *, int);
 137 static int      jme_encap(struct jme_softc *, struct mbuf **);
 138 static void     jme_rxpkt(struct jme_rxdata *);
 139 static int      jme_rxring_dma_alloc(struct jme_rxdata *);
 140 static int      jme_rxbuf_dma_alloc(struct jme_rxdata *);
 141
 142 static void     jme_tick(void *);
 143 static void     jme_stop(struct jme_softc *);
 144 static void     jme_reset(struct jme_softc *);
 145 static void     jme_set_msinum(struct jme_softc *);
 146 static void     jme_set_vlan(struct jme_softc *);
 147 static void     jme_set_filter(struct jme_softc *);
 148 static void     jme_stop_tx(struct jme_softc *);
 149 static void     jme_stop_rx(struct jme_softc *);
 150 static void     jme_mac_config(struct jme_softc *);
 151 static void     jme_reg_macaddr(struct jme_softc *, uint8_t[]);
 152 static int      jme_eeprom_macaddr(struct jme_softc *, uint8_t[]);
 153 static int      jme_eeprom_read_byte(struct jme_softc *, uint8_t, uint8_t *);
 154 #ifdef notyet
 155 static void     jme_setwol(struct jme_softc *);
 156 static void     jme_setlinkspeed(struct jme_softc *);
 157 #endif
 158 static void     jme_set_tx_coal(struct jme_softc *);
 159 static void     jme_set_rx_coal(struct jme_softc *);
 160 static void     jme_enable_rss(struct jme_softc *);
 161 static void     jme_disable_rss(struct jme_softc *);
 162
 163 static void     jme_sysctl_node(struct jme_softc *);
 164 static int      jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS);
 165 static int      jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS);
 166 static int      jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS);
 167 static int      jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS);
 168
 169 /*
 170  * Devices supported by this driver.
 171  */
 172 static const struct jme_dev {
 173         uint16_t        jme_vendorid;
 174         uint16_t        jme_deviceid;
 175         uint32_t        jme_caps;
 176         const char      *jme_name;
 177 } jme_devs[] = {
 178         { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC250,
 179             JME_CAP_JUMBO,
 180             "JMicron Inc, JMC250 Gigabit Ethernet" },
 181         { PCI_VENDOR_JMICRON, PCI_PRODUCT_JMICRON_JMC260,
 182             JME_CAP_FASTETH,
 183             "JMicron Inc, JMC260 Fast Ethernet" },
 184         { 0, 0, 0, NULL }
 185 };
 186
 187 static device_method_t jme_methods[] = {
 188         /* Device interface. */
 189         DEVMETHOD(device_probe,         jme_probe),
 190         DEVMETHOD(device_attach,        jme_attach),
 191         DEVMETHOD(device_detach,        jme_detach),
 192         DEVMETHOD(device_shutdown,      jme_shutdown),
 193         DEVMETHOD(device_suspend,       jme_suspend),
 194         DEVMETHOD(device_resume,        jme_resume),
 195
 196         /* Bus interface. */
 197         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 198         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 199
 200         /* MII interface. */
 201         DEVMETHOD(miibus_readreg,       jme_miibus_readreg),
 202         DEVMETHOD(miibus_writereg,      jme_miibus_writereg),
 203         DEVMETHOD(miibus_statchg,       jme_miibus_statchg),
 204
 205         { NULL, NULL }
 206 };
 207
 208 static driver_t jme_driver = {
 209         "jme",
 210         jme_methods,
 211         sizeof(struct jme_softc)
 212 };
 213
 214 static devclass_t jme_devclass;
 215
 216 DECLARE_DUMMY_MODULE(if_jme);
 217 MODULE_DEPEND(if_jme, miibus, 1, 1, 1);
 218 DRIVER_MODULE(if_jme, pci, jme_driver, jme_devclass, NULL, NULL);
 219 DRIVER_MODULE(miibus, jme, miibus_driver, miibus_devclass, NULL, NULL);
 220
 221 static const struct {
 222         uint32_t        jme_coal;
 223         uint32_t        jme_comp;
 224         uint32_t        jme_empty;
 225 } jme_rx_status[JME_NRXRING_MAX] = {
 226         { INTR_RXQ0_COAL | INTR_RXQ0_COAL_TO, INTR_RXQ0_COMP,
 227           INTR_RXQ0_DESC_EMPTY },
 228         { INTR_RXQ1_COAL | INTR_RXQ1_COAL_TO, INTR_RXQ1_COMP,
 229           INTR_RXQ1_DESC_EMPTY },
 230         { INTR_RXQ2_COAL | INTR_RXQ2_COAL_TO, INTR_RXQ2_COMP,
 231           INTR_RXQ2_DESC_EMPTY },
 232         { INTR_RXQ3_COAL | INTR_RXQ3_COAL_TO, INTR_RXQ3_COMP,
 233           INTR_RXQ3_DESC_EMPTY }
 234 };
 235
 236 static int      jme_rx_desc_count = JME_RX_DESC_CNT_DEF;
 237 static int      jme_tx_desc_count = JME_TX_DESC_CNT_DEF;
 238 static int      jme_rx_ring_count = 1;
 239 static int      jme_msi_enable = 1;
 240 static int      jme_msix_enable = 1;
 241
 242 TUNABLE_INT("hw.jme.rx_desc_count", &jme_rx_desc_count);
 243 TUNABLE_INT("hw.jme.tx_desc_count", &jme_tx_desc_count);
 244 TUNABLE_INT("hw.jme.rx_ring_count", &jme_rx_ring_count);
 245 TUNABLE_INT("hw.jme.msi.enable", &jme_msi_enable);
 246 TUNABLE_INT("hw.jme.msix.enable", &jme_msix_enable);
 247
 248 /*
 249  *      Read a PHY register on the MII of the JMC250.
 250  */
 251 static int
 252 jme_miibus_readreg(device_t dev, int phy, int reg)
 253 {
 254         struct jme_softc *sc = device_get_softc(dev);
 255         uint32_t val;
 256         int i;
 257
 258         /* For FPGA version, PHY address 0 should be ignored. */
 259         if (sc->jme_caps & JME_CAP_FPGA) {
 260                 if (phy == 0)
 261                         return (0);
 262         } else {
 263                 if (sc->jme_phyaddr != phy)
 264                         return (0);
 265         }
 266
 267         CSR_WRITE_4(sc, JME_SMI, SMI_OP_READ | SMI_OP_EXECUTE |
 268             SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
 269
 270         for (i = JME_PHY_TIMEOUT; i > 0; i--) {
 271                 DELAY(1);
 272                 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
 273                         break;
 274         }
 275         if (i == 0) {
 276                 device_printf(sc->jme_dev, "phy read timeout: "
 277                               "phy %d, reg %d\n", phy, reg);
 278                 return (0);
 279         }
 280
 281         return ((val & SMI_DATA_MASK) >> SMI_DATA_SHIFT);
 282 }
 283
 284 /*
 285  *      Write a PHY register on the MII of the JMC250.
 286  */
 287 static int
 288 jme_miibus_writereg(device_t dev, int phy, int reg, int val)
 289 {
 290         struct jme_softc *sc = device_get_softc(dev);
 291         int i;
 292
 293         /* For FPGA version, PHY address 0 should be ignored. */
 294         if (sc->jme_caps & JME_CAP_FPGA) {
 295                 if (phy == 0)
 296                         return (0);
 297         } else {
 298                 if (sc->jme_phyaddr != phy)
 299                         return (0);
 300         }
 301
 302         CSR_WRITE_4(sc, JME_SMI, SMI_OP_WRITE | SMI_OP_EXECUTE |
 303             ((val << SMI_DATA_SHIFT) & SMI_DATA_MASK) |
 304             SMI_PHY_ADDR(phy) | SMI_REG_ADDR(reg));
 305
 306         for (i = JME_PHY_TIMEOUT; i > 0; i--) {
 307                 DELAY(1);
 308                 if (((val = CSR_READ_4(sc, JME_SMI)) & SMI_OP_EXECUTE) == 0)
 309                         break;
 310         }
 311         if (i == 0) {
 312                 device_printf(sc->jme_dev, "phy write timeout: "
 313                               "phy %d, reg %d\n", phy, reg);
 314         }
 315
 316         return (0);
 317 }
 318
 319 /*
 320  *      Callback from MII layer when media changes.
 321  */
 322 static void
 323 jme_miibus_statchg(device_t dev)
 324 {
 325         struct jme_softc *sc = device_get_softc(dev);
 326         struct ifnet *ifp = &sc->arpcom.ac_if;
 327         struct mii_data *mii;
 328         struct jme_txdesc *txd;
 329         bus_addr_t paddr;
 330         int i, r;
 331
 332         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 333
 334         if ((ifp->if_flags & IFF_RUNNING) == 0)
 335                 return;
 336
 337         mii = device_get_softc(sc->jme_miibus);
 338
 339         sc->jme_flags &= ~JME_FLAG_LINK;
 340         if ((mii->mii_media_status & IFM_AVALID) != 0) {
 341                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
 342                 case IFM_10_T:
 343                 case IFM_100_TX:
 344                         sc->jme_flags |= JME_FLAG_LINK;
 345                         break;
 346                 case IFM_1000_T:
 347                         if (sc->jme_caps & JME_CAP_FASTETH)
 348                                 break;
 349                         sc->jme_flags |= JME_FLAG_LINK;
 350                         break;
 351                 default:
 352                         break;
 353                 }
 354         }
 355
 356         /*
 357          * Disabling Rx/Tx MACs have a side-effect of resetting
 358          * JME_TXNDA/JME_RXNDA register to the first address of
 359          * Tx/Rx descriptor address. So driver should reset its
 360          * internal procucer/consumer pointer and reclaim any
 361          * allocated resources.  Note, just saving the value of
 362          * JME_TXNDA and JME_RXNDA registers before stopping MAC
 363          * and restoring JME_TXNDA/JME_RXNDA register is not
 364          * sufficient to make sure correct MAC state because
 365          * stopping MAC operation can take a while and hardware
 366          * might have updated JME_TXNDA/JME_RXNDA registers
 367          * during the stop operation.
 368          */
 369
 370         /* Disable interrupts */
 371         CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
 372
 373         /* Stop driver */
 374         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
 375         ifp->if_timer = 0;
 376         callout_stop(&sc->jme_tick_ch);
 377
 378         /* Stop receiver/transmitter. */
 379         jme_stop_rx(sc);
 380         jme_stop_tx(sc);
 381
 382         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
 383                 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
 384
 385                 jme_rxeof(rdata, -1);
 386                 if (rdata->jme_rxhead != NULL)
 387                         m_freem(rdata->jme_rxhead);
 388                 JME_RXCHAIN_RESET(rdata);
 389
 390                 /*
 391                  * Reuse configured Rx descriptors and reset
 392                  * procuder/consumer index.
 393                  */
 394                 rdata->jme_rx_cons = 0;
 395         }
 396
 397         jme_txeof(sc);
 398         if (sc->jme_cdata.jme_tx_cnt != 0) {
 399                 /* Remove queued packets for transmit. */
 400                 for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
 401                         txd = &sc->jme_cdata.jme_txdesc[i];
 402                         if (txd->tx_m != NULL) {
 403                                 bus_dmamap_unload(
 404                                     sc->jme_cdata.jme_tx_tag,
 405                                     txd->tx_dmamap);
 406                                 m_freem(txd->tx_m);
 407                                 txd->tx_m = NULL;
 408                                 txd->tx_ndesc = 0;
 409                                 ifp->if_oerrors++;
 410                         }
 411                 }
 412         }
 413         jme_init_tx_ring(sc);
 414
 415         /* Initialize shadow status block. */
 416         jme_init_ssb(sc);
 417
 418         /* Program MAC with resolved speed/duplex/flow-control. */
 419         if (sc->jme_flags & JME_FLAG_LINK) {
 420                 jme_mac_config(sc);
 421
 422                 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
 423
 424                 /* Set Tx ring address to the hardware. */
 425                 paddr = sc->jme_cdata.jme_tx_ring_paddr;
 426                 CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
 427                 CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
 428
 429                 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
 430                         CSR_WRITE_4(sc, JME_RXCSR,
 431                             sc->jme_rxcsr | RXCSR_RXQ_N_SEL(r));
 432
 433                         /* Set Rx ring address to the hardware. */
 434                         paddr = sc->jme_cdata.jme_rx_data[r].jme_rx_ring_paddr;
 435                         CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
 436                         CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
 437                 }
 438
 439                 /* Restart receiver/transmitter. */
 440                 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RX_ENB |
 441                     RXCSR_RXQ_START);
 442                 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB);
 443         }
 444
 445         ifp->if_flags |= IFF_RUNNING;
 446         ifp->if_flags &= ~IFF_OACTIVE;
 447         callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
 448
 449 #ifdef DEVICE_POLLING
 450         if (!(ifp->if_flags & IFF_POLLING))
 451 #endif
 452         /* Reenable interrupts. */
 453         CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
 454 }
 455
 456 /*
 457  *      Get the current interface media status.
 458  */
 459 static void
 460 jme_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
 461 {
 462         struct jme_softc *sc = ifp->if_softc;
 463         struct mii_data *mii = device_get_softc(sc->jme_miibus);
 464
 465         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 466
 467         mii_pollstat(mii);
 468         ifmr->ifm_status = mii->mii_media_status;
 469         ifmr->ifm_active = mii->mii_media_active;
 470 }
 471
 472 /*
 473  *      Set hardware to newly-selected media.
 474  */
 475 static int
 476 jme_mediachange(struct ifnet *ifp)
 477 {
 478         struct jme_softc *sc = ifp->if_softc;
 479         struct mii_data *mii = device_get_softc(sc->jme_miibus);
 480         int error;
 481
 482         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 483
 484         if (mii->mii_instance != 0) {
 485                 struct mii_softc *miisc;
 486
 487                 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
 488                         mii_phy_reset(miisc);
 489         }
 490         error = mii_mediachg(mii);
 491
 492         return (error);
 493 }
 494
 495 static int
 496 jme_probe(device_t dev)
 497 {
 498         const struct jme_dev *sp;
 499         uint16_t vid, did;
 500
 501         vid = pci_get_vendor(dev);
 502         did = pci_get_device(dev);
 503         for (sp = jme_devs; sp->jme_name != NULL; ++sp) {
 504                 if (vid == sp->jme_vendorid && did == sp->jme_deviceid) {
 505                         struct jme_softc *sc = device_get_softc(dev);
 506
 507                         sc->jme_caps = sp->jme_caps;
 508                         device_set_desc(dev, sp->jme_name);
 509                         return (0);
 510                 }
 511         }
 512         return (ENXIO);
 513 }
 514
 515 static int
 516 jme_eeprom_read_byte(struct jme_softc *sc, uint8_t addr, uint8_t *val)
 517 {
 518         uint32_t reg;
 519         int i;
 520
 521         *val = 0;
 522         for (i = JME_TIMEOUT; i > 0; i--) {
 523                 reg = CSR_READ_4(sc, JME_SMBCSR);
 524                 if ((reg & SMBCSR_HW_BUSY_MASK) == SMBCSR_HW_IDLE)
 525                         break;
 526                 DELAY(1);
 527         }
 528
 529         if (i == 0) {
 530                 device_printf(sc->jme_dev, "EEPROM idle timeout!\n");
 531                 return (ETIMEDOUT);
 532         }
 533
 534         reg = ((uint32_t)addr << SMBINTF_ADDR_SHIFT) & SMBINTF_ADDR_MASK;
 535         CSR_WRITE_4(sc, JME_SMBINTF, reg | SMBINTF_RD | SMBINTF_CMD_TRIGGER);
 536         for (i = JME_TIMEOUT; i > 0; i--) {
 537                 DELAY(1);
 538                 reg = CSR_READ_4(sc, JME_SMBINTF);
 539                 if ((reg & SMBINTF_CMD_TRIGGER) == 0)
 540                         break;
 541         }
 542
 543         if (i == 0) {
 544                 device_printf(sc->jme_dev, "EEPROM read timeout!\n");
 545                 return (ETIMEDOUT);
 546         }
 547
 548         reg = CSR_READ_4(sc, JME_SMBINTF);
 549         *val = (reg & SMBINTF_RD_DATA_MASK) >> SMBINTF_RD_DATA_SHIFT;
 550
 551         return (0);
 552 }
 553
 554 static int
 555 jme_eeprom_macaddr(struct jme_softc *sc, uint8_t eaddr[])
 556 {
 557         uint8_t fup, reg, val;
 558         uint32_t offset;
 559         int match;
 560
 561         offset = 0;
 562         if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
 563             fup != JME_EEPROM_SIG0)
 564                 return (ENOENT);
 565         if (jme_eeprom_read_byte(sc, offset++, &fup) != 0 ||
 566             fup != JME_EEPROM_SIG1)
 567                 return (ENOENT);
 568         match = 0;
 569         do {
 570                 if (jme_eeprom_read_byte(sc, offset, &fup) != 0)
 571                         break;
 572                 if (JME_EEPROM_MKDESC(JME_EEPROM_FUNC0, JME_EEPROM_PAGE_BAR1) ==
 573                     (fup & (JME_EEPROM_FUNC_MASK | JME_EEPROM_PAGE_MASK))) {
 574                         if (jme_eeprom_read_byte(sc, offset + 1, &reg) != 0)
 575                                 break;
 576                         if (reg >= JME_PAR0 &&
 577                             reg < JME_PAR0 + ETHER_ADDR_LEN) {
 578                                 if (jme_eeprom_read_byte(sc, offset + 2,
 579                                     &val) != 0)
 580                                         break;
 581                                 eaddr[reg - JME_PAR0] = val;
 582                                 match++;
 583                         }
 584                 }
 585                 /* Check for the end of EEPROM descriptor. */
 586                 if ((fup & JME_EEPROM_DESC_END) == JME_EEPROM_DESC_END)
 587                         break;
 588                 /* Try next eeprom descriptor. */
 589                 offset += JME_EEPROM_DESC_BYTES;
 590         } while (match != ETHER_ADDR_LEN && offset < JME_EEPROM_END);
 591
 592         if (match == ETHER_ADDR_LEN)
 593                 return (0);
 594
 595         return (ENOENT);
 596 }
 597
 598 static void
 599 jme_reg_macaddr(struct jme_softc *sc, uint8_t eaddr[])
 600 {
 601         uint32_t par0, par1;
 602
 603         /* Read station address. */
 604         par0 = CSR_READ_4(sc, JME_PAR0);
 605         par1 = CSR_READ_4(sc, JME_PAR1);
 606         par1 &= 0xFFFF;
 607         if ((par0 == 0 && par1 == 0) || (par0 & 0x1)) {
 608                 device_printf(sc->jme_dev,
 609                     "generating fake ethernet address.\n");
 610                 par0 = karc4random();
 611                 /* Set OUI to JMicron. */
 612                 eaddr[0] = 0x00;
 613                 eaddr[1] = 0x1B;
 614                 eaddr[2] = 0x8C;
 615                 eaddr[3] = (par0 >> 16) & 0xff;
 616                 eaddr[4] = (par0 >> 8) & 0xff;
 617                 eaddr[5] = par0 & 0xff;
 618         } else {
 619                 eaddr[0] = (par0 >> 0) & 0xFF;
 620                 eaddr[1] = (par0 >> 8) & 0xFF;
 621                 eaddr[2] = (par0 >> 16) & 0xFF;
 622                 eaddr[3] = (par0 >> 24) & 0xFF;
 623                 eaddr[4] = (par1 >> 0) & 0xFF;
 624                 eaddr[5] = (par1 >> 8) & 0xFF;
 625         }
 626 }
 627
 628 static int
 629 jme_attach(device_t dev)
 630 {
 631         struct jme_softc *sc = device_get_softc(dev);
 632         struct ifnet *ifp = &sc->arpcom.ac_if;
 633         uint32_t reg;
 634         uint16_t did;
 635         uint8_t pcie_ptr, rev;
 636         int error = 0, i, j, rx_desc_cnt;
 637         uint8_t eaddr[ETHER_ADDR_LEN];
 638
 639         lwkt_serialize_init(&sc->jme_serialize);
 640         lwkt_serialize_init(&sc->jme_cdata.jme_tx_serialize);
 641         for (i = 0; i < JME_NRXRING_MAX; ++i) {
 642                 lwkt_serialize_init(
 643                     &sc->jme_cdata.jme_rx_data[i].jme_rx_serialize);
 644         }
 645
 646         rx_desc_cnt = device_getenv_int(dev, "rx_desc_count",
 647             jme_rx_desc_count);
 648         rx_desc_cnt = roundup(rx_desc_cnt, JME_NDESC_ALIGN);
 649         if (rx_desc_cnt > JME_NDESC_MAX)
 650                 rx_desc_cnt = JME_NDESC_MAX;
 651
 652         sc->jme_cdata.jme_tx_desc_cnt = device_getenv_int(dev, "tx_desc_count",
 653             jme_tx_desc_count);
 654         sc->jme_cdata.jme_tx_desc_cnt = roundup(sc->jme_cdata.jme_tx_desc_cnt,
 655             JME_NDESC_ALIGN);
 656         if (sc->jme_cdata.jme_tx_desc_cnt > JME_NDESC_MAX)
 657                 sc->jme_cdata.jme_tx_desc_cnt = JME_NDESC_MAX;
 658
 659         /*
 660          * Calculate rx rings
 661          */
 662         sc->jme_cdata.jme_rx_ring_cnt = device_getenv_int(dev, "rx_ring_count",
 663             jme_rx_ring_count);
 664         sc->jme_cdata.jme_rx_ring_cnt =
 665             if_ring_count2(sc->jme_cdata.jme_rx_ring_cnt, JME_NRXRING_MAX);
 666
 667         i = 0;
 668         sc->jme_serialize_arr[i++] = &sc->jme_serialize;
 669         sc->jme_serialize_arr[i++] = &sc->jme_cdata.jme_tx_serialize;
 670         for (j = 0; j < sc->jme_cdata.jme_rx_ring_cnt; ++j) {
 671                 sc->jme_serialize_arr[i++] =
 672                     &sc->jme_cdata.jme_rx_data[j].jme_rx_serialize;
 673         }
 674         KKASSERT(i <= JME_NSERIALIZE);
 675         sc->jme_serialize_cnt = i;
 676
 677         sc->jme_cdata.jme_sc = sc;
 678         for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
 679                 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[i];
 680
 681                 rdata->jme_sc = sc;
 682                 rdata->jme_rx_coal = jme_rx_status[i].jme_coal;
 683                 rdata->jme_rx_comp = jme_rx_status[i].jme_comp;
 684                 rdata->jme_rx_empty = jme_rx_status[i].jme_empty;
 685                 rdata->jme_rx_idx = i;
 686                 rdata->jme_rx_desc_cnt = rx_desc_cnt;
 687         }
 688
 689         sc->jme_dev = dev;
 690         sc->jme_lowaddr = BUS_SPACE_MAXADDR;
 691
 692         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 693
 694         callout_init(&sc->jme_tick_ch);
 695
 696 #ifndef BURN_BRIDGES
 697         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
 698                 uint32_t irq, mem;
 699
 700                 irq = pci_read_config(dev, PCIR_INTLINE, 4);
 701                 mem = pci_read_config(dev, JME_PCIR_BAR, 4);
 702
 703                 device_printf(dev, "chip is in D%d power mode "
 704                     "-- setting to D0\n", pci_get_powerstate(dev));
 705
 706                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
 707
 708                 pci_write_config(dev, PCIR_INTLINE, irq, 4);
 709                 pci_write_config(dev, JME_PCIR_BAR, mem, 4);
 710         }
 711 #endif  /* !BURN_BRIDGE */
 712
 713         /* Enable bus mastering */
 714         pci_enable_busmaster(dev);
 715
 716         /*
 717          * Allocate IO memory
 718          *
 719          * JMC250 supports both memory mapped and I/O register space
 720          * access.  Because I/O register access should use different
 721          * BARs to access registers it's waste of time to use I/O
 722          * register spce access.  JMC250 uses 16K to map entire memory
 723          * space.
 724          */
 725         sc->jme_mem_rid = JME_PCIR_BAR;
 726         sc->jme_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
 727                                                  &sc->jme_mem_rid, RF_ACTIVE);
 728         if (sc->jme_mem_res == NULL) {
 729                 device_printf(dev, "can't allocate IO memory\n");
 730                 return ENXIO;
 731         }
 732         sc->jme_mem_bt = rman_get_bustag(sc->jme_mem_res);
 733         sc->jme_mem_bh = rman_get_bushandle(sc->jme_mem_res);
 734
 735         /*
 736          * Allocate IRQ
 737          */
 738         error = jme_intr_alloc(dev);
 739         if (error)
 740                 goto fail;
 741
 742         /*
 743          * Extract revisions
 744          */
 745         reg = CSR_READ_4(sc, JME_CHIPMODE);
 746         if (((reg & CHIPMODE_FPGA_REV_MASK) >> CHIPMODE_FPGA_REV_SHIFT) !=
 747             CHIPMODE_NOT_FPGA) {
 748                 sc->jme_caps |= JME_CAP_FPGA;
 749                 if (bootverbose) {
 750                         device_printf(dev, "FPGA revision: 0x%04x\n",
 751                                       (reg & CHIPMODE_FPGA_REV_MASK) >>
 752                                       CHIPMODE_FPGA_REV_SHIFT);
 753                 }
 754         }
 755
 756         /* NOTE: FM revision is put in the upper 4 bits */
 757         rev = ((reg & CHIPMODE_REVFM_MASK) >> CHIPMODE_REVFM_SHIFT) << 4;
 758         rev |= (reg & CHIPMODE_REVECO_MASK) >> CHIPMODE_REVECO_SHIFT;
 759         if (bootverbose)
 760                 device_printf(dev, "Revision (FM/ECO): 0x%02x\n", rev);
 761
 762         did = pci_get_device(dev);
 763         switch (did) {
 764         case PCI_PRODUCT_JMICRON_JMC250:
 765                 if (rev == JME_REV1_A2)
 766                         sc->jme_workaround |= JME_WA_EXTFIFO | JME_WA_HDX;
 767                 break;
 768
 769         case PCI_PRODUCT_JMICRON_JMC260:
 770                 if (rev == JME_REV2)
 771                         sc->jme_lowaddr = BUS_SPACE_MAXADDR_32BIT;
 772                 break;
 773
 774         default:
 775                 panic("unknown device id 0x%04x", did);
 776         }
 777         if (rev >= JME_REV2) {
 778                 sc->jme_clksrc = GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC;
 779                 sc->jme_clksrc_1000 = GHC_TXOFL_CLKSRC_1000 |
 780                                       GHC_TXMAC_CLKSRC_1000;
 781         }
 782
 783         /* Reset the ethernet controller. */
 784         jme_reset(sc);
 785
 786         /* Map MSI/MSI-X vectors */
 787         jme_set_msinum(sc);
 788
 789         /* Get station address. */
 790         reg = CSR_READ_4(sc, JME_SMBCSR);
 791         if (reg & SMBCSR_EEPROM_PRESENT)
 792                 error = jme_eeprom_macaddr(sc, eaddr);
 793         if (error != 0 || (reg & SMBCSR_EEPROM_PRESENT) == 0) {
 794                 if (error != 0 && (bootverbose)) {
 795                         device_printf(dev, "ethernet hardware address "
 796                                       "not found in EEPROM.\n");
 797                 }
 798                 jme_reg_macaddr(sc, eaddr);
 799         }
 800
 801         /*
 802          * Save PHY address.
 803          * Integrated JR0211 has fixed PHY address whereas FPGA version
 804          * requires PHY probing to get correct PHY address.
 805          */
 806         if ((sc->jme_caps & JME_CAP_FPGA) == 0) {
 807                 sc->jme_phyaddr = CSR_READ_4(sc, JME_GPREG0) &
 808                     GPREG0_PHY_ADDR_MASK;
 809                 if (bootverbose) {
 810                         device_printf(dev, "PHY is at address %d.\n",
 811                             sc->jme_phyaddr);
 812                 }
 813         } else {
 814                 sc->jme_phyaddr = 0;
 815         }
 816
 817         /* Set max allowable DMA size. */
 818         pcie_ptr = pci_get_pciecap_ptr(dev);
 819         if (pcie_ptr != 0) {
 820                 uint16_t ctrl;
 821
 822                 sc->jme_caps |= JME_CAP_PCIE;
 823                 ctrl = pci_read_config(dev, pcie_ptr + PCIER_DEVCTRL, 2);
 824                 if (bootverbose) {
 825                         device_printf(dev, "Read request size : %d bytes.\n",
 826                             128 << ((ctrl >> 12) & 0x07));
 827                         device_printf(dev, "TLP payload size : %d bytes.\n",
 828                             128 << ((ctrl >> 5) & 0x07));
 829                 }
 830                 switch (ctrl & PCIEM_DEVCTL_MAX_READRQ_MASK) {
 831                 case PCIEM_DEVCTL_MAX_READRQ_128:
 832                         sc->jme_tx_dma_size = TXCSR_DMA_SIZE_128;
 833                         break;
 834                 case PCIEM_DEVCTL_MAX_READRQ_256:
 835                         sc->jme_tx_dma_size = TXCSR_DMA_SIZE_256;
 836                         break;
 837                 default:
 838                         sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
 839                         break;
 840                 }
 841                 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
 842         } else {
 843                 sc->jme_tx_dma_size = TXCSR_DMA_SIZE_512;
 844                 sc->jme_rx_dma_size = RXCSR_DMA_SIZE_128;
 845         }
 846
 847 #ifdef notyet
 848         if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0)
 849                 sc->jme_caps |= JME_CAP_PMCAP;
 850 #endif
 851
 852         /*
 853          * Create sysctl tree
 854          */
 855         jme_sysctl_node(sc);
 856
 857         /* Allocate DMA stuffs */
 858         error = jme_dma_alloc(sc);
 859         if (error)
 860                 goto fail;
 861
 862         ifp->if_softc = sc;
 863         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 864         ifp->if_init = jme_init;
 865         ifp->if_ioctl = jme_ioctl;
 866         ifp->if_start = jme_start;
 867 #ifdef DEVICE_POLLING
 868         ifp->if_poll = jme_poll;
 869 #endif
 870         ifp->if_watchdog = jme_watchdog;
 871         ifp->if_serialize = jme_serialize;
 872         ifp->if_deserialize = jme_deserialize;
 873         ifp->if_tryserialize = jme_tryserialize;
 874 #ifdef INVARIANTS
 875         ifp->if_serialize_assert = jme_serialize_assert;
 876 #endif
 877         ifq_set_maxlen(&ifp->if_snd,
 878             sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD);
 879         ifq_set_ready(&ifp->if_snd);
 880
 881         /* JMC250 supports Tx/Rx checksum offload and hardware vlan tagging. */
 882         ifp->if_capabilities = IFCAP_HWCSUM |
 883                                IFCAP_VLAN_MTU |
 884                                IFCAP_VLAN_HWTAGGING;
 885         if (sc->jme_cdata.jme_rx_ring_cnt > JME_NRXRING_MIN)
 886                 ifp->if_capabilities |= IFCAP_RSS;
 887         ifp->if_capenable = ifp->if_capabilities;
 888
 889         /*
 890          * Disable TXCSUM by default to improve bulk data
 891          * transmit performance (+20Mbps improvement).
 892          */
 893         ifp->if_capenable &= ~IFCAP_TXCSUM;
 894
 895         if (ifp->if_capenable & IFCAP_TXCSUM)
 896                 ifp->if_hwassist = JME_CSUM_FEATURES;
 897
 898         /* Set up MII bus. */
 899         error = mii_phy_probe(dev, &sc->jme_miibus,
 900                               jme_mediachange, jme_mediastatus);
 901         if (error) {
 902                 device_printf(dev, "no PHY found!\n");
 903                 goto fail;
 904         }
 905
 906         /*
 907          * Save PHYADDR for FPGA mode PHY.
 908          */
 909         if (sc->jme_caps & JME_CAP_FPGA) {
 910                 struct mii_data *mii = device_get_softc(sc->jme_miibus);
 911
 912                 if (mii->mii_instance != 0) {
 913                         struct mii_softc *miisc;
 914
 915                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list) {
 916                                 if (miisc->mii_phy != 0) {
 917                                         sc->jme_phyaddr = miisc->mii_phy;
 918                                         break;
 919                                 }
 920                         }
 921                         if (sc->jme_phyaddr != 0) {
 922                                 device_printf(sc->jme_dev,
 923                                     "FPGA PHY is at %d\n", sc->jme_phyaddr);
 924                                 /* vendor magic. */
 925                                 jme_miibus_writereg(dev, sc->jme_phyaddr,
 926                                     JMPHY_CONF, JMPHY_CONF_DEFFIFO);
 927
 928                                 /* XXX should we clear JME_WA_EXTFIFO */
 929                         }
 930                 }
 931         }
 932
 933         ether_ifattach(ifp, eaddr, NULL);
 934
 935         /* Tell the upper layer(s) we support long frames. */
 936         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
 937
 938         error = jme_intr_setup(dev);
 939         if (error) {
 940                 ether_ifdetach(ifp);
 941                 goto fail;
 942         }
 943
 944         return 0;
 945 fail:
 946         jme_detach(dev);
 947         return (error);
 948 }
 949
 950 static int
 951 jme_detach(device_t dev)
 952 {
 953         struct jme_softc *sc = device_get_softc(dev);
 954
 955         if (device_is_attached(dev)) {
 956                 struct ifnet *ifp = &sc->arpcom.ac_if;
 957
 958                 ifnet_serialize_all(ifp);
 959                 jme_stop(sc);
 960                 jme_intr_teardown(dev);
 961                 ifnet_deserialize_all(ifp);
 962
 963                 ether_ifdetach(ifp);
 964         }
 965
 966         if (sc->jme_sysctl_tree != NULL)
 967                 sysctl_ctx_free(&sc->jme_sysctl_ctx);
 968
 969         if (sc->jme_miibus != NULL)
 970                 device_delete_child(dev, sc->jme_miibus);
 971         bus_generic_detach(dev);
 972
 973         jme_intr_free(dev);
 974
 975         if (sc->jme_mem_res != NULL) {
 976                 bus_release_resource(dev, SYS_RES_MEMORY, sc->jme_mem_rid,
 977                                      sc->jme_mem_res);
 978         }
 979
 980         jme_dma_free(sc);
 981
 982         return (0);
 983 }
 984
 985 static void
 986 jme_sysctl_node(struct jme_softc *sc)
 987 {
 988         int coal_max;
 989 #ifdef JME_RSS_DEBUG
 990         int r;
 991 #endif
 992
 993         sysctl_ctx_init(&sc->jme_sysctl_ctx);
 994         sc->jme_sysctl_tree = SYSCTL_ADD_NODE(&sc->jme_sysctl_ctx,
 995                                 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
 996                                 device_get_nameunit(sc->jme_dev),
 997                                 CTLFLAG_RD, 0, "");
 998         if (sc->jme_sysctl_tree == NULL) {
 999                 device_printf(sc->jme_dev, "can't add sysctl node\n");
1000                 return;
1001         }
1002
1003         SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1004             SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1005             "tx_coal_to", CTLTYPE_INT | CTLFLAG_RW,
1006             sc, 0, jme_sysctl_tx_coal_to, "I", "jme tx coalescing timeout");
1007
1008         SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1009             SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1010             "tx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW,
1011             sc, 0, jme_sysctl_tx_coal_pkt, "I", "jme tx coalescing packet");
1012
1013         SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1014             SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1015             "rx_coal_to", CTLTYPE_INT | CTLFLAG_RW,
1016             sc, 0, jme_sysctl_rx_coal_to, "I", "jme rx coalescing timeout");
1017
1018         SYSCTL_ADD_PROC(&sc->jme_sysctl_ctx,
1019             SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1020             "rx_coal_pkt", CTLTYPE_INT | CTLFLAG_RW,
1021             sc, 0, jme_sysctl_rx_coal_pkt, "I", "jme rx coalescing packet");
1022
1023         SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1024                        SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1025                        "rx_desc_count", CTLFLAG_RD,
1026                        &sc->jme_cdata.jme_rx_data[0].jme_rx_desc_cnt,
1027                        0, "RX desc count");
1028         SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1029                        SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1030                        "tx_desc_count", CTLFLAG_RD,
1031                        &sc->jme_cdata.jme_tx_desc_cnt,
1032                        0, "TX desc count");
1033         SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1034                        SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1035                        "rx_ring_count", CTLFLAG_RD,
1036                        &sc->jme_cdata.jme_rx_ring_cnt,
1037                        0, "RX ring count");
1038 #ifdef JME_RSS_DEBUG
1039         SYSCTL_ADD_INT(&sc->jme_sysctl_ctx,
1040                        SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1041                        "rss_debug", CTLFLAG_RW, &sc->jme_rss_debug,
1042                        0, "RSS debug level");
1043         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
1044                 char rx_ring_pkt[32];
1045
1046                 ksnprintf(rx_ring_pkt, sizeof(rx_ring_pkt), "rx_ring%d_pkt", r);
1047                 SYSCTL_ADD_ULONG(&sc->jme_sysctl_ctx,
1048                     SYSCTL_CHILDREN(sc->jme_sysctl_tree), OID_AUTO,
1049                     rx_ring_pkt, CTLFLAG_RW,
1050                     &sc->jme_cdata.jme_rx_data[r].jme_rx_pkt, "RXed packets");
1051         }
1052 #endif
1053
1054         /*
1055          * Set default coalesce valves
1056          */
1057         sc->jme_tx_coal_to = PCCTX_COAL_TO_DEFAULT;
1058         sc->jme_tx_coal_pkt = PCCTX_COAL_PKT_DEFAULT;
1059         sc->jme_rx_coal_to = PCCRX_COAL_TO_DEFAULT;
1060         sc->jme_rx_coal_pkt = PCCRX_COAL_PKT_DEFAULT;
1061
1062         /*
1063          * Adjust coalesce valves, in case that the number of TX/RX
1064          * descs are set to small values by users.
1065          *
1066          * NOTE: coal_max will not be zero, since number of descs
1067          * must aligned by JME_NDESC_ALIGN (16 currently)
1068          */
1069         coal_max = sc->jme_cdata.jme_tx_desc_cnt / 6;
1070         if (coal_max < sc->jme_tx_coal_pkt)
1071                 sc->jme_tx_coal_pkt = coal_max;
1072
1073         coal_max = sc->jme_cdata.jme_rx_data[0].jme_rx_desc_cnt / 4;
1074         if (coal_max < sc->jme_rx_coal_pkt)
1075                 sc->jme_rx_coal_pkt = coal_max;
1076 }
1077
1078 static int
1079 jme_dma_alloc(struct jme_softc *sc)
1080 {
1081         struct jme_txdesc *txd;
1082         bus_dmamem_t dmem;
1083         int error, i, asize;
1084
1085         sc->jme_cdata.jme_txdesc =
1086         kmalloc(sc->jme_cdata.jme_tx_desc_cnt * sizeof(struct jme_txdesc),
1087                 M_DEVBUF, M_WAITOK | M_ZERO);
1088         for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
1089                 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[i];
1090
1091                 rdata->jme_rxdesc =
1092                 kmalloc(rdata->jme_rx_desc_cnt * sizeof(struct jme_rxdesc),
1093                         M_DEVBUF, M_WAITOK | M_ZERO);
1094         }
1095
1096         /* Create parent ring tag. */
1097         error = bus_dma_tag_create(NULL,/* parent */
1098             1, JME_RING_BOUNDARY,       /* algnmnt, boundary */
1099             sc->jme_lowaddr,            /* lowaddr */
1100             BUS_SPACE_MAXADDR,          /* highaddr */
1101             NULL, NULL,                 /* filter, filterarg */
1102             BUS_SPACE_MAXSIZE_32BIT,    /* maxsize */
1103             0,                          /* nsegments */
1104             BUS_SPACE_MAXSIZE_32BIT,    /* maxsegsize */
1105             0,                          /* flags */
1106             &sc->jme_cdata.jme_ring_tag);
1107         if (error) {
1108                 device_printf(sc->jme_dev,
1109                     "could not create parent ring DMA tag.\n");
1110                 return error;
1111         }
1112
1113         /*
1114          * Create DMA stuffs for TX ring
1115          */
1116         asize = roundup2(JME_TX_RING_SIZE(sc), JME_TX_RING_ALIGN);
1117         error = bus_dmamem_coherent(sc->jme_cdata.jme_ring_tag,
1118                         JME_TX_RING_ALIGN, 0,
1119                         BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1120                         asize, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
1121         if (error) {
1122                 device_printf(sc->jme_dev, "could not allocate Tx ring.\n");
1123                 return error;
1124         }
1125         sc->jme_cdata.jme_tx_ring_tag = dmem.dmem_tag;
1126         sc->jme_cdata.jme_tx_ring_map = dmem.dmem_map;
1127         sc->jme_cdata.jme_tx_ring = dmem.dmem_addr;
1128         sc->jme_cdata.jme_tx_ring_paddr = dmem.dmem_busaddr;
1129
1130         /*
1131          * Create DMA stuffs for RX rings
1132          */
1133         for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
1134                 error = jme_rxring_dma_alloc(&sc->jme_cdata.jme_rx_data[i]);
1135                 if (error)
1136                         return error;
1137         }
1138
1139         /* Create parent buffer tag. */
1140         error = bus_dma_tag_create(NULL,/* parent */
1141             1, 0,                       /* algnmnt, boundary */
1142             sc->jme_lowaddr,            /* lowaddr */
1143             BUS_SPACE_MAXADDR,          /* highaddr */
1144             NULL, NULL,                 /* filter, filterarg */
1145             BUS_SPACE_MAXSIZE_32BIT,    /* maxsize */
1146             0,                          /* nsegments */
1147             BUS_SPACE_MAXSIZE_32BIT,    /* maxsegsize */
1148             0,                          /* flags */
1149             &sc->jme_cdata.jme_buffer_tag);
1150         if (error) {
1151                 device_printf(sc->jme_dev,
1152                     "could not create parent buffer DMA tag.\n");
1153                 return error;
1154         }
1155
1156         /*
1157          * Create DMA stuffs for shadow status block
1158          */
1159         asize = roundup2(JME_SSB_SIZE, JME_SSB_ALIGN);
1160         error = bus_dmamem_coherent(sc->jme_cdata.jme_buffer_tag,
1161                         JME_SSB_ALIGN, 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
1162                         asize, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
1163         if (error) {
1164                 device_printf(sc->jme_dev,
1165                     "could not create shadow status block.\n");
1166                 return error;
1167         }
1168         sc->jme_cdata.jme_ssb_tag = dmem.dmem_tag;
1169         sc->jme_cdata.jme_ssb_map = dmem.dmem_map;
1170         sc->jme_cdata.jme_ssb_block = dmem.dmem_addr;
1171         sc->jme_cdata.jme_ssb_block_paddr = dmem.dmem_busaddr;
1172
1173         /*
1174          * Create DMA stuffs for TX buffers
1175          */
1176
1177         /* Create tag for Tx buffers. */
1178         error = bus_dma_tag_create(sc->jme_cdata.jme_buffer_tag,/* parent */
1179             1, 0,                       /* algnmnt, boundary */
1180             BUS_SPACE_MAXADDR,          /* lowaddr */
1181             BUS_SPACE_MAXADDR,          /* highaddr */
1182             NULL, NULL,                 /* filter, filterarg */
1183             JME_JUMBO_FRAMELEN,         /* maxsize */
1184             JME_MAXTXSEGS,              /* nsegments */
1185             JME_MAXSEGSIZE,             /* maxsegsize */
1186             BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,/* flags */
1187             &sc->jme_cdata.jme_tx_tag);
1188         if (error != 0) {
1189                 device_printf(sc->jme_dev, "could not create Tx DMA tag.\n");
1190                 return error;
1191         }
1192
1193         /* Create DMA maps for Tx buffers. */
1194         for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
1195                 txd = &sc->jme_cdata.jme_txdesc[i];
1196                 error = bus_dmamap_create(sc->jme_cdata.jme_tx_tag,
1197                                 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
1198                                 &txd->tx_dmamap);
1199                 if (error) {
1200                         int j;
1201
1202                         device_printf(sc->jme_dev,
1203                             "could not create %dth Tx dmamap.\n", i);
1204
1205                         for (j = 0; j < i; ++j) {
1206                                 txd = &sc->jme_cdata.jme_txdesc[j];
1207                                 bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag,
1208                                                    txd->tx_dmamap);
1209                         }
1210                         bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag);
1211                         sc->jme_cdata.jme_tx_tag = NULL;
1212                         return error;
1213                 }
1214         }
1215
1216         /*
1217          * Create DMA stuffs for RX buffers
1218          */
1219         for (i = 0; i < sc->jme_cdata.jme_rx_ring_cnt; ++i) {
1220                 error = jme_rxbuf_dma_alloc(&sc->jme_cdata.jme_rx_data[i]);
1221                 if (error)
1222                         return error;
1223         }
1224         return 0;
1225 }
1226
1227 static void
1228 jme_dma_free(struct jme_softc *sc)
1229 {
1230         struct jme_txdesc *txd;
1231         struct jme_rxdesc *rxd;
1232         struct jme_rxdata *rdata;
1233         int i, r;
1234
1235         /* Tx ring */
1236         if (sc->jme_cdata.jme_tx_ring_tag != NULL) {
1237                 bus_dmamap_unload(sc->jme_cdata.jme_tx_ring_tag,
1238                     sc->jme_cdata.jme_tx_ring_map);
1239                 bus_dmamem_free(sc->jme_cdata.jme_tx_ring_tag,
1240                     sc->jme_cdata.jme_tx_ring,
1241                     sc->jme_cdata.jme_tx_ring_map);
1242                 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_ring_tag);
1243                 sc->jme_cdata.jme_tx_ring_tag = NULL;
1244         }
1245
1246         /* Rx ring */
1247         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
1248                 rdata = &sc->jme_cdata.jme_rx_data[r];
1249                 if (rdata->jme_rx_ring_tag != NULL) {
1250                         bus_dmamap_unload(rdata->jme_rx_ring_tag,
1251                                           rdata->jme_rx_ring_map);
1252                         bus_dmamem_free(rdata->jme_rx_ring_tag,
1253                                         rdata->jme_rx_ring,
1254                                         rdata->jme_rx_ring_map);
1255                         bus_dma_tag_destroy(rdata->jme_rx_ring_tag);
1256                         rdata->jme_rx_ring_tag = NULL;
1257                 }
1258         }
1259
1260         /* Tx buffers */
1261         if (sc->jme_cdata.jme_tx_tag != NULL) {
1262                 for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
1263                         txd = &sc->jme_cdata.jme_txdesc[i];
1264                         bus_dmamap_destroy(sc->jme_cdata.jme_tx_tag,
1265                             txd->tx_dmamap);
1266                 }
1267                 bus_dma_tag_destroy(sc->jme_cdata.jme_tx_tag);
1268                 sc->jme_cdata.jme_tx_tag = NULL;
1269         }
1270
1271         /* Rx buffers */
1272         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
1273                 rdata = &sc->jme_cdata.jme_rx_data[r];
1274                 if (rdata->jme_rx_tag != NULL) {
1275                         for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
1276                                 rxd = &rdata->jme_rxdesc[i];
1277                                 bus_dmamap_destroy(rdata->jme_rx_tag,
1278                                                    rxd->rx_dmamap);
1279                         }
1280                         bus_dmamap_destroy(rdata->jme_rx_tag,
1281                                            rdata->jme_rx_sparemap);
1282                         bus_dma_tag_destroy(rdata->jme_rx_tag);
1283                         rdata->jme_rx_tag = NULL;
1284                 }
1285         }
1286
1287         /* Shadow status block. */
1288         if (sc->jme_cdata.jme_ssb_tag != NULL) {
1289                 bus_dmamap_unload(sc->jme_cdata.jme_ssb_tag,
1290                     sc->jme_cdata.jme_ssb_map);
1291                 bus_dmamem_free(sc->jme_cdata.jme_ssb_tag,
1292                     sc->jme_cdata.jme_ssb_block,
1293                     sc->jme_cdata.jme_ssb_map);
1294                 bus_dma_tag_destroy(sc->jme_cdata.jme_ssb_tag);
1295                 sc->jme_cdata.jme_ssb_tag = NULL;
1296         }
1297
1298         if (sc->jme_cdata.jme_buffer_tag != NULL) {
1299                 bus_dma_tag_destroy(sc->jme_cdata.jme_buffer_tag);
1300                 sc->jme_cdata.jme_buffer_tag = NULL;
1301         }
1302         if (sc->jme_cdata.jme_ring_tag != NULL) {
1303                 bus_dma_tag_destroy(sc->jme_cdata.jme_ring_tag);
1304                 sc->jme_cdata.jme_ring_tag = NULL;
1305         }
1306
1307         if (sc->jme_cdata.jme_txdesc != NULL) {
1308                 kfree(sc->jme_cdata.jme_txdesc, M_DEVBUF);
1309                 sc->jme_cdata.jme_txdesc = NULL;
1310         }
1311         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
1312                 rdata = &sc->jme_cdata.jme_rx_data[r];
1313                 if (rdata->jme_rxdesc != NULL) {
1314                         kfree(rdata->jme_rxdesc, M_DEVBUF);
1315                         rdata->jme_rxdesc = NULL;
1316                 }
1317         }
1318 }
1319
1320 /*
1321  *      Make sure the interface is stopped at reboot time.
1322  */
1323 static int
1324 jme_shutdown(device_t dev)
1325 {
1326         return jme_suspend(dev);
1327 }
1328
1329 #ifdef notyet
1330 /*
1331  * Unlike other ethernet controllers, JMC250 requires
1332  * explicit resetting link speed to 10/100Mbps as gigabit
1333  * link will cunsume more power than 375mA.
1334  * Note, we reset the link speed to 10/100Mbps with
1335  * auto-negotiation but we don't know whether that operation
1336  * would succeed or not as we have no control after powering
1337  * off. If the renegotiation fail WOL may not work. Running
1338  * at 1Gbps draws more power than 375mA at 3.3V which is
1339  * specified in PCI specification and that would result in
1340  * complete shutdowning power to ethernet controller.
1341  *
1342  * TODO
1343  *  Save current negotiated media speed/duplex/flow-control
1344  *  to softc and restore the same link again after resuming.
1345  *  PHY handling such as power down/resetting to 100Mbps
1346  *  may be better handled in suspend method in phy driver.
1347  */
1348 static void
1349 jme_setlinkspeed(struct jme_softc *sc)
1350 {
1351         struct mii_data *mii;
1352         int aneg, i;
1353
1354         JME_LOCK_ASSERT(sc);
1355
1356         mii = device_get_softc(sc->jme_miibus);
1357         mii_pollstat(mii);
1358         aneg = 0;
1359         if ((mii->mii_media_status & IFM_AVALID) != 0) {
1360                 switch IFM_SUBTYPE(mii->mii_media_active) {
1361                 case IFM_10_T:
1362                 case IFM_100_TX:
1363                         return;
1364                 case IFM_1000_T:
1365                         aneg++;
1366                 default:
1367                         break;
1368                 }
1369         }
1370         jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_100T2CR, 0);
1371         jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_ANAR,
1372             ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
1373         jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr, MII_BMCR,
1374             BMCR_AUTOEN | BMCR_STARTNEG);
1375         DELAY(1000);
1376         if (aneg != 0) {
1377                 /* Poll link state until jme(4) get a 10/100 link. */
1378                 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1379                         mii_pollstat(mii);
1380                         if ((mii->mii_media_status & IFM_AVALID) != 0) {
1381                                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
1382                                 case IFM_10_T:
1383                                 case IFM_100_TX:
1384                                         jme_mac_config(sc);
1385                                         return;
1386                                 default:
1387                                         break;
1388                                 }
1389                         }
1390                         JME_UNLOCK(sc);
1391                         pause("jmelnk", hz);
1392                         JME_LOCK(sc);
1393                 }
1394                 if (i == MII_ANEGTICKS_GIGE)
1395                         device_printf(sc->jme_dev, "establishing link failed, "
1396                             "WOL may not work!");
1397         }
1398         /*
1399          * No link, force MAC to have 100Mbps, full-duplex link.
1400          * This is the last resort and may/may not work.
1401          */
1402         mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1403         mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1404         jme_mac_config(sc);
1405 }
1406
1407 static void
1408 jme_setwol(struct jme_softc *sc)
1409 {
1410         struct ifnet *ifp = &sc->arpcom.ac_if;
1411         uint32_t gpr, pmcs;
1412         uint16_t pmstat;
1413         int pmc;
1414
1415         if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1416                 /* No PME capability, PHY power down. */
1417                 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1418                     MII_BMCR, BMCR_PDOWN);
1419                 return;
1420         }
1421
1422         gpr = CSR_READ_4(sc, JME_GPREG0) & ~GPREG0_PME_ENB;
1423         pmcs = CSR_READ_4(sc, JME_PMCS);
1424         pmcs &= ~PMCS_WOL_ENB_MASK;
1425         if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) {
1426                 pmcs |= PMCS_MAGIC_FRAME | PMCS_MAGIC_FRAME_ENB;
1427                 /* Enable PME message. */
1428                 gpr |= GPREG0_PME_ENB;
1429                 /* For gigabit controllers, reset link speed to 10/100. */
1430                 if ((sc->jme_caps & JME_CAP_FASTETH) == 0)
1431                         jme_setlinkspeed(sc);
1432         }
1433
1434         CSR_WRITE_4(sc, JME_PMCS, pmcs);
1435         CSR_WRITE_4(sc, JME_GPREG0, gpr);
1436
1437         /* Request PME. */
1438         pmstat = pci_read_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, 2);
1439         pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1440         if ((ifp->if_capenable & IFCAP_WOL) != 0)
1441                 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1442         pci_write_config(sc->jme_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1443         if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1444                 /* No WOL, PHY power down. */
1445                 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1446                     MII_BMCR, BMCR_PDOWN);
1447         }
1448 }
1449 #endif
1450
1451 static int
1452 jme_suspend(device_t dev)
1453 {
1454         struct jme_softc *sc = device_get_softc(dev);
1455         struct ifnet *ifp = &sc->arpcom.ac_if;
1456
1457         ifnet_serialize_all(ifp);
1458         jme_stop(sc);
1459 #ifdef notyet
1460         jme_setwol(sc);
1461 #endif
1462         ifnet_deserialize_all(ifp);
1463
1464         return (0);
1465 }
1466
1467 static int
1468 jme_resume(device_t dev)
1469 {
1470         struct jme_softc *sc = device_get_softc(dev);
1471         struct ifnet *ifp = &sc->arpcom.ac_if;
1472 #ifdef notyet
1473         int pmc;
1474 #endif
1475
1476         ifnet_serialize_all(ifp);
1477
1478 #ifdef notyet
1479         if (pci_find_extcap(sc->jme_dev, PCIY_PMG, &pmc) != 0) {
1480                 uint16_t pmstat;
1481
1482                 pmstat = pci_read_config(sc->jme_dev,
1483                     pmc + PCIR_POWER_STATUS, 2);
1484                 /* Disable PME clear PME status. */
1485                 pmstat &= ~PCIM_PSTAT_PMEENABLE;
1486                 pci_write_config(sc->jme_dev,
1487                     pmc + PCIR_POWER_STATUS, pmstat, 2);
1488         }
1489 #endif
1490
1491         if (ifp->if_flags & IFF_UP)
1492                 jme_init(sc);
1493
1494         ifnet_deserialize_all(ifp);
1495
1496         return (0);
1497 }
1498
1499 static int
1500 jme_encap(struct jme_softc *sc, struct mbuf **m_head)
1501 {
1502         struct jme_txdesc *txd;
1503         struct jme_desc *desc;
1504         struct mbuf *m;
1505         bus_dma_segment_t txsegs[JME_MAXTXSEGS];
1506         int maxsegs, nsegs;
1507         int error, i, prod, symbol_desc;
1508         uint32_t cflags, flag64;
1509
1510         M_ASSERTPKTHDR((*m_head));
1511
1512         prod = sc->jme_cdata.jme_tx_prod;
1513         txd = &sc->jme_cdata.jme_txdesc[prod];
1514
1515         if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT)
1516                 symbol_desc = 1;
1517         else
1518                 symbol_desc = 0;
1519
1520         maxsegs = (sc->jme_cdata.jme_tx_desc_cnt - sc->jme_cdata.jme_tx_cnt) -
1521                   (JME_TXD_RSVD + symbol_desc);
1522         if (maxsegs > JME_MAXTXSEGS)
1523                 maxsegs = JME_MAXTXSEGS;
1524         KASSERT(maxsegs >= (sc->jme_txd_spare - symbol_desc),
1525                 ("not enough segments %d", maxsegs));
1526
1527         error = bus_dmamap_load_mbuf_defrag(sc->jme_cdata.jme_tx_tag,
1528                         txd->tx_dmamap, m_head,
1529                         txsegs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1530         if (error)
1531                 goto fail;
1532
1533         bus_dmamap_sync(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap,
1534                         BUS_DMASYNC_PREWRITE);
1535
1536         m = *m_head;
1537         cflags = 0;
1538
1539         /* Configure checksum offload. */
1540         if (m->m_pkthdr.csum_flags & CSUM_IP)
1541                 cflags |= JME_TD_IPCSUM;
1542         if (m->m_pkthdr.csum_flags & CSUM_TCP)
1543                 cflags |= JME_TD_TCPCSUM;
1544         if (m->m_pkthdr.csum_flags & CSUM_UDP)
1545                 cflags |= JME_TD_UDPCSUM;
1546
1547         /* Configure VLAN. */
1548         if (m->m_flags & M_VLANTAG) {
1549                 cflags |= (m->m_pkthdr.ether_vlantag & JME_TD_VLAN_MASK);
1550                 cflags |= JME_TD_VLAN_TAG;
1551         }
1552
1553         desc = &sc->jme_cdata.jme_tx_ring[prod];
1554         desc->flags = htole32(cflags);
1555         desc->addr_hi = htole32(m->m_pkthdr.len);
1556         if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT) {
1557                 /*
1558                  * Use 64bits TX desc chain format.
1559                  *
1560                  * The first TX desc of the chain, which is setup here,
1561                  * is just a symbol TX desc carrying no payload.
1562                  */
1563                 flag64 = JME_TD_64BIT;
1564                 desc->buflen = 0;
1565                 desc->addr_lo = 0;
1566
1567                 /* No effective TX desc is consumed */
1568                 i = 0;
1569         } else {
1570                 /*
1571                  * Use 32bits TX desc chain format.
1572                  *
1573                  * The first TX desc of the chain, which is setup here,
1574                  * is an effective TX desc carrying the first segment of
1575                  * the mbuf chain.
1576                  */
1577                 flag64 = 0;
1578                 desc->buflen = htole32(txsegs[0].ds_len);
1579                 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[0].ds_addr));
1580
1581                 /* One effective TX desc is consumed */
1582                 i = 1;
1583         }
1584         sc->jme_cdata.jme_tx_cnt++;
1585         KKASSERT(sc->jme_cdata.jme_tx_cnt - i <
1586                  sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD);
1587         JME_DESC_INC(prod, sc->jme_cdata.jme_tx_desc_cnt);
1588
1589         txd->tx_ndesc = 1 - i;
1590         for (; i < nsegs; i++) {
1591                 desc = &sc->jme_cdata.jme_tx_ring[prod];
1592                 desc->buflen = htole32(txsegs[i].ds_len);
1593                 desc->addr_hi = htole32(JME_ADDR_HI(txsegs[i].ds_addr));
1594                 desc->addr_lo = htole32(JME_ADDR_LO(txsegs[i].ds_addr));
1595                 desc->flags = htole32(JME_TD_OWN | flag64);
1596
1597                 sc->jme_cdata.jme_tx_cnt++;
1598                 KKASSERT(sc->jme_cdata.jme_tx_cnt <=
1599                          sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD);
1600                 JME_DESC_INC(prod, sc->jme_cdata.jme_tx_desc_cnt);
1601         }
1602
1603         /* Update producer index. */
1604         sc->jme_cdata.jme_tx_prod = prod;
1605         /*
1606          * Finally request interrupt and give the first descriptor
1607          * owenership to hardware.
1608          */
1609         desc = txd->tx_desc;
1610         desc->flags |= htole32(JME_TD_OWN | JME_TD_INTR);
1611
1612         txd->tx_m = m;
1613         txd->tx_ndesc += nsegs;
1614
1615         return 0;
1616 fail:
1617         m_freem(*m_head);
1618         *m_head = NULL;
1619         return error;
1620 }
1621
1622 static void
1623 jme_start(struct ifnet *ifp)
1624 {
1625         struct jme_softc *sc = ifp->if_softc;
1626         struct mbuf *m_head;
1627         int enq = 0;
1628
1629         ASSERT_SERIALIZED(&sc->jme_cdata.jme_tx_serialize);
1630
1631         if ((sc->jme_flags & JME_FLAG_LINK) == 0) {
1632                 ifq_purge(&ifp->if_snd);
1633                 return;
1634         }
1635
1636         if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
1637                 return;
1638
1639         if (sc->jme_cdata.jme_tx_cnt >= JME_TX_DESC_HIWAT(sc))
1640                 jme_txeof(sc);
1641
1642         while (!ifq_is_empty(&ifp->if_snd)) {
1643                 /*
1644                  * Check number of available TX descs, always
1645                  * leave JME_TXD_RSVD free TX descs.
1646                  */
1647                 if (sc->jme_cdata.jme_tx_cnt + sc->jme_txd_spare >
1648                     sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD) {
1649                         ifp->if_flags |= IFF_OACTIVE;
1650                         break;
1651                 }
1652
1653                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1654                 if (m_head == NULL)
1655                         break;
1656
1657                 /*
1658                  * Pack the data into the transmit ring. If we
1659                  * don't have room, set the OACTIVE flag and wait
1660                  * for the NIC to drain the ring.
1661                  */
1662                 if (jme_encap(sc, &m_head)) {
1663                         KKASSERT(m_head == NULL);
1664                         ifp->if_oerrors++;
1665                         ifp->if_flags |= IFF_OACTIVE;
1666                         break;
1667                 }
1668                 enq++;
1669
1670                 /*
1671                  * If there's a BPF listener, bounce a copy of this frame
1672                  * to him.
1673                  */
1674                 ETHER_BPF_MTAP(ifp, m_head);
1675         }
1676
1677         if (enq > 0) {
1678                 /*
1679                  * Reading TXCSR takes very long time under heavy load
1680                  * so cache TXCSR value and writes the ORed value with
1681                  * the kick command to the TXCSR. This saves one register
1682                  * access cycle.
1683                  */
1684                 CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr | TXCSR_TX_ENB |
1685                     TXCSR_TXQ_N_START(TXCSR_TXQ0));
1686                 /* Set a timeout in case the chip goes out to lunch. */
1687                 ifp->if_timer = JME_TX_TIMEOUT;
1688         }
1689 }
1690
1691 static void
1692 jme_watchdog(struct ifnet *ifp)
1693 {
1694         struct jme_softc *sc = ifp->if_softc;
1695
1696         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1697
1698         if ((sc->jme_flags & JME_FLAG_LINK) == 0) {
1699                 if_printf(ifp, "watchdog timeout (missed link)\n");
1700                 ifp->if_oerrors++;
1701                 jme_init(sc);
1702                 return;
1703         }
1704
1705         jme_txeof(sc);
1706         if (sc->jme_cdata.jme_tx_cnt == 0) {
1707                 if_printf(ifp, "watchdog timeout (missed Tx interrupts) "
1708                           "-- recovering\n");
1709                 if (!ifq_is_empty(&ifp->if_snd))
1710                         if_devstart(ifp);
1711                 return;
1712         }
1713
1714         if_printf(ifp, "watchdog timeout\n");
1715         ifp->if_oerrors++;
1716         jme_init(sc);
1717         if (!ifq_is_empty(&ifp->if_snd))
1718                 if_devstart(ifp);
1719 }
1720
1721 static int
1722 jme_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
1723 {
1724         struct jme_softc *sc = ifp->if_softc;
1725         struct mii_data *mii = device_get_softc(sc->jme_miibus);
1726         struct ifreq *ifr = (struct ifreq *)data;
1727         int error = 0, mask;
1728
1729         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1730
1731         switch (cmd) {
1732         case SIOCSIFMTU:
1733                 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > JME_JUMBO_MTU ||
1734                     (!(sc->jme_caps & JME_CAP_JUMBO) &&
1735                      ifr->ifr_mtu > JME_MAX_MTU)) {
1736                         error = EINVAL;
1737                         break;
1738                 }
1739
1740                 if (ifp->if_mtu != ifr->ifr_mtu) {
1741                         /*
1742                          * No special configuration is required when interface
1743                          * MTU is changed but availability of Tx checksum
1744                          * offload should be chcked against new MTU size as
1745                          * FIFO size is just 2K.
1746                          */
1747                         if (ifr->ifr_mtu >= JME_TX_FIFO_SIZE) {
1748                                 ifp->if_capenable &= ~IFCAP_TXCSUM;
1749                                 ifp->if_hwassist &= ~JME_CSUM_FEATURES;
1750                         }
1751                         ifp->if_mtu = ifr->ifr_mtu;
1752                         if (ifp->if_flags & IFF_RUNNING)
1753                                 jme_init(sc);
1754                 }
1755                 break;
1756
1757         case SIOCSIFFLAGS:
1758                 if (ifp->if_flags & IFF_UP) {
1759                         if (ifp->if_flags & IFF_RUNNING) {
1760                                 if ((ifp->if_flags ^ sc->jme_if_flags) &
1761                                     (IFF_PROMISC | IFF_ALLMULTI))
1762                                         jme_set_filter(sc);
1763                         } else {
1764                                 jme_init(sc);
1765                         }
1766                 } else {
1767                         if (ifp->if_flags & IFF_RUNNING)
1768                                 jme_stop(sc);
1769                 }
1770                 sc->jme_if_flags = ifp->if_flags;
1771                 break;
1772
1773         case SIOCADDMULTI:
1774         case SIOCDELMULTI:
1775                 if (ifp->if_flags & IFF_RUNNING)
1776                         jme_set_filter(sc);
1777                 break;
1778
1779         case SIOCSIFMEDIA:
1780         case SIOCGIFMEDIA:
1781                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1782                 break;
1783
1784         case SIOCSIFCAP:
1785                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1786
1787                 if ((mask & IFCAP_TXCSUM) && ifp->if_mtu < JME_TX_FIFO_SIZE) {
1788                         ifp->if_capenable ^= IFCAP_TXCSUM;
1789                         if (IFCAP_TXCSUM & ifp->if_capenable)
1790                                 ifp->if_hwassist |= JME_CSUM_FEATURES;
1791                         else
1792                                 ifp->if_hwassist &= ~JME_CSUM_FEATURES;
1793                 }
1794                 if (mask & IFCAP_RXCSUM) {
1795                         uint32_t reg;
1796
1797                         ifp->if_capenable ^= IFCAP_RXCSUM;
1798                         reg = CSR_READ_4(sc, JME_RXMAC);
1799                         reg &= ~RXMAC_CSUM_ENB;
1800                         if (ifp->if_capenable & IFCAP_RXCSUM)
1801                                 reg |= RXMAC_CSUM_ENB;
1802                         CSR_WRITE_4(sc, JME_RXMAC, reg);
1803                 }
1804
1805                 if (mask & IFCAP_VLAN_HWTAGGING) {
1806                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1807                         jme_set_vlan(sc);
1808                 }
1809
1810                 if (mask & IFCAP_RSS)
1811                         ifp->if_capenable ^= IFCAP_RSS;
1812                 break;
1813
1814         default:
1815                 error = ether_ioctl(ifp, cmd, data);
1816                 break;
1817         }
1818         return (error);
1819 }
1820
1821 static void
1822 jme_mac_config(struct jme_softc *sc)
1823 {
1824         struct mii_data *mii;
1825         uint32_t ghc, rxmac, txmac, txpause, gp1;
1826         int phyconf = JMPHY_CONF_DEFFIFO, hdx = 0;
1827
1828         mii = device_get_softc(sc->jme_miibus);
1829
1830         CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
1831         DELAY(10);
1832         CSR_WRITE_4(sc, JME_GHC, 0);
1833         ghc = 0;
1834         rxmac = CSR_READ_4(sc, JME_RXMAC);
1835         rxmac &= ~RXMAC_FC_ENB;
1836         txmac = CSR_READ_4(sc, JME_TXMAC);
1837         txmac &= ~(TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST);
1838         txpause = CSR_READ_4(sc, JME_TXPFC);
1839         txpause &= ~TXPFC_PAUSE_ENB;
1840         if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1841                 ghc |= GHC_FULL_DUPLEX;
1842                 rxmac &= ~RXMAC_COLL_DET_ENB;
1843                 txmac &= ~(TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE |
1844                     TXMAC_BACKOFF | TXMAC_CARRIER_EXT |
1845                     TXMAC_FRAME_BURST);
1846 #ifdef notyet
1847                 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1848                         txpause |= TXPFC_PAUSE_ENB;
1849                 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1850                         rxmac |= RXMAC_FC_ENB;
1851 #endif
1852                 /* Disable retry transmit timer/retry limit. */
1853                 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) &
1854                     ~(TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB));
1855         } else {
1856                 rxmac |= RXMAC_COLL_DET_ENB;
1857                 txmac |= TXMAC_COLL_ENB | TXMAC_CARRIER_SENSE | TXMAC_BACKOFF;
1858                 /* Enable retry transmit timer/retry limit. */
1859                 CSR_WRITE_4(sc, JME_TXTRHD, CSR_READ_4(sc, JME_TXTRHD) |
1860                     TXTRHD_RT_PERIOD_ENB | TXTRHD_RT_LIMIT_ENB);
1861         }
1862
1863         /*
1864          * Reprogram Tx/Rx MACs with resolved speed/duplex.
1865          */
1866         gp1 = CSR_READ_4(sc, JME_GPREG1);
1867         gp1 &= ~GPREG1_WA_HDX;
1868
1869         if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) == 0)
1870                 hdx = 1;
1871
1872         switch (IFM_SUBTYPE(mii->mii_media_active)) {
1873         case IFM_10_T:
1874                 ghc |= GHC_SPEED_10 | sc->jme_clksrc;
1875                 if (hdx)
1876                         gp1 |= GPREG1_WA_HDX;
1877                 break;
1878
1879         case IFM_100_TX:
1880                 ghc |= GHC_SPEED_100 | sc->jme_clksrc;
1881                 if (hdx)
1882                         gp1 |= GPREG1_WA_HDX;
1883
1884                 /*
1885                  * Use extended FIFO depth to workaround CRC errors
1886                  * emitted by chips before JMC250B
1887                  */
1888                 phyconf = JMPHY_CONF_EXTFIFO;
1889                 break;
1890
1891         case IFM_1000_T:
1892                 if (sc->jme_caps & JME_CAP_FASTETH)
1893                         break;
1894
1895                 ghc |= GHC_SPEED_1000 | sc->jme_clksrc_1000;
1896                 if (hdx)
1897                         txmac |= TXMAC_CARRIER_EXT | TXMAC_FRAME_BURST;
1898                 break;
1899
1900         default:
1901                 break;
1902         }
1903         CSR_WRITE_4(sc, JME_GHC, ghc);
1904         CSR_WRITE_4(sc, JME_RXMAC, rxmac);
1905         CSR_WRITE_4(sc, JME_TXMAC, txmac);
1906         CSR_WRITE_4(sc, JME_TXPFC, txpause);
1907
1908         if (sc->jme_workaround & JME_WA_EXTFIFO) {
1909                 jme_miibus_writereg(sc->jme_dev, sc->jme_phyaddr,
1910                                     JMPHY_CONF, phyconf);
1911         }
1912         if (sc->jme_workaround & JME_WA_HDX)
1913                 CSR_WRITE_4(sc, JME_GPREG1, gp1);
1914 }
1915
1916 static void
1917 jme_intr(void *xsc)
1918 {
1919         struct jme_softc *sc = xsc;
1920         struct ifnet *ifp = &sc->arpcom.ac_if;
1921         uint32_t status;
1922         int r;
1923
1924         ASSERT_SERIALIZED(&sc->jme_serialize);
1925
1926         status = CSR_READ_4(sc, JME_INTR_REQ_STATUS);
1927         if (status == 0 || status == 0xFFFFFFFF)
1928                 return;
1929
1930         /* Disable interrupts. */
1931         CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
1932
1933         status = CSR_READ_4(sc, JME_INTR_STATUS);
1934         if ((status & JME_INTRS) == 0 || status == 0xFFFFFFFF)
1935                 goto back;
1936
1937         /* Reset PCC counter/timer and Ack interrupts. */
1938         status &= ~(INTR_TXQ_COMP | INTR_RXQ_COMP);
1939
1940         if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO))
1941                 status |= INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP;
1942
1943         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
1944                 if (status & jme_rx_status[r].jme_coal) {
1945                         status |= jme_rx_status[r].jme_coal |
1946                                   jme_rx_status[r].jme_comp;
1947                 }
1948         }
1949
1950         CSR_WRITE_4(sc, JME_INTR_STATUS, status);
1951
1952         if (ifp->if_flags & IFF_RUNNING) {
1953                 if (status & (INTR_RXQ_COAL | INTR_RXQ_COAL_TO))
1954                         jme_rx_intr(sc, status);
1955
1956                 if (status & INTR_RXQ_DESC_EMPTY) {
1957                         /*
1958                          * Notify hardware availability of new Rx buffers.
1959                          * Reading RXCSR takes very long time under heavy
1960                          * load so cache RXCSR value and writes the ORed
1961                          * value with the kick command to the RXCSR. This
1962                          * saves one register access cycle.
1963                          */
1964                         CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
1965                             RXCSR_RX_ENB | RXCSR_RXQ_START);
1966                 }
1967
1968                 if (status & (INTR_TXQ_COAL | INTR_TXQ_COAL_TO)) {
1969                         lwkt_serialize_enter(&sc->jme_cdata.jme_tx_serialize);
1970                         jme_txeof(sc);
1971                         if (!ifq_is_empty(&ifp->if_snd))
1972                                 if_devstart(ifp);
1973                         lwkt_serialize_exit(&sc->jme_cdata.jme_tx_serialize);
1974                 }
1975         }
1976 back:
1977         /* Reenable interrupts. */
1978         CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
1979 }
1980
1981 static void
1982 jme_txeof(struct jme_softc *sc)
1983 {
1984         struct ifnet *ifp = &sc->arpcom.ac_if;
1985         struct jme_txdesc *txd;
1986         uint32_t status;
1987         int cons, nsegs;
1988
1989         cons = sc->jme_cdata.jme_tx_cons;
1990         if (cons == sc->jme_cdata.jme_tx_prod)
1991                 return;
1992
1993         /*
1994          * Go through our Tx list and free mbufs for those
1995          * frames which have been transmitted.
1996          */
1997         while (cons != sc->jme_cdata.jme_tx_prod) {
1998                 txd = &sc->jme_cdata.jme_txdesc[cons];
1999                 KASSERT(txd->tx_m != NULL,
2000                         ("%s: freeing NULL mbuf!", __func__));
2001
2002                 status = le32toh(txd->tx_desc->flags);
2003                 if ((status & JME_TD_OWN) == JME_TD_OWN)
2004                         break;
2005
2006                 if (status & (JME_TD_TMOUT | JME_TD_RETRY_EXP)) {
2007                         ifp->if_oerrors++;
2008                 } else {
2009                         ifp->if_opackets++;
2010                         if (status & JME_TD_COLLISION) {
2011                                 ifp->if_collisions +=
2012                                     le32toh(txd->tx_desc->buflen) &
2013                                     JME_TD_BUF_LEN_MASK;
2014                         }
2015                 }
2016
2017                 /*
2018                  * Only the first descriptor of multi-descriptor
2019                  * transmission is updated so driver have to skip entire
2020                  * chained buffers for the transmiited frame. In other
2021                  * words, JME_TD_OWN bit is valid only at the first
2022                  * descriptor of a multi-descriptor transmission.
2023                  */
2024                 for (nsegs = 0; nsegs < txd->tx_ndesc; nsegs++) {
2025                         sc->jme_cdata.jme_tx_ring[cons].flags = 0;
2026                         JME_DESC_INC(cons, sc->jme_cdata.jme_tx_desc_cnt);
2027                 }
2028
2029                 /* Reclaim transferred mbufs. */
2030                 bus_dmamap_unload(sc->jme_cdata.jme_tx_tag, txd->tx_dmamap);
2031                 m_freem(txd->tx_m);
2032                 txd->tx_m = NULL;
2033                 sc->jme_cdata.jme_tx_cnt -= txd->tx_ndesc;
2034                 KASSERT(sc->jme_cdata.jme_tx_cnt >= 0,
2035                         ("%s: Active Tx desc counter was garbled", __func__));
2036                 txd->tx_ndesc = 0;
2037         }
2038         sc->jme_cdata.jme_tx_cons = cons;
2039
2040         if (sc->jme_cdata.jme_tx_cnt == 0)
2041                 ifp->if_timer = 0;
2042
2043         if (sc->jme_cdata.jme_tx_cnt + sc->jme_txd_spare <=
2044             sc->jme_cdata.jme_tx_desc_cnt - JME_TXD_RSVD)
2045                 ifp->if_flags &= ~IFF_OACTIVE;
2046 }
2047
2048 static __inline void
2049 jme_discard_rxbufs(struct jme_rxdata *rdata, int cons, int count)
2050 {
2051         int i;
2052
2053         for (i = 0; i < count; ++i) {
2054                 struct jme_desc *desc = &rdata->jme_rx_ring[cons];
2055
2056                 desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT);
2057                 desc->buflen = htole32(MCLBYTES);
2058                 JME_DESC_INC(cons, rdata->jme_rx_desc_cnt);
2059         }
2060 }
2061
2062 static __inline struct pktinfo *
2063 jme_pktinfo(struct pktinfo *pi, uint32_t flags)
2064 {
2065         if (flags & JME_RD_IPV4)
2066                 pi->pi_netisr = NETISR_IP;
2067         else if (flags & JME_RD_IPV6)
2068                 pi->pi_netisr = NETISR_IPV6;
2069         else
2070                 return NULL;
2071
2072         pi->pi_flags = 0;
2073         pi->pi_l3proto = IPPROTO_UNKNOWN;
2074
2075         if (flags & JME_RD_MORE_FRAG)
2076                 pi->pi_flags |= PKTINFO_FLAG_FRAG;
2077         else if (flags & JME_RD_TCP)
2078                 pi->pi_l3proto = IPPROTO_TCP;
2079         else if (flags & JME_RD_UDP)
2080                 pi->pi_l3proto = IPPROTO_UDP;
2081         else
2082                 pi = NULL;
2083         return pi;
2084 }
2085
2086 /* Receive a frame. */
2087 static void
2088 jme_rxpkt(struct jme_rxdata *rdata)
2089 {
2090         struct ifnet *ifp = &rdata->jme_sc->arpcom.ac_if;
2091         struct jme_desc *desc;
2092         struct jme_rxdesc *rxd;
2093         struct mbuf *mp, *m;
2094         uint32_t flags, status, hash, hashinfo;
2095         int cons, count, nsegs;
2096
2097         cons = rdata->jme_rx_cons;
2098         desc = &rdata->jme_rx_ring[cons];
2099         flags = le32toh(desc->flags);
2100         status = le32toh(desc->buflen);
2101         hash = le32toh(desc->addr_hi);
2102         hashinfo = le32toh(desc->addr_lo);
2103         nsegs = JME_RX_NSEGS(status);
2104
2105         JME_RSS_DPRINTF(rdata->jme_sc, 15, "ring%d, flags 0x%08x, "
2106                         "hash 0x%08x, hash info 0x%08x\n",
2107                         rdata->jme_rx_idx, flags, hash, hashinfo);
2108
2109         if (status & JME_RX_ERR_STAT) {
2110                 ifp->if_ierrors++;
2111                 jme_discard_rxbufs(rdata, cons, nsegs);
2112 #ifdef JME_SHOW_ERRORS
2113                 if_printf(ifp, "%s : receive error = 0x%b\n",
2114                     __func__, JME_RX_ERR(status), JME_RX_ERR_BITS);
2115 #endif
2116                 rdata->jme_rx_cons += nsegs;
2117                 rdata->jme_rx_cons %= rdata->jme_rx_desc_cnt;
2118                 return;
2119         }
2120
2121         rdata->jme_rxlen = JME_RX_BYTES(status) - JME_RX_PAD_BYTES;
2122         for (count = 0; count < nsegs; count++,
2123              JME_DESC_INC(cons, rdata->jme_rx_desc_cnt)) {
2124                 rxd = &rdata->jme_rxdesc[cons];
2125                 mp = rxd->rx_m;
2126
2127                 /* Add a new receive buffer to the ring. */
2128                 if (jme_newbuf(rdata, rxd, 0) != 0) {
2129                         ifp->if_iqdrops++;
2130                         /* Reuse buffer. */
2131                         jme_discard_rxbufs(rdata, cons, nsegs - count);
2132                         if (rdata->jme_rxhead != NULL) {
2133                                 m_freem(rdata->jme_rxhead);
2134                                 JME_RXCHAIN_RESET(rdata);
2135                         }
2136                         break;
2137                 }
2138
2139                 /*
2140                  * Assume we've received a full sized frame.
2141                  * Actual size is fixed when we encounter the end of
2142                  * multi-segmented frame.
2143                  */
2144                 mp->m_len = MCLBYTES;
2145
2146                 /* Chain received mbufs. */
2147                 if (rdata->jme_rxhead == NULL) {
2148                         rdata->jme_rxhead = mp;
2149                         rdata->jme_rxtail = mp;
2150                 } else {
2151                         /*
2152                          * Receive processor can receive a maximum frame
2153                          * size of 65535 bytes.
2154                          */
2155                         rdata->jme_rxtail->m_next = mp;
2156                         rdata->jme_rxtail = mp;
2157                 }
2158
2159                 if (count == nsegs - 1) {
2160                         struct pktinfo pi0, *pi;
2161
2162                         /* Last desc. for this frame. */
2163                         m = rdata->jme_rxhead;
2164                         m->m_pkthdr.len = rdata->jme_rxlen;
2165                         if (nsegs > 1) {
2166                                 /* Set first mbuf size. */
2167                                 m->m_len = MCLBYTES - JME_RX_PAD_BYTES;
2168                                 /* Set last mbuf size. */
2169                                 mp->m_len = rdata->jme_rxlen -
2170                                     ((MCLBYTES - JME_RX_PAD_BYTES) +
2171                                     (MCLBYTES * (nsegs - 2)));
2172                         } else {
2173                                 m->m_len = rdata->jme_rxlen;
2174                         }
2175                         m->m_pkthdr.rcvif = ifp;
2176
2177                         /*
2178                          * Account for 10bytes auto padding which is used
2179                          * to align IP header on 32bit boundary. Also note,
2180                          * CRC bytes is automatically removed by the
2181                          * hardware.
2182                          */
2183                         m->m_data += JME_RX_PAD_BYTES;
2184
2185                         /* Set checksum information. */
2186                         if ((ifp->if_capenable & IFCAP_RXCSUM) &&
2187                             (flags & JME_RD_IPV4)) {
2188                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2189                                 if (flags & JME_RD_IPCSUM)
2190                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2191                                 if ((flags & JME_RD_MORE_FRAG) == 0 &&
2192                                     ((flags & (JME_RD_TCP | JME_RD_TCPCSUM)) ==
2193                                      (JME_RD_TCP | JME_RD_TCPCSUM) ||
2194                                      (flags & (JME_RD_UDP | JME_RD_UDPCSUM)) ==
2195                                      (JME_RD_UDP | JME_RD_UDPCSUM))) {
2196                                         m->m_pkthdr.csum_flags |=
2197                                             CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2198                                         m->m_pkthdr.csum_data = 0xffff;
2199                                 }
2200                         }
2201
2202                         /* Check for VLAN tagged packets. */
2203                         if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) &&
2204                             (flags & JME_RD_VLAN_TAG)) {
2205                                 m->m_pkthdr.ether_vlantag =
2206                                     flags & JME_RD_VLAN_MASK;
2207                                 m->m_flags |= M_VLANTAG;
2208                         }
2209
2210                         ifp->if_ipackets++;
2211
2212                         if (ifp->if_capenable & IFCAP_RSS)
2213                                 pi = jme_pktinfo(&pi0, flags);
2214                         else
2215                                 pi = NULL;
2216
2217                         if (pi != NULL &&
2218                             (hashinfo & JME_RD_HASH_FN_MASK) != 0) {
2219                                 m->m_flags |= M_HASH;
2220                                 m->m_pkthdr.hash = toeplitz_hash(hash);
2221                         }
2222
2223 #ifdef JME_RSS_DEBUG
2224                         if (pi != NULL) {
2225                                 JME_RSS_DPRINTF(rdata->jme_sc, 10,
2226                                     "isr %d flags %08x, l3 %d %s\n",
2227                                     pi->pi_netisr, pi->pi_flags,
2228                                     pi->pi_l3proto,
2229                                     (m->m_flags & M_HASH) ? "hash" : "");
2230                         }
2231 #endif
2232
2233                         /* Pass it on. */
2234                         ether_input_pkt(ifp, m, pi);
2235
2236                         /* Reset mbuf chains. */
2237                         JME_RXCHAIN_RESET(rdata);
2238 #ifdef JME_RSS_DEBUG
2239                         rdata->jme_rx_pkt++;
2240 #endif
2241                 }
2242         }
2243
2244         rdata->jme_rx_cons += nsegs;
2245         rdata->jme_rx_cons %= rdata->jme_rx_desc_cnt;
2246 }
2247
2248 static void
2249 jme_rxeof(struct jme_rxdata *rdata, int count)
2250 {
2251         struct jme_desc *desc;
2252         int nsegs, pktlen;
2253
2254         for (;;) {
2255 #ifdef DEVICE_POLLING
2256                 if (count >= 0 && count-- == 0)
2257                         break;
2258 #endif
2259                 desc = &rdata->jme_rx_ring[rdata->jme_rx_cons];
2260                 if ((le32toh(desc->flags) & JME_RD_OWN) == JME_RD_OWN)
2261                         break;
2262                 if ((le32toh(desc->buflen) & JME_RD_VALID) == 0)
2263                         break;
2264
2265                 /*
2266                  * Check number of segments against received bytes.
2267                  * Non-matching value would indicate that hardware
2268                  * is still trying to update Rx descriptors. I'm not
2269                  * sure whether this check is needed.
2270                  */
2271                 nsegs = JME_RX_NSEGS(le32toh(desc->buflen));
2272                 pktlen = JME_RX_BYTES(le32toh(desc->buflen));
2273                 if (nsegs != howmany(pktlen, MCLBYTES)) {
2274                         if_printf(&rdata->jme_sc->arpcom.ac_if,
2275                             "RX fragment count(%d) and "
2276                             "packet size(%d) mismach\n", nsegs, pktlen);
2277                         break;
2278                 }
2279
2280                 /* Received a frame. */
2281                 jme_rxpkt(rdata);
2282         }
2283 }
2284
2285 static void
2286 jme_tick(void *xsc)
2287 {
2288         struct jme_softc *sc = xsc;
2289         struct ifnet *ifp = &sc->arpcom.ac_if;
2290         struct mii_data *mii = device_get_softc(sc->jme_miibus);
2291
2292         ifnet_serialize_all(ifp);
2293
2294         mii_tick(mii);
2295         callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2296
2297         ifnet_deserialize_all(ifp);
2298 }
2299
2300 static void
2301 jme_reset(struct jme_softc *sc)
2302 {
2303         uint32_t val;
2304
2305         /* Make sure that TX and RX are stopped */
2306         jme_stop_tx(sc);
2307         jme_stop_rx(sc);
2308
2309         /* Start reset */
2310         CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2311         DELAY(20);
2312
2313         /*
2314          * Hold reset bit before stop reset
2315          */
2316
2317         /* Disable TXMAC and TXOFL clock sources */
2318         CSR_WRITE_4(sc, JME_GHC, GHC_RESET);
2319         /* Disable RXMAC clock source */
2320         val = CSR_READ_4(sc, JME_GPREG1);
2321         CSR_WRITE_4(sc, JME_GPREG1, val | GPREG1_DIS_RXMAC_CLKSRC);
2322         /* Flush */
2323         CSR_READ_4(sc, JME_GHC);
2324
2325         /* Stop reset */
2326         CSR_WRITE_4(sc, JME_GHC, 0);
2327         /* Flush */
2328         CSR_READ_4(sc, JME_GHC);
2329
2330         /*
2331          * Clear reset bit after stop reset
2332          */
2333
2334         /* Enable TXMAC and TXOFL clock sources */
2335         CSR_WRITE_4(sc, JME_GHC, GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC);
2336         /* Enable RXMAC clock source */
2337         val = CSR_READ_4(sc, JME_GPREG1);
2338         CSR_WRITE_4(sc, JME_GPREG1, val & ~GPREG1_DIS_RXMAC_CLKSRC);
2339         /* Flush */
2340         CSR_READ_4(sc, JME_GHC);
2341
2342         /* Disable TXMAC and TXOFL clock sources */
2343         CSR_WRITE_4(sc, JME_GHC, 0);
2344         /* Disable RXMAC clock source */
2345         val = CSR_READ_4(sc, JME_GPREG1);
2346         CSR_WRITE_4(sc, JME_GPREG1, val | GPREG1_DIS_RXMAC_CLKSRC);
2347         /* Flush */
2348         CSR_READ_4(sc, JME_GHC);
2349
2350         /* Enable TX and RX */
2351         val = CSR_READ_4(sc, JME_TXCSR);
2352         CSR_WRITE_4(sc, JME_TXCSR, val | TXCSR_TX_ENB);
2353         val = CSR_READ_4(sc, JME_RXCSR);
2354         CSR_WRITE_4(sc, JME_RXCSR, val | RXCSR_RX_ENB);
2355         /* Flush */
2356         CSR_READ_4(sc, JME_TXCSR);
2357         CSR_READ_4(sc, JME_RXCSR);
2358
2359         /* Enable TXMAC and TXOFL clock sources */
2360         CSR_WRITE_4(sc, JME_GHC, GHC_TXOFL_CLKSRC | GHC_TXMAC_CLKSRC);
2361         /* Eisable RXMAC clock source */
2362         val = CSR_READ_4(sc, JME_GPREG1);
2363         CSR_WRITE_4(sc, JME_GPREG1, val & ~GPREG1_DIS_RXMAC_CLKSRC);
2364         /* Flush */
2365         CSR_READ_4(sc, JME_GHC);
2366
2367         /* Stop TX and RX */
2368         jme_stop_tx(sc);
2369         jme_stop_rx(sc);
2370 }
2371
2372 static void
2373 jme_init(void *xsc)
2374 {
2375         struct jme_softc *sc = xsc;
2376         struct ifnet *ifp = &sc->arpcom.ac_if;
2377         struct mii_data *mii;
2378         uint8_t eaddr[ETHER_ADDR_LEN];
2379         bus_addr_t paddr;
2380         uint32_t reg;
2381         int error, r;
2382
2383         ASSERT_IFNET_SERIALIZED_ALL(ifp);
2384
2385         /*
2386          * Cancel any pending I/O.
2387          */
2388         jme_stop(sc);
2389
2390         /*
2391          * Reset the chip to a known state.
2392          */
2393         jme_reset(sc);
2394
2395         /*
2396          * Setup MSI/MSI-X vectors to interrupts mapping
2397          */
2398         jme_set_msinum(sc);
2399
2400         sc->jme_txd_spare =
2401         howmany(ifp->if_mtu + sizeof(struct ether_vlan_header), MCLBYTES);
2402         KKASSERT(sc->jme_txd_spare >= 1);
2403
2404         /*
2405          * If we use 64bit address mode for transmitting, each Tx request
2406          * needs one more symbol descriptor.
2407          */
2408         if (sc->jme_lowaddr != BUS_SPACE_MAXADDR_32BIT)
2409                 sc->jme_txd_spare += 1;
2410
2411         if (sc->jme_cdata.jme_rx_ring_cnt > JME_NRXRING_MIN)
2412                 jme_enable_rss(sc);
2413         else
2414                 jme_disable_rss(sc);
2415
2416         /* Init RX descriptors */
2417         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
2418                 error = jme_init_rx_ring(&sc->jme_cdata.jme_rx_data[r]);
2419                 if (error) {
2420                         if_printf(ifp, "initialization failed: "
2421                                   "no memory for %dth RX ring.\n", r);
2422                         jme_stop(sc);
2423                         return;
2424                 }
2425         }
2426
2427         /* Init TX descriptors */
2428         jme_init_tx_ring(sc);
2429
2430         /* Initialize shadow status block. */
2431         jme_init_ssb(sc);
2432
2433         /* Reprogram the station address. */
2434         bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2435         CSR_WRITE_4(sc, JME_PAR0,
2436             eaddr[3] << 24 | eaddr[2] << 16 | eaddr[1] << 8 | eaddr[0]);
2437         CSR_WRITE_4(sc, JME_PAR1, eaddr[5] << 8 | eaddr[4]);
2438
2439         /*
2440          * Configure Tx queue.
2441          *  Tx priority queue weight value : 0
2442          *  Tx FIFO threshold for processing next packet : 16QW
2443          *  Maximum Tx DMA length : 512
2444          *  Allow Tx DMA burst.
2445          */
2446         sc->jme_txcsr = TXCSR_TXQ_N_SEL(TXCSR_TXQ0);
2447         sc->jme_txcsr |= TXCSR_TXQ_WEIGHT(TXCSR_TXQ_WEIGHT_MIN);
2448         sc->jme_txcsr |= TXCSR_FIFO_THRESH_16QW;
2449         sc->jme_txcsr |= sc->jme_tx_dma_size;
2450         sc->jme_txcsr |= TXCSR_DMA_BURST;
2451         CSR_WRITE_4(sc, JME_TXCSR, sc->jme_txcsr);
2452
2453         /* Set Tx descriptor counter. */
2454         CSR_WRITE_4(sc, JME_TXQDC, sc->jme_cdata.jme_tx_desc_cnt);
2455
2456         /* Set Tx ring address to the hardware. */
2457         paddr = sc->jme_cdata.jme_tx_ring_paddr;
2458         CSR_WRITE_4(sc, JME_TXDBA_HI, JME_ADDR_HI(paddr));
2459         CSR_WRITE_4(sc, JME_TXDBA_LO, JME_ADDR_LO(paddr));
2460
2461         /* Configure TxMAC parameters. */
2462         reg = TXMAC_IFG1_DEFAULT | TXMAC_IFG2_DEFAULT | TXMAC_IFG_ENB;
2463         reg |= TXMAC_THRESH_1_PKT;
2464         reg |= TXMAC_CRC_ENB | TXMAC_PAD_ENB;
2465         CSR_WRITE_4(sc, JME_TXMAC, reg);
2466
2467         /*
2468          * Configure Rx queue.
2469          *  FIFO full threshold for transmitting Tx pause packet : 128T
2470          *  FIFO threshold for processing next packet : 128QW
2471          *  Rx queue 0 select
2472          *  Max Rx DMA length : 128
2473          *  Rx descriptor retry : 32
2474          *  Rx descriptor retry time gap : 256ns
2475          *  Don't receive runt/bad frame.
2476          */
2477         sc->jme_rxcsr = RXCSR_FIFO_FTHRESH_128T;
2478 #if 0
2479         /*
2480          * Since Rx FIFO size is 4K bytes, receiving frames larger
2481          * than 4K bytes will suffer from Rx FIFO overruns. So
2482          * decrease FIFO threshold to reduce the FIFO overruns for
2483          * frames larger than 4000 bytes.
2484          * For best performance of standard MTU sized frames use
2485          * maximum allowable FIFO threshold, 128QW.
2486          */
2487         if ((ifp->if_mtu + ETHER_HDR_LEN + EVL_ENCAPLEN + ETHER_CRC_LEN) >
2488             JME_RX_FIFO_SIZE)
2489                 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2490         else
2491                 sc->jme_rxcsr |= RXCSR_FIFO_THRESH_128QW;
2492 #else
2493         /* Improve PCI Express compatibility */
2494         sc->jme_rxcsr |= RXCSR_FIFO_THRESH_16QW;
2495 #endif
2496         sc->jme_rxcsr |= sc->jme_rx_dma_size;
2497         sc->jme_rxcsr |= RXCSR_DESC_RT_CNT(RXCSR_DESC_RT_CNT_DEFAULT);
2498         sc->jme_rxcsr |= RXCSR_DESC_RT_GAP_256 & RXCSR_DESC_RT_GAP_MASK;
2499         /* XXX TODO DROP_BAD */
2500
2501         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
2502                 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
2503
2504                 CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr | RXCSR_RXQ_N_SEL(r));
2505
2506                 /* Set Rx descriptor counter. */
2507                 CSR_WRITE_4(sc, JME_RXQDC, rdata->jme_rx_desc_cnt);
2508
2509                 /* Set Rx ring address to the hardware. */
2510                 paddr = rdata->jme_rx_ring_paddr;
2511                 CSR_WRITE_4(sc, JME_RXDBA_HI, JME_ADDR_HI(paddr));
2512                 CSR_WRITE_4(sc, JME_RXDBA_LO, JME_ADDR_LO(paddr));
2513         }
2514
2515         /* Clear receive filter. */
2516         CSR_WRITE_4(sc, JME_RXMAC, 0);
2517
2518         /* Set up the receive filter. */
2519         jme_set_filter(sc);
2520         jme_set_vlan(sc);
2521
2522         /*
2523          * Disable all WOL bits as WOL can interfere normal Rx
2524          * operation. Also clear WOL detection status bits.
2525          */
2526         reg = CSR_READ_4(sc, JME_PMCS);
2527         reg &= ~PMCS_WOL_ENB_MASK;
2528         CSR_WRITE_4(sc, JME_PMCS, reg);
2529
2530         /*
2531          * Pad 10bytes right before received frame. This will greatly
2532          * help Rx performance on strict-alignment architectures as
2533          * it does not need to copy the frame to align the payload.
2534          */
2535         reg = CSR_READ_4(sc, JME_RXMAC);
2536         reg |= RXMAC_PAD_10BYTES;
2537
2538         if (ifp->if_capenable & IFCAP_RXCSUM)
2539                 reg |= RXMAC_CSUM_ENB;
2540         CSR_WRITE_4(sc, JME_RXMAC, reg);
2541
2542         /* Configure general purpose reg0 */
2543         reg = CSR_READ_4(sc, JME_GPREG0);
2544         reg &= ~GPREG0_PCC_UNIT_MASK;
2545         /* Set PCC timer resolution to micro-seconds unit. */
2546         reg |= GPREG0_PCC_UNIT_US;
2547         /*
2548          * Disable all shadow register posting as we have to read
2549          * JME_INTR_STATUS register in jme_intr. Also it seems
2550          * that it's hard to synchronize interrupt status between
2551          * hardware and software with shadow posting due to
2552          * requirements of bus_dmamap_sync(9).
2553          */
2554         reg |= GPREG0_SH_POST_DW7_DIS | GPREG0_SH_POST_DW6_DIS |
2555             GPREG0_SH_POST_DW5_DIS | GPREG0_SH_POST_DW4_DIS |
2556             GPREG0_SH_POST_DW3_DIS | GPREG0_SH_POST_DW2_DIS |
2557             GPREG0_SH_POST_DW1_DIS | GPREG0_SH_POST_DW0_DIS;
2558         /* Disable posting of DW0. */
2559         reg &= ~GPREG0_POST_DW0_ENB;
2560         /* Clear PME message. */
2561         reg &= ~GPREG0_PME_ENB;
2562         /* Set PHY address. */
2563         reg &= ~GPREG0_PHY_ADDR_MASK;
2564         reg |= sc->jme_phyaddr;
2565         CSR_WRITE_4(sc, JME_GPREG0, reg);
2566
2567         /* Configure Tx queue 0 packet completion coalescing. */
2568         jme_set_tx_coal(sc);
2569
2570         /* Configure Rx queues packet completion coalescing. */
2571         jme_set_rx_coal(sc);
2572
2573         /* Configure shadow status block but don't enable posting. */
2574         paddr = sc->jme_cdata.jme_ssb_block_paddr;
2575         CSR_WRITE_4(sc, JME_SHBASE_ADDR_HI, JME_ADDR_HI(paddr));
2576         CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO, JME_ADDR_LO(paddr));
2577
2578         /* Disable Timer 1 and Timer 2. */
2579         CSR_WRITE_4(sc, JME_TIMER1, 0);
2580         CSR_WRITE_4(sc, JME_TIMER2, 0);
2581
2582         /* Configure retry transmit period, retry limit value. */
2583         CSR_WRITE_4(sc, JME_TXTRHD,
2584             ((TXTRHD_RT_PERIOD_DEFAULT << TXTRHD_RT_PERIOD_SHIFT) &
2585             TXTRHD_RT_PERIOD_MASK) |
2586             ((TXTRHD_RT_LIMIT_DEFAULT << TXTRHD_RT_LIMIT_SHIFT) &
2587             TXTRHD_RT_LIMIT_SHIFT));
2588
2589 #ifdef DEVICE_POLLING
2590         if (!(ifp->if_flags & IFF_POLLING))
2591 #endif
2592         /* Initialize the interrupt mask. */
2593         CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
2594         CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2595
2596         /*
2597          * Enabling Tx/Rx DMA engines and Rx queue processing is
2598          * done after detection of valid link in jme_miibus_statchg.
2599          */
2600         sc->jme_flags &= ~JME_FLAG_LINK;
2601
2602         /* Set the current media. */
2603         mii = device_get_softc(sc->jme_miibus);
2604         mii_mediachg(mii);
2605
2606         callout_reset(&sc->jme_tick_ch, hz, jme_tick, sc);
2607
2608         ifp->if_flags |= IFF_RUNNING;
2609         ifp->if_flags &= ~IFF_OACTIVE;
2610 }
2611
2612 static void
2613 jme_stop(struct jme_softc *sc)
2614 {
2615         struct ifnet *ifp = &sc->arpcom.ac_if;
2616         struct jme_txdesc *txd;
2617         struct jme_rxdesc *rxd;
2618         struct jme_rxdata *rdata;
2619         int i, r;
2620
2621         ASSERT_IFNET_SERIALIZED_ALL(ifp);
2622
2623         /*
2624          * Mark the interface down and cancel the watchdog timer.
2625          */
2626         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2627         ifp->if_timer = 0;
2628
2629         callout_stop(&sc->jme_tick_ch);
2630         sc->jme_flags &= ~JME_FLAG_LINK;
2631
2632         /*
2633          * Disable interrupts.
2634          */
2635         CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
2636         CSR_WRITE_4(sc, JME_INTR_STATUS, 0xFFFFFFFF);
2637
2638         /* Disable updating shadow status block. */
2639         CSR_WRITE_4(sc, JME_SHBASE_ADDR_LO,
2640             CSR_READ_4(sc, JME_SHBASE_ADDR_LO) & ~SHBASE_POST_ENB);
2641
2642         /* Stop receiver, transmitter. */
2643         jme_stop_rx(sc);
2644         jme_stop_tx(sc);
2645
2646         /*
2647          * Free partial finished RX segments
2648          */
2649         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
2650                 rdata = &sc->jme_cdata.jme_rx_data[r];
2651                 if (rdata->jme_rxhead != NULL)
2652                         m_freem(rdata->jme_rxhead);
2653                 JME_RXCHAIN_RESET(rdata);
2654         }
2655
2656         /*
2657          * Free RX and TX mbufs still in the queues.
2658          */
2659         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
2660                 rdata = &sc->jme_cdata.jme_rx_data[r];
2661                 for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
2662                         rxd = &rdata->jme_rxdesc[i];
2663                         if (rxd->rx_m != NULL) {
2664                                 bus_dmamap_unload(rdata->jme_rx_tag,
2665                                                   rxd->rx_dmamap);
2666                                 m_freem(rxd->rx_m);
2667                                 rxd->rx_m = NULL;
2668                         }
2669                 }
2670         }
2671         for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
2672                 txd = &sc->jme_cdata.jme_txdesc[i];
2673                 if (txd->tx_m != NULL) {
2674                         bus_dmamap_unload(sc->jme_cdata.jme_tx_tag,
2675                             txd->tx_dmamap);
2676                         m_freem(txd->tx_m);
2677                         txd->tx_m = NULL;
2678                         txd->tx_ndesc = 0;
2679                 }
2680         }
2681 }
2682
2683 static void
2684 jme_stop_tx(struct jme_softc *sc)
2685 {
2686         uint32_t reg;
2687         int i;
2688
2689         reg = CSR_READ_4(sc, JME_TXCSR);
2690         if ((reg & TXCSR_TX_ENB) == 0)
2691                 return;
2692         reg &= ~TXCSR_TX_ENB;
2693         CSR_WRITE_4(sc, JME_TXCSR, reg);
2694         for (i = JME_TIMEOUT; i > 0; i--) {
2695                 DELAY(1);
2696                 if ((CSR_READ_4(sc, JME_TXCSR) & TXCSR_TX_ENB) == 0)
2697                         break;
2698         }
2699         if (i == 0)
2700                 device_printf(sc->jme_dev, "stopping transmitter timeout!\n");
2701 }
2702
2703 static void
2704 jme_stop_rx(struct jme_softc *sc)
2705 {
2706         uint32_t reg;
2707         int i;
2708
2709         reg = CSR_READ_4(sc, JME_RXCSR);
2710         if ((reg & RXCSR_RX_ENB) == 0)
2711                 return;
2712         reg &= ~RXCSR_RX_ENB;
2713         CSR_WRITE_4(sc, JME_RXCSR, reg);
2714         for (i = JME_TIMEOUT; i > 0; i--) {
2715                 DELAY(1);
2716                 if ((CSR_READ_4(sc, JME_RXCSR) & RXCSR_RX_ENB) == 0)
2717                         break;
2718         }
2719         if (i == 0)
2720                 device_printf(sc->jme_dev, "stopping recevier timeout!\n");
2721 }
2722
2723 static void
2724 jme_init_tx_ring(struct jme_softc *sc)
2725 {
2726         struct jme_chain_data *cd;
2727         struct jme_txdesc *txd;
2728         int i;
2729
2730         sc->jme_cdata.jme_tx_prod = 0;
2731         sc->jme_cdata.jme_tx_cons = 0;
2732         sc->jme_cdata.jme_tx_cnt = 0;
2733
2734         cd = &sc->jme_cdata;
2735         bzero(cd->jme_tx_ring, JME_TX_RING_SIZE(sc));
2736         for (i = 0; i < sc->jme_cdata.jme_tx_desc_cnt; i++) {
2737                 txd = &sc->jme_cdata.jme_txdesc[i];
2738                 txd->tx_m = NULL;
2739                 txd->tx_desc = &cd->jme_tx_ring[i];
2740                 txd->tx_ndesc = 0;
2741         }
2742 }
2743
2744 static void
2745 jme_init_ssb(struct jme_softc *sc)
2746 {
2747         struct jme_chain_data *cd;
2748
2749         cd = &sc->jme_cdata;
2750         bzero(cd->jme_ssb_block, JME_SSB_SIZE);
2751 }
2752
2753 static int
2754 jme_init_rx_ring(struct jme_rxdata *rdata)
2755 {
2756         struct jme_rxdesc *rxd;
2757         int i;
2758
2759         KKASSERT(rdata->jme_rxhead == NULL &&
2760                  rdata->jme_rxtail == NULL &&
2761                  rdata->jme_rxlen == 0);
2762         rdata->jme_rx_cons = 0;
2763
2764         bzero(rdata->jme_rx_ring, JME_RX_RING_SIZE(rdata));
2765         for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
2766                 int error;
2767
2768                 rxd = &rdata->jme_rxdesc[i];
2769                 rxd->rx_m = NULL;
2770                 rxd->rx_desc = &rdata->jme_rx_ring[i];
2771                 error = jme_newbuf(rdata, rxd, 1);
2772                 if (error)
2773                         return error;
2774         }
2775         return 0;
2776 }
2777
2778 static int
2779 jme_newbuf(struct jme_rxdata *rdata, struct jme_rxdesc *rxd, int init)
2780 {
2781         struct jme_desc *desc;
2782         struct mbuf *m;
2783         bus_dma_segment_t segs;
2784         bus_dmamap_t map;
2785         int error, nsegs;
2786
2787         m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2788         if (m == NULL)
2789                 return ENOBUFS;
2790         /*
2791          * JMC250 has 64bit boundary alignment limitation so jme(4)
2792          * takes advantage of 10 bytes padding feature of hardware
2793          * in order not to copy entire frame to align IP header on
2794          * 32bit boundary.
2795          */
2796         m->m_len = m->m_pkthdr.len = MCLBYTES;
2797
2798         error = bus_dmamap_load_mbuf_segment(rdata->jme_rx_tag,
2799                         rdata->jme_rx_sparemap, m, &segs, 1, &nsegs,
2800                         BUS_DMA_NOWAIT);
2801         if (error) {
2802                 m_freem(m);
2803                 if (init) {
2804                         if_printf(&rdata->jme_sc->arpcom.ac_if,
2805                             "can't load RX mbuf\n");
2806                 }
2807                 return error;
2808         }
2809
2810         if (rxd->rx_m != NULL) {
2811                 bus_dmamap_sync(rdata->jme_rx_tag, rxd->rx_dmamap,
2812                                 BUS_DMASYNC_POSTREAD);
2813                 bus_dmamap_unload(rdata->jme_rx_tag, rxd->rx_dmamap);
2814         }
2815         map = rxd->rx_dmamap;
2816         rxd->rx_dmamap = rdata->jme_rx_sparemap;
2817         rdata->jme_rx_sparemap = map;
2818         rxd->rx_m = m;
2819
2820         desc = rxd->rx_desc;
2821         desc->buflen = htole32(segs.ds_len);
2822         desc->addr_lo = htole32(JME_ADDR_LO(segs.ds_addr));
2823         desc->addr_hi = htole32(JME_ADDR_HI(segs.ds_addr));
2824         desc->flags = htole32(JME_RD_OWN | JME_RD_INTR | JME_RD_64BIT);
2825
2826         return 0;
2827 }
2828
2829 static void
2830 jme_set_vlan(struct jme_softc *sc)
2831 {
2832         struct ifnet *ifp = &sc->arpcom.ac_if;
2833         uint32_t reg;
2834
2835         ASSERT_IFNET_SERIALIZED_ALL(ifp);
2836
2837         reg = CSR_READ_4(sc, JME_RXMAC);
2838         reg &= ~RXMAC_VLAN_ENB;
2839         if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
2840                 reg |= RXMAC_VLAN_ENB;
2841         CSR_WRITE_4(sc, JME_RXMAC, reg);
2842 }
2843
2844 static void
2845 jme_set_filter(struct jme_softc *sc)
2846 {
2847         struct ifnet *ifp = &sc->arpcom.ac_if;
2848         struct ifmultiaddr *ifma;
2849         uint32_t crc;
2850         uint32_t mchash[2];
2851         uint32_t rxcfg;
2852
2853         ASSERT_IFNET_SERIALIZED_ALL(ifp);
2854
2855         rxcfg = CSR_READ_4(sc, JME_RXMAC);
2856         rxcfg &= ~(RXMAC_BROADCAST | RXMAC_PROMISC | RXMAC_MULTICAST |
2857             RXMAC_ALLMULTI);
2858
2859         /*
2860          * Always accept frames destined to our station address.
2861          * Always accept broadcast frames.
2862          */
2863         rxcfg |= RXMAC_UNICAST | RXMAC_BROADCAST;
2864
2865         if (ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) {
2866                 if (ifp->if_flags & IFF_PROMISC)
2867                         rxcfg |= RXMAC_PROMISC;
2868                 if (ifp->if_flags & IFF_ALLMULTI)
2869                         rxcfg |= RXMAC_ALLMULTI;
2870                 CSR_WRITE_4(sc, JME_MAR0, 0xFFFFFFFF);
2871                 CSR_WRITE_4(sc, JME_MAR1, 0xFFFFFFFF);
2872                 CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
2873                 return;
2874         }
2875
2876         /*
2877          * Set up the multicast address filter by passing all multicast
2878          * addresses through a CRC generator, and then using the low-order
2879          * 6 bits as an index into the 64 bit multicast hash table.  The
2880          * high order bits select the register, while the rest of the bits
2881          * select the bit within the register.
2882          */
2883         rxcfg |= RXMAC_MULTICAST;
2884         bzero(mchash, sizeof(mchash));
2885
2886         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2887                 if (ifma->ifma_addr->sa_family != AF_LINK)
2888                         continue;
2889                 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
2890                     ifma->ifma_addr), ETHER_ADDR_LEN);
2891
2892                 /* Just want the 6 least significant bits. */
2893                 crc &= 0x3f;
2894
2895                 /* Set the corresponding bit in the hash table. */
2896                 mchash[crc >> 5] |= 1 << (crc & 0x1f);
2897         }
2898
2899         CSR_WRITE_4(sc, JME_MAR0, mchash[0]);
2900         CSR_WRITE_4(sc, JME_MAR1, mchash[1]);
2901         CSR_WRITE_4(sc, JME_RXMAC, rxcfg);
2902 }
2903
2904 static int
2905 jme_sysctl_tx_coal_to(SYSCTL_HANDLER_ARGS)
2906 {
2907         struct jme_softc *sc = arg1;
2908         struct ifnet *ifp = &sc->arpcom.ac_if;
2909         int error, v;
2910
2911         ifnet_serialize_all(ifp);
2912
2913         v = sc->jme_tx_coal_to;
2914         error = sysctl_handle_int(oidp, &v, 0, req);
2915         if (error || req->newptr == NULL)
2916                 goto back;
2917
2918         if (v < PCCTX_COAL_TO_MIN || v > PCCTX_COAL_TO_MAX) {
2919                 error = EINVAL;
2920                 goto back;
2921         }
2922
2923         if (v != sc->jme_tx_coal_to) {
2924                 sc->jme_tx_coal_to = v;
2925                 if (ifp->if_flags & IFF_RUNNING)
2926                         jme_set_tx_coal(sc);
2927         }
2928 back:
2929         ifnet_deserialize_all(ifp);
2930         return error;
2931 }
2932
2933 static int
2934 jme_sysctl_tx_coal_pkt(SYSCTL_HANDLER_ARGS)
2935 {
2936         struct jme_softc *sc = arg1;
2937         struct ifnet *ifp = &sc->arpcom.ac_if;
2938         int error, v;
2939
2940         ifnet_serialize_all(ifp);
2941
2942         v = sc->jme_tx_coal_pkt;
2943         error = sysctl_handle_int(oidp, &v, 0, req);
2944         if (error || req->newptr == NULL)
2945                 goto back;
2946
2947         if (v < PCCTX_COAL_PKT_MIN || v > PCCTX_COAL_PKT_MAX) {
2948                 error = EINVAL;
2949                 goto back;
2950         }
2951
2952         if (v != sc->jme_tx_coal_pkt) {
2953                 sc->jme_tx_coal_pkt = v;
2954                 if (ifp->if_flags & IFF_RUNNING)
2955                         jme_set_tx_coal(sc);
2956         }
2957 back:
2958         ifnet_deserialize_all(ifp);
2959         return error;
2960 }
2961
2962 static int
2963 jme_sysctl_rx_coal_to(SYSCTL_HANDLER_ARGS)
2964 {
2965         struct jme_softc *sc = arg1;
2966         struct ifnet *ifp = &sc->arpcom.ac_if;
2967         int error, v;
2968
2969         ifnet_serialize_all(ifp);
2970
2971         v = sc->jme_rx_coal_to;
2972         error = sysctl_handle_int(oidp, &v, 0, req);
2973         if (error || req->newptr == NULL)
2974                 goto back;
2975
2976         if (v < PCCRX_COAL_TO_MIN || v > PCCRX_COAL_TO_MAX) {
2977                 error = EINVAL;
2978                 goto back;
2979         }
2980
2981         if (v != sc->jme_rx_coal_to) {
2982                 sc->jme_rx_coal_to = v;
2983                 if (ifp->if_flags & IFF_RUNNING)
2984                         jme_set_rx_coal(sc);
2985         }
2986 back:
2987         ifnet_deserialize_all(ifp);
2988         return error;
2989 }
2990
2991 static int
2992 jme_sysctl_rx_coal_pkt(SYSCTL_HANDLER_ARGS)
2993 {
2994         struct jme_softc *sc = arg1;
2995         struct ifnet *ifp = &sc->arpcom.ac_if;
2996         int error, v;
2997
2998         ifnet_serialize_all(ifp);
2999
3000         v = sc->jme_rx_coal_pkt;
3001         error = sysctl_handle_int(oidp, &v, 0, req);
3002         if (error || req->newptr == NULL)
3003                 goto back;
3004
3005         if (v < PCCRX_COAL_PKT_MIN || v > PCCRX_COAL_PKT_MAX) {
3006                 error = EINVAL;
3007                 goto back;
3008         }
3009
3010         if (v != sc->jme_rx_coal_pkt) {
3011                 sc->jme_rx_coal_pkt = v;
3012                 if (ifp->if_flags & IFF_RUNNING)
3013                         jme_set_rx_coal(sc);
3014         }
3015 back:
3016         ifnet_deserialize_all(ifp);
3017         return error;
3018 }
3019
3020 static void
3021 jme_set_tx_coal(struct jme_softc *sc)
3022 {
3023         uint32_t reg;
3024
3025         reg = (sc->jme_tx_coal_to << PCCTX_COAL_TO_SHIFT) &
3026             PCCTX_COAL_TO_MASK;
3027         reg |= (sc->jme_tx_coal_pkt << PCCTX_COAL_PKT_SHIFT) &
3028             PCCTX_COAL_PKT_MASK;
3029         reg |= PCCTX_COAL_TXQ0;
3030         CSR_WRITE_4(sc, JME_PCCTX, reg);
3031 }
3032
3033 static void
3034 jme_set_rx_coal(struct jme_softc *sc)
3035 {
3036         uint32_t reg;
3037         int r;
3038
3039         reg = (sc->jme_rx_coal_to << PCCRX_COAL_TO_SHIFT) &
3040             PCCRX_COAL_TO_MASK;
3041         reg |= (sc->jme_rx_coal_pkt << PCCRX_COAL_PKT_SHIFT) &
3042             PCCRX_COAL_PKT_MASK;
3043         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r)
3044                 CSR_WRITE_4(sc, JME_PCCRX(r), reg);
3045 }
3046
3047 #ifdef DEVICE_POLLING
3048
3049 static void
3050 jme_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
3051 {
3052         struct jme_softc *sc = ifp->if_softc;
3053         uint32_t status;
3054         int r;
3055
3056         ASSERT_SERIALIZED(&sc->jme_serialize);
3057
3058         switch (cmd) {
3059         case POLL_REGISTER:
3060                 CSR_WRITE_4(sc, JME_INTR_MASK_CLR, JME_INTRS);
3061                 break;
3062
3063         case POLL_DEREGISTER:
3064                 CSR_WRITE_4(sc, JME_INTR_MASK_SET, JME_INTRS);
3065                 break;
3066
3067         case POLL_AND_CHECK_STATUS:
3068         case POLL_ONLY:
3069                 status = CSR_READ_4(sc, JME_INTR_STATUS);
3070
3071                 for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
3072                         struct jme_rxdata *rdata =
3073                             &sc->jme_cdata.jme_rx_data[r];
3074
3075                         lwkt_serialize_enter(&rdata->jme_rx_serialize);
3076                         jme_rxeof(rdata, count);
3077                         lwkt_serialize_exit(&rdata->jme_rx_serialize);
3078                 }
3079
3080                 if (status & INTR_RXQ_DESC_EMPTY) {
3081                         CSR_WRITE_4(sc, JME_INTR_STATUS, status);
3082                         CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
3083                             RXCSR_RX_ENB | RXCSR_RXQ_START);
3084                 }
3085
3086                 lwkt_serialize_enter(&sc->jme_cdata.jme_tx_serialize);
3087                 jme_txeof(sc);
3088                 if (!ifq_is_empty(&ifp->if_snd))
3089                         if_devstart(ifp);
3090                 lwkt_serialize_exit(&sc->jme_cdata.jme_tx_serialize);
3091                 break;
3092         }
3093 }
3094
3095 #endif  /* DEVICE_POLLING */
3096
3097 static int
3098 jme_rxring_dma_alloc(struct jme_rxdata *rdata)
3099 {
3100         bus_dmamem_t dmem;
3101         int error, asize;
3102
3103         asize = roundup2(JME_RX_RING_SIZE(rdata), JME_RX_RING_ALIGN);
3104         error = bus_dmamem_coherent(rdata->jme_sc->jme_cdata.jme_ring_tag,
3105                         JME_RX_RING_ALIGN, 0,
3106                         BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3107                         asize, BUS_DMA_WAITOK | BUS_DMA_ZERO, &dmem);
3108         if (error) {
3109                 device_printf(rdata->jme_sc->jme_dev,
3110                     "could not allocate %dth Rx ring.\n", rdata->jme_rx_idx);
3111                 return error;
3112         }
3113         rdata->jme_rx_ring_tag = dmem.dmem_tag;
3114         rdata->jme_rx_ring_map = dmem.dmem_map;
3115         rdata->jme_rx_ring = dmem.dmem_addr;
3116         rdata->jme_rx_ring_paddr = dmem.dmem_busaddr;
3117
3118         return 0;
3119 }
3120
3121 static int
3122 jme_rxbuf_dma_alloc(struct jme_rxdata *rdata)
3123 {
3124         int i, error;
3125
3126         /* Create tag for Rx buffers. */
3127         error = bus_dma_tag_create(
3128             rdata->jme_sc->jme_cdata.jme_buffer_tag,/* parent */
3129             JME_RX_BUF_ALIGN, 0,        /* algnmnt, boundary */
3130             BUS_SPACE_MAXADDR,          /* lowaddr */
3131             BUS_SPACE_MAXADDR,          /* highaddr */
3132             NULL, NULL,                 /* filter, filterarg */
3133             MCLBYTES,                   /* maxsize */
3134             1,                          /* nsegments */
3135             MCLBYTES,                   /* maxsegsize */
3136             BUS_DMA_ALLOCNOW | BUS_DMA_WAITOK | BUS_DMA_ALIGNED,/* flags */
3137             &rdata->jme_rx_tag);
3138         if (error) {
3139                 device_printf(rdata->jme_sc->jme_dev,
3140                     "could not create %dth Rx DMA tag.\n", rdata->jme_rx_idx);
3141                 return error;
3142         }
3143
3144         /* Create DMA maps for Rx buffers. */
3145         error = bus_dmamap_create(rdata->jme_rx_tag, BUS_DMA_WAITOK,
3146                                   &rdata->jme_rx_sparemap);
3147         if (error) {
3148                 device_printf(rdata->jme_sc->jme_dev,
3149                     "could not create %dth spare Rx dmamap.\n",
3150                     rdata->jme_rx_idx);
3151                 bus_dma_tag_destroy(rdata->jme_rx_tag);
3152                 rdata->jme_rx_tag = NULL;
3153                 return error;
3154         }
3155         for (i = 0; i < rdata->jme_rx_desc_cnt; i++) {
3156                 struct jme_rxdesc *rxd = &rdata->jme_rxdesc[i];
3157
3158                 error = bus_dmamap_create(rdata->jme_rx_tag, BUS_DMA_WAITOK,
3159                                           &rxd->rx_dmamap);
3160                 if (error) {
3161                         int j;
3162
3163                         device_printf(rdata->jme_sc->jme_dev,
3164                             "could not create %dth Rx dmamap "
3165                             "for %dth RX ring.\n", i, rdata->jme_rx_idx);
3166
3167                         for (j = 0; j < i; ++j) {
3168                                 rxd = &rdata->jme_rxdesc[j];
3169                                 bus_dmamap_destroy(rdata->jme_rx_tag,
3170                                                    rxd->rx_dmamap);
3171                         }
3172                         bus_dmamap_destroy(rdata->jme_rx_tag,
3173                                            rdata->jme_rx_sparemap);
3174                         bus_dma_tag_destroy(rdata->jme_rx_tag);
3175                         rdata->jme_rx_tag = NULL;
3176                         return error;
3177                 }
3178         }
3179         return 0;
3180 }
3181
3182 static void
3183 jme_rx_intr(struct jme_softc *sc, uint32_t status)
3184 {
3185         int r;
3186
3187         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
3188                 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
3189
3190                 if (status & rdata->jme_rx_coal) {
3191                         lwkt_serialize_enter(&rdata->jme_rx_serialize);
3192                         jme_rxeof(rdata, -1);
3193                         lwkt_serialize_exit(&rdata->jme_rx_serialize);
3194                 }
3195         }
3196 }
3197
3198 static void
3199 jme_enable_rss(struct jme_softc *sc)
3200 {
3201         uint32_t rssc, ind;
3202         uint8_t key[RSSKEY_NREGS * RSSKEY_REGSIZE];
3203         int i;
3204
3205         KASSERT(sc->jme_cdata.jme_rx_ring_cnt == JME_NRXRING_2 ||
3206                 sc->jme_cdata.jme_rx_ring_cnt == JME_NRXRING_4,
3207                 ("%s: invalid # of RX rings (%d)",
3208                  sc->arpcom.ac_if.if_xname, sc->jme_cdata.jme_rx_ring_cnt));
3209
3210         rssc = RSSC_HASH_64_ENTRY;
3211         rssc |= RSSC_HASH_IPV4 | RSSC_HASH_IPV4_TCP;
3212         rssc |= sc->jme_cdata.jme_rx_ring_cnt >> 1;
3213         JME_RSS_DPRINTF(sc, 1, "rssc 0x%08x\n", rssc);
3214         CSR_WRITE_4(sc, JME_RSSC, rssc);
3215
3216         toeplitz_get_key(key, sizeof(key));
3217         for (i = 0; i < RSSKEY_NREGS; ++i) {
3218                 uint32_t keyreg;
3219
3220                 keyreg = RSSKEY_REGVAL(key, i);
3221                 JME_RSS_DPRINTF(sc, 5, "keyreg%d 0x%08x\n", i, keyreg);
3222
3223                 CSR_WRITE_4(sc, RSSKEY_REG(i), keyreg);
3224         }
3225
3226         /*
3227          * Create redirect table in following fashion:
3228          * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
3229          */
3230         ind = 0;
3231         for (i = 0; i < RSSTBL_REGSIZE; ++i) {
3232                 int q;
3233
3234                 q = i % sc->jme_cdata.jme_rx_ring_cnt;
3235                 ind |= q << (i * 8);
3236         }
3237         JME_RSS_DPRINTF(sc, 1, "ind 0x%08x\n", ind);
3238
3239         for (i = 0; i < RSSTBL_NREGS; ++i)
3240                 CSR_WRITE_4(sc, RSSTBL_REG(i), ind);
3241 }
3242
3243 static void
3244 jme_disable_rss(struct jme_softc *sc)
3245 {
3246         CSR_WRITE_4(sc, JME_RSSC, RSSC_DIS_RSS);
3247 }
3248
3249 static void
3250 jme_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3251 {
3252         struct jme_softc *sc = ifp->if_softc;
3253
3254         switch (slz) {
3255         case IFNET_SERIALIZE_ALL:
3256                 lwkt_serialize_array_enter(sc->jme_serialize_arr,
3257                     sc->jme_serialize_cnt, 0);
3258                 break;
3259
3260         case IFNET_SERIALIZE_MAIN:
3261                 lwkt_serialize_enter(&sc->jme_serialize);
3262                 break;
3263
3264         case IFNET_SERIALIZE_TX:
3265                 lwkt_serialize_enter(&sc->jme_cdata.jme_tx_serialize);
3266                 break;
3267
3268         case IFNET_SERIALIZE_RX(0):
3269                 lwkt_serialize_enter(
3270                     &sc->jme_cdata.jme_rx_data[0].jme_rx_serialize);
3271                 break;
3272
3273         case IFNET_SERIALIZE_RX(1):
3274                 lwkt_serialize_enter(
3275                     &sc->jme_cdata.jme_rx_data[1].jme_rx_serialize);
3276                 break;
3277
3278         case IFNET_SERIALIZE_RX(2):
3279                 lwkt_serialize_enter(
3280                     &sc->jme_cdata.jme_rx_data[2].jme_rx_serialize);
3281                 break;
3282
3283         case IFNET_SERIALIZE_RX(3):
3284                 lwkt_serialize_enter(
3285                     &sc->jme_cdata.jme_rx_data[3].jme_rx_serialize);
3286                 break;
3287
3288         default:
3289                 panic("%s unsupported serialize type", ifp->if_xname);
3290         }
3291 }
3292
3293 static void
3294 jme_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3295 {
3296         struct jme_softc *sc = ifp->if_softc;
3297
3298         switch (slz) {
3299         case IFNET_SERIALIZE_ALL:
3300                 lwkt_serialize_array_exit(sc->jme_serialize_arr,
3301                     sc->jme_serialize_cnt, 0);
3302                 break;
3303
3304         case IFNET_SERIALIZE_MAIN:
3305                 lwkt_serialize_exit(&sc->jme_serialize);
3306                 break;
3307
3308         case IFNET_SERIALIZE_TX:
3309                 lwkt_serialize_exit(&sc->jme_cdata.jme_tx_serialize);
3310                 break;
3311
3312         case IFNET_SERIALIZE_RX(0):
3313                 lwkt_serialize_exit(
3314                     &sc->jme_cdata.jme_rx_data[0].jme_rx_serialize);
3315                 break;
3316
3317         case IFNET_SERIALIZE_RX(1):
3318                 lwkt_serialize_exit(
3319                     &sc->jme_cdata.jme_rx_data[1].jme_rx_serialize);
3320                 break;
3321
3322         case IFNET_SERIALIZE_RX(2):
3323                 lwkt_serialize_exit(
3324                     &sc->jme_cdata.jme_rx_data[2].jme_rx_serialize);
3325                 break;
3326
3327         case IFNET_SERIALIZE_RX(3):
3328                 lwkt_serialize_exit(
3329                     &sc->jme_cdata.jme_rx_data[3].jme_rx_serialize);
3330                 break;
3331
3332         default:
3333                 panic("%s unsupported serialize type", ifp->if_xname);
3334         }
3335 }
3336
3337 static int
3338 jme_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3339 {
3340         struct jme_softc *sc = ifp->if_softc;
3341
3342         switch (slz) {
3343         case IFNET_SERIALIZE_ALL:
3344                 return lwkt_serialize_array_try(sc->jme_serialize_arr,
3345                     sc->jme_serialize_cnt, 0);
3346
3347         case IFNET_SERIALIZE_MAIN:
3348                 return lwkt_serialize_try(&sc->jme_serialize);
3349
3350         case IFNET_SERIALIZE_TX:
3351                 return lwkt_serialize_try(&sc->jme_cdata.jme_tx_serialize);
3352
3353         case IFNET_SERIALIZE_RX(0):
3354                 return lwkt_serialize_try(
3355                     &sc->jme_cdata.jme_rx_data[0].jme_rx_serialize);
3356
3357         case IFNET_SERIALIZE_RX(1):
3358                 return lwkt_serialize_try(
3359                     &sc->jme_cdata.jme_rx_data[1].jme_rx_serialize);
3360
3361         case IFNET_SERIALIZE_RX(2):
3362                 return lwkt_serialize_try(
3363                     &sc->jme_cdata.jme_rx_data[2].jme_rx_serialize);
3364
3365         case IFNET_SERIALIZE_RX(3):
3366                 return lwkt_serialize_try(
3367                     &sc->jme_cdata.jme_rx_data[3].jme_rx_serialize);
3368
3369         default:
3370                 panic("%s unsupported serialize type", ifp->if_xname);
3371         }
3372 }
3373
3374 #ifdef INVARIANTS
3375
3376 static void
3377 jme_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3378     boolean_t serialized)
3379 {
3380         struct jme_softc *sc = ifp->if_softc;
3381         struct jme_rxdata *rdata;
3382         int i;
3383
3384         switch (slz) {
3385         case IFNET_SERIALIZE_ALL:
3386                 if (serialized) {
3387                         for (i = 0; i < sc->jme_serialize_cnt; ++i)
3388                                 ASSERT_SERIALIZED(sc->jme_serialize_arr[i]);
3389                 } else {
3390                         for (i = 0; i < sc->jme_serialize_cnt; ++i)
3391                                 ASSERT_NOT_SERIALIZED(sc->jme_serialize_arr[i]);
3392                 }
3393                 break;
3394
3395         case IFNET_SERIALIZE_MAIN:
3396                 if (serialized)
3397                         ASSERT_SERIALIZED(&sc->jme_serialize);
3398                 else
3399                         ASSERT_NOT_SERIALIZED(&sc->jme_serialize);
3400                 break;
3401
3402         case IFNET_SERIALIZE_TX:
3403                 if (serialized)
3404                         ASSERT_SERIALIZED(&sc->jme_cdata.jme_tx_serialize);
3405                 else
3406                         ASSERT_NOT_SERIALIZED(&sc->jme_cdata.jme_tx_serialize);
3407                 break;
3408
3409         case IFNET_SERIALIZE_RX(0):
3410                 rdata = &sc->jme_cdata.jme_rx_data[0];
3411                 if (serialized)
3412                         ASSERT_SERIALIZED(&rdata->jme_rx_serialize);
3413                 else
3414                         ASSERT_NOT_SERIALIZED(&rdata->jme_rx_serialize);
3415                 break;
3416
3417         case IFNET_SERIALIZE_RX(1):
3418                 rdata = &sc->jme_cdata.jme_rx_data[1];
3419                 if (serialized)
3420                         ASSERT_SERIALIZED(&rdata->jme_rx_serialize);
3421                 else
3422                         ASSERT_NOT_SERIALIZED(&rdata->jme_rx_serialize);
3423                 break;
3424
3425         case IFNET_SERIALIZE_RX(2):
3426                 rdata = &sc->jme_cdata.jme_rx_data[2];
3427                 if (serialized)
3428                         ASSERT_SERIALIZED(&rdata->jme_rx_serialize);
3429                 else
3430                         ASSERT_NOT_SERIALIZED(&rdata->jme_rx_serialize);
3431                 break;
3432
3433         case IFNET_SERIALIZE_RX(3):
3434                 rdata = &sc->jme_cdata.jme_rx_data[3];
3435                 if (serialized)
3436                         ASSERT_SERIALIZED(&rdata->jme_rx_serialize);
3437                 else
3438                         ASSERT_NOT_SERIALIZED(&rdata->jme_rx_serialize);
3439                 break;
3440
3441         default:
3442                 panic("%s unsupported serialize type", ifp->if_xname);
3443         }
3444 }
3445
3446 #endif  /* INVARIANTS */
3447
3448 static void
3449 jme_msix_try_alloc(device_t dev)
3450 {
3451         struct jme_softc *sc = device_get_softc(dev);
3452         struct jme_msix_data *msix;
3453         int error, i, r, msix_enable, msix_count;
3454
3455         msix_count = 1 + sc->jme_cdata.jme_rx_ring_cnt;
3456         KKASSERT(msix_count <= JME_NMSIX);
3457
3458         msix_enable = device_getenv_int(dev, "msix.enable", jme_msix_enable);
3459
3460         /*
3461          * We leave the 1st MSI-X vector unused, so we
3462          * actually need msix_count + 1 MSI-X vectors.
3463          */
3464         if (!msix_enable || pci_msix_count(dev) < (msix_count + 1))
3465                 return;
3466
3467         for (i = 0; i < msix_count; ++i)
3468                 sc->jme_msix[i].jme_msix_rid = -1;
3469
3470         i = 0;
3471
3472         msix = &sc->jme_msix[i++];
3473         msix->jme_msix_cpuid = 0;               /* XXX Put TX to cpu0 */
3474         msix->jme_msix_arg = &sc->jme_cdata;
3475         msix->jme_msix_func = jme_msix_tx;
3476         msix->jme_msix_intrs = INTR_TXQ_COAL | INTR_TXQ_COAL_TO;
3477         msix->jme_msix_serialize = &sc->jme_cdata.jme_tx_serialize;
3478         ksnprintf(msix->jme_msix_desc, sizeof(msix->jme_msix_desc), "%s tx",
3479             device_get_nameunit(dev));
3480
3481         for (r = 0; r < sc->jme_cdata.jme_rx_ring_cnt; ++r) {
3482                 struct jme_rxdata *rdata = &sc->jme_cdata.jme_rx_data[r];
3483
3484                 msix = &sc->jme_msix[i++];
3485                 msix->jme_msix_cpuid = r;       /* XXX Put RX to cpuX */
3486                 msix->jme_msix_arg = rdata;
3487                 msix->jme_msix_func = jme_msix_rx;
3488                 msix->jme_msix_intrs = rdata->jme_rx_coal | rdata->jme_rx_empty;
3489                 msix->jme_msix_serialize = &rdata->jme_rx_serialize;
3490                 ksnprintf(msix->jme_msix_desc, sizeof(msix->jme_msix_desc),
3491                     "%s rx%d", device_get_nameunit(dev), r);
3492         }
3493
3494         KKASSERT(i == msix_count);
3495
3496         error = pci_setup_msix(dev);
3497         if (error)
3498                 return;
3499
3500         /* Setup jme_msix_cnt early, so we could cleanup */
3501         sc->jme_msix_cnt = msix_count;
3502
3503         for (i = 0; i < msix_count; ++i) {
3504                 msix = &sc->jme_msix[i];
3505
3506                 msix->jme_msix_vector = i + 1;
3507                 error = pci_alloc_msix_vector(dev, msix->jme_msix_vector,
3508                     &msix->jme_msix_rid, msix->jme_msix_cpuid);
3509                 if (error)
3510                         goto back;
3511
3512                 msix->jme_msix_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
3513                     &msix->jme_msix_rid, RF_ACTIVE);
3514                 if (msix->jme_msix_res == NULL) {
3515                         error = ENOMEM;
3516                         goto back;
3517                 }
3518         }
3519
3520         for (i = 0; i < JME_INTR_CNT; ++i) {
3521                 uint32_t intr_mask = (1 << i);
3522                 int x;
3523
3524                 if ((JME_INTRS & intr_mask) == 0)
3525                         continue;
3526
3527                 for (x = 0; x < msix_count; ++x) {
3528                         msix = &sc->jme_msix[x];
3529                         if (msix->jme_msix_intrs & intr_mask) {
3530                                 int reg, shift;
3531
3532                                 reg = i / JME_MSINUM_FACTOR;
3533                                 KKASSERT(reg < JME_MSINUM_CNT);
3534
3535                                 shift = (i % JME_MSINUM_FACTOR) * 4;
3536
3537                                 sc->jme_msinum[reg] |=
3538                                     (msix->jme_msix_vector << shift);
3539
3540                                 break;
3541                         }
3542                 }
3543         }
3544
3545         if (bootverbose) {
3546                 for (i = 0; i < JME_MSINUM_CNT; ++i) {
3547                         device_printf(dev, "MSINUM%d: %#x\n", i,
3548                             sc->jme_msinum[i]);
3549                 }
3550         }
3551
3552         pci_enable_msix(dev);
3553         sc->jme_irq_type = PCI_INTR_TYPE_MSIX;
3554
3555 back:
3556         if (error)
3557                 jme_msix_free(dev);
3558 }
3559
3560 static int
3561 jme_intr_alloc(device_t dev)
3562 {
3563         struct jme_softc *sc = device_get_softc(dev);
3564         u_int irq_flags;
3565
3566         jme_msix_try_alloc(dev);
3567
3568         if (sc->jme_irq_type != PCI_INTR_TYPE_MSIX) {
3569                 sc->jme_irq_type = pci_alloc_1intr(dev, jme_msi_enable,
3570                     &sc->jme_irq_rid, &irq_flags);
3571
3572                 sc->jme_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
3573                     &sc->jme_irq_rid, irq_flags);
3574                 if (sc->jme_irq_res == NULL) {
3575                         device_printf(dev, "can't allocate irq\n");
3576                         return ENXIO;
3577                 }
3578         }
3579         return 0;
3580 }
3581
3582 static void
3583 jme_msix_free(device_t dev)
3584 {
3585         struct jme_softc *sc = device_get_softc(dev);
3586         int i;
3587
3588         KKASSERT(sc->jme_msix_cnt > 1);
3589
3590         for (i = 0; i < sc->jme_msix_cnt; ++i) {
3591                 struct jme_msix_data *msix = &sc->jme_msix[i];
3592
3593                 if (msix->jme_msix_res != NULL) {
3594                         bus_release_resource(dev, SYS_RES_IRQ,
3595                             msix->jme_msix_rid, msix->jme_msix_res);
3596                         msix->jme_msix_res = NULL;
3597                 }
3598                 if (msix->jme_msix_rid >= 0) {
3599                         pci_release_msix_vector(dev, msix->jme_msix_rid);
3600                         msix->jme_msix_rid = -1;
3601                 }
3602         }
3603         pci_teardown_msix(dev);
3604 }
3605
3606 static void
3607 jme_intr_free(device_t dev)
3608 {
3609         struct jme_softc *sc = device_get_softc(dev);
3610
3611         if (sc->jme_irq_type != PCI_INTR_TYPE_MSIX) {
3612                 if (sc->jme_irq_res != NULL) {
3613                         bus_release_resource(dev, SYS_RES_IRQ, sc->jme_irq_rid,
3614                                              sc->jme_irq_res);
3615                 }
3616                 if (sc->jme_irq_type == PCI_INTR_TYPE_MSI)
3617                         pci_release_msi(dev);
3618         } else {
3619                 jme_msix_free(dev);
3620         }
3621 }
3622
3623 static void
3624 jme_msix_tx(void *xcd)
3625 {
3626         struct jme_chain_data *cd = xcd;
3627         struct jme_softc *sc = cd->jme_sc;
3628         struct ifnet *ifp = &sc->arpcom.ac_if;
3629
3630         ASSERT_SERIALIZED(&cd->jme_tx_serialize);
3631
3632         CSR_WRITE_4(sc, JME_INTR_MASK_CLR, INTR_TXQ_COAL | INTR_TXQ_COAL_TO);
3633
3634         CSR_WRITE_4(sc, JME_INTR_STATUS,
3635             INTR_TXQ_COAL | INTR_TXQ_COAL_TO | INTR_TXQ_COMP);
3636
3637         if (ifp->if_flags & IFF_RUNNING) {
3638                 jme_txeof(sc);
3639                 if (!ifq_is_empty(&ifp->if_snd))
3640                         if_devstart(ifp);
3641         }
3642
3643         CSR_WRITE_4(sc, JME_INTR_MASK_SET, INTR_TXQ_COAL | INTR_TXQ_COAL_TO);
3644 }
3645
3646 static void
3647 jme_msix_rx(void *xrdata)
3648 {
3649         struct jme_rxdata *rdata = xrdata;
3650         struct jme_softc *sc = rdata->jme_sc;
3651         struct ifnet *ifp = &sc->arpcom.ac_if;
3652         uint32_t status;
3653
3654         ASSERT_SERIALIZED(&rdata->jme_rx_serialize);
3655
3656         CSR_WRITE_4(sc, JME_INTR_MASK_CLR,
3657             (rdata->jme_rx_coal | rdata->jme_rx_empty));
3658
3659         status = CSR_READ_4(sc, JME_INTR_STATUS);
3660         status &= (rdata->jme_rx_coal | rdata->jme_rx_empty);
3661
3662         if (status & rdata->jme_rx_coal)
3663                 status |= (rdata->jme_rx_coal | rdata->jme_rx_comp);
3664         CSR_WRITE_4(sc, JME_INTR_STATUS, status);
3665
3666         if (ifp->if_flags & IFF_RUNNING) {
3667                 if (status & rdata->jme_rx_coal)
3668                         jme_rxeof(rdata, -1);
3669
3670                 if (status & rdata->jme_rx_empty) {
3671                         CSR_WRITE_4(sc, JME_RXCSR, sc->jme_rxcsr |
3672                             RXCSR_RX_ENB | RXCSR_RXQ_START);
3673                 }
3674         }
3675
3676         CSR_WRITE_4(sc, JME_INTR_MASK_SET,
3677             (rdata->jme_rx_coal | rdata->jme_rx_empty));
3678 }
3679
3680 static void
3681 jme_set_msinum(struct jme_softc *sc)
3682 {
3683         int i;
3684
3685         for (i = 0; i < JME_MSINUM_CNT; ++i)
3686                 CSR_WRITE_4(sc, JME_MSINUM(i), sc->jme_msinum[i]);
3687 }
3688
3689 static int
3690 jme_intr_setup(device_t dev)
3691 {
3692         struct jme_softc *sc = device_get_softc(dev);
3693         struct ifnet *ifp = &sc->arpcom.ac_if;
3694         int error;
3695
3696         if (sc->jme_irq_type == PCI_INTR_TYPE_MSIX)
3697                 return jme_msix_setup(dev);
3698
3699         error = bus_setup_intr(dev, sc->jme_irq_res, INTR_MPSAFE,
3700             jme_intr, sc, &sc->jme_irq_handle, &sc->jme_serialize);
3701         if (error) {
3702                 device_printf(dev, "could not set up interrupt handler.\n");
3703                 return error;
3704         }
3705
3706         ifp->if_cpuid = rman_get_cpuid(sc->jme_irq_res);
3707         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
3708         return 0;
3709 }
3710
3711 static void
3712 jme_intr_teardown(device_t dev)
3713 {
3714         struct jme_softc *sc = device_get_softc(dev);
3715
3716         if (sc->jme_irq_type == PCI_INTR_TYPE_MSIX)
3717                 jme_msix_teardown(dev, sc->jme_msix_cnt);
3718         else
3719                 bus_teardown_intr(dev, sc->jme_irq_res, sc->jme_irq_handle);
3720 }
3721
3722 static int
3723 jme_msix_setup(device_t dev)
3724 {
3725         struct jme_softc *sc = device_get_softc(dev);
3726         struct ifnet *ifp = &sc->arpcom.ac_if;
3727         int x;
3728
3729         for (x = 0; x < sc->jme_msix_cnt; ++x) {
3730                 struct jme_msix_data *msix = &sc->jme_msix[x];
3731                 int error;
3732
3733                 error = bus_setup_intr_descr(dev, msix->jme_msix_res,
3734                     INTR_MPSAFE, msix->jme_msix_func, msix->jme_msix_arg,
3735                     &msix->jme_msix_handle, msix->jme_msix_serialize,
3736                     msix->jme_msix_desc);
3737                 if (error) {
3738                         device_printf(dev, "could not set up %s "
3739                             "interrupt handler.\n", msix->jme_msix_desc);
3740                         jme_msix_teardown(dev, x);
3741                         return error;
3742                 }
3743         }
3744         ifp->if_cpuid = 0; /* XXX */
3745         return 0;
3746 }
3747
3748 static void
3749 jme_msix_teardown(device_t dev, int msix_count)
3750 {
3751         struct jme_softc *sc = device_get_softc(dev);
3752         int x;
3753
3754         for (x = 0; x < msix_count; ++x) {
3755                 struct jme_msix_data *msix = &sc->jme_msix[x];
3756
3757                 bus_teardown_intr(dev, msix->jme_msix_res,
3758                     msix->jme_msix_handle);
3759         }
3760 }