2 * THIS FILE AUTOMATICALLY GENERATED. DO NOT EDIT.
4 /* $FreeBSD: src/sys/dev/mii/miidevs,v 1.4.2.13 2003/07/22 02:12:55 ps Exp $ */
5 /*$NetBSD: miidevs,v 1.6 1999/05/14 11:37:30 drochner Exp $*/
8 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc.
11 * This code is derived from software contributed to The NetBSD Foundation
12 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
13 * NASA Ames Research Center.
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 * 3. All advertising materials mentioning features or use of this software
24 * must display the following acknowledgement:
25 * This product includes software developed by the NetBSD
26 * Foundation, Inc. and its contributors.
27 * 4. Neither the name of The NetBSD Foundation nor the names of its
28 * contributors may be used to endorse or promote products derived
29 * from this software without specific prior written permission.
31 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
32 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
33 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
34 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
35 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
36 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
37 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
38 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
39 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
40 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
41 * POSSIBILITY OF SUCH DAMAGE.
45 * List of known MII OUIs.
46 * For a complete list see http://standards.ieee.org/regauth/oui/
48 * XXX Vendors do obviously not agree how OUIs (18 bit) are mapped
49 * to the 16 bits available in the id registers. The MII_OUI() macro
50 * in "mii.h" reflects the most obvious way. If a vendor uses a
51 * different mapping, an "xx" prefixed OUI is defined here which is
52 * mangled accordingly to compensate.
55 #define MII_OUI_ALTIMA 0x0010a9 /* Altima Communications */
56 #define MII_OUI_AMD 0x00001a /* Advanced Micro Devices */
57 #define MII_OUI_ATHEROS 0x001374 /* Atheros Communications */
58 #define MII_OUI_BROADCOM 0x001018 /* Broadcom Corporation */
59 #define MII_OUI_BROADCOM2 0x000af7 /* Broadcom Corporation */
60 #define MII_OUI_CICADA 0x0003f1 /* Cicada Semiconductor */
61 #define MII_OUI_DAVICOM 0x00606e /* Davicom Semiconductor */
62 #define MII_OUI_ICS 0x00a0be /* Integrated Circuit Systems */
63 #define MII_OUI_INTEL 0x00aa00 /* Intel */
64 #define MII_OUI_JATO 0x00e083 /* Jato Technologies */
65 #define MII_OUI_JMICRON 0x001b8c /* JMicron Technologies */
66 #define MII_OUI_LEVEL1 0x00207b /* Level 1 */
67 #define MII_OUI_NATSEMI 0x080017 /* National Semiconductor */
68 #define MII_OUI_QUALSEMI 0x006051 /* Quality Semiconductor */
69 #define MII_OUI_REALTEK 0x000020 /* RealTek Semicondctor */
70 #define MII_OUI_REALTEK2 0x00e04c /* RealTek Semicondctor */
71 #define MII_OUI_SEEQ 0x00a07d /* Seeq */
72 #define MII_OUI_AGERE 0x00a0bc /* Agere Systems */
73 #define MII_OUI_SIS 0x00e006 /* Silicon Integrated Systems */
74 #define MII_OUI_TDK 0x00c039 /* TDK */
75 #define MII_OUI_TI 0x080028 /* Texas Instruments */
76 #define MII_OUI_XAQTI 0x00e0ae /* XaQti Corp. */
77 #define MII_OUI_MARVELL 0x005043 /* Marvell Semiconductor */
78 #define MII_OUI_ICPLUS 0x0090c3 /* IC Plus Corp. */
79 #define MII_OUI_VITESSE 0x0001c1 /* Vitesse Semiconductor */
81 /* in the 79c873, AMD uses another OUI (which matches Davicom!) */
82 #define MII_OUI_xxAMD 0x00606e /* Advanced Micro Devices */
84 /* Intel 82553 A/B steppings */
85 #define MII_OUI_xxINTEL 0x00f800 /* Intel */
87 /* some vendors have the bits swapped within bytes
88 (ie, ordered as on the wire) */
89 #define MII_OUI_xxALTIMA 0x000895 /* Altima Communications */
90 #define MII_OUI_xxBROADCOM 0x000818 /* Broadcom Corporation */
91 #define MII_OUI_xxICS 0x00057d /* Integrated Circuit Systems */
92 #define MII_OUI_xxSEEQ 0x0005be /* Seeq */
93 #define MII_OUI_xxSIS 0x000760 /* Silicon Integrated Systems */
94 #define MII_OUI_xxTI 0x100014 /* Texas Instruments */
95 #define MII_OUI_xxXAQTI 0x350700 /* XaQti Corp. */
97 /* Level 1 is completely different - from right to left.
98 (Two bits get lost in the third OUI byte.) */
99 #define MII_OUI_xxLEVEL1 0x1e0400 /* Level 1 */
100 #define MII_OUI_xxLEVEL1a 0x0004de /* Level 1 */
102 /* Don't know what's going on here. */
103 #define MII_OUI_xxDAVICOM 0x006040 /* Davicom Semiconductor */
104 #define MII_OUI_xxBROADCOM2 0x0050ef /* Broadcom Corporation */
105 #define MII_OUI_xxBROADCOM3 0x00d897 /* Broadcom Corporation */
107 /* This is the OUI of the gigE PHY in the RealTek 8211B/8169S/8110S chips */
108 #define MII_OUI_xxREALTEK 0x000732 /* */
110 #define MII_OUI_xxMARVELL 0x000ac2 /* Marvell Semiconductor */
111 #define MII_OUI_xxCICADA 0x00c08f /* Cicada Semiconductor */
114 * List of known models. Grouped by oui.
117 /* Agere Systems PHYs */
118 #define MII_MODEL_AGERE_ET1011C 0x0004
119 #define MII_STR_AGERE_ET1011C "ET1011C 10/100/1000baseT PHY"
121 /* Altima Communications PHYs */
122 #define MII_MODEL_xxALTIMA_AC_UNKNOWN 0x0001
123 #define MII_STR_xxALTIMA_AC_UNKNOWN "AC_UNKNOWN 10/100 media interface"
124 #define MII_MODEL_xxALTIMA_AC101L 0x0012
125 #define MII_STR_xxALTIMA_AC101L "AC101L 10/100 media interface"
126 #define MII_MODEL_xxALTIMA_AC101 0x0021
127 #define MII_STR_xxALTIMA_AC101 "AC101 10/100 media interface"
128 /* AMD Am79C875 have ALTIMA OUI */
129 #define MII_MODEL_xxALTIMA_Am79C875 0x0014
130 #define MII_STR_xxALTIMA_Am79C875 "Am79C875 10/100 media interface"
132 /* Advanced Micro Devices PHYs */
133 #define MII_MODEL_xxAMD_79C873 0x0000
134 #define MII_STR_xxAMD_79C873 "Am79C873 10/100 media interface"
135 #define MII_MODEL_AMD_79c973phy 0x0036
136 #define MII_STR_AMD_79c973phy "Am79c973 internal PHY"
137 #define MII_MODEL_AMD_79c978 0x0039
138 #define MII_STR_AMD_79c978 "Am79c978 HomePNA PHY"
140 /* Atheros Communications/Attansic PHYs. */
141 #define MII_MODEL_ATHEROS_F1 0x0001
142 #define MII_STR_ATHEROS_F1 "Atheros F1 10/100/1000 PHY"
143 #define MII_MODEL_ATHEROS_F2 0x0002
144 #define MII_STR_ATHEROS_F2 "Atheros F2 10/100 PHY"
146 /* Broadcom Corp. PHYs. */
147 #define MII_MODEL_BROADCOM_BCM5400 0x0004
148 #define MII_STR_BROADCOM_BCM5400 "BCM5400 100/1000baseT PHY"
149 #define MII_MODEL_BROADCOM_BCM5401 0x0005
150 #define MII_STR_BROADCOM_BCM5401 "BCM5401 1000baseT PHY"
151 #define MII_MODEL_BROADCOM_BCM5411 0x0007
152 #define MII_STR_BROADCOM_BCM5411 "BCM5411 1000baseT PHY"
153 #define MII_MODEL_BROADCOM_3C905B 0x0012
154 #define MII_STR_BROADCOM_3C905B "Broadcom 3C905B internal PHY"
155 #define MII_MODEL_BROADCOM_3C905C 0x0017
156 #define MII_STR_BROADCOM_3C905C "Broadcom 3C905C internal PHY"
157 #define MII_MODEL_BROADCOM_BCM5221 0x001e
158 #define MII_STR_BROADCOM_BCM5221 "BCM5221 100baseTX PHY"
159 #define MII_MODEL_BROADCOM_BCM5201 0x0021
160 #define MII_STR_BROADCOM_BCM5201 "BCM5201 10/100 PHY"
161 #define MII_MODEL_BROADCOM_BCM5214 0x0028
162 #define MII_STR_BROADCOM_BCM5214 "BCM5214 Quad 10/100 PHY"
163 #define MII_MODEL_BROADCOM_BCM5222 0x0032
164 #define MII_STR_BROADCOM_BCM5222 "BCM5222 Dual 10/100 PHY"
165 #define MII_MODEL_BROADCOM_BCM5220 0x0033
166 #define MII_STR_BROADCOM_BCM5220 "BCM5220 10/100 PHY"
167 #define MII_MODEL_BROADCOM_BCM4401 0x0036
168 #define MII_STR_BROADCOM_BCM4401 "BCM4401 10/100baseTX PHY"
169 #define MII_MODEL_xxBROADCOM_BCM5400 0x0004
170 #define MII_STR_xxBROADCOM_BCM5400 "Broadcom 100/1000baseT PHY"
171 #define MII_MODEL_xxBROADCOM_BCM5401 0x0005
172 #define MII_STR_xxBROADCOM_BCM5401 "BCM5401 10/100/1000baseT PHY"
173 #define MII_MODEL_xxBROADCOM_BCM5411 0x0007
174 #define MII_STR_xxBROADCOM_BCM5411 "BCM5411 10/100/1000baseT PHY"
175 #define MII_MODEL_xxBROADCOM_BCM5464 0x000b
176 #define MII_STR_xxBROADCOM_BCM5464 "BCM5464 10/100/1000baseT PHY"
177 #define MII_MODEL_xxBROADCOM_BCM5461 0x000c
178 #define MII_STR_xxBROADCOM_BCM5461 "BCM5461 10/100/1000baseT PHY"
179 #define MII_MODEL_xxBROADCOM_BCM5462 0x000d
180 #define MII_STR_xxBROADCOM_BCM5462 "BCM5462 10/100/1000baseT PHY"
181 #define MII_MODEL_xxBROADCOM_BCM5421 0x000e
182 #define MII_STR_xxBROADCOM_BCM5421 "BCM5421 10/100/1000baseT PHY"
183 #define MII_MODEL_xxBROADCOM_BCM5752 0x0010
184 #define MII_STR_xxBROADCOM_BCM5752 "BCM5752 10/100/1000baseT PHY"
185 #define MII_MODEL_xxBROADCOM_BCM5701 0x0011
186 #define MII_STR_xxBROADCOM_BCM5701 "BCM5701 10/100/1000baseT PHY"
187 #define MII_MODEL_xxBROADCOM_BCM5706C 0x0015
188 #define MII_STR_xxBROADCOM_BCM5706C "BCM5706C 10/100/1000baseT PHY"
189 #define MII_MODEL_xxBROADCOM_BCM5703 0x0016
190 #define MII_STR_xxBROADCOM_BCM5703 "BCM5703 10/100/1000baseT PHY"
191 #define MII_MODEL_xxBROADCOM_BCM5750 0x0018
192 #define MII_STR_xxBROADCOM_BCM5750 "BCM5750 10/100/1000baseT PHY"
193 #define MII_MODEL_xxBROADCOM_BCM5704 0x0019
194 #define MII_STR_xxBROADCOM_BCM5704 "BCM5704 10/100/1000baseT PHY"
195 #define MII_MODEL_xxBROADCOM_BCM5705 0x001a
196 #define MII_STR_xxBROADCOM_BCM5705 "BCM5705 10/100/1000baseT PHY"
197 #define MII_MODEL_xxBROADCOM_BCM54K2 0x002e
198 #define MII_STR_xxBROADCOM_BCM54K2 "BCM54K2 10/100/1000baseT PHY"
199 #define MII_MODEL_xxBROADCOM_BCM5714 0x0034
200 #define MII_STR_xxBROADCOM_BCM5714 "BCM5714 10/100/1000baseT PHY"
201 #define MII_MODEL_xxBROADCOM_BCM5780 0x0035
202 #define MII_STR_xxBROADCOM_BCM5780 "BCM5780 10/100/1000baseT PHY"
203 #define MII_MODEL_xxBROADCOM_BCM5708C 0x0036
204 #define MII_STR_xxBROADCOM_BCM5708C "BCM5708C 10/100/1000baseT PHY"
205 #define MII_MODEL_xxBROADCOM2_BCM54XX 0x0007
206 #define MII_STR_xxBROADCOM2_BCM54XX "BCM54XX 10/100/1000baseT PHY"
207 #define MII_MODEL_xxBROADCOM2_BCM5481 0x000a
208 #define MII_STR_xxBROADCOM2_BCM5481 "BCM5481 10/100/1000baseT PHY"
209 #define MII_MODEL_xxBROADCOM2_BCM5482 0x000b
210 #define MII_STR_xxBROADCOM2_BCM5482 "BCM5482 10/100/1000baseT PHY"
211 #define MII_MODEL_xxBROADCOM2_BCM5755 0x000c
212 #define MII_STR_xxBROADCOM2_BCM5755 "BCM5755 10/100/1000baseT PHY"
213 #define MII_MODEL_xxBROADCOM2_BCM5787 0x000e
214 #define MII_STR_xxBROADCOM2_BCM5787 "BCM5787 10/100/1000baseT PHY"
215 #define MII_MODEL_xxBROADCOM2_BCM5708S 0x0015
216 #define MII_STR_xxBROADCOM2_BCM5708S "BCM5708S 1000/2500baseSX PHY"
217 #define MII_MODEL_xxBROADCOM2_BCM5709CAX 0x002c
218 #define MII_STR_xxBROADCOM2_BCM5709CAX "BCM5709C(AX) 10/100/1000baseT PHY"
219 #define MII_MODEL_xxBROADCOM2_BCM5722 0x002d
220 #define MII_STR_xxBROADCOM2_BCM5722 "BCM5722 10/100/1000baseT PHY"
221 #define MII_MODEL_xxBROADCOM2_BCM5784 0x003a
222 #define MII_STR_xxBROADCOM2_BCM5784 "BCM5784 10/100/1000baseT PHY"
223 #define MII_MODEL_xxBROADCOM2_BCM5709C 0x003c
224 #define MII_STR_xxBROADCOM2_BCM5709C "BCM5709C 10/100/1000baseT PHY"
225 #define MII_MODEL_xxBROADCOM2_BCM5761 0x003d
226 #define MII_STR_xxBROADCOM2_BCM5761 "BCM5761 10/100/1000baseT PHY"
227 #define MII_MODEL_xxBROADCOM2_BCM5709S 0x003f
228 #define MII_STR_xxBROADCOM2_BCM5709S "BCM5709S 1000/2500baseSX PHY"
229 #define MII_MODEL_xxBROADCOM3_BCM57780 0x0019
230 #define MII_STR_xxBROADCOM3_BCM57780 "BCM57780 10/100/1000baseT PHY"
231 #define MII_MODEL_xxBROADCOM3_BCM5717C 0x0020
232 #define MII_STR_xxBROADCOM3_BCM5717C "BCM5717C 10/100/1000baseT PHY"
233 #define MII_MODEL_xxBROADCOM3_BCM5719C 0x0022
234 #define MII_STR_xxBROADCOM3_BCM5719C "BCM5719C 10/100/1000baseT PHY"
235 #define MII_MODEL_xxBROADCOM3_BCM57765 0x0024
236 #define MII_STR_xxBROADCOM3_BCM57765 "BCM57765 10/100/1000baseT PHY"
237 #define MII_MODEL_BROADCOM2_BCM5906 0x0004
238 #define MII_STR_BROADCOM2_BCM5906 "BCM5906 10/100baseTX PHY"
240 /* Cicada Semiconductor PHYs (now owned by Vitesse?) */
241 #define MII_MODEL_CICADA_CS8201 0x0001
242 #define MII_STR_CICADA_CS8201 "Cicada CS8201 10/100/1000T PHY"
243 #define MII_MODEL_CICADA_CS8201A 0x0020
244 #define MII_STR_CICADA_CS8201A "Cicada CS8201 10/100/1000T PHY"
245 #define MII_MODEL_CICADA_CS8201B 0x0021
246 #define MII_STR_CICADA_CS8201B "Cicada CS8201 10/100/1000T PHY"
247 #define MII_MODEL_xxCICADA_CS8201 0x0001
248 #define MII_STR_xxCICADA_CS8201 "Cicada CS8201 10/100/1000T PHY"
249 #define MII_MODEL_xxCICADA_CS8201A 0x0020
250 #define MII_STR_xxCICADA_CS8201A "Cicada CS8201 10/100/1000T PHY"
251 #define MII_MODEL_xxCICADA_CS8201B 0x0021
252 #define MII_STR_xxCICADA_CS8201B "Cicada CS8201 10/100/1000T PHY"
254 /* Davicom Semiconductor PHYs */
255 #define MII_MODEL_xxDAVICOM_DM9101 0x0000
256 #define MII_STR_xxDAVICOM_DM9101 "DM9101 10/100 media interface"
257 #define MII_MODEL_DAVICOM_DM9102 0x0004
258 #define MII_STR_DAVICOM_DM9102 "DM9102 10/100 media interface"
259 #define MII_MODEL_DAVICOM_DM9601 0x000c
260 #define MII_STR_DAVICOM_DM9601 "DM9601 10/100 media interface"
262 /* Integrated Circuit Systems PHYs */
263 #define MII_MODEL_xxICS_1890 0x0002
264 #define MII_STR_xxICS_1890 "ICS1890 10/100 media interface"
267 #define MII_MODEL_xxINTEL_I82553AB 0x0000
268 #define MII_STR_xxINTEL_I82553AB "i83553 10/100 media interface"
269 #define MII_MODEL_INTEL_I82555 0x0015
270 #define MII_STR_INTEL_I82555 "i82555 10/100 media interface"
271 #define MII_MODEL_INTEL_I82562EM 0x0032
272 #define MII_STR_INTEL_I82562EM "i82562EM 10/100 media interface"
273 #define MII_MODEL_INTEL_I82562ET 0x0033
274 #define MII_STR_INTEL_I82562ET "i82562ET 10/100 media interface"
275 #define MII_MODEL_INTEL_I82553C 0x0035
276 #define MII_STR_INTEL_I82553C "i82553 10/100 media interface"
278 /* Jato Technologies PHYs */
279 #define MII_MODEL_JATO_BASEX 0x0000
280 #define MII_STR_JATO_BASEX "Jato 1000baseX media interface"
282 /* JMicron Technologies PHYs */
283 #define MII_MODEL_JMICRON_JMP211 0x0021
284 #define MII_STR_JMICRON_JMP211 "JMP211 10/100/1000 media interface"
285 #define MII_MODEL_JMICRON_JMP202 0x0022
286 #define MII_STR_JMICRON_JMP202 "JMP202 10/100 media interface"
289 #define MII_MODEL_xxLEVEL1_LXT970 0x0000
290 #define MII_STR_xxLEVEL1_LXT970 "LXT970 10/100 media interface"
291 #define MII_MODEL_xxLEVEL1a_LXT971 0x000e
292 #define MII_STR_xxLEVEL1a_LXT971 "LXT971 10/100 media interface"
294 /* National Semiconductor PHYs */
295 #define MII_MODEL_NATSEMI_DP83840 0x0000
296 #define MII_STR_NATSEMI_DP83840 "DP83840 10/100 media interface"
297 #define MII_MODEL_NATSEMI_DP83843 0x0001
298 #define MII_STR_NATSEMI_DP83843 "DP83843 10/100 media interface"
299 #define MII_MODEL_NATSEMI_DP83891 0x0005
300 #define MII_STR_NATSEMI_DP83891 "DP83891 10/100/1000 media interface"
301 #define MII_MODEL_NATSEMI_DP83861 0x0006
302 #define MII_STR_NATSEMI_DP83861 "DP83861 10/100/1000 media interface"
304 /* Quality Semiconductor PHYs */
305 #define MII_MODEL_QUALSEMI_QS6612 0x0000
306 #define MII_STR_QUALSEMI_QS6612 "QS6612 10/100 media interface"
308 /* RealTek Semiconductor PHYs */
309 #define MII_MODEL_REALTEK_RTL8201L 0x0020
310 #define MII_STR_REALTEK_RTL8201L "RTL8201L 10/100 media interface"
311 #define MII_MODEL_xxREALTEK_RTL8169S 0x0011
312 #define MII_STR_xxREALTEK_RTL8169S "8211B/RTL8169S/8110S media interface"
313 #define MII_MODEL_REALTEK2_RTL8169S 0x0011
314 #define MII_STR_REALTEK2_RTL8169S "RTL8169S/8110S media interface"
317 #define MII_MODEL_xxSEEQ_80220 0x0003
318 #define MII_STR_xxSEEQ_80220 "Seeq 80220 10/100 media interface"
319 #define MII_MODEL_xxSEEQ_84220 0x0004
320 #define MII_STR_xxSEEQ_84220 "Seeq 84220 10/100 media interface"
322 /* Silicon Integrated Systems PHYs */
323 #define MII_MODEL_xxSIS_900 0x0000
324 #define MII_STR_xxSIS_900 "SiS 900 10/100 media interface"
327 #define MII_MODEL_TDK_78Q2120 0x0014
328 #define MII_STR_TDK_78Q2120 "TDK 78Q2120 media interface"
330 /* Texas Instruments PHYs */
331 #define MII_MODEL_xxTI_TLAN10T 0x0001
332 #define MII_STR_xxTI_TLAN10T "ThunderLAN 10baseT media interface"
333 #define MII_MODEL_xxTI_100VGPMI 0x0002
334 #define MII_STR_xxTI_100VGPMI "ThunderLAN 100VG-AnyLan media interface"
336 /* XaQti Corp. PHYs. */
337 #define MII_MODEL_xxXAQTI_XMACII 0x0000
338 #define MII_STR_xxXAQTI_XMACII "XaQti Corp. XMAC II gigabit interface"
340 /* Marvell Semiconductor PHYs */
341 #define MII_MODEL_MARVELL_E1000 0x0000
342 #define MII_STR_MARVELL_E1000 "Marvell Semiconductor 88E1000* gigabit PHY"
343 #define MII_MODEL_MARVELL_E1011 0x0002
344 #define MII_STR_MARVELL_E1011 "Marvell Semiconductor 88E1011 Gigabit PHY"
345 #define MII_MODEL_MARVELL_E1000_3 0x0003
346 #define MII_STR_MARVELL_E1000_3 "Marvell 88E1000 Gigabit PHY"
347 #define MII_MODEL_MARVELL_E1000S 0x0004
348 #define MII_STR_MARVELL_E1000S "Marvell 88E1000S Gigabit PHY"
349 #define MII_MODEL_MARVELL_E1000_5 0x0005
350 #define MII_STR_MARVELL_E1000_5 "Marvell 88E1000 Gigabit PHY"
351 #define MII_MODEL_MARVELL_E1101 0x0006
352 #define MII_STR_MARVELL_E1101 "Marvell 88E1101 Gigabit PHY"
353 #define MII_MODEL_MARVELL_E3082 0x0008
354 #define MII_STR_MARVELL_E3082 "Marvell 88E3082 10/100 PHY"
355 #define MII_MODEL_MARVELL_E1112 0x0009
356 #define MII_STR_MARVELL_E1112 "Marvell 88E1112 Gigabit PHY"
357 #define MII_MODEL_MARVELL_E1149 0x000b
358 #define MII_STR_MARVELL_E1149 "Marvell 88E1149 Gigabit PHY"
359 #define MII_MODEL_MARVELL_E1111 0x000c
360 #define MII_STR_MARVELL_E1111 "Marvell 88E1111 Gigabit PHY"
361 #define MII_MODEL_MARVELL_E1116 0x0021
362 #define MII_STR_MARVELL_E1116 "Marvell 88E1116 Gigabit PHY"
363 #define MII_MODEL_MARVELL_E1118 0x0022
364 #define MII_STR_MARVELL_E1118 "Marvell 88E1118 Gigabit PHY"
365 #define MII_MODEL_MARVELL_E1116R 0x0024
366 #define MII_STR_MARVELL_E1116R "Marvell 88E1116R Gigabit PHY"
367 #define MII_MODEL_MARVELL_E1149R 0x0025
368 #define MII_STR_MARVELL_E1149R "Marvell 88E1149R Quad Gigabit PHY"
369 #define MII_MODEL_MARVELL_E3016 0x0026
370 #define MII_STR_MARVELL_E3016 "Marvell 88E3016 10/100 PHY"
371 #define MII_MODEL_MARVELL_PHYG65G 0x0027
372 #define MII_STR_MARVELL_PHYG65G "Marvell PHYG65G Gigabit PHY"
373 #define MII_MODEL_xxMARVELL_E1011 0x0002
374 #define MII_STR_xxMARVELL_E1011 "Marvell 88E1000 Gigabit PHY"
375 #define MII_MODEL_xxMARVELL_E1000_3 0x0003
376 #define MII_STR_xxMARVELL_E1000_3 "Marvell 88E1000 Gigabit PHY"
377 #define MII_MODEL_xxMARVELL_E1000_5 0x0005
378 #define MII_STR_xxMARVELL_E1000_5 "Marvell 88E1000 Gigabit PHY"
379 #define MII_MODEL_xxMARVELL_E1111 0x000c
380 #define MII_STR_xxMARVELL_E1111 "Marvell 88E1111 Gigabit PHY"
382 /* IC Plus Corp. PHYs */
383 #define MII_MODEL_ICPLUS_IP101 0x0005
384 #define MII_STR_ICPLUS_IP101 "IP101 10/100 PHY"
385 #define MII_MODEL_ICPLUS_IP1000A 0x0008
386 #define MII_STR_ICPLUS_IP1000A "IC Plus 10/100/1000 media interface"
388 /* Vitesse Semiconductor PHYs */
389 #define MII_MODEL_VITESSE_VSC8601 0x0002
390 #define MII_STR_VITESSE_VSC8601 "VSC8601 10/100/1000TX PHY"