2 * Copyright (c) 1995, David Greenman
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * $FreeBSD: src/sys/dev/ed/if_ed.c,v 1.224 2003/12/08 07:54:12 obrien Exp $
28 * $DragonFly: src/sys/dev/netif/ed/if_ed.c,v 1.19 2005/02/15 20:26:29 joerg Exp $
32 * Device driver for National Semiconductor DS8390/WD83C690 based ethernet
33 * adapters. By David Greenman, 29-April-1993
35 * Currently supports the Western Digital/SMC 8003 and 8013 series,
36 * the SMC Elite Ultra (8216), the 3Com 3c503, the NE1000 and NE2000,
37 * and a variety of similar clones.
43 #include <sys/param.h>
44 #include <sys/systm.h>
45 #include <sys/sockio.h>
47 #include <sys/kernel.h>
48 #include <sys/socket.h>
49 #include <sys/syslog.h>
51 #include <sys/module.h>
54 #include <machine/bus.h>
56 #include <machine/resource.h>
58 #include <net/ethernet.h>
60 #include <net/ifq_var.h>
61 #include <net/if_arp.h>
62 #include <net/if_dl.h>
63 #include <net/if_mib.h>
64 #include <net/if_media.h>
67 #include <dev/netif/mii_layer/mii.h>
68 #include <dev/netif/mii_layer/miivar.h>
73 #include <net/bridge/bridge.h>
75 #include <machine/md_var.h>
80 devclass_t ed_devclass;
82 static void ed_init (void *);
83 static int ed_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
84 static void ed_start (struct ifnet *);
85 static void ed_reset (struct ifnet *);
86 static void ed_watchdog (struct ifnet *);
88 static void ed_tick (void *);
91 static void ds_getmcaf (struct ed_softc *, u_int32_t *);
93 static void ed_get_packet (struct ed_softc *, char *, /* u_short */ int);
95 static __inline void ed_rint (struct ed_softc *);
96 static __inline void ed_xmit (struct ed_softc *);
97 static __inline char * ed_ring_copy (struct ed_softc *, char *, char *,
99 static void ed_hpp_set_physical_link (struct ed_softc *);
100 static void ed_hpp_readmem (struct ed_softc *, int, unsigned char *,
102 static void ed_hpp_writemem (struct ed_softc *, unsigned char *,
103 /* u_short */ int, /* u_short */ int);
104 static u_short ed_hpp_write_mbufs (struct ed_softc *, struct mbuf *,
107 static u_short ed_pio_write_mbufs (struct ed_softc *, struct mbuf *,
110 static void ed_setrcr (struct ed_softc *);
112 static uint32_t ds_mchash (const uint8_t *);
114 DECLARE_DUMMY_MODULE(if_ed);
117 * Interrupt conversion table for WD/SMC ASIC/83C584
119 static unsigned short ed_intr_val[] = {
131 * Interrupt conversion table for 83C790
133 static unsigned short ed_790_intr_val[] = {
145 * Interrupt conversion table for the HP PC LAN+
148 static unsigned short ed_hpp_intr_val[] = {
168 * Generic probe routine for testing for the existance of a DS8390.
169 * Must be called after the NIC has just been reset. This routine
170 * works by looking at certain register values that are guaranteed
171 * to be initialized a certain way after power-up or reset. Seems
172 * not to currently work on the 83C690.
176 * Register reset bits set bits
177 * Command Register (CR) TXP, STA RD2, STP
178 * Interrupt Status (ISR) RST
179 * Interrupt Mask (IMR) All bits
180 * Data Control (DCR) LAS
181 * Transmit Config. (TCR) LB1, LB0
183 * We only look at the CR and ISR registers, however, because looking at
184 * the others would require changing register pages (which would be
185 * intrusive if this isn't an 8390).
187 * Return 1 if 8390 was found, 0 if not.
191 ed_probe_generic8390(sc)
194 if ((ed_nic_inb(sc, ED_P0_CR) &
195 (ED_CR_RD2 | ED_CR_TXP | ED_CR_STA | ED_CR_STP)) !=
196 (ED_CR_RD2 | ED_CR_STP))
198 if ((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) != ED_ISR_RST)
205 * Probe and vendor-specific initialization routine for SMC/WD80x3 boards
208 ed_probe_WD80x3_generic(dev, flags, intr_vals)
211 unsigned short *intr_vals[];
213 struct ed_softc *sc = device_get_softc(dev);
216 u_int memsize, maddr;
217 u_char iptr, isa16bit, sum, totalsum;
218 u_long conf_maddr, conf_msize, irq, junk;
220 sc->chip_type = ED_CHIP_TYPE_DP8390;
222 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_TOSH_ETHER) {
223 totalsum = ED_WD_ROM_CHECKSUM_TOTAL_TOSH_ETHER;
224 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_POW);
228 totalsum = ED_WD_ROM_CHECKSUM_TOTAL;
231 * Attempt to do a checksum over the station address PROM. If it
232 * fails, it's probably not a SMC/WD board. There is a problem with
233 * this, though: some clone WD boards don't pass the checksum test.
234 * Danpex boards for one.
236 for (sum = 0, i = 0; i < 8; ++i)
237 sum += ed_asic_inb(sc, ED_WD_PROM + i);
239 if (sum != totalsum) {
242 * Checksum is invalid. This often happens with cheap WD8003E
243 * clones. In this case, the checksum byte (the eighth byte)
244 * seems to always be zero.
246 if (ed_asic_inb(sc, ED_WD_CARD_ID) != ED_TYPE_WD8003E ||
247 ed_asic_inb(sc, ED_WD_PROM + 7) != 0)
250 /* reset card to force it into a known state. */
251 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_TOSH_ETHER)
252 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_RST | ED_WD_MSR_POW);
254 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_RST);
257 ed_asic_outb(sc, ED_WD_MSR, ed_asic_inb(sc, ED_WD_MSR) & ~ED_WD_MSR_RST);
258 /* wait in the case this card is reading its EEROM */
261 sc->vendor = ED_VENDOR_WD_SMC;
262 sc->type = ed_asic_inb(sc, ED_WD_CARD_ID);
265 * Set initial values for width/size.
270 case ED_TYPE_WD8003S:
271 sc->type_str = "WD8003S";
273 case ED_TYPE_WD8003E:
274 sc->type_str = "WD8003E";
276 case ED_TYPE_WD8003EB:
277 sc->type_str = "WD8003EB";
279 case ED_TYPE_WD8003W:
280 sc->type_str = "WD8003W";
282 case ED_TYPE_WD8013EBT:
283 sc->type_str = "WD8013EBT";
287 case ED_TYPE_WD8013W:
288 sc->type_str = "WD8013W";
292 case ED_TYPE_WD8013EP: /* also WD8003EP */
293 if (ed_asic_inb(sc, ED_WD_ICR) & ED_WD_ICR_16BIT) {
296 sc->type_str = "WD8013EP";
298 sc->type_str = "WD8003EP";
301 case ED_TYPE_WD8013WC:
302 sc->type_str = "WD8013WC";
306 case ED_TYPE_WD8013EBP:
307 sc->type_str = "WD8013EBP";
311 case ED_TYPE_WD8013EPC:
312 sc->type_str = "WD8013EPC";
316 case ED_TYPE_SMC8216C: /* 8216 has 16K shared mem -- 8416 has 8K */
317 case ED_TYPE_SMC8216T:
318 if (sc->type == ED_TYPE_SMC8216C) {
319 sc->type_str = "SMC8216/SMC8216C";
321 sc->type_str = "SMC8216T";
324 ed_asic_outb(sc, ED_WD790_HWR,
325 ed_asic_inb(sc, ED_WD790_HWR) | ED_WD790_HWR_SWH);
326 switch (ed_asic_inb(sc, ED_WD790_RAR) & ED_WD790_RAR_SZ64) {
327 case ED_WD790_RAR_SZ64:
330 case ED_WD790_RAR_SZ32:
333 case ED_WD790_RAR_SZ16:
336 case ED_WD790_RAR_SZ8:
337 /* 8216 has 16K shared mem -- 8416 has 8K */
338 if (sc->type == ED_TYPE_SMC8216C) {
339 sc->type_str = "SMC8416C/SMC8416BT";
341 sc->type_str = "SMC8416T";
346 ed_asic_outb(sc, ED_WD790_HWR,
347 ed_asic_inb(sc, ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
350 sc->chip_type = ED_CHIP_TYPE_WD790;
352 case ED_TYPE_TOSHIBA1:
353 sc->type_str = "Toshiba1";
357 case ED_TYPE_TOSHIBA4:
358 sc->type_str = "Toshiba4";
368 * Make some adjustments to initial values depending on what is found
371 if (isa16bit && (sc->type != ED_TYPE_WD8013EBT)
372 && (sc->type != ED_TYPE_TOSHIBA1) && (sc->type != ED_TYPE_TOSHIBA4)
373 && ((ed_asic_inb(sc, ED_WD_ICR) & ED_WD_ICR_16BIT) == 0)) {
378 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
379 &conf_maddr, &conf_msize);
384 printf("type = %x type_str=%s isa16bit=%d memsize=%d id_msize=%d\n",
385 sc->type, sc->type_str, isa16bit, memsize, conf_msize);
386 for (i = 0; i < 8; i++)
387 printf("%x -> %x\n", i, ed_asic_inb(sc, i));
391 * Allow the user to override the autoconfiguration
394 memsize = conf_msize;
397 if (maddr < 0xa0000 || maddr + memsize > 0x1000000) {
398 device_printf(dev, "Invalid ISA memory address range configured: 0x%x - 0x%x\n",
399 maddr, maddr + memsize);
404 * (note that if the user specifies both of the following flags that
405 * '8bit' mode intentionally has precedence)
407 if (flags & ED_FLAGS_FORCE_16BIT_MODE)
409 if (flags & ED_FLAGS_FORCE_8BIT_MODE)
413 * If possible, get the assigned interrupt number from the card and
416 if ((sc->type & ED_WD_SOFTCONFIG) &&
417 (sc->chip_type != ED_CHIP_TYPE_WD790)) {
420 * Assemble together the encoded interrupt number.
422 iptr = (ed_asic_inb(sc, ED_WD_ICR) & ED_WD_ICR_IR2) |
423 ((ed_asic_inb(sc, ED_WD_IRR) &
424 (ED_WD_IRR_IR0 | ED_WD_IRR_IR1)) >> 5);
427 * If no interrupt specified (or "?"), use what the board tells us.
429 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
431 if (error && intr_vals[0] != NULL) {
432 error = bus_set_resource(dev, SYS_RES_IRQ, 0,
433 intr_vals[0][iptr], 1);
439 * Enable the interrupt.
441 ed_asic_outb(sc, ED_WD_IRR,
442 ed_asic_inb(sc, ED_WD_IRR) | ED_WD_IRR_IEN);
444 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
445 ed_asic_outb(sc, ED_WD790_HWR,
446 ed_asic_inb(sc, ED_WD790_HWR) | ED_WD790_HWR_SWH);
447 iptr = (((ed_asic_inb(sc, ED_WD790_GCR) & ED_WD790_GCR_IR2) >> 4) |
448 (ed_asic_inb(sc, ED_WD790_GCR) &
449 (ED_WD790_GCR_IR1 | ED_WD790_GCR_IR0)) >> 2);
450 ed_asic_outb(sc, ED_WD790_HWR,
451 ed_asic_inb(sc, ED_WD790_HWR) & ~ED_WD790_HWR_SWH);
454 * If no interrupt specified (or "?"), use what the board tells us.
456 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
458 if (error && intr_vals[1] != NULL) {
459 error = bus_set_resource(dev, SYS_RES_IRQ, 0,
460 intr_vals[1][iptr], 1);
468 ed_asic_outb(sc, ED_WD790_ICR,
469 ed_asic_inb(sc, ED_WD790_ICR) | ED_WD790_ICR_EIL);
471 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
474 device_printf(dev, "%s cards don't support auto-detected/assigned interrupts.\n",
478 sc->isa16bit = isa16bit;
481 error = ed_alloc_memory(dev, 0, memsize);
483 printf("*** ed_alloc_memory() failed! (%d)\n", error);
486 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res);
489 * allocate one xmit buffer if < 16k, two buffers otherwise
491 if ((memsize < 16384) ||
492 (flags & ED_FLAGS_NO_MULTI_BUFFERING)) {
497 sc->tx_page_start = ED_WD_PAGE_OFFSET;
498 sc->rec_page_start = ED_WD_PAGE_OFFSET + ED_TXBUF_SIZE * sc->txb_cnt;
499 sc->rec_page_stop = ED_WD_PAGE_OFFSET + memsize / ED_PAGE_SIZE;
500 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * sc->rec_page_start);
501 sc->mem_size = memsize;
502 sc->mem_end = sc->mem_start + memsize;
505 * Get station address from on-board ROM
507 for (i = 0; i < ETHER_ADDR_LEN; ++i)
508 sc->arpcom.ac_enaddr[i] = ed_asic_inb(sc, ED_WD_PROM + i);
511 * Set upper address bits and 8/16 bit access to shared memory.
514 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
515 sc->wd_laar_proto = ed_asic_inb(sc, ED_WD_LAAR);
517 sc->wd_laar_proto = ED_WD_LAAR_L16EN |
518 ((kvtop(sc->mem_start) >> 19) & ED_WD_LAAR_ADDRHI);
521 * Enable 16bit access
523 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto |
526 if (((sc->type & ED_WD_SOFTCONFIG) ||
527 (sc->type == ED_TYPE_TOSHIBA1) ||
528 (sc->type == ED_TYPE_TOSHIBA4) ||
529 (sc->type == ED_TYPE_WD8013EBT)) &&
530 (sc->chip_type != ED_CHIP_TYPE_WD790)) {
531 sc->wd_laar_proto = (kvtop(sc->mem_start) >> 19) &
533 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto);
538 * Set address and enable interface shared memory.
540 if (sc->chip_type != ED_CHIP_TYPE_WD790) {
541 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_TOSH_ETHER) {
542 ed_asic_outb(sc, ED_WD_MSR + 1,
543 ((kvtop(sc->mem_start) >> 8) & 0xe0) | 4);
544 ed_asic_outb(sc, ED_WD_MSR + 2,
545 ((kvtop(sc->mem_start) >> 16) & 0x0f));
546 ed_asic_outb(sc, ED_WD_MSR,
547 ED_WD_MSR_MENB | ED_WD_MSR_POW);
549 ed_asic_outb(sc, ED_WD_MSR,
550 ((kvtop(sc->mem_start) >> 13) &
551 ED_WD_MSR_ADDR) | ED_WD_MSR_MENB);
553 sc->cr_proto = ED_CR_RD2;
555 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_MENB);
556 ed_asic_outb(sc, ED_WD790_HWR, (ed_asic_inb(sc, ED_WD790_HWR) | ED_WD790_HWR_SWH));
557 ed_asic_outb(sc, ED_WD790_RAR, ((kvtop(sc->mem_start) >> 13) & 0x0f) |
558 ((kvtop(sc->mem_start) >> 11) & 0x40) |
559 (ed_asic_inb(sc, ED_WD790_RAR) & 0xb0));
560 ed_asic_outb(sc, ED_WD790_HWR, (ed_asic_inb(sc, ED_WD790_HWR) & ~ED_WD790_HWR_SWH));
565 printf("starting memory performance test at 0x%x, size %d...\n",
566 sc->mem_start, memsize*16384);
567 for (i = 0; i < 16384; i++)
568 bzero(sc->mem_start, memsize);
569 printf("***DONE***\n");
573 * Now zero memory and verify that it is clear
575 bzero(sc->mem_start, memsize);
577 for (i = 0; i < memsize; ++i) {
578 if (sc->mem_start[i]) {
579 device_printf(dev, "failed to clear shared memory at %llx - check configuration\n",
580 (long long)kvtop(sc->mem_start + i));
583 * Disable 16 bit access to shared memory
586 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
587 ed_asic_outb(sc, ED_WD_MSR, 0x00);
589 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto &
597 * Disable 16bit access to shared memory - we leave it
598 * disabled so that 1) machines reboot properly when the board
599 * is set 16 bit mode and there are conflicting 8bit
600 * devices/ROMS in the same 128k address space as this boards
601 * shared memory. and 2) so that other 8 bit devices with
602 * shared memory can be used in this 128k region, too.
605 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
606 ed_asic_outb(sc, ED_WD_MSR, 0x00);
608 ed_asic_outb(sc, ED_WD_LAAR, sc->wd_laar_proto &
615 ed_probe_WD80x3(dev, port_rid, flags)
620 struct ed_softc *sc = device_get_softc(dev);
622 static unsigned short *intr_vals[] = {ed_intr_val, ed_790_intr_val};
624 error = ed_alloc_port(dev, port_rid, ED_WD_IO_PORTS);
628 sc->asic_offset = ED_WD_ASIC_OFFSET;
629 sc->nic_offset = ED_WD_NIC_OFFSET;
631 return ed_probe_WD80x3_generic(dev, flags, intr_vals);
635 * Probe and vendor-specific initialization routine for 3Com 3c503 boards
638 ed_probe_3Com(dev, port_rid, flags)
643 struct ed_softc *sc = device_get_softc(dev);
648 u_long conf_maddr, conf_msize, irq, junk;
650 error = ed_alloc_port(dev, 0, ED_3COM_IO_PORTS);
654 sc->asic_offset = ED_3COM_ASIC_OFFSET;
655 sc->nic_offset = ED_3COM_NIC_OFFSET;
658 * Verify that the kernel configured I/O address matches the board
661 switch (ed_asic_inb(sc, ED_3COM_BCFR)) {
662 case ED_3COM_BCFR_300:
663 if (rman_get_start(sc->port_res) != 0x300)
666 case ED_3COM_BCFR_310:
667 if (rman_get_start(sc->port_res) != 0x310)
670 case ED_3COM_BCFR_330:
671 if (rman_get_start(sc->port_res) != 0x330)
674 case ED_3COM_BCFR_350:
675 if (rman_get_start(sc->port_res) != 0x350)
678 case ED_3COM_BCFR_250:
679 if (rman_get_start(sc->port_res) != 0x250)
682 case ED_3COM_BCFR_280:
683 if (rman_get_start(sc->port_res) != 0x280)
686 case ED_3COM_BCFR_2A0:
687 if (rman_get_start(sc->port_res) != 0x2a0)
690 case ED_3COM_BCFR_2E0:
691 if (rman_get_start(sc->port_res) != 0x2e0)
698 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
699 &conf_maddr, &conf_msize);
704 * Verify that the kernel shared memory address matches the board
705 * configured address.
707 switch (ed_asic_inb(sc, ED_3COM_PCFR)) {
708 case ED_3COM_PCFR_DC000:
709 if (conf_maddr != 0xdc000)
712 case ED_3COM_PCFR_D8000:
713 if (conf_maddr != 0xd8000)
716 case ED_3COM_PCFR_CC000:
717 if (conf_maddr != 0xcc000)
720 case ED_3COM_PCFR_C8000:
721 if (conf_maddr != 0xc8000)
730 * Reset NIC and ASIC. Enable on-board transceiver throughout reset
731 * sequence because it'll lock up if the cable isn't connected if we
734 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_RST | ED_3COM_CR_XSEL);
737 * Wait for a while, then un-reset it
742 * The 3Com ASIC defaults to rather strange settings for the CR after
743 * a reset - it's important to set it again after the following outb
744 * (this is done when we map the PROM below).
746 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
749 * Wait a bit for the NIC to recover from the reset
753 sc->vendor = ED_VENDOR_3COM;
754 sc->type_str = "3c503";
756 sc->cr_proto = ED_CR_RD2;
759 * Hmmm...a 16bit 3Com board has 16k of memory, but only an 8k window
765 * Get station address from on-board ROM
769 * First, map ethernet address PROM over the top of where the NIC
770 * registers normally appear.
772 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_EALO | ED_3COM_CR_XSEL);
774 for (i = 0; i < ETHER_ADDR_LEN; ++i)
775 sc->arpcom.ac_enaddr[i] = ed_nic_inb(sc, i);
778 * Unmap PROM - select NIC registers. The proper setting of the
779 * tranceiver is set in ed_init so that the attach code is given a
780 * chance to set the default based on a compile-time config option
782 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
785 * Determine if this is an 8bit or 16bit board
789 * select page 0 registers
791 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STP);
794 * Attempt to clear WTS bit. If it doesn't clear, then this is a 16bit
797 ed_nic_outb(sc, ED_P0_DCR, 0);
800 * select page 2 registers
802 ed_nic_outb(sc, ED_P0_CR, ED_CR_PAGE_2 | ED_CR_RD2 | ED_CR_STP);
805 * The 3c503 forces the WTS bit to a one if this is a 16bit board
807 if (ed_nic_inb(sc, ED_P2_DCR) & ED_DCR_WTS)
813 * select page 0 registers
815 ed_nic_outb(sc, ED_P2_CR, ED_CR_RD2 | ED_CR_STP);
817 error = ed_alloc_memory(dev, 0, memsize);
821 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res);
822 sc->mem_size = memsize;
823 sc->mem_end = sc->mem_start + memsize;
826 * We have an entire 8k window to put the transmit buffers on the
827 * 16bit boards. But since the 16bit 3c503's shared memory is only
828 * fast enough to overlap the loading of one full-size packet, trying
829 * to load more than 2 buffers can actually leave the transmitter idle
830 * during the load. So 2 seems the best value. (Although a mix of
831 * variable-sized packets might change this assumption. Nonetheless,
832 * we optimize for linear transfers of same-size packets.)
835 if (flags & ED_FLAGS_NO_MULTI_BUFFERING)
840 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_16BIT;
841 sc->rec_page_start = ED_3COM_RX_PAGE_OFFSET_16BIT;
842 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
843 ED_3COM_RX_PAGE_OFFSET_16BIT;
844 sc->mem_ring = sc->mem_start;
847 sc->tx_page_start = ED_3COM_TX_PAGE_OFFSET_8BIT;
848 sc->rec_page_start = ED_TXBUF_SIZE + ED_3COM_TX_PAGE_OFFSET_8BIT;
849 sc->rec_page_stop = memsize / ED_PAGE_SIZE +
850 ED_3COM_TX_PAGE_OFFSET_8BIT;
851 sc->mem_ring = sc->mem_start + (ED_PAGE_SIZE * ED_TXBUF_SIZE);
854 sc->isa16bit = isa16bit;
857 * Initialize GA page start/stop registers. Probably only needed if
858 * doing DMA, but what the hell.
860 ed_asic_outb(sc, ED_3COM_PSTR, sc->rec_page_start);
861 ed_asic_outb(sc, ED_3COM_PSPR, sc->rec_page_stop);
864 * Set IRQ. 3c503 only allows a choice of irq 2-5.
866 error = bus_get_resource(dev, SYS_RES_IRQ, 0, &irq, &junk);
873 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ2);
876 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ3);
879 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ4);
882 ed_asic_outb(sc, ED_3COM_IDCFR, ED_3COM_IDCFR_IRQ5);
885 device_printf(dev, "Invalid irq configuration (%ld) must be 3-5,9 for 3c503\n",
891 * Initialize GA configuration register. Set bank and enable shared
894 ed_asic_outb(sc, ED_3COM_GACFR, ED_3COM_GACFR_RSEL |
898 * Initialize "Vector Pointer" registers. These gawd-awful things are
899 * compared to 20 bits of the address on ISA, and if they match, the
900 * shared memory is disabled. We set them to 0xffff0...allegedly the
903 ed_asic_outb(sc, ED_3COM_VPTR2, 0xff);
904 ed_asic_outb(sc, ED_3COM_VPTR1, 0xff);
905 ed_asic_outb(sc, ED_3COM_VPTR0, 0x00);
908 * Zero memory and verify that it is clear
910 bzero(sc->mem_start, memsize);
912 for (i = 0; i < memsize; ++i)
913 if (sc->mem_start[i]) {
914 device_printf(dev, "failed to clear shared memory at %llx - check configuration\n",
915 (unsigned long long)kvtop(sc->mem_start + i));
922 * Probe and vendor-specific initialization routine for SIC boards
925 ed_probe_SIC(dev, port_rid, flags)
930 struct ed_softc *sc = device_get_softc(dev);
934 u_long conf_maddr, conf_msize;
937 error = ed_alloc_port(dev, 0, ED_SIC_IO_PORTS);
941 sc->asic_offset = ED_SIC_ASIC_OFFSET;
942 sc->nic_offset = ED_SIC_NIC_OFFSET;
944 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
945 &conf_maddr, &conf_msize);
951 memsize = conf_msize;
953 error = ed_alloc_memory(dev, 0, memsize);
957 sc->mem_start = (caddr_t) rman_get_virtual(sc->mem_res);
958 sc->mem_size = memsize;
960 /* Reset card to force it into a known state. */
961 ed_asic_outb(sc, 0, 0x00);
965 * Here we check the card ROM, if the checksum passes, and the
966 * type code and ethernet address check out, then we know we have
969 ed_asic_outb(sc, 0, 0x81);
972 sum = sc->mem_start[6];
973 for (i = 0; i < ETHER_ADDR_LEN; i++) {
974 sum ^= (sc->arpcom.ac_enaddr[i] = sc->mem_start[i]);
977 device_printf(dev, "ed_probe_sic: got address %6D\n",
978 sc->arpcom.ac_enaddr, ":");
983 if ((sc->arpcom.ac_enaddr[0] | sc->arpcom.ac_enaddr[1] |
984 sc->arpcom.ac_enaddr[2]) == 0) {
988 sc->vendor = ED_VENDOR_SIC;
989 sc->type_str = "SIC";
994 * SIC RAM page 0x0000-0x3fff(or 0x7fff)
996 ed_asic_outb(sc, 0, 0x80);
1000 * Now zero memory and verify that it is clear
1002 bzero(sc->mem_start, sc->mem_size);
1004 for (i = 0; i < sc->mem_size; i++) {
1005 if (sc->mem_start[i]) {
1006 device_printf(dev, "failed to clear shared memory "
1007 "at %llx - check configuration\n",
1008 (long long)kvtop(sc->mem_start + i));
1015 sc->mem_end = sc->mem_start + sc->mem_size;
1018 * allocate one xmit buffer if < 16k, two buffers otherwise
1020 if ((sc->mem_size < 16384) || (flags & ED_FLAGS_NO_MULTI_BUFFERING)) {
1025 sc->tx_page_start = 0;
1027 sc->rec_page_start = sc->tx_page_start + ED_TXBUF_SIZE * sc->txb_cnt;
1028 sc->rec_page_stop = sc->tx_page_start + sc->mem_size / ED_PAGE_SIZE;
1030 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE;
1036 * Probe and vendor-specific initialization routine for NE1000/2000 boards
1039 ed_probe_Novell_generic(dev, flags)
1043 struct ed_softc *sc = device_get_softc(dev);
1045 u_char romdata[16], tmp;
1046 static char test_pattern[32] = "THIS is A memory TEST pattern";
1047 char test_buffer[32];
1049 /* XXX - do Novell-specific probe here */
1051 /* Reset the board */
1052 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_GWETHER) {
1053 ed_asic_outb(sc, ED_NOVELL_RESET, 0);
1056 tmp = ed_asic_inb(sc, ED_NOVELL_RESET);
1059 * I don't know if this is necessary; probably cruft leftover from
1060 * Clarkson packet driver code. Doesn't do a thing on the boards I've
1061 * tested. -DG [note that an outb(0x84, 0) seems to work here, and is
1062 * non-invasive...but some boards don't seem to reset and I don't have
1063 * complete documentation on what the 'right' thing to do is...so we
1064 * do the invasive thing for now. Yuck.]
1066 ed_asic_outb(sc, ED_NOVELL_RESET, tmp);
1070 * This is needed because some NE clones apparently don't reset the
1071 * NIC properly (or the NIC chip doesn't reset fully on power-up) XXX
1072 * - this makes the probe invasive! ...Done against my better
1075 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STP);
1079 /* Make sure that we really have an 8390 based board */
1080 if (!ed_probe_generic8390(sc))
1083 sc->vendor = ED_VENDOR_NOVELL;
1085 sc->cr_proto = ED_CR_RD2;
1088 * Test the ability to read and write to the NIC memory. This has the
1089 * side affect of determining if this is an NE1000 or an NE2000.
1093 * This prevents packets from being stored in the NIC memory when the
1094 * readmem routine turns on the start bit in the CR.
1096 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_MON);
1098 /* Temporarily initialize DCR for byte operations */
1099 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
1101 ed_nic_outb(sc, ED_P0_PSTART, 8192 / ED_PAGE_SIZE);
1102 ed_nic_outb(sc, ED_P0_PSTOP, 16384 / ED_PAGE_SIZE);
1107 * Write a test pattern in byte mode. If this fails, then there
1108 * probably isn't any memory at 8k - which likely means that the board
1111 ed_pio_writemem(sc, test_pattern, 8192, sizeof(test_pattern));
1112 ed_pio_readmem(sc, 8192, test_buffer, sizeof(test_pattern));
1114 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)) == 0) {
1115 sc->type = ED_TYPE_NE1000;
1116 sc->type_str = "NE1000";
1119 /* neither an NE1000 nor a Linksys - try NE2000 */
1120 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_WTS | ED_DCR_FT1 | ED_DCR_LS);
1121 ed_nic_outb(sc, ED_P0_PSTART, 16384 / ED_PAGE_SIZE);
1122 ed_nic_outb(sc, ED_P0_PSTOP, 32768 / ED_PAGE_SIZE);
1127 * Write a test pattern in word mode. If this also fails, then
1128 * we don't know what this board is.
1130 ed_pio_writemem(sc, test_pattern, 16384, sizeof(test_pattern));
1131 ed_pio_readmem(sc, 16384, test_buffer, sizeof(test_pattern));
1132 if (bcmp(test_pattern, test_buffer, sizeof(test_pattern)) == 0) {
1133 sc->type = ED_TYPE_NE2000;
1134 sc->type_str = "NE2000";
1141 /* 8k of memory plus an additional 8k if 16bit */
1142 memsize = 8192 + sc->isa16bit * 8192;
1144 #if 0 /* probably not useful - NE boards only come two ways */
1145 /* allow kernel config file overrides */
1146 if (isa_dev->id_msize)
1147 memsize = isa_dev->id_msize;
1150 sc->mem_size = memsize;
1152 /* NIC memory doesn't start at zero on an NE board */
1153 /* The start address is tied to the bus width */
1154 sc->mem_start = (char *) 8192 + sc->isa16bit * 8192;
1155 sc->mem_end = sc->mem_start + memsize;
1156 sc->tx_page_start = memsize / ED_PAGE_SIZE;
1158 if (ED_FLAGS_GETTYPE(flags) == ED_FLAGS_GWETHER) {
1159 int x, i, mstart = 0, msize = 0;
1160 char pbuf0[ED_PAGE_SIZE], pbuf[ED_PAGE_SIZE], tbuf[ED_PAGE_SIZE];
1162 for (i = 0; i < ED_PAGE_SIZE; i++)
1165 /* Clear all the memory. */
1166 for (x = 1; x < 256; x++)
1167 ed_pio_writemem(sc, pbuf0, x * 256, ED_PAGE_SIZE);
1169 /* Search for the start of RAM. */
1170 for (x = 1; x < 256; x++) {
1171 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1172 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) {
1173 for (i = 0; i < ED_PAGE_SIZE; i++)
1175 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE);
1176 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1177 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0) {
1178 mstart = x * ED_PAGE_SIZE;
1179 msize = ED_PAGE_SIZE;
1186 device_printf(dev, "Cannot find start of RAM.\n");
1189 /* Search for the start of RAM. */
1190 for (x = (mstart / ED_PAGE_SIZE) + 1; x < 256; x++) {
1191 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1192 if (bcmp(pbuf0, tbuf, ED_PAGE_SIZE) == 0) {
1193 for (i = 0; i < ED_PAGE_SIZE; i++)
1195 ed_pio_writemem(sc, pbuf, x * 256, ED_PAGE_SIZE);
1196 ed_pio_readmem(sc, x * 256, tbuf, ED_PAGE_SIZE);
1197 if (bcmp(pbuf, tbuf, ED_PAGE_SIZE) == 0)
1198 msize += ED_PAGE_SIZE;
1208 device_printf(dev, "Cannot find any RAM, start : %d, x = %d.\n", mstart, x);
1211 device_printf(dev, "RAM start at %d, size : %d.\n", mstart, msize);
1213 sc->mem_size = msize;
1214 sc->mem_start = (caddr_t) mstart;
1215 sc->mem_end = (caddr_t) (msize + mstart);
1216 sc->tx_page_start = mstart / ED_PAGE_SIZE;
1220 * Use one xmit buffer if < 16k, two buffers otherwise (if not told
1223 if ((memsize < 16384) || (flags & ED_FLAGS_NO_MULTI_BUFFERING))
1228 sc->rec_page_start = sc->tx_page_start + sc->txb_cnt * ED_TXBUF_SIZE;
1229 sc->rec_page_stop = sc->tx_page_start + memsize / ED_PAGE_SIZE;
1231 sc->mem_ring = sc->mem_start + sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE;
1233 ed_pio_readmem(sc, 0, romdata, 16);
1234 for (n = 0; n < ETHER_ADDR_LEN; n++)
1235 sc->arpcom.ac_enaddr[n] = romdata[n * (sc->isa16bit + 1)];
1237 if ((ED_FLAGS_GETTYPE(flags) == ED_FLAGS_GWETHER) &&
1238 (sc->arpcom.ac_enaddr[2] == 0x86)) {
1239 sc->type_str = "Gateway AT";
1242 /* clear any pending interrupts that might have occurred above */
1243 ed_nic_outb(sc, ED_P0_ISR, 0xff);
1249 ed_probe_Novell(dev, port_rid, flags)
1254 struct ed_softc *sc = device_get_softc(dev);
1257 error = ed_alloc_port(dev, port_rid, ED_NOVELL_IO_PORTS);
1261 sc->asic_offset = ED_NOVELL_ASIC_OFFSET;
1262 sc->nic_offset = ED_NOVELL_NIC_OFFSET;
1264 return ed_probe_Novell_generic(dev, flags);
1267 #define ED_HPP_TEST_SIZE 16
1270 * Probe and vendor specific initialization for the HP PC Lan+ Cards.
1271 * (HP Part nos: 27247B and 27252A).
1273 * The card has an asic wrapper around a DS8390 core. The asic handles
1274 * host accesses and offers both standard register IO and memory mapped
1275 * IO. Memory mapped I/O allows better performance at the expense of greater
1276 * chance of an incompatibility with existing ISA cards.
1278 * The card has a few caveats: it isn't tolerant of byte wide accesses, only
1279 * short (16 bit) or word (32 bit) accesses are allowed. Some card revisions
1280 * don't allow 32 bit accesses; these are indicated by a bit in the software
1281 * ID register (see if_edreg.h).
1283 * Other caveats are: we should read the MAC address only when the card
1286 * For more information; please consult the CRYNWR packet driver.
1288 * The AUI port is turned on using the "link2" option on the ifconfig
1292 ed_probe_HP_pclanp(dev, port_rid, flags)
1297 struct ed_softc *sc = device_get_softc(dev);
1299 int n; /* temp var */
1300 int memsize; /* mem on board */
1301 u_char checksum; /* checksum of board address */
1302 u_char irq; /* board configured IRQ */
1303 char test_pattern[ED_HPP_TEST_SIZE]; /* read/write areas for */
1304 char test_buffer[ED_HPP_TEST_SIZE]; /* probing card */
1305 u_long conf_maddr, conf_msize, conf_irq, junk;
1307 error = ed_alloc_port(dev, 0, ED_HPP_IO_PORTS);
1311 /* Fill in basic information */
1312 sc->asic_offset = ED_HPP_ASIC_OFFSET;
1313 sc->nic_offset = ED_HPP_NIC_OFFSET;
1315 sc->chip_type = ED_CHIP_TYPE_DP8390;
1316 sc->isa16bit = 0; /* the 8390 core needs to be in byte mode */
1319 * Look for the HP PCLAN+ signature: "0x50,0x48,0x00,0x53"
1322 if ((ed_asic_inb(sc, ED_HPP_ID) != 0x50) ||
1323 (ed_asic_inb(sc, ED_HPP_ID + 1) != 0x48) ||
1324 ((ed_asic_inb(sc, ED_HPP_ID + 2) & 0xF0) != 0) ||
1325 (ed_asic_inb(sc, ED_HPP_ID + 3) != 0x53))
1329 * Read the MAC address and verify checksum on the address.
1332 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_MAC);
1333 for (n = 0, checksum = 0; n < ETHER_ADDR_LEN; n++)
1334 checksum += (sc->arpcom.ac_enaddr[n] =
1335 ed_asic_inb(sc, ED_HPP_MAC_ADDR + n));
1337 checksum += ed_asic_inb(sc, ED_HPP_MAC_ADDR + ETHER_ADDR_LEN);
1339 if (checksum != 0xFF)
1343 * Verify that the software model number is 0.
1346 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_ID);
1347 if (((sc->hpp_id = ed_asic_inw(sc, ED_HPP_PAGE_4)) &
1348 ED_HPP_ID_SOFT_MODEL_MASK) != 0x0000)
1352 * Read in and save the current options configured on card.
1355 sc->hpp_options = ed_asic_inw(sc, ED_HPP_OPTION);
1357 sc->hpp_options |= (ED_HPP_OPTION_NIC_RESET |
1358 ED_HPP_OPTION_CHIP_RESET |
1359 ED_HPP_OPTION_ENABLE_IRQ);
1362 * Reset the chip. This requires writing to the option register
1363 * so take care to preserve the other bits.
1366 ed_asic_outw(sc, ED_HPP_OPTION,
1367 (sc->hpp_options & ~(ED_HPP_OPTION_NIC_RESET |
1368 ED_HPP_OPTION_CHIP_RESET)));
1370 DELAY(5000); /* wait for chip reset to complete */
1372 ed_asic_outw(sc, ED_HPP_OPTION,
1373 (sc->hpp_options | (ED_HPP_OPTION_NIC_RESET |
1374 ED_HPP_OPTION_CHIP_RESET |
1375 ED_HPP_OPTION_ENABLE_IRQ)));
1379 if (!(ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST))
1380 return ENXIO; /* reset did not complete */
1383 * Read out configuration information.
1386 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW);
1388 irq = ed_asic_inb(sc, ED_HPP_HW_IRQ);
1391 * Check for impossible IRQ.
1394 if (irq >= (sizeof(ed_hpp_intr_val) / sizeof(ed_hpp_intr_val[0])))
1398 * If the kernel IRQ was specified with a '?' use the cards idea
1399 * of the IRQ. If the kernel IRQ was explicitly specified, it
1400 * should match that of the hardware.
1402 error = bus_get_resource(dev, SYS_RES_IRQ, 0,
1405 bus_set_resource(dev, SYS_RES_IRQ, 0,
1406 ed_hpp_intr_val[irq], 1);
1408 if (conf_irq != ed_hpp_intr_val[irq])
1413 * Fill in softconfig info.
1416 sc->vendor = ED_VENDOR_HP;
1417 sc->type = ED_TYPE_HP_PCLANPLUS;
1418 sc->type_str = "HP-PCLAN+";
1420 sc->mem_shared = 0; /* we DON'T have dual ported RAM */
1421 sc->mem_start = 0; /* we use offsets inside the card RAM */
1423 sc->hpp_mem_start = NULL;/* no memory mapped I/O by default */
1426 * The board has 32KB of memory. Is there a way to determine
1427 * this programmatically?
1433 * Check if memory mapping of the I/O registers possible.
1436 if (sc->hpp_options & ED_HPP_OPTION_MEM_ENABLE)
1441 * determine the memory address from the board.
1444 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW);
1445 mem_addr = (ed_asic_inw(sc, ED_HPP_HW_MEM_MAP) << 8);
1448 * Check that the kernel specified start of memory and
1449 * hardware's idea of it match.
1451 error = bus_get_resource(dev, SYS_RES_MEMORY, 0,
1452 &conf_maddr, &conf_msize);
1456 if (mem_addr != conf_maddr)
1459 error = ed_alloc_memory(dev, 0, memsize);
1463 sc->hpp_mem_start = rman_get_virtual(sc->mem_res);
1467 * Fill in the rest of the soft config structure.
1471 * The transmit page index.
1474 sc->tx_page_start = ED_HPP_TX_PAGE_OFFSET;
1476 if (device_get_flags(dev) & ED_FLAGS_NO_MULTI_BUFFERING)
1482 * Memory description
1485 sc->mem_size = memsize;
1486 sc->mem_ring = sc->mem_start +
1487 (sc->txb_cnt * ED_PAGE_SIZE * ED_TXBUF_SIZE);
1488 sc->mem_end = sc->mem_start + sc->mem_size;
1491 * Receive area starts after the transmit area and
1492 * continues till the end of memory.
1495 sc->rec_page_start = sc->tx_page_start +
1496 (sc->txb_cnt * ED_TXBUF_SIZE);
1497 sc->rec_page_stop = (sc->mem_size / ED_PAGE_SIZE);
1500 sc->cr_proto = 0; /* value works */
1503 * Set the wrap registers for string I/O reads.
1506 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_HW);
1507 ed_asic_outw(sc, ED_HPP_HW_WRAP,
1508 ((sc->rec_page_start / ED_PAGE_SIZE) |
1509 (((sc->rec_page_stop / ED_PAGE_SIZE) - 1) << 8)));
1512 * Reset the register page to normal operation.
1515 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_PERF);
1518 * Verify that we can read/write from adapter memory.
1519 * Create test pattern.
1522 for (n = 0; n < ED_HPP_TEST_SIZE; n++)
1524 test_pattern[n] = (n*n) ^ ~n;
1527 #undef ED_HPP_TEST_SIZE
1530 * Check that the memory is accessible thru the I/O ports.
1531 * Write out the contents of "test_pattern", read back
1532 * into "test_buffer" and compare the two for any
1536 for (n = 0; n < (32768 / ED_PAGE_SIZE); n ++) {
1538 ed_hpp_writemem(sc, test_pattern, (n * ED_PAGE_SIZE),
1539 sizeof(test_pattern));
1540 ed_hpp_readmem(sc, (n * ED_PAGE_SIZE),
1541 test_buffer, sizeof(test_pattern));
1543 if (bcmp(test_pattern, test_buffer,
1544 sizeof(test_pattern)))
1553 * HP PC Lan+ : Set the physical link to use AUI or TP/TL.
1557 ed_hpp_set_physical_link(struct ed_softc *sc)
1559 struct ifnet *ifp = &sc->arpcom.ac_if;
1562 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1563 lan_page = ed_asic_inw(sc, ED_HPP_PAGE_0);
1565 if (ifp->if_flags & IFF_ALTPHYS) {
1571 lan_page |= ED_HPP_LAN_AUI;
1573 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1574 ed_asic_outw(sc, ED_HPP_PAGE_0, lan_page);
1580 * Use the ThinLan interface
1583 lan_page &= ~ED_HPP_LAN_AUI;
1585 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_LAN);
1586 ed_asic_outw(sc, ED_HPP_PAGE_0, lan_page);
1591 * Wait for the lan card to re-initialize itself
1594 DELAY(150000); /* wait 150 ms */
1597 * Restore normal pages.
1600 ed_asic_outw(sc, ED_HPP_PAGING, ED_HPP_PAGE_PERF);
1605 * Allocate a port resource with the given resource id.
1608 ed_alloc_port(dev, rid, size)
1613 struct ed_softc *sc = device_get_softc(dev);
1614 struct resource *res;
1616 res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid,
1617 0ul, ~0ul, size, RF_ACTIVE);
1621 sc->port_used = size;
1629 * Allocate a memory resource with the given resource id.
1632 ed_alloc_memory(dev, rid, size)
1637 struct ed_softc *sc = device_get_softc(dev);
1638 struct resource *res;
1640 res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
1641 0ul, ~0ul, size, RF_ACTIVE);
1645 sc->mem_used = size;
1653 * Allocate an irq resource with the given resource id.
1656 ed_alloc_irq(dev, rid, flags)
1661 struct ed_softc *sc = device_get_softc(dev);
1662 struct resource *res;
1664 res = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
1665 0ul, ~0ul, 1, (RF_ACTIVE | flags));
1676 * Release all resources
1679 ed_release_resources(dev)
1682 struct ed_softc *sc = device_get_softc(dev);
1685 bus_deactivate_resource(dev, SYS_RES_IOPORT,
1686 sc->port_rid, sc->port_res);
1687 bus_release_resource(dev, SYS_RES_IOPORT,
1688 sc->port_rid, sc->port_res);
1692 bus_deactivate_resource(dev, SYS_RES_MEMORY,
1693 sc->mem_rid, sc->mem_res);
1694 bus_release_resource(dev, SYS_RES_MEMORY,
1695 sc->mem_rid, sc->mem_res);
1699 bus_deactivate_resource(dev, SYS_RES_IRQ,
1700 sc->irq_rid, sc->irq_res);
1701 bus_release_resource(dev, SYS_RES_IRQ,
1702 sc->irq_rid, sc->irq_res);
1708 * Install interface into kernel networking data structures
1711 ed_attach(device_t dev)
1713 struct ed_softc *sc = device_get_softc(dev);
1714 struct ifnet *ifp = &sc->arpcom.ac_if;
1716 callout_init(&sc->ed_timer);
1718 * Set interface to stopped condition (reset)
1723 * Initialize ifnet structure
1726 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1727 ifp->if_mtu = ETHERMTU;
1728 ifp->if_start = ed_start;
1729 ifp->if_ioctl = ed_ioctl;
1730 ifp->if_watchdog = ed_watchdog;
1731 ifp->if_init = ed_init;
1732 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN);
1733 ifq_set_ready(&ifp->if_snd);
1734 ifp->if_linkmib = &sc->mibdata;
1735 ifp->if_linkmiblen = sizeof sc->mibdata;
1736 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1738 * XXX - should do a better job.
1740 if (sc->chip_type == ED_CHIP_TYPE_WD790)
1741 sc->mibdata.dot3StatsEtherChipSet =
1742 DOT3CHIPSET(dot3VendorWesternDigital,
1743 dot3ChipSetWesternDigital83C790);
1745 sc->mibdata.dot3StatsEtherChipSet =
1746 DOT3CHIPSET(dot3VendorNational,
1747 dot3ChipSetNational8390);
1748 sc->mibdata.dot3Compliance = DOT3COMPLIANCE_COLLS;
1751 * Set default state for ALTPHYS flag (used to disable the
1752 * tranceiver for AUI operation), based on compile-time
1755 if (device_get_flags(dev) & ED_FLAGS_DISABLE_TRANCEIVER)
1756 ifp->if_flags |= IFF_ALTPHYS;
1759 * Attach the interface
1761 ether_ifattach(ifp, sc->arpcom.ac_enaddr);
1763 /* device attach does transition from UNCONFIGURED to IDLE state */
1765 if (sc->type_str && (*sc->type_str != 0))
1766 printf("type %s ", sc->type_str);
1768 printf("type unknown (0x%x) ", sc->type);
1770 if (sc->vendor == ED_VENDOR_HP)
1771 printf("(%s %s IO)", (sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS) ?
1772 "16-bit" : "32-bit",
1773 sc->hpp_mem_start ? "memory mapped" : "regular");
1775 printf("%s ", sc->isa16bit ? "(16 bit)" : "(8 bit)");
1777 printf("%s\n", (((sc->vendor == ED_VENDOR_3COM) ||
1778 (sc->vendor == ED_VENDOR_HP)) &&
1779 (ifp->if_flags & IFF_ALTPHYS)) ? " tranceiver disabled" : "");
1791 struct ed_softc *sc = ifp->if_softc;
1799 * Stop interface and re-initialize.
1808 * Take interface offline.
1812 struct ed_softc *sc;
1816 #ifndef ED_NO_MIIBUS
1817 callout_stop(&sc->ed_timer);
1822 * Stop everything on the interface, and select page 0 registers.
1824 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
1827 * Wait for interface to enter stopped state, but limit # of checks to
1828 * 'n' (about 5ms). It shouldn't even take 5us on modern DS8390's, but
1829 * just in case it's an old one.
1831 if (sc->chip_type != ED_CHIP_TYPE_AX88190)
1832 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RST) == 0) && --n);
1836 * Device timeout/watchdog routine. Entered if the device neglects to
1837 * generate an interrupt after a transmit has been started on it.
1843 struct ed_softc *sc = ifp->if_softc;
1847 log(LOG_ERR, "%s: device timeout\n", ifp->if_xname);
1853 #ifndef ED_NO_MIIBUS
1858 struct ed_softc *sc = arg;
1859 struct mii_data *mii;
1865 if (sc->miibus != NULL) {
1866 mii = device_get_softc(sc->miibus);
1869 callout_reset(&sc->ed_timer, hz, ed_tick, sc);
1875 * Initialize device.
1881 struct ed_softc *sc = xsc;
1882 struct ifnet *ifp = &sc->arpcom.ac_if;
1888 /* address not known */
1889 if (TAILQ_EMPTY(&ifp->if_addrhead)) /* unlikely? XXX */
1893 * Initialize the NIC in the exact order outlined in the NS manual.
1894 * This init procedure is "mandatory"...don't change what or when
1899 /* reset transmitter flags */
1905 sc->txb_next_tx = 0;
1907 /* This variable is used below - don't move this assignment */
1908 sc->next_packet = sc->rec_page_start + 1;
1911 * Set interface for page 0, Remote DMA complete, Stopped
1913 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
1918 * Set FIFO threshold to 8, No auto-init Remote DMA, byte
1919 * order=80x86, word-wide DMA xfers,
1921 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_WTS | ED_DCR_LS);
1925 * Same as above, but byte-wide DMA xfers
1927 ed_nic_outb(sc, ED_P0_DCR, ED_DCR_FT1 | ED_DCR_LS);
1931 * Clear Remote Byte Count Registers
1933 ed_nic_outb(sc, ED_P0_RBCR0, 0);
1934 ed_nic_outb(sc, ED_P0_RBCR1, 0);
1937 * For the moment, don't store incoming packets in memory.
1939 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_MON);
1942 * Place NIC in internal loopback mode
1944 ed_nic_outb(sc, ED_P0_TCR, ED_TCR_LB0);
1947 * Initialize transmit/receive (ring-buffer) Page Start
1949 ed_nic_outb(sc, ED_P0_TPSR, sc->tx_page_start);
1950 ed_nic_outb(sc, ED_P0_PSTART, sc->rec_page_start);
1951 /* Set lower bits of byte addressable framing to 0 */
1952 if (sc->chip_type == ED_CHIP_TYPE_WD790)
1953 ed_nic_outb(sc, 0x09, 0);
1956 * Initialize Receiver (ring-buffer) Page Stop and Boundry
1958 ed_nic_outb(sc, ED_P0_PSTOP, sc->rec_page_stop);
1959 ed_nic_outb(sc, ED_P0_BNRY, sc->rec_page_start);
1962 * Clear all interrupts. A '1' in each bit position clears the
1963 * corresponding flag.
1965 ed_nic_outb(sc, ED_P0_ISR, 0xff);
1968 * Enable the following interrupts: receive/transmit complete,
1969 * receive/transmit error, and Receiver OverWrite.
1971 * Counter overflow and Remote DMA complete are *not* enabled.
1973 ed_nic_outb(sc, ED_P0_IMR,
1974 ED_IMR_PRXE | ED_IMR_PTXE | ED_IMR_RXEE | ED_IMR_TXEE | ED_IMR_OVWE);
1977 * Program Command Register for page 1
1979 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
1982 * Copy out our station address
1984 for (i = 0; i < ETHER_ADDR_LEN; ++i)
1985 ed_nic_outb(sc, ED_P1_PAR(i), sc->arpcom.ac_enaddr[i]);
1988 * Set Current Page pointer to next_packet (initialized above)
1990 ed_nic_outb(sc, ED_P1_CURR, sc->next_packet);
1993 * Program Receiver Configuration Register and multicast filter. CR is
1994 * set to page 0 on return.
1999 * Take interface out of loopback
2001 ed_nic_outb(sc, ED_P0_TCR, 0);
2004 * If this is a 3Com board, the tranceiver must be software enabled
2005 * (there is no settable hardware default).
2007 if (sc->vendor == ED_VENDOR_3COM) {
2008 if (ifp->if_flags & IFF_ALTPHYS) {
2009 ed_asic_outb(sc, ED_3COM_CR, 0);
2011 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
2015 #ifndef ED_NO_MIIBUS
2016 if (sc->miibus != NULL) {
2017 struct mii_data *mii;
2018 mii = device_get_softc(sc->miibus);
2023 * Set 'running' flag, and clear output active flag.
2025 ifp->if_flags |= IFF_RUNNING;
2026 ifp->if_flags &= ~IFF_OACTIVE;
2029 * ...and attempt to start output
2033 #ifndef ED_NO_MIIBUS
2034 callout_reset(&sc->ed_timer, hz, ed_tick, sc);
2040 * This routine actually starts the transmission on the interface
2042 static __inline void
2044 struct ed_softc *sc;
2046 struct ifnet *ifp = (struct ifnet *)sc;
2051 len = sc->txb_len[sc->txb_next_tx];
2054 * Set NIC for page 0 register access
2056 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
2059 * Set TX buffer start page
2061 ed_nic_outb(sc, ED_P0_TPSR, sc->tx_page_start +
2062 sc->txb_next_tx * ED_TXBUF_SIZE);
2067 ed_nic_outb(sc, ED_P0_TBCR0, len);
2068 ed_nic_outb(sc, ED_P0_TBCR1, len >> 8);
2071 * Set page 0, Remote DMA complete, Transmit Packet, and *Start*
2073 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_TXP | ED_CR_STA);
2077 * Point to next transmit buffer slot and wrap if necessary.
2080 if (sc->txb_next_tx == sc->txb_cnt)
2081 sc->txb_next_tx = 0;
2084 * Set a timer just in case we never hear from the board again
2090 * Start output on interface.
2091 * We make two assumptions here:
2092 * 1) that the current priority is set to splimp _before_ this code
2093 * is called *and* is returned to the appropriate priority after
2095 * 2) that the IFF_OACTIVE flag is checked before this code is called
2096 * (i.e. that the output part of the interface is idle)
2102 struct ed_softc *sc = ifp->if_softc;
2103 struct mbuf *m0, *m;
2108 printf("ed_start(%p) GONE\n",ifp);
2114 * First, see if there are buffered packets and an idle transmitter -
2115 * should never happen at this point.
2117 if (sc->txb_inuse && (sc->xmit_busy == 0)) {
2118 printf("ed: packets buffered, but transmitter idle\n");
2123 * See if there is room to put another packet in the buffer.
2125 if (sc->txb_inuse == sc->txb_cnt) {
2128 * No room. Indicate this to the outside world and exit.
2130 ifp->if_flags |= IFF_OACTIVE;
2133 m = ifq_dequeue(&ifp->if_snd);
2137 * We are using the !OACTIVE flag to indicate to the outside
2138 * world that we can accept an additional packet rather than
2139 * that the transmitter is _actually_ active. Indeed, the
2140 * transmitter may be active, but if we haven't filled all the
2141 * buffers with data then we still want to accept more.
2143 ifp->if_flags &= ~IFF_OACTIVE;
2148 * Copy the mbuf chain into the transmit buffer
2153 /* txb_new points to next open buffer slot */
2154 buffer = sc->mem_start + (sc->txb_new * ED_TXBUF_SIZE * ED_PAGE_SIZE);
2156 if (sc->mem_shared) {
2159 * Special case setup for 16 bit boards...
2162 switch (sc->vendor) {
2165 * For 16bit 3Com boards (which have 16k of
2166 * memory), we have the xmit buffers in a
2167 * different page of memory ('page 0') - so
2170 case ED_VENDOR_3COM:
2171 ed_asic_outb(sc, ED_3COM_GACFR,
2172 ED_3COM_GACFR_RSEL);
2176 * Enable 16bit access to shared memory on
2179 case ED_VENDOR_WD_SMC:
2180 ed_asic_outb(sc, ED_WD_LAAR,
2181 sc->wd_laar_proto | ED_WD_LAAR_M16EN);
2182 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2183 ed_asic_outb(sc, ED_WD_MSR, ED_WD_MSR_MENB);
2188 for (len = 0; m != 0; m = m->m_next) {
2189 bcopy(mtod(m, caddr_t), buffer, m->m_len);
2195 * Restore previous shared memory access
2198 switch (sc->vendor) {
2199 case ED_VENDOR_3COM:
2200 ed_asic_outb(sc, ED_3COM_GACFR,
2201 ED_3COM_GACFR_RSEL | ED_3COM_GACFR_MBS0);
2203 case ED_VENDOR_WD_SMC:
2204 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2205 ed_asic_outb(sc, ED_WD_MSR, 0x00);
2207 ed_asic_outb(sc, ED_WD_LAAR,
2208 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
2213 len = ed_pio_write_mbufs(sc, m, (int)buffer);
2220 sc->txb_len[sc->txb_new] = max(len, (ETHER_MIN_LEN-ETHER_CRC_LEN));
2225 * Point to next buffer slot and wrap if necessary.
2228 if (sc->txb_new == sc->txb_cnt)
2231 if (sc->xmit_busy == 0)
2239 * Loop back to the top to possibly buffer more packets
2245 * Ethernet interface receiver interrupt.
2247 static __inline void
2249 struct ed_softc *sc;
2251 struct ifnet *ifp = &sc->arpcom.ac_if;
2254 struct ed_ring packet_hdr;
2261 * Set NIC to page 1 registers to get 'current' pointer
2263 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
2266 * 'sc->next_packet' is the logical beginning of the ring-buffer -
2267 * i.e. it points to where new data has been buffered. The 'CURR'
2268 * (current) register points to the logical end of the ring-buffer -
2269 * i.e. it points to where additional new data will be added. We loop
2270 * here until the logical beginning equals the logical end (or in
2271 * other words, until the ring-buffer is empty).
2273 while (sc->next_packet != ed_nic_inb(sc, ED_P1_CURR)) {
2275 /* get pointer to this buffer's header structure */
2276 packet_ptr = sc->mem_ring +
2277 (sc->next_packet - sc->rec_page_start) * ED_PAGE_SIZE;
2280 * The byte count includes a 4 byte header that was added by
2284 packet_hdr = *(struct ed_ring *) packet_ptr;
2286 ed_pio_readmem(sc, (int)packet_ptr, (char *) &packet_hdr,
2287 sizeof(packet_hdr));
2288 len = packet_hdr.count;
2289 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring)) ||
2290 len < (ETHER_MIN_LEN - ETHER_CRC_LEN + sizeof(struct ed_ring))) {
2292 * Length is a wild value. There's a good chance that
2293 * this was caused by the NIC being old and buggy.
2294 * The bug is that the length low byte is duplicated in
2295 * the high byte. Try to recalculate the length based on
2296 * the pointer to the next packet.
2299 * NOTE: sc->next_packet is pointing at the current packet.
2301 len &= ED_PAGE_SIZE - 1; /* preserve offset into page */
2302 if (packet_hdr.next_packet >= sc->next_packet) {
2303 len += (packet_hdr.next_packet - sc->next_packet) * ED_PAGE_SIZE;
2305 len += ((packet_hdr.next_packet - sc->rec_page_start) +
2306 (sc->rec_page_stop - sc->next_packet)) * ED_PAGE_SIZE;
2309 * because buffers are aligned on 256-byte boundary,
2310 * the length computed above is off by 256 in almost
2311 * all cases. Fix it...
2315 if (len > (ETHER_MAX_LEN - ETHER_CRC_LEN
2316 + sizeof(struct ed_ring)))
2317 sc->mibdata.dot3StatsFrameTooLongs++;
2320 * Be fairly liberal about what we allow as a "reasonable" length
2321 * so that a [crufty] packet will make it to BPF (and can thus
2322 * be analyzed). Note that all that is really important is that
2323 * we have a length that will fit into one mbuf cluster or less;
2324 * the upper layer protocols can then figure out the length from
2325 * their own length field(s).
2326 * But make sure that we have at least a full ethernet header
2327 * or we would be unable to call ether_input() later.
2329 if ((len >= sizeof(struct ed_ring) + ETHER_HDR_LEN) &&
2330 (len <= MCLBYTES) &&
2331 (packet_hdr.next_packet >= sc->rec_page_start) &&
2332 (packet_hdr.next_packet < sc->rec_page_stop)) {
2336 ed_get_packet(sc, packet_ptr + sizeof(struct ed_ring),
2337 len - sizeof(struct ed_ring));
2341 * Really BAD. The ring pointers are corrupted.
2344 "%s: NIC memory corrupt - invalid packet length %d\n",
2345 ifp->if_xname, len);
2352 * Update next packet pointer
2354 sc->next_packet = packet_hdr.next_packet;
2357 * Update NIC boundry pointer - being careful to keep it one
2358 * buffer behind. (as recommended by NS databook)
2360 boundry = sc->next_packet - 1;
2361 if (boundry < sc->rec_page_start)
2362 boundry = sc->rec_page_stop - 1;
2365 * Set NIC to page 0 registers to update boundry register
2367 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
2369 ed_nic_outb(sc, ED_P0_BNRY, boundry);
2372 * Set NIC to page 1 registers before looping to top (prepare
2373 * to get 'CURR' current pointer)
2375 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STA);
2380 * Ethernet interface interrupt processor
2386 struct ed_softc *sc = (struct ed_softc*) arg;
2387 struct ifnet *ifp = (struct ifnet *)sc;
2394 * Set NIC to page 0 registers
2396 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
2399 * loop until there are no more new interrupts. When the card
2400 * goes away, the hardware will read back 0xff. Looking at
2401 * the interrupts, it would appear that 0xff is impossible,
2402 * or at least extremely unlikely.
2404 while ((isr = ed_nic_inb(sc, ED_P0_ISR)) != 0 && isr != 0xff) {
2407 * reset all the bits that we are 'acknowledging' by writing a
2408 * '1' to each bit position that was set (writing a '1'
2411 ed_nic_outb(sc, ED_P0_ISR, isr);
2414 * XXX workaround for AX88190
2415 * We limit this to 5000 iterations. At 1us per inb/outb,
2416 * this translates to about 15ms, which should be plenty
2417 * of time, and also gives protection in the card eject
2420 if (sc->chip_type == ED_CHIP_TYPE_AX88190) {
2421 count = 5000; /* 15ms */
2422 while (count-- && (ed_nic_inb(sc, ED_P0_ISR) & isr)) {
2423 ed_nic_outb(sc, ED_P0_ISR,0);
2424 ed_nic_outb(sc, ED_P0_ISR,isr);
2431 * Handle transmitter interrupts. Handle these first because
2432 * the receiver will reset the board under some conditions.
2434 if (isr & (ED_ISR_PTX | ED_ISR_TXE)) {
2435 u_char collisions = ed_nic_inb(sc, ED_P0_NCR) & 0x0f;
2438 * Check for transmit error. If a TX completed with an
2439 * error, we end up throwing the packet away. Really
2440 * the only error that is possible is excessive
2441 * collisions, and in this case it is best to allow
2442 * the automatic mechanisms of TCP to backoff the
2443 * flow. Of course, with UDP we're screwed, but this
2444 * is expected when a network is heavily loaded.
2446 (void) ed_nic_inb(sc, ED_P0_TSR);
2447 if (isr & ED_ISR_TXE) {
2451 * Excessive collisions (16)
2453 tsr = ed_nic_inb(sc, ED_P0_TSR);
2454 if ((tsr & ED_TSR_ABT)
2455 && (collisions == 0)) {
2458 * When collisions total 16, the
2459 * P0_NCR will indicate 0, and the
2463 sc->mibdata.dot3StatsExcessiveCollisions++;
2464 sc->mibdata.dot3StatsCollFrequencies[15]++;
2466 if (tsr & ED_TSR_OWC)
2467 sc->mibdata.dot3StatsLateCollisions++;
2468 if (tsr & ED_TSR_CDH)
2469 sc->mibdata.dot3StatsSQETestErrors++;
2470 if (tsr & ED_TSR_CRS)
2471 sc->mibdata.dot3StatsCarrierSenseErrors++;
2472 if (tsr & ED_TSR_FU)
2473 sc->mibdata.dot3StatsInternalMacTransmitErrors++;
2476 * update output errors counter
2482 * Update total number of successfully
2483 * transmitted packets.
2489 * reset tx busy and output active flags
2492 ifp->if_flags &= ~IFF_OACTIVE;
2495 * clear watchdog timer
2500 * Add in total number of collisions on last
2503 ifp->if_collisions += collisions;
2504 switch(collisions) {
2509 sc->mibdata.dot3StatsSingleCollisionFrames++;
2510 sc->mibdata.dot3StatsCollFrequencies[0]++;
2513 sc->mibdata.dot3StatsMultipleCollisionFrames++;
2515 dot3StatsCollFrequencies[collisions-1]
2521 * Decrement buffer in-use count if not zero (can only
2522 * be zero if a transmitter interrupt occured while
2523 * not actually transmitting). If data is ready to
2524 * transmit, start it transmitting, otherwise defer
2525 * until after handling receiver
2527 if (sc->txb_inuse && --sc->txb_inuse)
2532 * Handle receiver interrupts
2534 if (isr & (ED_ISR_PRX | ED_ISR_RXE | ED_ISR_OVW)) {
2537 * Overwrite warning. In order to make sure that a
2538 * lockup of the local DMA hasn't occurred, we reset
2539 * and re-init the NIC. The NSC manual suggests only a
2540 * partial reset/re-init is necessary - but some chips
2541 * seem to want more. The DMA lockup has been seen
2542 * only with early rev chips - Methinks this bug was
2543 * fixed in later revs. -DG
2545 if (isr & ED_ISR_OVW) {
2549 "%s: warning - receiver ring buffer overrun\n",
2554 * Stop/reset/re-init NIC
2560 * Receiver Error. One or more of: CRC error,
2561 * frame alignment error FIFO overrun, or
2564 if (isr & ED_ISR_RXE) {
2566 rsr = ed_nic_inb(sc, ED_P0_RSR);
2567 if (rsr & ED_RSR_CRC)
2568 sc->mibdata.dot3StatsFCSErrors++;
2569 if (rsr & ED_RSR_FAE)
2570 sc->mibdata.dot3StatsAlignmentErrors++;
2571 if (rsr & ED_RSR_FO)
2572 sc->mibdata.dot3StatsInternalMacReceiveErrors++;
2575 if_printf("receive error %x\n",
2576 ed_nic_inb(sc, ED_P0_RSR));
2581 * Go get the packet(s) XXX - Doing this on an
2582 * error is dubious because there shouldn't be
2583 * any data to get (we've configured the
2584 * interface to not accept packets with
2589 * Enable 16bit access to shared memory first
2593 (sc->vendor == ED_VENDOR_WD_SMC)) {
2595 ed_asic_outb(sc, ED_WD_LAAR,
2596 sc->wd_laar_proto | ED_WD_LAAR_M16EN);
2597 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2598 ed_asic_outb(sc, ED_WD_MSR,
2604 /* disable 16bit access */
2606 (sc->vendor == ED_VENDOR_WD_SMC)) {
2608 if (sc->chip_type == ED_CHIP_TYPE_WD790) {
2609 ed_asic_outb(sc, ED_WD_MSR, 0x00);
2611 ed_asic_outb(sc, ED_WD_LAAR,
2612 sc->wd_laar_proto & ~ED_WD_LAAR_M16EN);
2618 * If it looks like the transmitter can take more data,
2619 * attempt to start output on the interface. This is done
2620 * after handling the receiver to give the receiver priority.
2622 if ((ifp->if_flags & IFF_OACTIVE) == 0)
2626 * return NIC CR to standard state: page 0, remote DMA
2627 * complete, start (toggling the TXP bit off, even if was just
2628 * set in the transmit routine, is *okay* - it is 'edge'
2629 * triggered from low to high)
2631 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
2634 * If the Network Talley Counters overflow, read them to reset
2635 * them. It appears that old 8390's won't clear the ISR flag
2636 * otherwise - resulting in an infinite loop.
2638 if (isr & ED_ISR_CNT) {
2639 (void) ed_nic_inb(sc, ED_P0_CNTR0);
2640 (void) ed_nic_inb(sc, ED_P0_CNTR1);
2641 (void) ed_nic_inb(sc, ED_P0_CNTR2);
2647 * Process an ioctl request. This code needs some work - it looks
2651 ed_ioctl(ifp, command, data, cr)
2657 struct ed_softc *sc = ifp->if_softc;
2658 #ifndef ED_NO_MIIBUS
2659 struct ifreq *ifr = (struct ifreq *)data;
2660 struct mii_data *mii;
2664 if (sc == NULL || sc->gone) {
2665 ifp->if_flags &= ~IFF_RUNNING;
2675 error = ether_ioctl(ifp, command, data);
2681 * If the interface is marked up and stopped, then start it.
2682 * If it is marked down and running, then stop it.
2684 if (ifp->if_flags & IFF_UP) {
2685 if ((ifp->if_flags & IFF_RUNNING) == 0)
2688 if (ifp->if_flags & IFF_RUNNING) {
2690 ifp->if_flags &= ~IFF_RUNNING;
2695 * Promiscuous flag may have changed, so reprogram the RCR.
2700 * An unfortunate hack to provide the (required) software
2701 * control of the tranceiver for 3Com boards. The ALTPHYS flag
2702 * disables the tranceiver if set.
2704 if (sc->vendor == ED_VENDOR_3COM) {
2705 if (ifp->if_flags & IFF_ALTPHYS) {
2706 ed_asic_outb(sc, ED_3COM_CR, 0);
2708 ed_asic_outb(sc, ED_3COM_CR, ED_3COM_CR_XSEL);
2710 } else if (sc->vendor == ED_VENDOR_HP)
2711 ed_hpp_set_physical_link(sc);
2717 * Multicast list has changed; set the hardware filter
2724 #ifndef ED_NO_MIIBUS
2727 if (sc->miibus == NULL) {
2731 mii = device_get_softc(sc->miibus);
2732 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
2744 * Given a source and destination address, copy 'amount' of a packet from
2745 * the ring buffer into a linear destination buffer. Takes into account
2748 static __inline char *
2749 ed_ring_copy(sc, src, dst, amount)
2750 struct ed_softc *sc;
2757 /* does copy wrap to lower addr in ring buffer? */
2758 if (src + amount > sc->mem_end) {
2759 tmp_amount = sc->mem_end - src;
2761 /* copy amount up to end of NIC memory */
2763 bcopy(src, dst, tmp_amount);
2765 ed_pio_readmem(sc, (int)src, dst, tmp_amount);
2767 amount -= tmp_amount;
2772 bcopy(src, dst, amount);
2774 ed_pio_readmem(sc, (int)src, dst, amount);
2776 return (src + amount);
2780 * Retreive packet from shared memory and send to the next level up via
2784 ed_get_packet(sc, buf, len)
2785 struct ed_softc *sc;
2789 struct ifnet *ifp = &sc->arpcom.ac_if;
2790 struct ether_header *eh;
2793 /* Allocate a header mbuf */
2794 MGETHDR(m, MB_DONTWAIT, MT_DATA);
2797 m->m_pkthdr.rcvif = ifp;
2798 m->m_pkthdr.len = m->m_len = len;
2801 * We always put the received packet in a single buffer -
2802 * either with just an mbuf header or in a cluster attached
2803 * to the header. The +2 is to compensate for the alignment
2806 if ((len + 2) > MHLEN) {
2807 /* Attach an mbuf cluster */
2808 MCLGET(m, MB_DONTWAIT);
2810 /* Insist on getting a cluster */
2811 if ((m->m_flags & M_EXT) == 0) {
2818 * The +2 is to longword align the start of the real packet.
2819 * This is important for NFS.
2822 eh = mtod(m, struct ether_header *);
2825 * Don't read in the entire packet if we know we're going to drop it
2826 * and no bpf is active.
2828 if (!ifp->if_bpf && BDG_ACTIVE( (ifp) ) ) {
2831 ed_ring_copy(sc, buf, (char *)eh, ETHER_HDR_LEN);
2832 bif = bridge_in_ptr(ifp, eh) ;
2833 if (bif == BDG_DROP) {
2837 if (len > ETHER_HDR_LEN)
2838 ed_ring_copy(sc, buf + ETHER_HDR_LEN,
2839 (char *)(eh + 1), len - ETHER_HDR_LEN);
2842 * Get packet, including link layer address, from interface.
2844 ed_ring_copy(sc, buf, (char *)eh, len);
2846 m->m_pkthdr.len = m->m_len = len;
2848 (*ifp->if_input)(ifp, m);
2852 * Supporting routines
2856 * Given a NIC memory source address and a host memory destination
2857 * address, copy 'amount' from NIC to host using Programmed I/O.
2858 * The 'amount' is rounded up to a word - okay as long as mbufs
2860 * This routine is currently Novell-specific.
2863 ed_pio_readmem(sc, src, dst, amount)
2864 struct ed_softc *sc;
2867 unsigned short amount;
2869 /* HP PC Lan+ cards need special handling */
2870 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) {
2871 ed_hpp_readmem(sc, src, dst, amount);
2875 /* Regular Novell cards */
2876 /* select page 0 registers */
2877 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2879 /* round up to a word */
2883 /* set up DMA byte count */
2884 ed_nic_outb(sc, ED_P0_RBCR0, amount);
2885 ed_nic_outb(sc, ED_P0_RBCR1, amount >> 8);
2887 /* set up source address in NIC mem */
2888 ed_nic_outb(sc, ED_P0_RSAR0, src);
2889 ed_nic_outb(sc, ED_P0_RSAR1, src >> 8);
2891 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD0 | ED_CR_STA);
2894 ed_asic_insw(sc, ED_NOVELL_DATA, dst, amount / 2);
2896 ed_asic_insb(sc, ED_NOVELL_DATA, dst, amount);
2901 * Stripped down routine for writing a linear buffer to NIC memory.
2902 * Only used in the probe routine to test the memory. 'len' must
2906 ed_pio_writemem(sc, src, dst, len)
2907 struct ed_softc *sc;
2912 int maxwait = 200; /* about 240us */
2914 /* select page 0 registers */
2915 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2917 /* reset remote DMA complete flag */
2918 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
2920 /* set up DMA byte count */
2921 ed_nic_outb(sc, ED_P0_RBCR0, len);
2922 ed_nic_outb(sc, ED_P0_RBCR1, len >> 8);
2924 /* set up destination address in NIC mem */
2925 ed_nic_outb(sc, ED_P0_RSAR0, dst);
2926 ed_nic_outb(sc, ED_P0_RSAR1, dst >> 8);
2928 /* set remote DMA write */
2929 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
2932 ed_asic_outsw(sc, ED_NOVELL_DATA, src, len / 2);
2934 ed_asic_outsb(sc, ED_NOVELL_DATA, src, len);
2938 * Wait for remote DMA complete. This is necessary because on the
2939 * transmit side, data is handled internally by the NIC in bursts and
2940 * we can't start another remote DMA until this one completes. Not
2941 * waiting causes really bad things to happen - like the NIC
2942 * irrecoverably jamming the ISA bus.
2944 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
2948 * Write an mbuf chain to the destination NIC memory address using
2952 ed_pio_write_mbufs(sc, m, dst)
2953 struct ed_softc *sc;
2957 struct ifnet *ifp = (struct ifnet *)sc;
2958 unsigned short total_len, dma_len;
2960 int maxwait = 200; /* about 240us */
2962 /* HP PC Lan+ cards need special handling */
2963 if (sc->vendor == ED_VENDOR_HP && sc->type == ED_TYPE_HP_PCLANPLUS) {
2964 return ed_hpp_write_mbufs(sc, m, dst);
2967 /* Regular Novell cards */
2968 /* First, count up the total number of bytes to copy */
2969 for (total_len = 0, mp = m; mp; mp = mp->m_next)
2970 total_len += mp->m_len;
2972 dma_len = total_len;
2973 if (sc->isa16bit && (dma_len & 1))
2976 /* select page 0 registers */
2977 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD2 | ED_CR_STA);
2979 /* reset remote DMA complete flag */
2980 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
2982 /* set up DMA byte count */
2983 ed_nic_outb(sc, ED_P0_RBCR0, dma_len);
2984 ed_nic_outb(sc, ED_P0_RBCR1, dma_len >> 8);
2986 /* set up destination address in NIC mem */
2987 ed_nic_outb(sc, ED_P0_RSAR0, dst);
2988 ed_nic_outb(sc, ED_P0_RSAR1, dst >> 8);
2990 /* set remote DMA write */
2991 ed_nic_outb(sc, ED_P0_CR, ED_CR_RD1 | ED_CR_STA);
2994 * Transfer the mbuf chain to the NIC memory.
2995 * 16-bit cards require that data be transferred as words, and only words.
2996 * So that case requires some extra code to patch over odd-length mbufs.
2999 if (!sc->isa16bit) {
3000 /* NE1000s are easy */
3003 ed_asic_outsb(sc, ED_NOVELL_DATA,
3004 m->m_data, m->m_len);
3009 /* NE2000s are a pain */
3010 unsigned char *data;
3012 unsigned char savebyte[2];
3019 data = mtod(m, caddr_t);
3020 /* finish the last word */
3022 savebyte[1] = *data;
3023 ed_asic_outw(sc, ED_NOVELL_DATA,
3024 *(u_short *)savebyte);
3029 /* output contiguous words */
3031 ed_asic_outsw(sc, ED_NOVELL_DATA,
3036 /* save last byte, if necessary */
3038 savebyte[0] = *data;
3044 /* spit last byte */
3046 ed_asic_outw(sc, ED_NOVELL_DATA, *(u_short *)savebyte);
3051 * Wait for remote DMA complete. This is necessary because on the
3052 * transmit side, data is handled internally by the NIC in bursts and
3053 * we can't start another remote DMA until this one completes. Not
3054 * waiting causes really bad things to happen - like the NIC
3055 * irrecoverably jamming the ISA bus.
3057 while (((ed_nic_inb(sc, ED_P0_ISR) & ED_ISR_RDC) != ED_ISR_RDC) && --maxwait);
3060 log(LOG_WARNING, "%s: remote transmit DMA failed to complete\n",
3069 * Support routines to handle the HP PC Lan+ card.
3073 * HP PC Lan+: Read from NIC memory, using either PIO or memory mapped
3078 ed_hpp_readmem(sc, src, dst, amount)
3079 struct ed_softc *sc;
3082 unsigned short amount;
3085 int use_32bit_access = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS);
3088 /* Program the source address in RAM */
3089 ed_asic_outw(sc, ED_HPP_PAGE_2, src);
3092 * The HP PC Lan+ card supports word reads as well as
3093 * a memory mapped i/o port that is aliased to every
3094 * even address on the board.
3097 if (sc->hpp_mem_start) {
3099 /* Enable memory mapped access. */
3100 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options &
3101 ~(ED_HPP_OPTION_MEM_DISABLE |
3102 ED_HPP_OPTION_BOOT_ROM_ENB));
3104 if (use_32bit_access && (amount > 3)) {
3105 u_int32_t *dl = (u_int32_t *) dst;
3106 volatile u_int32_t *const sl =
3107 (u_int32_t *) sc->hpp_mem_start;
3108 u_int32_t *const fence = dl + (amount >> 2);
3110 /* Copy out NIC data. We could probably write this
3111 as a `movsl'. The currently generated code is lousy.
3117 dst += (amount & ~3);
3122 /* Finish off any words left, as a series of short reads */
3124 u_short *d = (u_short *) dst;
3125 volatile u_short *const s =
3126 (u_short *) sc->hpp_mem_start;
3127 u_short *const fence = d + (amount >> 1);
3129 /* Copy out NIC data. */
3134 dst += (amount & ~1);
3139 * read in a byte; however we need to always read 16 bits
3140 * at a time or the hardware gets into a funny state
3144 /* need to read in a short and copy LSB */
3145 volatile u_short *const s =
3146 (volatile u_short *) sc->hpp_mem_start;
3151 /* Restore Boot ROM access. */
3153 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options);
3157 /* Read in data using the I/O port */
3158 if (use_32bit_access && (amount > 3)) {
3159 ed_asic_insl(sc, ED_HPP_PAGE_4, dst, amount >> 2);
3160 dst += (amount & ~3);
3164 ed_asic_insw(sc, ED_HPP_PAGE_4, dst, amount >> 1);
3165 dst += (amount & ~1);
3168 if (amount == 1) { /* read in a short and keep the LSB */
3169 *dst = ed_asic_inw(sc, ED_HPP_PAGE_4) & 0xFF;
3175 * HP PC Lan+: Write to NIC memory, using either PIO or memory mapped
3177 * Only used in the probe routine to test the memory. 'len' must
3181 ed_hpp_writemem(sc, src, dst, len)
3182 struct ed_softc *sc;
3187 /* reset remote DMA complete flag */
3188 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
3190 /* program the write address in RAM */
3191 ed_asic_outw(sc, ED_HPP_PAGE_0, dst);
3193 if (sc->hpp_mem_start) {
3194 u_short *s = (u_short *) src;
3195 volatile u_short *d = (u_short *) sc->hpp_mem_start;
3196 u_short *const fence = s + (len >> 1);
3199 * Enable memory mapped access.
3202 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options &
3203 ~(ED_HPP_OPTION_MEM_DISABLE |
3204 ED_HPP_OPTION_BOOT_ROM_ENB));
3207 * Copy to NIC memory.
3214 * Restore Boot ROM access.
3217 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options);
3220 /* write data using I/O writes */
3221 ed_asic_outsw(sc, ED_HPP_PAGE_4, src, len / 2);
3226 * Write to HP PC Lan+ NIC memory. Access to the NIC can be by using
3227 * outsw() or via the memory mapped interface to the same register.
3228 * Writes have to be in word units; byte accesses won't work and may cause
3229 * the NIC to behave weirdly. Long word accesses are permitted if the ASIC
3234 ed_hpp_write_mbufs(struct ed_softc *sc, struct mbuf *m, int dst)
3237 unsigned short total_len;
3238 unsigned char savebyte[2];
3239 volatile u_short * const d =
3240 (volatile u_short *) sc->hpp_mem_start;
3241 int use_32bit_accesses = !(sc->hpp_id & ED_HPP_ID_16_BIT_ACCESS);
3243 /* select page 0 registers */
3244 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
3246 /* reset remote DMA complete flag */
3247 ed_nic_outb(sc, ED_P0_ISR, ED_ISR_RDC);
3249 /* program the write address in RAM */
3250 ed_asic_outw(sc, ED_HPP_PAGE_0, dst);
3252 if (sc->hpp_mem_start) /* enable memory mapped I/O */
3253 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options &
3254 ~(ED_HPP_OPTION_MEM_DISABLE |
3255 ED_HPP_OPTION_BOOT_ROM_ENB));
3260 if (sc->hpp_mem_start) { /* Memory mapped I/O port */
3262 total_len += (len = m->m_len);
3264 caddr_t data = mtod(m, caddr_t);
3265 /* finish the last word of the previous mbuf */
3267 savebyte[1] = *data;
3268 *d = *((u_short *) savebyte);
3269 data++; len--; wantbyte = 0;
3271 /* output contiguous words */
3272 if ((len > 3) && (use_32bit_accesses)) {
3273 volatile u_int32_t *const dl =
3274 (volatile u_int32_t *) d;
3275 u_int32_t *sl = (u_int32_t *) data;
3276 u_int32_t *fence = sl + (len >> 2);
3284 /* finish off remain 16 bit writes */
3286 u_short *s = (u_short *) data;
3287 u_short *fence = s + (len >> 1);
3295 /* save last byte if needed */
3296 if ((wantbyte = (len == 1)) != 0)
3297 savebyte[0] = *data;
3299 m = m->m_next; /* to next mbuf */
3301 if (wantbyte) /* write last byte */
3302 *d = *((u_short *) savebyte);
3304 /* use programmed I/O */
3306 total_len += (len = m->m_len);
3308 caddr_t data = mtod(m, caddr_t);
3309 /* finish the last word of the previous mbuf */
3311 savebyte[1] = *data;
3312 ed_asic_outw(sc, ED_HPP_PAGE_4,
3313 *((u_short *)savebyte));
3318 /* output contiguous words */
3319 if ((len > 3) && use_32bit_accesses) {
3320 ed_asic_outsl(sc, ED_HPP_PAGE_4,
3325 /* finish off remaining 16 bit accesses */
3327 ed_asic_outsw(sc, ED_HPP_PAGE_4,
3332 if ((wantbyte = (len == 1)) != 0)
3333 savebyte[0] = *data;
3338 if (wantbyte) /* spit last byte */
3339 ed_asic_outw(sc, ED_HPP_PAGE_4, *(u_short *)savebyte);
3343 if (sc->hpp_mem_start) /* turn off memory mapped i/o */
3344 ed_asic_outw(sc, ED_HPP_OPTION, sc->hpp_options);
3349 #ifndef ED_NO_MIIBUS
3351 * MII bus support routines.
3354 ed_miibus_readreg(dev, phy, reg)
3358 struct ed_softc *sc;
3362 sc = device_get_softc(dev);
3368 (*sc->mii_writebits)(sc, 0xffffffff, 32);
3369 (*sc->mii_writebits)(sc, ED_MII_STARTDELIM, ED_MII_STARTDELIM_BITS);
3370 (*sc->mii_writebits)(sc, ED_MII_READOP, ED_MII_OP_BITS);
3371 (*sc->mii_writebits)(sc, phy, ED_MII_PHY_BITS);
3372 (*sc->mii_writebits)(sc, reg, ED_MII_REG_BITS);
3374 failed = (*sc->mii_readbits)(sc, ED_MII_ACK_BITS);
3375 val = (*sc->mii_readbits)(sc, ED_MII_DATA_BITS);
3376 (*sc->mii_writebits)(sc, ED_MII_IDLE, ED_MII_IDLE_BITS);
3379 return (failed ? 0 : val);
3383 ed_miibus_writereg(dev, phy, reg, data)
3387 struct ed_softc *sc;
3391 sc = device_get_softc(dev);
3397 (*sc->mii_writebits)(sc, 0xffffffff, 32);
3398 (*sc->mii_writebits)(sc, ED_MII_STARTDELIM, ED_MII_STARTDELIM_BITS);
3399 (*sc->mii_writebits)(sc, ED_MII_WRITEOP, ED_MII_OP_BITS);
3400 (*sc->mii_writebits)(sc, phy, ED_MII_PHY_BITS);
3401 (*sc->mii_writebits)(sc, reg, ED_MII_REG_BITS);
3402 (*sc->mii_writebits)(sc, ED_MII_TURNAROUND, ED_MII_TURNAROUND_BITS);
3403 (*sc->mii_writebits)(sc, data, ED_MII_DATA_BITS);
3404 (*sc->mii_writebits)(sc, ED_MII_IDLE, ED_MII_IDLE_BITS);
3413 struct ed_softc *sc;
3414 struct mii_data *mii;
3417 if (sc->gone || sc->miibus == NULL)
3420 mii = device_get_softc(sc->miibus);
3421 return mii_mediachg(mii);
3425 ed_ifmedia_sts(ifp, ifmr)
3427 struct ifmediareq *ifmr;
3429 struct ed_softc *sc;
3430 struct mii_data *mii;
3433 if (sc->gone || sc->miibus == NULL)
3436 mii = device_get_softc(sc->miibus);
3438 ifmr->ifm_active = mii->mii_media_active;
3439 ifmr->ifm_status = mii->mii_media_status;
3443 ed_child_detached(dev, child)
3447 struct ed_softc *sc;
3449 sc = device_get_softc(dev);
3450 if (child == sc->miibus)
3457 struct ed_softc *sc;
3459 struct ifnet *ifp = (struct ifnet *)sc;
3463 /* Bit 6 in AX88190 RCR register must be set. */
3464 if (sc->chip_type == ED_CHIP_TYPE_AX88190)
3469 /* set page 1 registers */
3470 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_PAGE_1 | ED_CR_STP);
3472 if (ifp->if_flags & IFF_PROMISC) {
3475 * Reconfigure the multicast filter.
3477 for (i = 0; i < 8; i++)
3478 ed_nic_outb(sc, ED_P1_MAR(i), 0xff);
3481 * And turn on promiscuous mode. Also enable reception of
3482 * runts and packets with CRC & alignment errors.
3484 /* Set page 0 registers */
3485 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
3487 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_PRO | ED_RCR_AM |
3488 ED_RCR_AB | ED_RCR_AR | ED_RCR_SEP | reg1);
3490 /* set up multicast addresses and filter modes */
3491 if (ifp->if_flags & IFF_MULTICAST) {
3494 if (ifp->if_flags & IFF_ALLMULTI) {
3495 mcaf[0] = 0xffffffff;
3496 mcaf[1] = 0xffffffff;
3498 ds_getmcaf(sc, mcaf);
3501 * Set multicast filter on chip.
3503 for (i = 0; i < 8; i++)
3504 ed_nic_outb(sc, ED_P1_MAR(i), ((u_char *) mcaf)[i]);
3506 /* Set page 0 registers */
3507 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
3509 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_AM | ED_RCR_AB | reg1);
3513 * Initialize multicast address hashing registers to
3514 * not accept multicasts.
3516 for (i = 0; i < 8; ++i)
3517 ed_nic_outb(sc, ED_P1_MAR(i), 0x00);
3519 /* Set page 0 registers */
3520 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STP);
3522 ed_nic_outb(sc, ED_P0_RCR, ED_RCR_AB | reg1);
3529 ed_nic_outb(sc, ED_P0_CR, sc->cr_proto | ED_CR_STA);
3533 * Compute crc for ethernet address
3537 const uint8_t *addr;
3539 #define ED_POLYNOMIAL 0x04c11db6
3540 uint32_t crc = 0xffffffff;
3541 int carry, idx, bit;
3544 for (idx = 6; --idx >= 0;) {
3545 for (data = *addr++, bit = 8; --bit >= 0; data >>=1 ) {
3546 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01);
3549 crc = (crc ^ ED_POLYNOMIAL) | carry;
3557 * Compute the multicast address filter from the
3558 * list of multicast addresses we need to listen to.
3561 ds_getmcaf(sc, mcaf)
3562 struct ed_softc *sc;
3566 u_char *af = (u_char *) mcaf;
3567 struct ifmultiaddr *ifma;
3572 for (ifma = sc->arpcom.ac_if.if_multiaddrs.lh_first; ifma;
3573 ifma = ifma->ifma_link.le_next) {
3574 if (ifma->ifma_addr->sa_family != AF_LINK)
3576 index = ds_mchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr))
3578 af[index >> 3] |= 1 << (index & 7);