2 * Copyright (c) 1997, Stefan Esser <se@kfreebsd.org>
3 * Copyright (c) 2000, Michael Smith <msmith@kfreebsd.org>
4 * Copyright (c) 2000, BSDi
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice unmodified, this list of conditions, and the following
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 * __FBSDID("$FreeBSD: src/sys/dev/pci/pci.c,v 1.355.2.9.2.1 2009/04/15 03:14:26 kensmith Exp $");
30 #include <sys/cdefs.h>
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/malloc.h>
37 #include <sys/module.h>
38 #include <sys/linker.h>
39 #include <sys/fcntl.h>
41 #include <sys/kernel.h>
42 #include <sys/queue.h>
43 #include <sys/sysctl.h>
44 #include <sys/endian.h>
47 #include <machine/smp.h>
52 #include <vm/vm_extern.h>
56 #include <sys/device.h>
58 #include <sys/pciio.h>
59 #include <bus/pci/pcireg.h>
60 #include <bus/pci/pcivar.h>
61 #include <bus/pci/pci_private.h>
67 #include <contrib/dev/acpica/acpi.h>
70 #define ACPI_PWR_FOR_SLEEP(x, y, z)
73 static uint32_t pci_mapbase(unsigned mapreg);
74 static const char *pci_maptype(unsigned mapreg);
75 static int pci_mapsize(unsigned testval);
76 static int pci_maprange(unsigned mapreg);
77 static void pci_fixancient(pcicfgregs *cfg);
79 static int pci_porten(device_t pcib, int b, int s, int f);
80 static int pci_memen(device_t pcib, int b, int s, int f);
81 static void pci_assign_interrupt(device_t bus, device_t dev,
83 static int pci_add_map(device_t pcib, device_t bus, device_t dev,
84 int b, int s, int f, int reg,
85 struct resource_list *rl, int force, int prefetch);
86 static int pci_probe(device_t dev);
87 static int pci_attach(device_t dev);
88 static void pci_load_vendor_data(void);
89 static int pci_describe_parse_line(char **ptr, int *vendor,
90 int *device, char **desc);
91 static char *pci_describe_device(device_t dev);
92 static int pci_modevent(module_t mod, int what, void *arg);
93 static void pci_hdrtypedata(device_t pcib, int b, int s, int f,
95 static void pci_read_extcap(device_t pcib, pcicfgregs *cfg);
96 static int pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg,
97 int reg, uint32_t *data);
99 static int pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg,
100 int reg, uint32_t data);
102 static void pci_read_vpd(device_t pcib, pcicfgregs *cfg);
103 static void pci_disable_msi(device_t dev);
104 static void pci_enable_msi(device_t dev, uint64_t address,
106 static void pci_enable_msix(device_t dev, u_int index,
107 uint64_t address, uint32_t data);
108 static void pci_mask_msix(device_t dev, u_int index);
109 static void pci_unmask_msix(device_t dev, u_int index);
110 static int pci_msi_blacklisted(void);
111 static void pci_resume_msi(device_t dev);
112 static void pci_resume_msix(device_t dev);
114 static device_method_t pci_methods[] = {
115 /* Device interface */
116 DEVMETHOD(device_probe, pci_probe),
117 DEVMETHOD(device_attach, pci_attach),
118 DEVMETHOD(device_detach, bus_generic_detach),
119 DEVMETHOD(device_shutdown, bus_generic_shutdown),
120 DEVMETHOD(device_suspend, pci_suspend),
121 DEVMETHOD(device_resume, pci_resume),
124 DEVMETHOD(bus_print_child, pci_print_child),
125 DEVMETHOD(bus_probe_nomatch, pci_probe_nomatch),
126 DEVMETHOD(bus_read_ivar, pci_read_ivar),
127 DEVMETHOD(bus_write_ivar, pci_write_ivar),
128 DEVMETHOD(bus_driver_added, pci_driver_added),
129 DEVMETHOD(bus_setup_intr, pci_setup_intr),
130 DEVMETHOD(bus_teardown_intr, pci_teardown_intr),
132 DEVMETHOD(bus_get_resource_list,pci_get_resource_list),
133 DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
134 DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
135 DEVMETHOD(bus_delete_resource, pci_delete_resource),
136 DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
137 DEVMETHOD(bus_release_resource, bus_generic_rl_release_resource),
138 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
139 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
140 DEVMETHOD(bus_child_pnpinfo_str, pci_child_pnpinfo_str_method),
141 DEVMETHOD(bus_child_location_str, pci_child_location_str_method),
144 DEVMETHOD(pci_read_config, pci_read_config_method),
145 DEVMETHOD(pci_write_config, pci_write_config_method),
146 DEVMETHOD(pci_enable_busmaster, pci_enable_busmaster_method),
147 DEVMETHOD(pci_disable_busmaster, pci_disable_busmaster_method),
148 DEVMETHOD(pci_enable_io, pci_enable_io_method),
149 DEVMETHOD(pci_disable_io, pci_disable_io_method),
150 DEVMETHOD(pci_get_vpd_ident, pci_get_vpd_ident_method),
151 DEVMETHOD(pci_get_vpd_readonly, pci_get_vpd_readonly_method),
152 DEVMETHOD(pci_get_powerstate, pci_get_powerstate_method),
153 DEVMETHOD(pci_set_powerstate, pci_set_powerstate_method),
154 DEVMETHOD(pci_assign_interrupt, pci_assign_interrupt_method),
155 DEVMETHOD(pci_find_extcap, pci_find_extcap_method),
156 DEVMETHOD(pci_alloc_msi, pci_alloc_msi_method),
157 DEVMETHOD(pci_alloc_msix, pci_alloc_msix_method),
158 DEVMETHOD(pci_remap_msix, pci_remap_msix_method),
159 DEVMETHOD(pci_release_msi, pci_release_msi_method),
160 DEVMETHOD(pci_msi_count, pci_msi_count_method),
161 DEVMETHOD(pci_msix_count, pci_msix_count_method),
166 DEFINE_CLASS_0(pci, pci_driver, pci_methods, 0);
168 static devclass_t pci_devclass;
169 DRIVER_MODULE(pci, pcib, pci_driver, pci_devclass, pci_modevent, 0);
170 MODULE_VERSION(pci, 1);
172 static char *pci_vendordata;
173 static size_t pci_vendordata_size;
177 uint32_t devid; /* Vendor/device of the card */
179 #define PCI_QUIRK_MAP_REG 1 /* PCI map register in weird place */
180 #define PCI_QUIRK_DISABLE_MSI 2 /* MSI/MSI-X doesn't work */
185 struct pci_quirk pci_quirks[] = {
186 /* The Intel 82371AB and 82443MX has a map register at offset 0x90. */
187 { 0x71138086, PCI_QUIRK_MAP_REG, 0x90, 0 },
188 { 0x719b8086, PCI_QUIRK_MAP_REG, 0x90, 0 },
189 /* As does the Serverworks OSB4 (the SMBus mapping register) */
190 { 0x02001166, PCI_QUIRK_MAP_REG, 0x90, 0 },
193 * MSI doesn't work with the ServerWorks CNB20-HE Host Bridge
194 * or the CMIC-SL (AKA ServerWorks GC_LE).
196 { 0x00141166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
197 { 0x00171166, PCI_QUIRK_DISABLE_MSI, 0, 0 },
200 * MSI doesn't work on earlier Intel chipsets including
201 * E7500, E7501, E7505, 845, 865, 875/E7210, and 855.
203 { 0x25408086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
204 { 0x254c8086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
205 { 0x25508086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
206 { 0x25608086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
207 { 0x25708086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
208 { 0x25788086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
209 { 0x35808086, PCI_QUIRK_DISABLE_MSI, 0, 0 },
212 * MSI doesn't work with devices behind the AMD 8131 HT-PCIX
215 { 0x74501022, PCI_QUIRK_DISABLE_MSI, 0, 0 },
220 /* map register information */
221 #define PCI_MAPMEM 0x01 /* memory map */
222 #define PCI_MAPMEMP 0x02 /* prefetchable memory map */
223 #define PCI_MAPPORT 0x04 /* port map */
225 struct devlist pci_devq;
226 uint32_t pci_generation;
227 uint32_t pci_numdevs = 0;
228 static int pcie_chipset, pcix_chipset;
231 SYSCTL_NODE(_hw, OID_AUTO, pci, CTLFLAG_RD, 0, "PCI bus tuning parameters");
233 static int pci_enable_io_modes = 1;
234 TUNABLE_INT("hw.pci.enable_io_modes", &pci_enable_io_modes);
235 SYSCTL_INT(_hw_pci, OID_AUTO, enable_io_modes, CTLFLAG_RW,
236 &pci_enable_io_modes, 1,
237 "Enable I/O and memory bits in the config register. Some BIOSes do not\n\
238 enable these bits correctly. We'd like to do this all the time, but there\n\
239 are some peripherals that this causes problems with.");
241 static int pci_do_power_nodriver = 0;
242 TUNABLE_INT("hw.pci.do_power_nodriver", &pci_do_power_nodriver);
243 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_nodriver, CTLFLAG_RW,
244 &pci_do_power_nodriver, 0,
245 "Place a function into D3 state when no driver attaches to it. 0 means\n\
246 disable. 1 means conservatively place devices into D3 state. 2 means\n\
247 agressively place devices into D3 state. 3 means put absolutely everything\n\
250 static int pci_do_power_resume = 1;
251 TUNABLE_INT("hw.pci.do_power_resume", &pci_do_power_resume);
252 SYSCTL_INT(_hw_pci, OID_AUTO, do_power_resume, CTLFLAG_RW,
253 &pci_do_power_resume, 1,
254 "Transition from D3 -> D0 on resume.");
256 static int pci_do_msi = 1;
257 TUNABLE_INT("hw.pci.enable_msi", &pci_do_msi);
258 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msi, CTLFLAG_RW, &pci_do_msi, 1,
259 "Enable support for MSI interrupts");
261 static int pci_do_msix = 1;
262 TUNABLE_INT("hw.pci.enable_msix", &pci_do_msix);
263 SYSCTL_INT(_hw_pci, OID_AUTO, enable_msix, CTLFLAG_RW, &pci_do_msix, 1,
264 "Enable support for MSI-X interrupts");
266 static int pci_honor_msi_blacklist = 1;
267 TUNABLE_INT("hw.pci.honor_msi_blacklist", &pci_honor_msi_blacklist);
268 SYSCTL_INT(_hw_pci, OID_AUTO, honor_msi_blacklist, CTLFLAG_RD,
269 &pci_honor_msi_blacklist, 1, "Honor chipset blacklist for MSI");
271 /* Find a device_t by bus/slot/function in domain 0 */
274 pci_find_bsf(uint8_t bus, uint8_t slot, uint8_t func)
277 return (pci_find_dbsf(0, bus, slot, func));
280 /* Find a device_t by domain/bus/slot/function */
283 pci_find_dbsf(uint32_t domain, uint8_t bus, uint8_t slot, uint8_t func)
285 struct pci_devinfo *dinfo;
287 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
288 if ((dinfo->cfg.domain == domain) &&
289 (dinfo->cfg.bus == bus) &&
290 (dinfo->cfg.slot == slot) &&
291 (dinfo->cfg.func == func)) {
292 return (dinfo->cfg.dev);
299 /* Find a device_t by vendor/device ID */
302 pci_find_device(uint16_t vendor, uint16_t device)
304 struct pci_devinfo *dinfo;
306 STAILQ_FOREACH(dinfo, &pci_devq, pci_links) {
307 if ((dinfo->cfg.vendor == vendor) &&
308 (dinfo->cfg.device == device)) {
309 return (dinfo->cfg.dev);
316 /* return base address of memory or port map */
319 pci_mapbase(uint32_t mapreg)
322 if (PCI_BAR_MEM(mapreg))
323 return (mapreg & PCIM_BAR_MEM_BASE);
325 return (mapreg & PCIM_BAR_IO_BASE);
328 /* return map type of memory or port map */
331 pci_maptype(unsigned mapreg)
334 if (PCI_BAR_IO(mapreg))
336 if (mapreg & PCIM_BAR_MEM_PREFETCH)
337 return ("Prefetchable Memory");
341 /* return log2 of map size decoded for memory or port map */
344 pci_mapsize(uint32_t testval)
348 testval = pci_mapbase(testval);
351 while ((testval & 1) == 0)
360 /* return log2 of address range supported by map register */
363 pci_maprange(unsigned mapreg)
367 if (PCI_BAR_IO(mapreg))
370 switch (mapreg & PCIM_BAR_MEM_TYPE) {
371 case PCIM_BAR_MEM_32:
374 case PCIM_BAR_MEM_1MB:
377 case PCIM_BAR_MEM_64:
384 /* adjust some values from PCI 1.0 devices to match 2.0 standards ... */
387 pci_fixancient(pcicfgregs *cfg)
389 if (cfg->hdrtype != 0)
392 /* PCI to PCI bridges use header type 1 */
393 if (cfg->baseclass == PCIC_BRIDGE && cfg->subclass == PCIS_BRIDGE_PCI)
397 /* extract header type specific config data */
400 pci_hdrtypedata(device_t pcib, int b, int s, int f, pcicfgregs *cfg)
402 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
403 switch (cfg->hdrtype) {
405 cfg->subvendor = REG(PCIR_SUBVEND_0, 2);
406 cfg->subdevice = REG(PCIR_SUBDEV_0, 2);
407 cfg->nummaps = PCI_MAXMAPS_0;
410 cfg->nummaps = PCI_MAXMAPS_1;
413 cfg->subvendor = REG(PCIR_SUBVEND_2, 2);
414 cfg->subdevice = REG(PCIR_SUBDEV_2, 2);
415 cfg->nummaps = PCI_MAXMAPS_2;
421 /* read configuration header into pcicfgregs structure */
423 pci_read_device(device_t pcib, int d, int b, int s, int f, size_t size)
425 #define REG(n, w) PCIB_READ_CONFIG(pcib, b, s, f, n, w)
426 pcicfgregs *cfg = NULL;
427 struct pci_devinfo *devlist_entry;
428 struct devlist *devlist_head;
430 devlist_head = &pci_devq;
432 devlist_entry = NULL;
434 if (REG(PCIR_DEVVENDOR, 4) != -1) {
435 devlist_entry = kmalloc(size, M_DEVBUF, M_WAITOK | M_ZERO);
437 cfg = &devlist_entry->cfg;
443 cfg->vendor = REG(PCIR_VENDOR, 2);
444 cfg->device = REG(PCIR_DEVICE, 2);
445 cfg->cmdreg = REG(PCIR_COMMAND, 2);
446 cfg->statreg = REG(PCIR_STATUS, 2);
447 cfg->baseclass = REG(PCIR_CLASS, 1);
448 cfg->subclass = REG(PCIR_SUBCLASS, 1);
449 cfg->progif = REG(PCIR_PROGIF, 1);
450 cfg->revid = REG(PCIR_REVID, 1);
451 cfg->hdrtype = REG(PCIR_HDRTYPE, 1);
452 cfg->cachelnsz = REG(PCIR_CACHELNSZ, 1);
453 cfg->lattimer = REG(PCIR_LATTIMER, 1);
454 cfg->intpin = REG(PCIR_INTPIN, 1);
455 cfg->intline = REG(PCIR_INTLINE, 1);
459 * If using the APIC the intpin is probably wrong, since it
460 * is often setup by the BIOS with the PIC in mind.
462 if (cfg->intpin != 0) {
465 airq = pci_apic_irq(cfg->bus, cfg->slot, cfg->intpin);
467 /* PCI specific entry found in MP table */
468 if (airq != cfg->intline) {
469 undirect_pci_irq(cfg->intline);
474 * PCI interrupts might be redirected to the
475 * ISA bus according to some MP tables. Use the
476 * same methods as used by the ISA devices
477 * devices to find the proper IOAPIC int pin.
479 airq = isa_apic_irq(cfg->intline);
480 if ((airq >= 0) && (airq != cfg->intline)) {
481 /* XXX: undirect_pci_irq() ? */
482 undirect_isa_irq(cfg->intline);
489 cfg->mingnt = REG(PCIR_MINGNT, 1);
490 cfg->maxlat = REG(PCIR_MAXLAT, 1);
492 cfg->mfdev = (cfg->hdrtype & PCIM_MFDEV) != 0;
493 cfg->hdrtype &= ~PCIM_MFDEV;
496 pci_hdrtypedata(pcib, b, s, f, cfg);
498 if (REG(PCIR_STATUS, 2) & PCIM_STATUS_CAPPRESENT)
499 pci_read_extcap(pcib, cfg);
501 STAILQ_INSERT_TAIL(devlist_head, devlist_entry, pci_links);
503 devlist_entry->conf.pc_sel.pc_domain = cfg->domain;
504 devlist_entry->conf.pc_sel.pc_bus = cfg->bus;
505 devlist_entry->conf.pc_sel.pc_dev = cfg->slot;
506 devlist_entry->conf.pc_sel.pc_func = cfg->func;
507 devlist_entry->conf.pc_hdr = cfg->hdrtype;
509 devlist_entry->conf.pc_subvendor = cfg->subvendor;
510 devlist_entry->conf.pc_subdevice = cfg->subdevice;
511 devlist_entry->conf.pc_vendor = cfg->vendor;
512 devlist_entry->conf.pc_device = cfg->device;
514 devlist_entry->conf.pc_class = cfg->baseclass;
515 devlist_entry->conf.pc_subclass = cfg->subclass;
516 devlist_entry->conf.pc_progif = cfg->progif;
517 devlist_entry->conf.pc_revid = cfg->revid;
522 return (devlist_entry);
527 pci_read_extcap(device_t pcib, pcicfgregs *cfg)
529 #define REG(n, w) PCIB_READ_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, w)
530 #define WREG(n, v, w) PCIB_WRITE_CONFIG(pcib, cfg->bus, cfg->slot, cfg->func, n, v, w)
531 #if defined(__i386__) || defined(__amd64__)
535 int ptr, nextptr, ptrptr;
537 switch (cfg->hdrtype & PCIM_HDRTYPE) {
540 ptrptr = PCIR_CAP_PTR;
543 ptrptr = PCIR_CAP_PTR_2; /* cardbus capabilities ptr */
546 return; /* no extended capabilities support */
548 nextptr = REG(ptrptr, 1); /* sanity check? */
551 * Read capability entries.
553 while (nextptr != 0) {
556 kprintf("illegal PCI extended capability offset %d\n",
560 /* Find the next entry */
562 nextptr = REG(ptr + PCICAP_NEXTPTR, 1);
564 /* Process this entry */
565 switch (REG(ptr + PCICAP_ID, 1)) {
566 case PCIY_PMG: /* PCI power management */
567 if (cfg->pp.pp_cap == 0) {
568 cfg->pp.pp_cap = REG(ptr + PCIR_POWER_CAP, 2);
569 cfg->pp.pp_status = ptr + PCIR_POWER_STATUS;
570 cfg->pp.pp_pmcsr = ptr + PCIR_POWER_PMCSR;
571 if ((nextptr - ptr) > PCIR_POWER_DATA)
572 cfg->pp.pp_data = ptr + PCIR_POWER_DATA;
576 #if defined(__i386__) || defined(__amd64__)
577 case PCIY_HT: /* HyperTransport */
578 /* Determine HT-specific capability type. */
579 val = REG(ptr + PCIR_HT_COMMAND, 2);
580 switch (val & PCIM_HTCMD_CAP_MASK) {
581 case PCIM_HTCAP_MSI_MAPPING:
582 if (!(val & PCIM_HTCMD_MSI_FIXED)) {
583 /* Sanity check the mapping window. */
584 addr = REG(ptr + PCIR_HTMSI_ADDRESS_HI,
587 addr |= REG(ptr + PCIR_HTMSI_ADDRESS_LO,
589 if (addr != MSI_INTEL_ADDR_BASE)
591 "HT Bridge at pci%d:%d:%d:%d has non-default MSI window 0x%llx\n",
592 cfg->domain, cfg->bus,
593 cfg->slot, cfg->func,
596 addr = MSI_INTEL_ADDR_BASE;
598 cfg->ht.ht_msimap = ptr;
599 cfg->ht.ht_msictrl = val;
600 cfg->ht.ht_msiaddr = addr;
605 case PCIY_MSI: /* PCI MSI */
606 cfg->msi.msi_location = ptr;
607 cfg->msi.msi_ctrl = REG(ptr + PCIR_MSI_CTRL, 2);
608 cfg->msi.msi_msgnum = 1 << ((cfg->msi.msi_ctrl &
609 PCIM_MSICTRL_MMC_MASK)>>1);
611 case PCIY_MSIX: /* PCI MSI-X */
612 cfg->msix.msix_location = ptr;
613 cfg->msix.msix_ctrl = REG(ptr + PCIR_MSIX_CTRL, 2);
614 cfg->msix.msix_msgnum = (cfg->msix.msix_ctrl &
615 PCIM_MSIXCTRL_TABLE_SIZE) + 1;
616 val = REG(ptr + PCIR_MSIX_TABLE, 4);
617 cfg->msix.msix_table_bar = PCIR_BAR(val &
619 cfg->msix.msix_table_offset = val & ~PCIM_MSIX_BIR_MASK;
620 val = REG(ptr + PCIR_MSIX_PBA, 4);
621 cfg->msix.msix_pba_bar = PCIR_BAR(val &
623 cfg->msix.msix_pba_offset = val & ~PCIM_MSIX_BIR_MASK;
626 case PCIY_VPD: /* PCI Vital Product Data */
627 cfg->vpd.vpd_reg = ptr;
630 /* Should always be true. */
631 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1) {
632 val = REG(ptr + PCIR_SUBVENDCAP_ID, 4);
633 cfg->subvendor = val & 0xffff;
634 cfg->subdevice = val >> 16;
637 case PCIY_PCIX: /* PCI-X */
639 * Assume we have a PCI-X chipset if we have
640 * at least one PCI-PCI bridge with a PCI-X
641 * capability. Note that some systems with
642 * PCI-express or HT chipsets might match on
643 * this check as well.
645 if ((cfg->hdrtype & PCIM_HDRTYPE) == 1)
648 case PCIY_EXPRESS: /* PCI-express */
650 * Assume we have a PCI-express chipset if we have
651 * at least one PCI-express device.
659 /* REG and WREG use carry through to next functions */
663 * PCI Vital Product Data
666 #define PCI_VPD_TIMEOUT 1000000
669 pci_read_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t *data)
671 int count = PCI_VPD_TIMEOUT;
673 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
675 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg, 2);
677 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) != 0x8000) {
680 DELAY(1); /* limit looping */
682 *data = (REG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, 4));
689 pci_write_vpd_reg(device_t pcib, pcicfgregs *cfg, int reg, uint32_t data)
691 int count = PCI_VPD_TIMEOUT;
693 KASSERT((reg & 3) == 0, ("VPD register must by 4 byte aligned"));
695 WREG(cfg->vpd.vpd_reg + PCIR_VPD_DATA, data, 4);
696 WREG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, reg | 0x8000, 2);
697 while ((REG(cfg->vpd.vpd_reg + PCIR_VPD_ADDR, 2) & 0x8000) == 0x8000) {
700 DELAY(1); /* limit looping */
707 #undef PCI_VPD_TIMEOUT
709 struct vpd_readstate {
719 vpd_nextbyte(struct vpd_readstate *vrs, uint8_t *data)
724 if (vrs->bytesinval == 0) {
725 if (pci_read_vpd_reg(vrs->pcib, vrs->cfg, vrs->off, ®))
727 vrs->val = le32toh(reg);
729 byte = vrs->val & 0xff;
732 vrs->val = vrs->val >> 8;
733 byte = vrs->val & 0xff;
743 pcie_set_max_readrq(device_t dev, uint16_t rqsize)
747 rqsize &= PCIEM_DEVCTL_MAX_READRQ_MASK;
748 if (rqsize > PCIEM_DEVCTL_MAX_READRQ_4096) {
749 panic("%s: invalid max read request size 0x%02x\n",
750 device_get_nameunit(dev), rqsize);
752 #warning "this code is incorrect, I think"
753 pci_find_extcap_method(device_get_parent(dev), dev, PCIY_EXPRESS, &expr_ptr);
755 panic("%s: not PCI Express\n", device_get_nameunit(dev));
756 val = pci_read_config(dev, expr_ptr + PCIER_DEVCTRL, 2);
757 if ((val & PCIEM_DEVCTL_MAX_READRQ_MASK) != rqsize) {
759 device_printf(dev, "adjust device control 0x%04x", val);
760 val &= ~PCIEM_DEVCTL_MAX_READRQ_MASK;
762 pci_write_config(dev, expr_ptr + PCIER_DEVCTRL, val, 2);
765 kprintf(" -> 0x%04x\n", val);
770 pci_read_vpd(device_t pcib, pcicfgregs *cfg)
772 struct vpd_readstate vrs;
777 int alloc, off; /* alloc/off for RO/W arrays */
783 /* init vpd reader */
791 name = remain = i = 0; /* shut up stupid gcc */
792 alloc = off = 0; /* shut up stupid gcc */
793 dflen = 0; /* shut up stupid gcc */
796 if (vpd_nextbyte(&vrs, &byte)) {
801 kprintf("vpd: val: %#x, off: %d, bytesinval: %d, byte: %#hhx, " \
802 "state: %d, remain: %d, name: %#x, i: %d\n", vrs.val,
803 vrs.off, vrs.bytesinval, byte, state, remain, name, i);
806 case 0: /* item name */
808 if (vpd_nextbyte(&vrs, &byte2)) {
813 if (vpd_nextbyte(&vrs, &byte2)) {
817 remain |= byte2 << 8;
818 if (remain > (0x7f*4 - vrs.off)) {
821 "pci%d:%d:%d:%d: invalid VPD data, remain %#x\n",
822 cfg->domain, cfg->bus, cfg->slot,
828 name = (byte >> 3) & 0xf;
831 case 0x2: /* String */
832 cfg->vpd.vpd_ident = kmalloc(remain + 1,
840 case 0x10: /* VPD-R */
843 cfg->vpd.vpd_ros = kmalloc(alloc *
844 sizeof(*cfg->vpd.vpd_ros), M_DEVBUF,
848 case 0x11: /* VPD-W */
851 cfg->vpd.vpd_w = kmalloc(alloc *
852 sizeof(*cfg->vpd.vpd_w), M_DEVBUF,
856 default: /* Invalid data, abort */
862 case 1: /* Identifier String */
863 cfg->vpd.vpd_ident[i++] = byte;
866 cfg->vpd.vpd_ident[i] = '\0';
871 case 2: /* VPD-R Keyword Header */
873 cfg->vpd.vpd_ros = krealloc(cfg->vpd.vpd_ros,
874 (alloc *= 2) * sizeof(*cfg->vpd.vpd_ros),
875 M_DEVBUF, M_WAITOK | M_ZERO);
877 cfg->vpd.vpd_ros[off].keyword[0] = byte;
878 if (vpd_nextbyte(&vrs, &byte2)) {
882 cfg->vpd.vpd_ros[off].keyword[1] = byte2;
883 if (vpd_nextbyte(&vrs, &byte2)) {
889 strncmp(cfg->vpd.vpd_ros[off].keyword, "RV",
892 * if this happens, we can't trust the rest
896 "pci%d:%d:%d:%d: bad keyword length: %d\n",
897 cfg->domain, cfg->bus, cfg->slot,
902 } else if (dflen == 0) {
903 cfg->vpd.vpd_ros[off].value = kmalloc(1 *
904 sizeof(*cfg->vpd.vpd_ros[off].value),
906 cfg->vpd.vpd_ros[off].value[0] = '\x00';
908 cfg->vpd.vpd_ros[off].value = kmalloc(
910 sizeof(*cfg->vpd.vpd_ros[off].value),
914 /* keep in sync w/ state 3's transistions */
915 if (dflen == 0 && remain == 0)
923 case 3: /* VPD-R Keyword Value */
924 cfg->vpd.vpd_ros[off].value[i++] = byte;
925 if (strncmp(cfg->vpd.vpd_ros[off].keyword,
926 "RV", 2) == 0 && cksumvalid == -1) {
932 "pci%d:%d:%d:%d: bad VPD cksum, remain %hhu\n",
933 cfg->domain, cfg->bus,
934 cfg->slot, cfg->func,
943 /* keep in sync w/ state 2's transistions */
945 cfg->vpd.vpd_ros[off++].value[i++] = '\0';
946 if (dflen == 0 && remain == 0) {
947 cfg->vpd.vpd_rocnt = off;
948 cfg->vpd.vpd_ros = krealloc(cfg->vpd.vpd_ros,
949 off * sizeof(*cfg->vpd.vpd_ros),
950 M_DEVBUF, M_WAITOK | M_ZERO);
952 } else if (dflen == 0)
962 case 5: /* VPD-W Keyword Header */
964 cfg->vpd.vpd_w = krealloc(cfg->vpd.vpd_w,
965 (alloc *= 2) * sizeof(*cfg->vpd.vpd_w),
966 M_DEVBUF, M_WAITOK | M_ZERO);
968 cfg->vpd.vpd_w[off].keyword[0] = byte;
969 if (vpd_nextbyte(&vrs, &byte2)) {
973 cfg->vpd.vpd_w[off].keyword[1] = byte2;
974 if (vpd_nextbyte(&vrs, &byte2)) {
978 cfg->vpd.vpd_w[off].len = dflen = byte2;
979 cfg->vpd.vpd_w[off].start = vrs.off - vrs.bytesinval;
980 cfg->vpd.vpd_w[off].value = kmalloc((dflen + 1) *
981 sizeof(*cfg->vpd.vpd_w[off].value),
985 /* keep in sync w/ state 6's transistions */
986 if (dflen == 0 && remain == 0)
994 case 6: /* VPD-W Keyword Value */
995 cfg->vpd.vpd_w[off].value[i++] = byte;
998 /* keep in sync w/ state 5's transistions */
1000 cfg->vpd.vpd_w[off++].value[i++] = '\0';
1001 if (dflen == 0 && remain == 0) {
1002 cfg->vpd.vpd_wcnt = off;
1003 cfg->vpd.vpd_w = krealloc(cfg->vpd.vpd_w,
1004 off * sizeof(*cfg->vpd.vpd_w),
1005 M_DEVBUF, M_WAITOK | M_ZERO);
1007 } else if (dflen == 0)
1012 kprintf("pci%d:%d:%d:%d: invalid state: %d\n",
1013 cfg->domain, cfg->bus, cfg->slot, cfg->func,
1020 if (cksumvalid == 0 || state < -1) {
1021 /* read-only data bad, clean up */
1022 if (cfg->vpd.vpd_ros != NULL) {
1023 for (off = 0; cfg->vpd.vpd_ros[off].value; off++)
1024 kfree(cfg->vpd.vpd_ros[off].value, M_DEVBUF);
1025 kfree(cfg->vpd.vpd_ros, M_DEVBUF);
1026 cfg->vpd.vpd_ros = NULL;
1030 /* I/O error, clean up */
1031 kprintf("pci%d:%d:%d:%d: failed to read VPD data.\n",
1032 cfg->domain, cfg->bus, cfg->slot, cfg->func);
1033 if (cfg->vpd.vpd_ident != NULL) {
1034 kfree(cfg->vpd.vpd_ident, M_DEVBUF);
1035 cfg->vpd.vpd_ident = NULL;
1037 if (cfg->vpd.vpd_w != NULL) {
1038 for (off = 0; cfg->vpd.vpd_w[off].value; off++)
1039 kfree(cfg->vpd.vpd_w[off].value, M_DEVBUF);
1040 kfree(cfg->vpd.vpd_w, M_DEVBUF);
1041 cfg->vpd.vpd_w = NULL;
1044 cfg->vpd.vpd_cached = 1;
1050 pci_get_vpd_ident_method(device_t dev, device_t child, const char **identptr)
1052 struct pci_devinfo *dinfo = device_get_ivars(child);
1053 pcicfgregs *cfg = &dinfo->cfg;
1055 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1056 pci_read_vpd(device_get_parent(dev), cfg);
1058 *identptr = cfg->vpd.vpd_ident;
1060 if (*identptr == NULL)
1067 pci_get_vpd_readonly_method(device_t dev, device_t child, const char *kw,
1070 struct pci_devinfo *dinfo = device_get_ivars(child);
1071 pcicfgregs *cfg = &dinfo->cfg;
1074 if (!cfg->vpd.vpd_cached && cfg->vpd.vpd_reg != 0)
1075 pci_read_vpd(device_get_parent(dev), cfg);
1077 for (i = 0; i < cfg->vpd.vpd_rocnt; i++)
1078 if (memcmp(kw, cfg->vpd.vpd_ros[i].keyword,
1079 sizeof(cfg->vpd.vpd_ros[i].keyword)) == 0) {
1080 *vptr = cfg->vpd.vpd_ros[i].value;
1083 if (i != cfg->vpd.vpd_rocnt)
1091 * Return the offset in configuration space of the requested extended
1092 * capability entry or 0 if the specified capability was not found.
1095 pci_find_extcap_method(device_t dev, device_t child, int capability,
1098 struct pci_devinfo *dinfo = device_get_ivars(child);
1099 pcicfgregs *cfg = &dinfo->cfg;
1104 * Check the CAP_LIST bit of the PCI status register first.
1106 status = pci_read_config(child, PCIR_STATUS, 2);
1107 if (!(status & PCIM_STATUS_CAPPRESENT))
1111 * Determine the start pointer of the capabilities list.
1113 switch (cfg->hdrtype & PCIM_HDRTYPE) {
1119 ptr = PCIR_CAP_PTR_2;
1123 return (ENXIO); /* no extended capabilities support */
1125 ptr = pci_read_config(child, ptr, 1);
1128 * Traverse the capabilities list.
1131 if (pci_read_config(child, ptr + PCICAP_ID, 1) == capability) {
1136 ptr = pci_read_config(child, ptr + PCICAP_NEXTPTR, 1);
1143 * Support for MSI-X message interrupts.
1146 pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data)
1148 struct pci_devinfo *dinfo = device_get_ivars(dev);
1149 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1152 KASSERT(msix->msix_table_len > index, ("bogus index"));
1153 offset = msix->msix_table_offset + index * 16;
1154 bus_write_4(msix->msix_table_res, offset, address & 0xffffffff);
1155 bus_write_4(msix->msix_table_res, offset + 4, address >> 32);
1156 bus_write_4(msix->msix_table_res, offset + 8, data);
1158 /* Enable MSI -> HT mapping. */
1159 pci_ht_map_msi(dev, address);
1163 pci_mask_msix(device_t dev, u_int index)
1165 struct pci_devinfo *dinfo = device_get_ivars(dev);
1166 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1167 uint32_t offset, val;
1169 KASSERT(msix->msix_msgnum > index, ("bogus index"));
1170 offset = msix->msix_table_offset + index * 16 + 12;
1171 val = bus_read_4(msix->msix_table_res, offset);
1172 if (!(val & PCIM_MSIX_VCTRL_MASK)) {
1173 val |= PCIM_MSIX_VCTRL_MASK;
1174 bus_write_4(msix->msix_table_res, offset, val);
1179 pci_unmask_msix(device_t dev, u_int index)
1181 struct pci_devinfo *dinfo = device_get_ivars(dev);
1182 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1183 uint32_t offset, val;
1185 KASSERT(msix->msix_table_len > index, ("bogus index"));
1186 offset = msix->msix_table_offset + index * 16 + 12;
1187 val = bus_read_4(msix->msix_table_res, offset);
1188 if (val & PCIM_MSIX_VCTRL_MASK) {
1189 val &= ~PCIM_MSIX_VCTRL_MASK;
1190 bus_write_4(msix->msix_table_res, offset, val);
1195 pci_pending_msix(device_t dev, u_int index)
1197 struct pci_devinfo *dinfo = device_get_ivars(dev);
1198 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1199 uint32_t offset, bit;
1201 KASSERT(msix->msix_table_len > index, ("bogus index"));
1202 offset = msix->msix_pba_offset + (index / 32) * 4;
1203 bit = 1 << index % 32;
1204 return (bus_read_4(msix->msix_pba_res, offset) & bit);
1208 * Restore MSI-X registers and table during resume. If MSI-X is
1209 * enabled then walk the virtual table to restore the actual MSI-X
1213 pci_resume_msix(device_t dev)
1215 struct pci_devinfo *dinfo = device_get_ivars(dev);
1216 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1217 struct msix_table_entry *mte;
1218 struct msix_vector *mv;
1221 if (msix->msix_alloc > 0) {
1222 /* First, mask all vectors. */
1223 for (i = 0; i < msix->msix_msgnum; i++)
1224 pci_mask_msix(dev, i);
1226 /* Second, program any messages with at least one handler. */
1227 for (i = 0; i < msix->msix_table_len; i++) {
1228 mte = &msix->msix_table[i];
1229 if (mte->mte_vector == 0 || mte->mte_handlers == 0)
1231 mv = &msix->msix_vectors[mte->mte_vector - 1];
1232 pci_enable_msix(dev, i, mv->mv_address, mv->mv_data);
1233 pci_unmask_msix(dev, i);
1236 pci_write_config(dev, msix->msix_location + PCIR_MSIX_CTRL,
1237 msix->msix_ctrl, 2);
1241 * Attempt to allocate *count MSI-X messages. The actual number allocated is
1242 * returned in *count. After this function returns, each message will be
1243 * available to the driver as SYS_RES_IRQ resources starting at rid 1.
1246 pci_alloc_msix_method(device_t dev, device_t child, int *count)
1248 struct pci_devinfo *dinfo = device_get_ivars(child);
1249 pcicfgregs *cfg = &dinfo->cfg;
1250 struct resource_list_entry *rle;
1251 int actual, error, i, irq, max;
1253 /* Don't let count == 0 get us into trouble. */
1257 /* If rid 0 is allocated, then fail. */
1258 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1259 if (rle != NULL && rle->res != NULL)
1262 /* Already have allocated messages? */
1263 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
1266 /* If MSI is blacklisted for this system, fail. */
1267 if (pci_msi_blacklisted())
1270 /* MSI-X capability present? */
1271 if (cfg->msix.msix_location == 0 || !pci_do_msix)
1274 /* Make sure the appropriate BARs are mapped. */
1275 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1276 cfg->msix.msix_table_bar);
1277 if (rle == NULL || rle->res == NULL ||
1278 !(rman_get_flags(rle->res) & RF_ACTIVE))
1280 cfg->msix.msix_table_res = rle->res;
1281 if (cfg->msix.msix_pba_bar != cfg->msix.msix_table_bar) {
1282 rle = resource_list_find(&dinfo->resources, SYS_RES_MEMORY,
1283 cfg->msix.msix_pba_bar);
1284 if (rle == NULL || rle->res == NULL ||
1285 !(rman_get_flags(rle->res) & RF_ACTIVE))
1288 cfg->msix.msix_pba_res = rle->res;
1291 device_printf(child,
1292 "attempting to allocate %d MSI-X vectors (%d supported)\n",
1293 *count, cfg->msix.msix_msgnum);
1294 max = min(*count, cfg->msix.msix_msgnum);
1295 for (i = 0; i < max; i++) {
1296 /* Allocate a message. */
1297 error = PCIB_ALLOC_MSIX(device_get_parent(dev), child, &irq);
1300 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
1306 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 1);
1308 device_printf(child, "using IRQ %lu for MSI-X\n",
1314 * Be fancy and try to print contiguous runs of
1315 * IRQ values as ranges. 'irq' is the previous IRQ.
1316 * 'run' is true if we are in a range.
1318 device_printf(child, "using IRQs %lu", rle->start);
1321 for (i = 1; i < actual; i++) {
1322 rle = resource_list_find(&dinfo->resources,
1323 SYS_RES_IRQ, i + 1);
1325 /* Still in a run? */
1326 if (rle->start == irq + 1) {
1332 /* Finish previous range. */
1334 kprintf("-%d", irq);
1338 /* Start new range. */
1339 kprintf(",%lu", rle->start);
1343 /* Unfinished range? */
1345 kprintf("-%d", irq);
1346 kprintf(" for MSI-X\n");
1350 /* Mask all vectors. */
1351 for (i = 0; i < cfg->msix.msix_msgnum; i++)
1352 pci_mask_msix(child, i);
1354 /* Allocate and initialize vector data and virtual table. */
1355 cfg->msix.msix_vectors = kmalloc(sizeof(struct msix_vector) * actual,
1356 M_DEVBUF, M_WAITOK | M_ZERO);
1357 cfg->msix.msix_table = kmalloc(sizeof(struct msix_table_entry) * actual,
1358 M_DEVBUF, M_WAITOK | M_ZERO);
1359 for (i = 0; i < actual; i++) {
1360 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1361 cfg->msix.msix_vectors[i].mv_irq = rle->start;
1362 cfg->msix.msix_table[i].mte_vector = i + 1;
1365 /* Update control register to enable MSI-X. */
1366 cfg->msix.msix_ctrl |= PCIM_MSIXCTRL_MSIX_ENABLE;
1367 pci_write_config(child, cfg->msix.msix_location + PCIR_MSIX_CTRL,
1368 cfg->msix.msix_ctrl, 2);
1370 /* Update counts of alloc'd messages. */
1371 cfg->msix.msix_alloc = actual;
1372 cfg->msix.msix_table_len = actual;
1378 * By default, pci_alloc_msix() will assign the allocated IRQ
1379 * resources consecutively to the first N messages in the MSI-X table.
1380 * However, device drivers may want to use different layouts if they
1381 * either receive fewer messages than they asked for, or they wish to
1382 * populate the MSI-X table sparsely. This method allows the driver
1383 * to specify what layout it wants. It must be called after a
1384 * successful pci_alloc_msix() but before any of the associated
1385 * SYS_RES_IRQ resources are allocated via bus_alloc_resource().
1387 * The 'vectors' array contains 'count' message vectors. The array
1388 * maps directly to the MSI-X table in that index 0 in the array
1389 * specifies the vector for the first message in the MSI-X table, etc.
1390 * The vector value in each array index can either be 0 to indicate
1391 * that no vector should be assigned to a message slot, or it can be a
1392 * number from 1 to N (where N is the count returned from a
1393 * succcessful call to pci_alloc_msix()) to indicate which message
1394 * vector (IRQ) to be used for the corresponding message.
1396 * On successful return, each message with a non-zero vector will have
1397 * an associated SYS_RES_IRQ whose rid is equal to the array index +
1398 * 1. Additionally, if any of the IRQs allocated via the previous
1399 * call to pci_alloc_msix() are not used in the mapping, those IRQs
1400 * will be kfreed back to the system automatically.
1402 * For example, suppose a driver has a MSI-X table with 6 messages and
1403 * asks for 6 messages, but pci_alloc_msix() only returns a count of
1404 * 3. Call the three vectors allocated by pci_alloc_msix() A, B, and
1405 * C. After the call to pci_alloc_msix(), the device will be setup to
1406 * have an MSI-X table of ABC--- (where - means no vector assigned).
1407 * If the driver ten passes a vector array of { 1, 0, 1, 2, 0, 2 },
1408 * then the MSI-X table will look like A-AB-B, and the 'C' vector will
1409 * be kfreed back to the system. This device will also have valid
1410 * SYS_RES_IRQ rids of 1, 3, 4, and 6.
1412 * In any case, the SYS_RES_IRQ rid X will always map to the message
1413 * at MSI-X table index X - 1 and will only be valid if a vector is
1414 * assigned to that table entry.
1417 pci_remap_msix_method(device_t dev, device_t child, int count,
1418 const u_int *vectors)
1420 struct pci_devinfo *dinfo = device_get_ivars(child);
1421 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1422 struct resource_list_entry *rle;
1423 int i, irq, j, *used;
1426 * Have to have at least one message in the table but the
1427 * table can't be bigger than the actual MSI-X table in the
1430 if (count == 0 || count > msix->msix_msgnum)
1433 /* Sanity check the vectors. */
1434 for (i = 0; i < count; i++)
1435 if (vectors[i] > msix->msix_alloc)
1439 * Make sure there aren't any holes in the vectors to be used.
1440 * It's a big pain to support it, and it doesn't really make
1441 * sense anyway. Also, at least one vector must be used.
1443 used = kmalloc(sizeof(int) * msix->msix_alloc, M_DEVBUF, M_WAITOK |
1445 for (i = 0; i < count; i++)
1446 if (vectors[i] != 0)
1447 used[vectors[i] - 1] = 1;
1448 for (i = 0; i < msix->msix_alloc - 1; i++)
1449 if (used[i] == 0 && used[i + 1] == 1) {
1450 kfree(used, M_DEVBUF);
1454 kfree(used, M_DEVBUF);
1458 /* Make sure none of the resources are allocated. */
1459 for (i = 0; i < msix->msix_table_len; i++) {
1460 if (msix->msix_table[i].mte_vector == 0)
1462 if (msix->msix_table[i].mte_handlers > 0)
1464 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1465 KASSERT(rle != NULL, ("missing resource"));
1466 if (rle->res != NULL)
1470 /* Free the existing resource list entries. */
1471 for (i = 0; i < msix->msix_table_len; i++) {
1472 if (msix->msix_table[i].mte_vector == 0)
1474 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1478 * Build the new virtual table keeping track of which vectors are
1481 kfree(msix->msix_table, M_DEVBUF);
1482 msix->msix_table = kmalloc(sizeof(struct msix_table_entry) * count,
1483 M_DEVBUF, M_WAITOK | M_ZERO);
1484 for (i = 0; i < count; i++)
1485 msix->msix_table[i].mte_vector = vectors[i];
1486 msix->msix_table_len = count;
1488 /* Free any unused IRQs and resize the vectors array if necessary. */
1489 j = msix->msix_alloc - 1;
1491 struct msix_vector *vec;
1493 while (used[j] == 0) {
1494 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
1495 msix->msix_vectors[j].mv_irq);
1498 vec = kmalloc(sizeof(struct msix_vector) * (j + 1), M_DEVBUF,
1500 bcopy(msix->msix_vectors, vec, sizeof(struct msix_vector) *
1502 kfree(msix->msix_vectors, M_DEVBUF);
1503 msix->msix_vectors = vec;
1504 msix->msix_alloc = j + 1;
1506 kfree(used, M_DEVBUF);
1508 /* Map the IRQs onto the rids. */
1509 for (i = 0; i < count; i++) {
1510 if (vectors[i] == 0)
1512 irq = msix->msix_vectors[vectors[i]].mv_irq;
1513 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1, irq,
1518 device_printf(child, "Remapped MSI-X IRQs as: ");
1519 for (i = 0; i < count; i++) {
1522 if (vectors[i] == 0)
1526 msix->msix_vectors[vectors[i]].mv_irq);
1535 pci_release_msix(device_t dev, device_t child)
1537 struct pci_devinfo *dinfo = device_get_ivars(child);
1538 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1539 struct resource_list_entry *rle;
1542 /* Do we have any messages to release? */
1543 if (msix->msix_alloc == 0)
1546 /* Make sure none of the resources are allocated. */
1547 for (i = 0; i < msix->msix_table_len; i++) {
1548 if (msix->msix_table[i].mte_vector == 0)
1550 if (msix->msix_table[i].mte_handlers > 0)
1552 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1553 KASSERT(rle != NULL, ("missing resource"));
1554 if (rle->res != NULL)
1558 /* Update control register to disable MSI-X. */
1559 msix->msix_ctrl &= ~PCIM_MSIXCTRL_MSIX_ENABLE;
1560 pci_write_config(child, msix->msix_location + PCIR_MSIX_CTRL,
1561 msix->msix_ctrl, 2);
1563 /* Free the resource list entries. */
1564 for (i = 0; i < msix->msix_table_len; i++) {
1565 if (msix->msix_table[i].mte_vector == 0)
1567 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1569 kfree(msix->msix_table, M_DEVBUF);
1570 msix->msix_table_len = 0;
1572 /* Release the IRQs. */
1573 for (i = 0; i < msix->msix_alloc; i++)
1574 PCIB_RELEASE_MSIX(device_get_parent(dev), child,
1575 msix->msix_vectors[i].mv_irq);
1576 kfree(msix->msix_vectors, M_DEVBUF);
1577 msix->msix_alloc = 0;
1582 * Return the max supported MSI-X messages this device supports.
1583 * Basically, assuming the MD code can alloc messages, this function
1584 * should return the maximum value that pci_alloc_msix() can return.
1585 * Thus, it is subject to the tunables, etc.
1588 pci_msix_count_method(device_t dev, device_t child)
1590 struct pci_devinfo *dinfo = device_get_ivars(child);
1591 struct pcicfg_msix *msix = &dinfo->cfg.msix;
1593 if (pci_do_msix && msix->msix_location != 0)
1594 return (msix->msix_msgnum);
1599 * HyperTransport MSI mapping control
1602 pci_ht_map_msi(device_t dev, uint64_t addr)
1604 struct pci_devinfo *dinfo = device_get_ivars(dev);
1605 struct pcicfg_ht *ht = &dinfo->cfg.ht;
1610 if (addr && !(ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) &&
1611 ht->ht_msiaddr >> 20 == addr >> 20) {
1612 /* Enable MSI -> HT mapping. */
1613 ht->ht_msictrl |= PCIM_HTCMD_MSI_ENABLE;
1614 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1618 if (!addr && ht->ht_msictrl & PCIM_HTCMD_MSI_ENABLE) {
1619 /* Disable MSI -> HT mapping. */
1620 ht->ht_msictrl &= ~PCIM_HTCMD_MSI_ENABLE;
1621 pci_write_config(dev, ht->ht_msimap + PCIR_HT_COMMAND,
1627 * Support for MSI message signalled interrupts.
1630 pci_enable_msi(device_t dev, uint64_t address, uint16_t data)
1632 struct pci_devinfo *dinfo = device_get_ivars(dev);
1633 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1635 /* Write data and address values. */
1636 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1637 address & 0xffffffff, 4);
1638 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1639 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR_HIGH,
1641 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA_64BIT,
1644 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA, data,
1647 /* Enable MSI in the control register. */
1648 msi->msi_ctrl |= PCIM_MSICTRL_MSI_ENABLE;
1649 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1652 /* Enable MSI -> HT mapping. */
1653 pci_ht_map_msi(dev, address);
1657 pci_disable_msi(device_t dev)
1659 struct pci_devinfo *dinfo = device_get_ivars(dev);
1660 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1662 /* Disable MSI -> HT mapping. */
1663 pci_ht_map_msi(dev, 0);
1665 /* Disable MSI in the control register. */
1666 msi->msi_ctrl &= ~PCIM_MSICTRL_MSI_ENABLE;
1667 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1672 * Restore MSI registers during resume. If MSI is enabled then
1673 * restore the data and address registers in addition to the control
1677 pci_resume_msi(device_t dev)
1679 struct pci_devinfo *dinfo = device_get_ivars(dev);
1680 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1684 if (msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE) {
1685 address = msi->msi_addr;
1686 data = msi->msi_data;
1687 pci_write_config(dev, msi->msi_location + PCIR_MSI_ADDR,
1688 address & 0xffffffff, 4);
1689 if (msi->msi_ctrl & PCIM_MSICTRL_64BIT) {
1690 pci_write_config(dev, msi->msi_location +
1691 PCIR_MSI_ADDR_HIGH, address >> 32, 4);
1692 pci_write_config(dev, msi->msi_location +
1693 PCIR_MSI_DATA_64BIT, data, 2);
1695 pci_write_config(dev, msi->msi_location + PCIR_MSI_DATA,
1698 pci_write_config(dev, msi->msi_location + PCIR_MSI_CTRL, msi->msi_ctrl,
1703 pci_remap_msi_irq(device_t dev, u_int irq)
1705 struct pci_devinfo *dinfo = device_get_ivars(dev);
1706 pcicfgregs *cfg = &dinfo->cfg;
1707 struct resource_list_entry *rle;
1708 struct msix_table_entry *mte;
1709 struct msix_vector *mv;
1715 bus = device_get_parent(dev);
1718 * Handle MSI first. We try to find this IRQ among our list
1719 * of MSI IRQs. If we find it, we request updated address and
1720 * data registers and apply the results.
1722 if (cfg->msi.msi_alloc > 0) {
1724 /* If we don't have any active handlers, nothing to do. */
1725 if (cfg->msi.msi_handlers == 0)
1727 for (i = 0; i < cfg->msi.msi_alloc; i++) {
1728 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ,
1730 if (rle->start == irq) {
1731 error = PCIB_MAP_MSI(device_get_parent(bus),
1732 dev, irq, &addr, &data);
1735 pci_disable_msi(dev);
1736 dinfo->cfg.msi.msi_addr = addr;
1737 dinfo->cfg.msi.msi_data = data;
1738 pci_enable_msi(dev, addr, data);
1746 * For MSI-X, we check to see if we have this IRQ. If we do,
1747 * we request the updated mapping info. If that works, we go
1748 * through all the slots that use this IRQ and update them.
1750 if (cfg->msix.msix_alloc > 0) {
1751 for (i = 0; i < cfg->msix.msix_alloc; i++) {
1752 mv = &cfg->msix.msix_vectors[i];
1753 if (mv->mv_irq == irq) {
1754 error = PCIB_MAP_MSI(device_get_parent(bus),
1755 dev, irq, &addr, &data);
1758 mv->mv_address = addr;
1760 for (j = 0; j < cfg->msix.msix_table_len; j++) {
1761 mte = &cfg->msix.msix_table[j];
1762 if (mte->mte_vector != i + 1)
1764 if (mte->mte_handlers == 0)
1766 pci_mask_msix(dev, j);
1767 pci_enable_msix(dev, j, addr, data);
1768 pci_unmask_msix(dev, j);
1779 * Returns true if the specified device is blacklisted because MSI
1783 pci_msi_device_blacklisted(device_t dev)
1785 struct pci_quirk *q;
1787 if (!pci_honor_msi_blacklist)
1790 for (q = &pci_quirks[0]; q->devid; q++) {
1791 if (q->devid == pci_get_devid(dev) &&
1792 q->type == PCI_QUIRK_DISABLE_MSI)
1799 * Determine if MSI is blacklisted globally on this sytem. Currently,
1800 * we just check for blacklisted chipsets as represented by the
1801 * host-PCI bridge at device 0:0:0. In the future, it may become
1802 * necessary to check other system attributes, such as the kenv values
1803 * that give the motherboard manufacturer and model number.
1806 pci_msi_blacklisted(void)
1810 if (!pci_honor_msi_blacklist)
1813 /* Blacklist all non-PCI-express and non-PCI-X chipsets. */
1814 if (!(pcie_chipset || pcix_chipset))
1817 dev = pci_find_bsf(0, 0, 0);
1819 return (pci_msi_device_blacklisted(dev));
1824 * Attempt to allocate *count MSI messages. The actual number allocated is
1825 * returned in *count. After this function returns, each message will be
1826 * available to the driver as SYS_RES_IRQ resources starting at a rid 1.
1829 pci_alloc_msi_method(device_t dev, device_t child, int *count)
1831 struct pci_devinfo *dinfo = device_get_ivars(child);
1832 pcicfgregs *cfg = &dinfo->cfg;
1833 struct resource_list_entry *rle;
1834 int actual, error, i, irqs[32];
1837 /* Don't let count == 0 get us into trouble. */
1841 /* If rid 0 is allocated, then fail. */
1842 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, 0);
1843 if (rle != NULL && rle->res != NULL)
1846 /* Already have allocated messages? */
1847 if (cfg->msi.msi_alloc != 0 || cfg->msix.msix_alloc != 0)
1850 /* If MSI is blacklisted for this system, fail. */
1851 if (pci_msi_blacklisted())
1854 /* MSI capability present? */
1855 if (cfg->msi.msi_location == 0 || !pci_do_msi)
1859 device_printf(child,
1860 "attempting to allocate %d MSI vectors (%d supported)\n",
1861 *count, cfg->msi.msi_msgnum);
1863 /* Don't ask for more than the device supports. */
1864 actual = min(*count, cfg->msi.msi_msgnum);
1866 /* Don't ask for more than 32 messages. */
1867 actual = min(actual, 32);
1869 /* MSI requires power of 2 number of messages. */
1870 if (!powerof2(actual))
1874 /* Try to allocate N messages. */
1875 error = PCIB_ALLOC_MSI(device_get_parent(dev), child, actual,
1876 cfg->msi.msi_msgnum, irqs);
1887 * We now have N actual messages mapped onto SYS_RES_IRQ
1888 * resources in the irqs[] array, so add new resources
1889 * starting at rid 1.
1891 for (i = 0; i < actual; i++)
1892 resource_list_add(&dinfo->resources, SYS_RES_IRQ, i + 1,
1893 irqs[i], irqs[i], 1);
1897 device_printf(child, "using IRQ %d for MSI\n", irqs[0]);
1902 * Be fancy and try to print contiguous runs
1903 * of IRQ values as ranges. 'run' is true if
1904 * we are in a range.
1906 device_printf(child, "using IRQs %d", irqs[0]);
1908 for (i = 1; i < actual; i++) {
1910 /* Still in a run? */
1911 if (irqs[i] == irqs[i - 1] + 1) {
1916 /* Finish previous range. */
1918 kprintf("-%d", irqs[i - 1]);
1922 /* Start new range. */
1923 kprintf(",%d", irqs[i]);
1926 /* Unfinished range? */
1928 kprintf("-%d", irqs[actual - 1]);
1929 kprintf(" for MSI\n");
1933 /* Update control register with actual count. */
1934 ctrl = cfg->msi.msi_ctrl;
1935 ctrl &= ~PCIM_MSICTRL_MME_MASK;
1936 ctrl |= (ffs(actual) - 1) << 4;
1937 cfg->msi.msi_ctrl = ctrl;
1938 pci_write_config(child, cfg->msi.msi_location + PCIR_MSI_CTRL, ctrl, 2);
1940 /* Update counts of alloc'd messages. */
1941 cfg->msi.msi_alloc = actual;
1942 cfg->msi.msi_handlers = 0;
1947 /* Release the MSI messages associated with this device. */
1949 pci_release_msi_method(device_t dev, device_t child)
1951 struct pci_devinfo *dinfo = device_get_ivars(child);
1952 struct pcicfg_msi *msi = &dinfo->cfg.msi;
1953 struct resource_list_entry *rle;
1954 int error, i, irqs[32];
1956 /* Try MSI-X first. */
1957 error = pci_release_msix(dev, child);
1958 if (error != ENODEV)
1961 /* Do we have any messages to release? */
1962 if (msi->msi_alloc == 0)
1964 KASSERT(msi->msi_alloc <= 32, ("more than 32 alloc'd messages"));
1966 /* Make sure none of the resources are allocated. */
1967 if (msi->msi_handlers > 0)
1969 for (i = 0; i < msi->msi_alloc; i++) {
1970 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, i + 1);
1971 KASSERT(rle != NULL, ("missing MSI resource"));
1972 if (rle->res != NULL)
1974 irqs[i] = rle->start;
1977 /* Update control register with 0 count. */
1978 KASSERT(!(msi->msi_ctrl & PCIM_MSICTRL_MSI_ENABLE),
1979 ("%s: MSI still enabled", __func__));
1980 msi->msi_ctrl &= ~PCIM_MSICTRL_MME_MASK;
1981 pci_write_config(child, msi->msi_location + PCIR_MSI_CTRL,
1984 /* Release the messages. */
1985 PCIB_RELEASE_MSI(device_get_parent(dev), child, msi->msi_alloc, irqs);
1986 for (i = 0; i < msi->msi_alloc; i++)
1987 resource_list_delete(&dinfo->resources, SYS_RES_IRQ, i + 1);
1989 /* Update alloc count. */
1997 * Return the max supported MSI messages this device supports.
1998 * Basically, assuming the MD code can alloc messages, this function
1999 * should return the maximum value that pci_alloc_msi() can return.
2000 * Thus, it is subject to the tunables, etc.
2003 pci_msi_count_method(device_t dev, device_t child)
2005 struct pci_devinfo *dinfo = device_get_ivars(child);
2006 struct pcicfg_msi *msi = &dinfo->cfg.msi;
2008 if (pci_do_msi && msi->msi_location != 0)
2009 return (msi->msi_msgnum);
2013 /* kfree pcicfgregs structure and all depending data structures */
2016 pci_freecfg(struct pci_devinfo *dinfo)
2018 struct devlist *devlist_head;
2021 devlist_head = &pci_devq;
2023 if (dinfo->cfg.vpd.vpd_reg) {
2024 kfree(dinfo->cfg.vpd.vpd_ident, M_DEVBUF);
2025 for (i = 0; i < dinfo->cfg.vpd.vpd_rocnt; i++)
2026 kfree(dinfo->cfg.vpd.vpd_ros[i].value, M_DEVBUF);
2027 kfree(dinfo->cfg.vpd.vpd_ros, M_DEVBUF);
2028 for (i = 0; i < dinfo->cfg.vpd.vpd_wcnt; i++)
2029 kfree(dinfo->cfg.vpd.vpd_w[i].value, M_DEVBUF);
2030 kfree(dinfo->cfg.vpd.vpd_w, M_DEVBUF);
2032 STAILQ_REMOVE(devlist_head, dinfo, pci_devinfo, pci_links);
2033 kfree(dinfo, M_DEVBUF);
2035 /* increment the generation count */
2038 /* we're losing one device */
2044 * PCI power manangement
2047 pci_set_powerstate_method(device_t dev, device_t child, int state)
2049 struct pci_devinfo *dinfo = device_get_ivars(child);
2050 pcicfgregs *cfg = &dinfo->cfg;
2052 int result, oldstate, highest, delay;
2054 if (cfg->pp.pp_cap == 0)
2055 return (EOPNOTSUPP);
2058 * Optimize a no state change request away. While it would be OK to
2059 * write to the hardware in theory, some devices have shown odd
2060 * behavior when going from D3 -> D3.
2062 oldstate = pci_get_powerstate(child);
2063 if (oldstate == state)
2067 * The PCI power management specification states that after a state
2068 * transition between PCI power states, system software must
2069 * guarantee a minimal delay before the function accesses the device.
2070 * Compute the worst case delay that we need to guarantee before we
2071 * access the device. Many devices will be responsive much more
2072 * quickly than this delay, but there are some that don't respond
2073 * instantly to state changes. Transitions to/from D3 state require
2074 * 10ms, while D2 requires 200us, and D0/1 require none. The delay
2075 * is done below with DELAY rather than a sleeper function because
2076 * this function can be called from contexts where we cannot sleep.
2078 highest = (oldstate > state) ? oldstate : state;
2079 if (highest == PCI_POWERSTATE_D3)
2081 else if (highest == PCI_POWERSTATE_D2)
2085 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2)
2086 & ~PCIM_PSTAT_DMASK;
2089 case PCI_POWERSTATE_D0:
2090 status |= PCIM_PSTAT_D0;
2092 case PCI_POWERSTATE_D1:
2093 if ((cfg->pp.pp_cap & PCIM_PCAP_D1SUPP) == 0)
2094 return (EOPNOTSUPP);
2095 status |= PCIM_PSTAT_D1;
2097 case PCI_POWERSTATE_D2:
2098 if ((cfg->pp.pp_cap & PCIM_PCAP_D2SUPP) == 0)
2099 return (EOPNOTSUPP);
2100 status |= PCIM_PSTAT_D2;
2102 case PCI_POWERSTATE_D3:
2103 status |= PCIM_PSTAT_D3;
2111 "pci%d:%d:%d:%d: Transition from D%d to D%d\n",
2112 dinfo->cfg.domain, dinfo->cfg.bus, dinfo->cfg.slot,
2113 dinfo->cfg.func, oldstate, state);
2115 PCI_WRITE_CONFIG(dev, child, cfg->pp.pp_status, status, 2);
2122 pci_get_powerstate_method(device_t dev, device_t child)
2124 struct pci_devinfo *dinfo = device_get_ivars(child);
2125 pcicfgregs *cfg = &dinfo->cfg;
2129 if (cfg->pp.pp_cap != 0) {
2130 status = PCI_READ_CONFIG(dev, child, cfg->pp.pp_status, 2);
2131 switch (status & PCIM_PSTAT_DMASK) {
2133 result = PCI_POWERSTATE_D0;
2136 result = PCI_POWERSTATE_D1;
2139 result = PCI_POWERSTATE_D2;
2142 result = PCI_POWERSTATE_D3;
2145 result = PCI_POWERSTATE_UNKNOWN;
2149 /* No support, device is always at D0 */
2150 result = PCI_POWERSTATE_D0;
2156 * Some convenience functions for PCI device drivers.
2159 static __inline void
2160 pci_set_command_bit(device_t dev, device_t child, uint16_t bit)
2164 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2166 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2169 static __inline void
2170 pci_clear_command_bit(device_t dev, device_t child, uint16_t bit)
2174 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2176 PCI_WRITE_CONFIG(dev, child, PCIR_COMMAND, command, 2);
2180 pci_enable_busmaster_method(device_t dev, device_t child)
2182 pci_set_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2187 pci_disable_busmaster_method(device_t dev, device_t child)
2189 pci_clear_command_bit(dev, child, PCIM_CMD_BUSMASTEREN);
2194 pci_enable_io_method(device_t dev, device_t child, int space)
2204 case SYS_RES_IOPORT:
2205 bit = PCIM_CMD_PORTEN;
2208 case SYS_RES_MEMORY:
2209 bit = PCIM_CMD_MEMEN;
2215 pci_set_command_bit(dev, child, bit);
2216 /* Some devices seem to need a brief stall here, what do to? */
2217 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2220 device_printf(child, "failed to enable %s mapping!\n", error);
2225 pci_disable_io_method(device_t dev, device_t child, int space)
2235 case SYS_RES_IOPORT:
2236 bit = PCIM_CMD_PORTEN;
2239 case SYS_RES_MEMORY:
2240 bit = PCIM_CMD_MEMEN;
2246 pci_clear_command_bit(dev, child, bit);
2247 command = PCI_READ_CONFIG(dev, child, PCIR_COMMAND, 2);
2248 if (command & bit) {
2249 device_printf(child, "failed to disable %s mapping!\n", error);
2256 * New style pci driver. Parent device is either a pci-host-bridge or a
2257 * pci-pci-bridge. Both kinds are represented by instances of pcib.
2261 pci_print_verbose(struct pci_devinfo *dinfo)
2265 pcicfgregs *cfg = &dinfo->cfg;
2267 kprintf("found->\tvendor=0x%04x, dev=0x%04x, revid=0x%02x\n",
2268 cfg->vendor, cfg->device, cfg->revid);
2269 kprintf("\tdomain=%d, bus=%d, slot=%d, func=%d\n",
2270 cfg->domain, cfg->bus, cfg->slot, cfg->func);
2271 kprintf("\tclass=%02x-%02x-%02x, hdrtype=0x%02x, mfdev=%d\n",
2272 cfg->baseclass, cfg->subclass, cfg->progif, cfg->hdrtype,
2274 kprintf("\tcmdreg=0x%04x, statreg=0x%04x, cachelnsz=%d (dwords)\n",
2275 cfg->cmdreg, cfg->statreg, cfg->cachelnsz);
2276 kprintf("\tlattimer=0x%02x (%d ns), mingnt=0x%02x (%d ns), maxlat=0x%02x (%d ns)\n",
2277 cfg->lattimer, cfg->lattimer * 30, cfg->mingnt,
2278 cfg->mingnt * 250, cfg->maxlat, cfg->maxlat * 250);
2279 if (cfg->intpin > 0)
2280 kprintf("\tintpin=%c, irq=%d\n",
2281 cfg->intpin +'a' -1, cfg->intline);
2282 if (cfg->pp.pp_cap) {
2285 status = pci_read_config(cfg->dev, cfg->pp.pp_status, 2);
2286 kprintf("\tpowerspec %d supports D0%s%s D3 current D%d\n",
2287 cfg->pp.pp_cap & PCIM_PCAP_SPEC,
2288 cfg->pp.pp_cap & PCIM_PCAP_D1SUPP ? " D1" : "",
2289 cfg->pp.pp_cap & PCIM_PCAP_D2SUPP ? " D2" : "",
2290 status & PCIM_PSTAT_DMASK);
2292 if (cfg->msi.msi_location) {
2295 ctrl = cfg->msi.msi_ctrl;
2296 kprintf("\tMSI supports %d message%s%s%s\n",
2297 cfg->msi.msi_msgnum,
2298 (cfg->msi.msi_msgnum == 1) ? "" : "s",
2299 (ctrl & PCIM_MSICTRL_64BIT) ? ", 64 bit" : "",
2300 (ctrl & PCIM_MSICTRL_VECTOR) ? ", vector masks":"");
2302 if (cfg->msix.msix_location) {
2303 kprintf("\tMSI-X supports %d message%s ",
2304 cfg->msix.msix_msgnum,
2305 (cfg->msix.msix_msgnum == 1) ? "" : "s");
2306 if (cfg->msix.msix_table_bar == cfg->msix.msix_pba_bar)
2307 kprintf("in map 0x%x\n",
2308 cfg->msix.msix_table_bar);
2310 kprintf("in maps 0x%x and 0x%x\n",
2311 cfg->msix.msix_table_bar,
2312 cfg->msix.msix_pba_bar);
2318 pci_porten(device_t pcib, int b, int s, int f)
2320 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
2321 & PCIM_CMD_PORTEN) != 0;
2325 pci_memen(device_t pcib, int b, int s, int f)
2327 return (PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2)
2328 & PCIM_CMD_MEMEN) != 0;
2332 * Add a resource based on a pci map register. Return 1 if the map
2333 * register is a 32bit map register or 2 if it is a 64bit register.
2336 pci_add_map(device_t pcib, device_t bus, device_t dev,
2337 int b, int s, int f, int reg, struct resource_list *rl, int force,
2342 pci_addr_t start, end, count;
2349 struct resource *res;
2351 map = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
2352 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, 0xffffffff, 4);
2353 testval = PCIB_READ_CONFIG(pcib, b, s, f, reg, 4);
2354 PCIB_WRITE_CONFIG(pcib, b, s, f, reg, map, 4);
2356 if (PCI_BAR_MEM(map)) {
2357 type = SYS_RES_MEMORY;
2358 if (map & PCIM_BAR_MEM_PREFETCH)
2361 type = SYS_RES_IOPORT;
2362 ln2size = pci_mapsize(testval);
2363 ln2range = pci_maprange(testval);
2364 base = pci_mapbase(map);
2365 barlen = ln2range == 64 ? 2 : 1;
2368 * For I/O registers, if bottom bit is set, and the next bit up
2369 * isn't clear, we know we have a BAR that doesn't conform to the
2370 * spec, so ignore it. Also, sanity check the size of the data
2371 * areas to the type of memory involved. Memory must be at least
2372 * 16 bytes in size, while I/O ranges must be at least 4.
2374 if (PCI_BAR_IO(testval) && (testval & PCIM_BAR_IO_RESERVED) != 0)
2376 if ((type == SYS_RES_MEMORY && ln2size < 4) ||
2377 (type == SYS_RES_IOPORT && ln2size < 2))
2381 /* Read the other half of a 64bit map register */
2382 base |= (uint64_t) PCIB_READ_CONFIG(pcib, b, s, f, reg + 4, 4) << 32;
2384 kprintf("\tmap[%02x]: type %s, range %2d, base %#jx, size %2d",
2385 reg, pci_maptype(map), ln2range, (uintmax_t)base, ln2size);
2386 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
2387 kprintf(", port disabled\n");
2388 else if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
2389 kprintf(", memory disabled\n");
2391 kprintf(", enabled\n");
2395 * If base is 0, then we have problems. It is best to ignore
2396 * such entries for the moment. These will be allocated later if
2397 * the driver specifically requests them. However, some
2398 * removable busses look better when all resources are allocated,
2399 * so allow '0' to be overriden.
2401 * Similarly treat maps whose values is the same as the test value
2402 * read back. These maps have had all f's written to them by the
2403 * BIOS in an attempt to disable the resources.
2405 if (!force && (base == 0 || map == testval))
2407 if ((u_long)base != base) {
2409 "pci%d:%d:%d:%d bar %#x too many address bits",
2410 pci_get_domain(dev), b, s, f, reg);
2415 * This code theoretically does the right thing, but has
2416 * undesirable side effects in some cases where peripherals
2417 * respond oddly to having these bits enabled. Let the user
2418 * be able to turn them off (since pci_enable_io_modes is 1 by
2421 if (pci_enable_io_modes) {
2422 /* Turn on resources that have been left off by a lazy BIOS */
2423 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f)) {
2424 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
2425 cmd |= PCIM_CMD_PORTEN;
2426 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
2428 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f)) {
2429 cmd = PCIB_READ_CONFIG(pcib, b, s, f, PCIR_COMMAND, 2);
2430 cmd |= PCIM_CMD_MEMEN;
2431 PCIB_WRITE_CONFIG(pcib, b, s, f, PCIR_COMMAND, cmd, 2);
2434 if (type == SYS_RES_IOPORT && !pci_porten(pcib, b, s, f))
2436 if (type == SYS_RES_MEMORY && !pci_memen(pcib, b, s, f))
2440 count = 1 << ln2size;
2441 if (base == 0 || base == pci_mapbase(testval)) {
2442 start = 0; /* Let the parent decide. */
2446 end = base + (1 << ln2size) - 1;
2448 resource_list_add(rl, type, reg, start, end, count);
2451 * Try to allocate the resource for this BAR from our parent
2452 * so that this resource range is already reserved. The
2453 * driver for this device will later inherit this resource in
2454 * pci_alloc_resource().
2456 res = resource_list_alloc(rl, bus, dev, type, ®, start, end, count,
2457 prefetch ? RF_PREFETCHABLE : 0);
2460 * If the allocation fails, clear the BAR and delete
2461 * the resource list entry to force
2462 * pci_alloc_resource() to allocate resources from the
2465 resource_list_delete(rl, type, reg);
2468 start = rman_get_start(res);
2469 pci_write_config(dev, reg, start, 4);
2471 pci_write_config(dev, reg + 4, start >> 32, 4);
2476 * For ATA devices we need to decide early what addressing mode to use.
2477 * Legacy demands that the primary and secondary ATA ports sits on the
2478 * same addresses that old ISA hardware did. This dictates that we use
2479 * those addresses and ignore the BAR's if we cannot set PCI native
2483 pci_ata_maps(device_t pcib, device_t bus, device_t dev, int b,
2484 int s, int f, struct resource_list *rl, int force, uint32_t prefetchmask)
2486 int rid, type, progif;
2488 /* if this device supports PCI native addressing use it */
2489 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2490 if ((progif & 0x8a) == 0x8a) {
2491 if (pci_mapbase(pci_read_config(dev, PCIR_BAR(0), 4)) &&
2492 pci_mapbase(pci_read_config(dev, PCIR_BAR(2), 4))) {
2493 kprintf("Trying ATA native PCI addressing mode\n");
2494 pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);
2498 progif = pci_read_config(dev, PCIR_PROGIF, 1);
2499 type = SYS_RES_IOPORT;
2500 if (progif & PCIP_STORAGE_IDE_MODEPRIM) {
2501 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(0), rl, force,
2502 prefetchmask & (1 << 0));
2503 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(1), rl, force,
2504 prefetchmask & (1 << 1));
2507 resource_list_add(rl, type, rid, 0x1f0, 0x1f7, 8);
2508 resource_list_alloc(rl, bus, dev, type, &rid, 0x1f0, 0x1f7, 8,
2511 resource_list_add(rl, type, rid, 0x3f6, 0x3f6, 1);
2512 resource_list_alloc(rl, bus, dev, type, &rid, 0x3f6, 0x3f6, 1,
2515 if (progif & PCIP_STORAGE_IDE_MODESEC) {
2516 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(2), rl, force,
2517 prefetchmask & (1 << 2));
2518 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(3), rl, force,
2519 prefetchmask & (1 << 3));
2522 resource_list_add(rl, type, rid, 0x170, 0x177, 8);
2523 resource_list_alloc(rl, bus, dev, type, &rid, 0x170, 0x177, 8,
2526 resource_list_add(rl, type, rid, 0x376, 0x376, 1);
2527 resource_list_alloc(rl, bus, dev, type, &rid, 0x376, 0x376, 1,
2530 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(4), rl, force,
2531 prefetchmask & (1 << 4));
2532 pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(5), rl, force,
2533 prefetchmask & (1 << 5));
2537 pci_assign_interrupt(device_t bus, device_t dev, int force_route)
2539 struct pci_devinfo *dinfo = device_get_ivars(dev);
2540 pcicfgregs *cfg = &dinfo->cfg;
2541 char tunable_name[64];
2544 /* Has to have an intpin to have an interrupt. */
2545 if (cfg->intpin == 0)
2548 /* Let the user override the IRQ with a tunable. */
2549 irq = PCI_INVALID_IRQ;
2550 ksnprintf(tunable_name, sizeof(tunable_name),
2551 "hw.pci%d.%d.%d.INT%c.irq",
2552 cfg->domain, cfg->bus, cfg->slot, cfg->intpin + 'A' - 1);
2553 if (TUNABLE_INT_FETCH(tunable_name, &irq) && (irq >= 255 || irq <= 0))
2554 irq = PCI_INVALID_IRQ;
2557 * If we didn't get an IRQ via the tunable, then we either use the
2558 * IRQ value in the intline register or we ask the bus to route an
2559 * interrupt for us. If force_route is true, then we only use the
2560 * value in the intline register if the bus was unable to assign an
2563 if (!PCI_INTERRUPT_VALID(irq)) {
2564 if (!PCI_INTERRUPT_VALID(cfg->intline) || force_route)
2565 irq = PCI_ASSIGN_INTERRUPT(bus, dev);
2566 if (!PCI_INTERRUPT_VALID(irq))
2570 /* If after all that we don't have an IRQ, just bail. */
2571 if (!PCI_INTERRUPT_VALID(irq))
2574 /* Update the config register if it changed. */
2575 if (irq != cfg->intline) {
2577 pci_write_config(dev, PCIR_INTLINE, irq, 1);
2580 /* Add this IRQ as rid 0 interrupt resource. */
2581 resource_list_add(&dinfo->resources, SYS_RES_IRQ, 0, irq, irq, 1);
2585 pci_add_resources(device_t pcib, device_t bus, device_t dev, int force, uint32_t prefetchmask)
2587 struct pci_devinfo *dinfo = device_get_ivars(dev);
2588 pcicfgregs *cfg = &dinfo->cfg;
2589 struct resource_list *rl = &dinfo->resources;
2590 struct pci_quirk *q;
2597 /* ATA devices needs special map treatment */
2598 if ((pci_get_class(dev) == PCIC_STORAGE) &&
2599 (pci_get_subclass(dev) == PCIS_STORAGE_IDE) &&
2600 ((pci_get_progif(dev) & PCIP_STORAGE_IDE_MASTERDEV) ||
2601 (!pci_read_config(dev, PCIR_BAR(0), 4) &&
2602 !pci_read_config(dev, PCIR_BAR(2), 4))) )
2603 pci_ata_maps(pcib, bus, dev, b, s, f, rl, force, prefetchmask);
2605 for (i = 0; i < cfg->nummaps;)
2606 i += pci_add_map(pcib, bus, dev, b, s, f, PCIR_BAR(i),
2607 rl, force, prefetchmask & (1 << i));
2610 * Add additional, quirked resources.
2612 for (q = &pci_quirks[0]; q->devid; q++) {
2613 if (q->devid == ((cfg->device << 16) | cfg->vendor)
2614 && q->type == PCI_QUIRK_MAP_REG)
2615 pci_add_map(pcib, bus, dev, b, s, f, q->arg1, rl,
2619 if (cfg->intpin > 0 && PCI_INTERRUPT_VALID(cfg->intline)) {
2620 #ifdef __PCI_REROUTE_INTERRUPT
2622 * Try to re-route interrupts. Sometimes the BIOS or
2623 * firmware may leave bogus values in these registers.
2624 * If the re-route fails, then just stick with what we
2627 pci_assign_interrupt(bus, dev, 1);
2629 pci_assign_interrupt(bus, dev, 0);
2635 pci_add_children(device_t dev, int domain, int busno, size_t dinfo_size)
2637 #define REG(n, w) PCIB_READ_CONFIG(pcib, busno, s, f, n, w)
2638 device_t pcib = device_get_parent(dev);
2639 struct pci_devinfo *dinfo;
2641 int s, f, pcifunchigh;
2644 KASSERT(dinfo_size >= sizeof(struct pci_devinfo),
2645 ("dinfo_size too small"));
2646 maxslots = PCIB_MAXSLOTS(pcib);
2647 for (s = 0; s <= maxslots; s++) {
2651 hdrtype = REG(PCIR_HDRTYPE, 1);
2652 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
2654 if (hdrtype & PCIM_MFDEV)
2655 pcifunchigh = PCI_FUNCMAX;
2656 for (f = 0; f <= pcifunchigh; f++) {
2657 dinfo = pci_read_device(pcib, domain, busno, s, f,
2659 if (dinfo != NULL) {
2660 pci_add_child(dev, dinfo);
2668 pci_add_child(device_t bus, struct pci_devinfo *dinfo)
2672 pcib = device_get_parent(bus);
2673 dinfo->cfg.dev = device_add_child(bus, NULL, -1);
2674 device_set_ivars(dinfo->cfg.dev, dinfo);
2675 resource_list_init(&dinfo->resources);
2676 pci_cfg_save(dinfo->cfg.dev, dinfo, 0);
2677 pci_cfg_restore(dinfo->cfg.dev, dinfo);
2678 pci_print_verbose(dinfo);
2679 pci_add_resources(pcib, bus, dinfo->cfg.dev, 0, 0);
2683 pci_probe(device_t dev)
2685 device_set_desc(dev, "PCI bus");
2687 /* Allow other subclasses to override this driver. */
2692 pci_attach(device_t dev)
2697 * Since there can be multiple independantly numbered PCI
2698 * busses on systems with multiple PCI domains, we can't use
2699 * the unit number to decide which bus we are probing. We ask
2700 * the parent pcib what our domain and bus numbers are.
2702 domain = pcib_get_domain(dev);
2703 busno = pcib_get_bus(dev);
2705 device_printf(dev, "domain=%d, physical bus=%d\n",
2708 pci_add_children(dev, domain, busno, sizeof(struct pci_devinfo));
2710 return (bus_generic_attach(dev));
2714 pci_suspend(device_t dev)
2716 int dstate, error, i, numdevs;
2717 device_t acpi_dev, child, *devlist;
2718 struct pci_devinfo *dinfo;
2721 * Save the PCI configuration space for each child and set the
2722 * device in the appropriate power state for this sleep state.
2725 if (pci_do_power_resume)
2726 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
2727 device_get_children(dev, &devlist, &numdevs);
2728 for (i = 0; i < numdevs; i++) {
2730 dinfo = (struct pci_devinfo *) device_get_ivars(child);
2731 pci_cfg_save(child, dinfo, 0);
2734 /* Suspend devices before potentially powering them down. */
2735 error = bus_generic_suspend(dev);
2737 kfree(devlist, M_TEMP);
2742 * Always set the device to D3. If ACPI suggests a different
2743 * power state, use it instead. If ACPI is not present, the
2744 * firmware is responsible for managing device power. Skip
2745 * children who aren't attached since they are powered down
2746 * separately. Only manage type 0 devices for now.
2748 for (i = 0; acpi_dev && i < numdevs; i++) {
2750 dinfo = (struct pci_devinfo *) device_get_ivars(child);
2751 if (device_is_attached(child) && dinfo->cfg.hdrtype == 0) {
2752 dstate = PCI_POWERSTATE_D3;
2753 ACPI_PWR_FOR_SLEEP(acpi_dev, child, &dstate);
2754 pci_set_powerstate(child, dstate);
2757 kfree(devlist, M_TEMP);
2762 pci_resume(device_t dev)
2765 device_t acpi_dev, child, *devlist;
2766 struct pci_devinfo *dinfo;
2769 * Set each child to D0 and restore its PCI configuration space.
2772 if (pci_do_power_resume)
2773 acpi_dev = devclass_get_device(devclass_find("acpi"), 0);
2774 device_get_children(dev, &devlist, &numdevs);
2775 for (i = 0; i < numdevs; i++) {
2777 * Notify ACPI we're going to D0 but ignore the result. If
2778 * ACPI is not present, the firmware is responsible for
2779 * managing device power. Only manage type 0 devices for now.
2782 dinfo = (struct pci_devinfo *) device_get_ivars(child);
2783 if (acpi_dev && device_is_attached(child) &&
2784 dinfo->cfg.hdrtype == 0) {
2785 ACPI_PWR_FOR_SLEEP(acpi_dev, child, NULL);
2786 pci_set_powerstate(child, PCI_POWERSTATE_D0);
2789 /* Now the device is powered up, restore its config space. */
2790 pci_cfg_restore(child, dinfo);
2792 kfree(devlist, M_TEMP);
2793 return (bus_generic_resume(dev));
2797 pci_load_vendor_data(void)
2799 caddr_t vendordata, info;
2801 if ((vendordata = preload_search_by_type("pci_vendor_data")) != NULL) {
2802 info = preload_search_info(vendordata, MODINFO_ADDR);
2803 pci_vendordata = *(char **)info;
2804 info = preload_search_info(vendordata, MODINFO_SIZE);
2805 pci_vendordata_size = *(size_t *)info;
2806 /* terminate the database */
2807 pci_vendordata[pci_vendordata_size] = '\n';
2812 pci_driver_added(device_t dev, driver_t *driver)
2817 struct pci_devinfo *dinfo;
2821 device_printf(dev, "driver added\n");
2822 DEVICE_IDENTIFY(driver, dev);
2823 device_get_children(dev, &devlist, &numdevs);
2824 for (i = 0; i < numdevs; i++) {
2826 if (device_get_state(child) != DS_NOTPRESENT)
2828 dinfo = device_get_ivars(child);
2829 pci_print_verbose(dinfo);
2831 kprintf("pci%d:%d:%d:%d: reprobing on driver added\n",
2832 dinfo->cfg.domain, dinfo->cfg.bus, dinfo->cfg.slot,
2834 pci_cfg_restore(child, dinfo);
2835 if (device_probe_and_attach(child) != 0)
2836 pci_cfg_save(child, dinfo, 1);
2838 kfree(devlist, M_TEMP);
2842 pci_setup_intr(device_t dev, device_t child, struct resource *irq, int flags,
2843 driver_intr_t *intr, void *arg, void **cookiep, lwkt_serialize_t serializer)
2846 struct pci_devinfo *dinfo;
2847 struct msix_table_entry *mte;
2848 struct msix_vector *mv;
2854 error = bus_generic_setup_intr(dev, child, irq, flags, intr,
2855 arg, &cookie, serializer);
2859 /* If this is not a direct child, just bail out. */
2860 if (device_get_parent(child) != dev) {
2865 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
2867 rid = rman_get_rid(irq);
2869 /* Make sure that INTx is enabled */
2870 pci_clear_command_bit(dev, child, PCIM_CMD_INTxDIS);
2873 * Check to see if the interrupt is MSI or MSI-X.
2874 * Ask our parent to map the MSI and give
2875 * us the address and data register values.
2876 * If we fail for some reason, teardown the
2877 * interrupt handler.
2879 dinfo = device_get_ivars(child);
2880 if (dinfo->cfg.msi.msi_alloc > 0) {
2881 if (dinfo->cfg.msi.msi_addr == 0) {
2882 KASSERT(dinfo->cfg.msi.msi_handlers == 0,
2883 ("MSI has handlers, but vectors not mapped"));
2884 error = PCIB_MAP_MSI(device_get_parent(dev),
2885 child, rman_get_start(irq), &addr, &data);
2888 dinfo->cfg.msi.msi_addr = addr;
2889 dinfo->cfg.msi.msi_data = data;
2890 pci_enable_msi(child, addr, data);
2892 dinfo->cfg.msi.msi_handlers++;
2894 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
2895 ("No MSI or MSI-X interrupts allocated"));
2896 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
2897 ("MSI-X index too high"));
2898 mte = &dinfo->cfg.msix.msix_table[rid - 1];
2899 KASSERT(mte->mte_vector != 0, ("no message vector"));
2900 mv = &dinfo->cfg.msix.msix_vectors[mte->mte_vector - 1];
2901 KASSERT(mv->mv_irq == rman_get_start(irq),
2903 if (mv->mv_address == 0) {
2904 KASSERT(mte->mte_handlers == 0,
2905 ("MSI-X table entry has handlers, but vector not mapped"));
2906 error = PCIB_MAP_MSI(device_get_parent(dev),
2907 child, rman_get_start(irq), &addr, &data);
2910 mv->mv_address = addr;
2913 if (mte->mte_handlers == 0) {
2914 pci_enable_msix(child, rid - 1, mv->mv_address,
2916 pci_unmask_msix(child, rid - 1);
2918 mte->mte_handlers++;
2921 /* Make sure that INTx is disabled if we are using MSI/MSIX */
2922 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
2925 (void)bus_generic_teardown_intr(dev, child, irq,
2936 pci_teardown_intr(device_t dev, device_t child, struct resource *irq,
2940 struct msix_table_entry *mte;
2941 struct resource_list_entry *rle;
2942 struct pci_devinfo *dinfo;
2946 if (irq == NULL || !(rman_get_flags(irq) & RF_ACTIVE))
2949 /* If this isn't a direct child, just bail out */
2950 if (device_get_parent(child) != dev)
2951 return(bus_generic_teardown_intr(dev, child, irq, cookie));
2953 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
2955 rid = rman_get_rid(irq);
2958 pci_set_command_bit(dev, child, PCIM_CMD_INTxDIS);
2961 * Check to see if the interrupt is MSI or MSI-X. If so,
2962 * decrement the appropriate handlers count and mask the
2963 * MSI-X message, or disable MSI messages if the count
2966 dinfo = device_get_ivars(child);
2967 rle = resource_list_find(&dinfo->resources, SYS_RES_IRQ, rid);
2968 if (rle->res != irq)
2970 if (dinfo->cfg.msi.msi_alloc > 0) {
2971 KASSERT(rid <= dinfo->cfg.msi.msi_alloc,
2972 ("MSI-X index too high"));
2973 if (dinfo->cfg.msi.msi_handlers == 0)
2975 dinfo->cfg.msi.msi_handlers--;
2976 if (dinfo->cfg.msi.msi_handlers == 0)
2977 pci_disable_msi(child);
2979 KASSERT(dinfo->cfg.msix.msix_alloc > 0,
2980 ("No MSI or MSI-X interrupts allocated"));
2981 KASSERT(rid <= dinfo->cfg.msix.msix_table_len,
2982 ("MSI-X index too high"));
2983 mte = &dinfo->cfg.msix.msix_table[rid - 1];
2984 if (mte->mte_handlers == 0)
2986 mte->mte_handlers--;
2987 if (mte->mte_handlers == 0)
2988 pci_mask_msix(child, rid - 1);
2991 error = bus_generic_teardown_intr(dev, child, irq, cookie);
2994 ("%s: generic teardown failed for MSI/MSI-X", __func__));
2996 error = bus_generic_teardown_intr(dev, child, irq, cookie);
3001 pci_print_child(device_t dev, device_t child)
3003 struct pci_devinfo *dinfo;
3004 struct resource_list *rl;
3007 dinfo = device_get_ivars(child);
3008 rl = &dinfo->resources;
3010 retval += bus_print_child_header(dev, child);
3012 retval += resource_list_print_type(rl, "port", SYS_RES_IOPORT, "%#lx");
3013 retval += resource_list_print_type(rl, "mem", SYS_RES_MEMORY, "%#lx");
3014 retval += resource_list_print_type(rl, "irq", SYS_RES_IRQ, "%ld");
3015 if (device_get_flags(dev))
3016 retval += kprintf(" flags %#x", device_get_flags(dev));
3018 retval += kprintf(" at device %d.%d", pci_get_slot(child),
3019 pci_get_function(child));
3021 retval += bus_print_child_footer(dev, child);
3031 } pci_nomatch_tab[] = {
3032 {PCIC_OLD, -1, "old"},
3033 {PCIC_OLD, PCIS_OLD_NONVGA, "non-VGA display device"},
3034 {PCIC_OLD, PCIS_OLD_VGA, "VGA-compatible display device"},
3035 {PCIC_STORAGE, -1, "mass storage"},
3036 {PCIC_STORAGE, PCIS_STORAGE_SCSI, "SCSI"},
3037 {PCIC_STORAGE, PCIS_STORAGE_IDE, "ATA"},
3038 {PCIC_STORAGE, PCIS_STORAGE_FLOPPY, "floppy disk"},
3039 {PCIC_STORAGE, PCIS_STORAGE_IPI, "IPI"},
3040 {PCIC_STORAGE, PCIS_STORAGE_RAID, "RAID"},
3041 {PCIC_STORAGE, PCIS_STORAGE_ATA_ADMA, "ATA (ADMA)"},
3042 {PCIC_STORAGE, PCIS_STORAGE_SATA, "SATA"},
3043 {PCIC_STORAGE, PCIS_STORAGE_SAS, "SAS"},
3044 {PCIC_NETWORK, -1, "network"},
3045 {PCIC_NETWORK, PCIS_NETWORK_ETHERNET, "ethernet"},
3046 {PCIC_NETWORK, PCIS_NETWORK_TOKENRING, "token ring"},
3047 {PCIC_NETWORK, PCIS_NETWORK_FDDI, "fddi"},
3048 {PCIC_NETWORK, PCIS_NETWORK_ATM, "ATM"},
3049 {PCIC_NETWORK, PCIS_NETWORK_ISDN, "ISDN"},
3050 {PCIC_DISPLAY, -1, "display"},
3051 {PCIC_DISPLAY, PCIS_DISPLAY_VGA, "VGA"},
3052 {PCIC_DISPLAY, PCIS_DISPLAY_XGA, "XGA"},
3053 {PCIC_DISPLAY, PCIS_DISPLAY_3D, "3D"},
3054 {PCIC_MULTIMEDIA, -1, "multimedia"},
3055 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_VIDEO, "video"},
3056 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_AUDIO, "audio"},
3057 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_TELE, "telephony"},
3058 {PCIC_MULTIMEDIA, PCIS_MULTIMEDIA_HDA, "HDA"},
3059 {PCIC_MEMORY, -1, "memory"},
3060 {PCIC_MEMORY, PCIS_MEMORY_RAM, "RAM"},
3061 {PCIC_MEMORY, PCIS_MEMORY_FLASH, "flash"},
3062 {PCIC_BRIDGE, -1, "bridge"},
3063 {PCIC_BRIDGE, PCIS_BRIDGE_HOST, "HOST-PCI"},
3064 {PCIC_BRIDGE, PCIS_BRIDGE_ISA, "PCI-ISA"},
3065 {PCIC_BRIDGE, PCIS_BRIDGE_EISA, "PCI-EISA"},
3066 {PCIC_BRIDGE, PCIS_BRIDGE_MCA, "PCI-MCA"},
3067 {PCIC_BRIDGE, PCIS_BRIDGE_PCI, "PCI-PCI"},
3068 {PCIC_BRIDGE, PCIS_BRIDGE_PCMCIA, "PCI-PCMCIA"},
3069 {PCIC_BRIDGE, PCIS_BRIDGE_NUBUS, "PCI-NuBus"},
3070 {PCIC_BRIDGE, PCIS_BRIDGE_CARDBUS, "PCI-CardBus"},
3071 {PCIC_BRIDGE, PCIS_BRIDGE_RACEWAY, "PCI-RACEway"},
3072 {PCIC_SIMPLECOMM, -1, "simple comms"},
3073 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_UART, "UART"}, /* could detect 16550 */
3074 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_PAR, "parallel port"},
3075 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MULSER, "multiport serial"},
3076 {PCIC_SIMPLECOMM, PCIS_SIMPLECOMM_MODEM, "generic modem"},
3077 {PCIC_BASEPERIPH, -1, "base peripheral"},
3078 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PIC, "interrupt controller"},
3079 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_DMA, "DMA controller"},
3080 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_TIMER, "timer"},
3081 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_RTC, "realtime clock"},
3082 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_PCIHOT, "PCI hot-plug controller"},
3083 {PCIC_BASEPERIPH, PCIS_BASEPERIPH_SDHC, "SD host controller"},
3084 {PCIC_INPUTDEV, -1, "input device"},
3085 {PCIC_INPUTDEV, PCIS_INPUTDEV_KEYBOARD, "keyboard"},
3086 {PCIC_INPUTDEV, PCIS_INPUTDEV_DIGITIZER,"digitizer"},
3087 {PCIC_INPUTDEV, PCIS_INPUTDEV_MOUSE, "mouse"},
3088 {PCIC_INPUTDEV, PCIS_INPUTDEV_SCANNER, "scanner"},
3089 {PCIC_INPUTDEV, PCIS_INPUTDEV_GAMEPORT, "gameport"},
3090 {PCIC_DOCKING, -1, "docking station"},
3091 {PCIC_PROCESSOR, -1, "processor"},
3092 {PCIC_SERIALBUS, -1, "serial bus"},
3093 {PCIC_SERIALBUS, PCIS_SERIALBUS_FW, "FireWire"},
3094 {PCIC_SERIALBUS, PCIS_SERIALBUS_ACCESS, "AccessBus"},
3095 {PCIC_SERIALBUS, PCIS_SERIALBUS_SSA, "SSA"},
3096 {PCIC_SERIALBUS, PCIS_SERIALBUS_USB, "USB"},
3097 {PCIC_SERIALBUS, PCIS_SERIALBUS_FC, "Fibre Channel"},
3098 {PCIC_SERIALBUS, PCIS_SERIALBUS_SMBUS, "SMBus"},
3099 {PCIC_WIRELESS, -1, "wireless controller"},
3100 {PCIC_WIRELESS, PCIS_WIRELESS_IRDA, "iRDA"},
3101 {PCIC_WIRELESS, PCIS_WIRELESS_IR, "IR"},
3102 {PCIC_WIRELESS, PCIS_WIRELESS_RF, "RF"},
3103 {PCIC_INTELLIIO, -1, "intelligent I/O controller"},
3104 {PCIC_INTELLIIO, PCIS_INTELLIIO_I2O, "I2O"},
3105 {PCIC_SATCOM, -1, "satellite communication"},
3106 {PCIC_SATCOM, PCIS_SATCOM_TV, "sat TV"},
3107 {PCIC_SATCOM, PCIS_SATCOM_AUDIO, "sat audio"},
3108 {PCIC_SATCOM, PCIS_SATCOM_VOICE, "sat voice"},
3109 {PCIC_SATCOM, PCIS_SATCOM_DATA, "sat data"},
3110 {PCIC_CRYPTO, -1, "encrypt/decrypt"},
3111 {PCIC_CRYPTO, PCIS_CRYPTO_NETCOMP, "network/computer crypto"},
3112 {PCIC_CRYPTO, PCIS_CRYPTO_ENTERTAIN, "entertainment crypto"},
3113 {PCIC_DASP, -1, "dasp"},
3114 {PCIC_DASP, PCIS_DASP_DPIO, "DPIO module"},
3119 pci_probe_nomatch(device_t dev, device_t child)
3122 char *cp, *scp, *device;
3125 * Look for a listing for this device in a loaded device database.
3127 if ((device = pci_describe_device(child)) != NULL) {
3128 device_printf(dev, "<%s>", device);
3129 kfree(device, M_DEVBUF);
3132 * Scan the class/subclass descriptions for a general
3137 for (i = 0; pci_nomatch_tab[i].desc != NULL; i++) {
3138 if (pci_nomatch_tab[i].class == pci_get_class(child)) {
3139 if (pci_nomatch_tab[i].subclass == -1) {
3140 cp = pci_nomatch_tab[i].desc;
3141 } else if (pci_nomatch_tab[i].subclass ==
3142 pci_get_subclass(child)) {
3143 scp = pci_nomatch_tab[i].desc;
3147 device_printf(dev, "<%s%s%s>",
3149 ((cp != NULL) && (scp != NULL)) ? ", " : "",
3152 kprintf(" at device %d.%d (no driver attached)\n",
3153 pci_get_slot(child), pci_get_function(child));
3154 pci_cfg_save(child, (struct pci_devinfo *)device_get_ivars(child), 1);
3159 * Parse the PCI device database, if loaded, and return a pointer to a
3160 * description of the device.
3162 * The database is flat text formatted as follows:
3164 * Any line not in a valid format is ignored.
3165 * Lines are terminated with newline '\n' characters.
3167 * A VENDOR line consists of the 4 digit (hex) vendor code, a TAB, then
3170 * A DEVICE line is entered immediately below the corresponding VENDOR ID.
3171 * - devices cannot be listed without a corresponding VENDOR line.
3172 * A DEVICE line consists of a TAB, the 4 digit (hex) device code,
3173 * another TAB, then the device name.
3177 * Assuming (ptr) points to the beginning of a line in the database,
3178 * return the vendor or device and description of the next entry.
3179 * The value of (vendor) or (device) inappropriate for the entry type
3180 * is set to -1. Returns nonzero at the end of the database.
3182 * Note that this is slightly unrobust in the face of corrupt data;
3183 * we attempt to safeguard against this by spamming the end of the
3184 * database with a newline when we initialise.
3187 pci_describe_parse_line(char **ptr, int *vendor, int *device, char **desc)
3196 left = pci_vendordata_size - (cp - pci_vendordata);
3204 ksscanf(cp, "%x\t%80[^\n]", vendor, *desc) == 2)
3208 ksscanf(cp, "%x\t%80[^\n]", device, *desc) == 2)
3211 /* skip to next line */
3212 while (*cp != '\n' && left > 0) {
3221 /* skip to next line */
3222 while (*cp != '\n' && left > 0) {
3226 if (*cp == '\n' && left > 0)
3233 pci_describe_device(device_t dev)
3236 char *desc, *vp, *dp, *line;
3238 desc = vp = dp = NULL;
3241 * If we have no vendor data, we can't do anything.
3243 if (pci_vendordata == NULL)
3247 * Scan the vendor data looking for this device
3249 line = pci_vendordata;
3250 if ((vp = kmalloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3253 if (pci_describe_parse_line(&line, &vendor, &device, &vp))
3255 if (vendor == pci_get_vendor(dev))
3258 if ((dp = kmalloc(80, M_DEVBUF, M_NOWAIT)) == NULL)
3261 if (pci_describe_parse_line(&line, &vendor, &device, &dp)) {
3269 if (device == pci_get_device(dev))
3273 ksnprintf(dp, 80, "0x%x", pci_get_device(dev));
3274 if ((desc = kmalloc(strlen(vp) + strlen(dp) + 3, M_DEVBUF, M_NOWAIT)) !=
3276 ksprintf(desc, "%s, %s", vp, dp);
3279 kfree(vp, M_DEVBUF);
3281 kfree(dp, M_DEVBUF);
3286 pci_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
3288 struct pci_devinfo *dinfo;
3291 dinfo = device_get_ivars(child);
3295 case PCI_IVAR_ETHADDR:
3297 * The generic accessor doesn't deal with failure, so
3298 * we set the return value, then return an error.
3300 *((uint8_t **) result) = NULL;
3302 case PCI_IVAR_SUBVENDOR:
3303 *result = cfg->subvendor;
3305 case PCI_IVAR_SUBDEVICE:
3306 *result = cfg->subdevice;
3308 case PCI_IVAR_VENDOR:
3309 *result = cfg->vendor;
3311 case PCI_IVAR_DEVICE:
3312 *result = cfg->device;
3314 case PCI_IVAR_DEVID:
3315 *result = (cfg->device << 16) | cfg->vendor;
3317 case PCI_IVAR_CLASS:
3318 *result = cfg->baseclass;
3320 case PCI_IVAR_SUBCLASS:
3321 *result = cfg->subclass;
3323 case PCI_IVAR_PROGIF:
3324 *result = cfg->progif;
3326 case PCI_IVAR_REVID:
3327 *result = cfg->revid;
3329 case PCI_IVAR_INTPIN:
3330 *result = cfg->intpin;
3333 *result = cfg->intline;
3335 case PCI_IVAR_DOMAIN:
3336 *result = cfg->domain;
3342 *result = cfg->slot;
3344 case PCI_IVAR_FUNCTION:
3345 *result = cfg->func;
3347 case PCI_IVAR_CMDREG:
3348 *result = cfg->cmdreg;
3350 case PCI_IVAR_CACHELNSZ:
3351 *result = cfg->cachelnsz;
3353 case PCI_IVAR_MINGNT:
3354 *result = cfg->mingnt;
3356 case PCI_IVAR_MAXLAT:
3357 *result = cfg->maxlat;
3359 case PCI_IVAR_LATTIMER:
3360 *result = cfg->lattimer;
3369 pci_write_ivar(device_t dev, device_t child, int which, uintptr_t value)
3371 struct pci_devinfo *dinfo;
3373 dinfo = device_get_ivars(child);
3376 case PCI_IVAR_INTPIN:
3377 dinfo->cfg.intpin = value;
3379 case PCI_IVAR_ETHADDR:
3380 case PCI_IVAR_SUBVENDOR:
3381 case PCI_IVAR_SUBDEVICE:
3382 case PCI_IVAR_VENDOR:
3383 case PCI_IVAR_DEVICE:
3384 case PCI_IVAR_DEVID:
3385 case PCI_IVAR_CLASS:
3386 case PCI_IVAR_SUBCLASS:
3387 case PCI_IVAR_PROGIF:
3388 case PCI_IVAR_REVID:
3390 case PCI_IVAR_DOMAIN:
3393 case PCI_IVAR_FUNCTION:
3394 return (EINVAL); /* disallow for now */
3401 #include "opt_ddb.h"
3403 #include <ddb/ddb.h>
3404 #include <sys/cons.h>
3407 * List resources based on pci map registers, used for within ddb
3410 DB_SHOW_COMMAND(pciregs, db_pci_dump)
3412 struct pci_devinfo *dinfo;
3413 struct devlist *devlist_head;
3416 int i, error, none_count;
3419 /* get the head of the device queue */
3420 devlist_head = &pci_devq;
3423 * Go through the list of devices and print out devices
3425 for (error = 0, i = 0,
3426 dinfo = STAILQ_FIRST(devlist_head);
3427 (dinfo != NULL) && (error == 0) && (i < pci_numdevs) && !db_pager_quit;
3428 dinfo = STAILQ_NEXT(dinfo, pci_links), i++) {
3430 /* Populate pd_name and pd_unit */
3433 name = device_get_name(dinfo->cfg.dev);
3436 db_kprintf("%s%d@pci%d:%d:%d:%d:\tclass=0x%06x card=0x%08x "
3437 "chip=0x%08x rev=0x%02x hdr=0x%02x\n",
3438 (name && *name) ? name : "none",
3439 (name && *name) ? (int)device_get_unit(dinfo->cfg.dev) :
3441 p->pc_sel.pc_domain, p->pc_sel.pc_bus, p->pc_sel.pc_dev,
3442 p->pc_sel.pc_func, (p->pc_class << 16) |
3443 (p->pc_subclass << 8) | p->pc_progif,
3444 (p->pc_subdevice << 16) | p->pc_subvendor,
3445 (p->pc_device << 16) | p->pc_vendor,
3446 p->pc_revid, p->pc_hdr);
3452 static struct resource *
3453 pci_alloc_map(device_t dev, device_t child, int type, int *rid,
3454 u_long start, u_long end, u_long count, u_int flags)
3456 struct pci_devinfo *dinfo = device_get_ivars(child);
3457 struct resource_list *rl = &dinfo->resources;
3458 struct resource_list_entry *rle;
3459 struct resource *res;
3460 pci_addr_t map, testval;
3464 * Weed out the bogons, and figure out how large the BAR/map
3465 * is. Bars that read back 0 here are bogus and unimplemented.
3466 * Note: atapci in legacy mode are special and handled elsewhere
3467 * in the code. If you have a atapci device in legacy mode and
3468 * it fails here, that other code is broken.
3471 map = pci_read_config(child, *rid, 4);
3472 pci_write_config(child, *rid, 0xffffffff, 4);
3473 testval = pci_read_config(child, *rid, 4);
3474 if (pci_maprange(testval) == 64)
3475 map |= (pci_addr_t)pci_read_config(child, *rid + 4, 4) << 32;
3476 if (pci_mapbase(testval) == 0)
3480 * Restore the original value of the BAR. We may have reprogrammed
3481 * the BAR of the low-level console device and when booting verbose,
3482 * we need the console device addressable.
3484 pci_write_config(child, *rid, map, 4);
3486 if (PCI_BAR_MEM(testval)) {
3487 if (type != SYS_RES_MEMORY) {
3490 "child %s requested type %d for rid %#x,"
3491 " but the BAR says it is an memio\n",
3492 device_get_nameunit(child), type, *rid);
3496 if (type != SYS_RES_IOPORT) {
3499 "child %s requested type %d for rid %#x,"
3500 " but the BAR says it is an ioport\n",
3501 device_get_nameunit(child), type, *rid);
3506 * For real BARs, we need to override the size that
3507 * the driver requests, because that's what the BAR
3508 * actually uses and we would otherwise have a
3509 * situation where we might allocate the excess to
3510 * another driver, which won't work.
3512 mapsize = pci_mapsize(testval);
3513 count = 1UL << mapsize;
3514 if (RF_ALIGNMENT(flags) < mapsize)
3515 flags = (flags & ~RF_ALIGNMENT_MASK) | RF_ALIGNMENT_LOG2(mapsize);
3516 if (PCI_BAR_MEM(testval) && (testval & PCIM_BAR_MEM_PREFETCH))
3517 flags |= RF_PREFETCHABLE;
3520 * Allocate enough resource, and then write back the
3521 * appropriate bar for that resource.
3523 res = BUS_ALLOC_RESOURCE(device_get_parent(dev), child, type, rid,
3524 start, end, count, flags);
3526 device_printf(child,
3527 "%#lx bytes of rid %#x res %d failed (%#lx, %#lx).\n",
3528 count, *rid, type, start, end);
3531 resource_list_add(rl, type, *rid, start, end, count);
3532 rle = resource_list_find(rl, type, *rid);
3534 panic("pci_alloc_map: unexpectedly can't find resource.");
3536 rle->start = rman_get_start(res);
3537 rle->end = rman_get_end(res);
3540 device_printf(child,
3541 "Lazy allocation of %#lx bytes rid %#x type %d at %#lx\n",
3542 count, *rid, type, rman_get_start(res));
3543 map = rman_get_start(res);
3545 pci_write_config(child, *rid, map, 4);
3546 if (pci_maprange(testval) == 64)
3547 pci_write_config(child, *rid + 4, map >> 32, 4);
3553 pci_alloc_resource(device_t dev, device_t child, int type, int *rid,
3554 u_long start, u_long end, u_long count, u_int flags)
3556 struct pci_devinfo *dinfo = device_get_ivars(child);
3557 struct resource_list *rl = &dinfo->resources;
3558 struct resource_list_entry *rle;
3559 pcicfgregs *cfg = &dinfo->cfg;
3560 //kprintf("%s on %s: requesting resource\n", device_get_desc(child), device_get_desc(dev));
3562 * Perform lazy resource allocation
3564 if (device_get_parent(child) == dev) {
3568 * Can't alloc legacy interrupt once MSI messages
3569 * have been allocated.
3572 if (*rid == 0 && (cfg->msi.msi_alloc > 0 ||
3573 cfg->msix.msix_alloc > 0))
3577 * If the child device doesn't have an
3578 * interrupt routed and is deserving of an
3579 * interrupt, try to assign it one.
3581 if (*rid == 0 && !PCI_INTERRUPT_VALID(cfg->intline) &&
3583 pci_assign_interrupt(dev, child, 0);
3585 case SYS_RES_IOPORT:
3586 case SYS_RES_MEMORY:
3587 if (*rid < PCIR_BAR(cfg->nummaps)) {
3589 * Enable the I/O mode. We should
3590 * also be assigning resources too
3591 * when none are present. The
3592 * resource_list_alloc kind of sorta does
3595 if (PCI_ENABLE_IO(dev, child, type))
3598 rle = resource_list_find(rl, type, *rid);
3600 return (pci_alloc_map(dev, child, type, rid,
3601 start, end, count, flags));
3605 * If we've already allocated the resource, then
3606 * return it now. But first we may need to activate
3607 * it, since we don't allocate the resource as active
3608 * above. Normally this would be done down in the
3609 * nexus, but since we short-circuit that path we have
3610 * to do its job here. Not sure if we should kfree the
3611 * resource if it fails to activate.
3613 rle = resource_list_find(rl, type, *rid);
3614 if (rle != NULL && rle->res != NULL) {
3616 device_printf(child,
3617 "Reserved %#lx bytes for rid %#x type %d at %#lx\n",
3618 rman_get_size(rle->res), *rid, type,
3619 rman_get_start(rle->res));
3620 if ((flags & RF_ACTIVE) &&
3621 bus_generic_activate_resource(dev, child, type,
3622 *rid, rle->res) != 0)
3627 return (resource_list_alloc(rl, dev, child, type, rid,
3628 start, end, count, flags));
3632 pci_delete_resource(device_t dev, device_t child, int type, int rid)
3634 struct pci_devinfo *dinfo;
3635 struct resource_list *rl;
3636 struct resource_list_entry *rle;
3638 if (device_get_parent(child) != dev)
3641 dinfo = device_get_ivars(child);
3642 rl = &dinfo->resources;
3643 rle = resource_list_find(rl, type, rid);
3646 if (rman_get_device(rle->res) != dev ||
3647 rman_get_flags(rle->res) & RF_ACTIVE) {
3648 device_printf(dev, "delete_resource: "
3649 "Resource still owned by child, oops. "
3650 "(type=%d, rid=%d, addr=%lx)\n",
3651 rle->type, rle->rid,
3652 rman_get_start(rle->res));
3655 bus_release_resource(dev, type, rid, rle->res);
3657 resource_list_delete(rl, type, rid);
3660 * Why do we turn off the PCI configuration BAR when we delete a
3663 pci_write_config(child, rid, 0, 4);
3664 BUS_DELETE_RESOURCE(device_get_parent(dev), child, type, rid);
3667 struct resource_list *
3668 pci_get_resource_list (device_t dev, device_t child)
3670 struct pci_devinfo *dinfo = device_get_ivars(child);
3675 return (&dinfo->resources);
3679 pci_read_config_method(device_t dev, device_t child, int reg, int width)
3681 struct pci_devinfo *dinfo = device_get_ivars(child);
3682 pcicfgregs *cfg = &dinfo->cfg;
3684 return (PCIB_READ_CONFIG(device_get_parent(dev),
3685 cfg->bus, cfg->slot, cfg->func, reg, width));
3689 pci_write_config_method(device_t dev, device_t child, int reg,
3690 uint32_t val, int width)
3692 struct pci_devinfo *dinfo = device_get_ivars(child);
3693 pcicfgregs *cfg = &dinfo->cfg;
3695 PCIB_WRITE_CONFIG(device_get_parent(dev),
3696 cfg->bus, cfg->slot, cfg->func, reg, val, width);
3700 pci_child_location_str_method(device_t dev, device_t child, char *buf,
3704 ksnprintf(buf, buflen, "slot=%d function=%d", pci_get_slot(child),
3705 pci_get_function(child));
3710 pci_child_pnpinfo_str_method(device_t dev, device_t child, char *buf,
3713 struct pci_devinfo *dinfo;
3716 dinfo = device_get_ivars(child);
3718 ksnprintf(buf, buflen, "vendor=0x%04x device=0x%04x subvendor=0x%04x "
3719 "subdevice=0x%04x class=0x%02x%02x%02x", cfg->vendor, cfg->device,
3720 cfg->subvendor, cfg->subdevice, cfg->baseclass, cfg->subclass,
3726 pci_assign_interrupt_method(device_t dev, device_t child)
3728 struct pci_devinfo *dinfo = device_get_ivars(child);
3729 pcicfgregs *cfg = &dinfo->cfg;
3731 return (PCIB_ROUTE_INTERRUPT(device_get_parent(dev), child,
3736 pci_modevent(module_t mod, int what, void *arg)
3738 static struct cdev *pci_cdev;
3739 extern struct dev_ops pcic_ops;
3743 STAILQ_INIT(&pci_devq);
3745 dev_ops_add(&pcic_ops, -1, 0);
3746 pci_cdev = make_dev(&pcic_ops, 0, UID_ROOT, GID_WHEEL, 0644,
3748 pci_load_vendor_data();
3752 destroy_dev(pci_cdev);
3760 pci_cfg_restore(device_t dev, struct pci_devinfo *dinfo)
3765 * Only do header type 0 devices. Type 1 devices are bridges,
3766 * which we know need special treatment. Type 2 devices are
3767 * cardbus bridges which also require special treatment.
3768 * Other types are unknown, and we err on the side of safety
3771 if (dinfo->cfg.hdrtype != 0)
3775 * Restore the device to full power mode. We must do this
3776 * before we restore the registers because moving from D3 to
3777 * D0 will cause the chip's BARs and some other registers to
3778 * be reset to some unknown power on reset values. Cut down
3779 * the noise on boot by doing nothing if we are already in
3782 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
3783 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
3785 for (i = 0; i < dinfo->cfg.nummaps; i++)
3786 pci_write_config(dev, PCIR_BAR(i), dinfo->cfg.bar[i], 4);
3787 pci_write_config(dev, PCIR_BIOS, dinfo->cfg.bios, 4);
3788 pci_write_config(dev, PCIR_COMMAND, dinfo->cfg.cmdreg, 2);
3789 pci_write_config(dev, PCIR_INTLINE, dinfo->cfg.intline, 1);
3790 pci_write_config(dev, PCIR_INTPIN, dinfo->cfg.intpin, 1);
3791 pci_write_config(dev, PCIR_MINGNT, dinfo->cfg.mingnt, 1);
3792 pci_write_config(dev, PCIR_MAXLAT, dinfo->cfg.maxlat, 1);
3793 pci_write_config(dev, PCIR_CACHELNSZ, dinfo->cfg.cachelnsz, 1);
3794 pci_write_config(dev, PCIR_LATTIMER, dinfo->cfg.lattimer, 1);
3795 pci_write_config(dev, PCIR_PROGIF, dinfo->cfg.progif, 1);
3796 pci_write_config(dev, PCIR_REVID, dinfo->cfg.revid, 1);
3798 /* Restore MSI and MSI-X configurations if they are present. */
3799 if (dinfo->cfg.msi.msi_location != 0)
3800 pci_resume_msi(dev);
3801 if (dinfo->cfg.msix.msix_location != 0)
3802 pci_resume_msix(dev);
3806 pci_cfg_save(device_t dev, struct pci_devinfo *dinfo, int setstate)
3813 * Only do header type 0 devices. Type 1 devices are bridges, which
3814 * we know need special treatment. Type 2 devices are cardbus bridges
3815 * which also require special treatment. Other types are unknown, and
3816 * we err on the side of safety by ignoring them. Powering down
3817 * bridges should not be undertaken lightly.
3819 if (dinfo->cfg.hdrtype != 0)
3821 for (i = 0; i < dinfo->cfg.nummaps; i++)
3822 dinfo->cfg.bar[i] = pci_read_config(dev, PCIR_BAR(i), 4);
3823 dinfo->cfg.bios = pci_read_config(dev, PCIR_BIOS, 4);
3826 * Some drivers apparently write to these registers w/o updating our
3827 * cached copy. No harm happens if we update the copy, so do so here
3828 * so we can restore them. The COMMAND register is modified by the
3829 * bus w/o updating the cache. This should represent the normally
3830 * writable portion of the 'defined' part of type 0 headers. In
3831 * theory we also need to save/restore the PCI capability structures
3832 * we know about, but apart from power we don't know any that are
3835 dinfo->cfg.subvendor = pci_read_config(dev, PCIR_SUBVEND_0, 2);
3836 dinfo->cfg.subdevice = pci_read_config(dev, PCIR_SUBDEV_0, 2);
3837 dinfo->cfg.vendor = pci_read_config(dev, PCIR_VENDOR, 2);
3838 dinfo->cfg.device = pci_read_config(dev, PCIR_DEVICE, 2);
3839 dinfo->cfg.cmdreg = pci_read_config(dev, PCIR_COMMAND, 2);
3840 dinfo->cfg.intline = pci_read_config(dev, PCIR_INTLINE, 1);
3841 dinfo->cfg.intpin = pci_read_config(dev, PCIR_INTPIN, 1);
3842 dinfo->cfg.mingnt = pci_read_config(dev, PCIR_MINGNT, 1);
3843 dinfo->cfg.maxlat = pci_read_config(dev, PCIR_MAXLAT, 1);
3844 dinfo->cfg.cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
3845 dinfo->cfg.lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
3846 dinfo->cfg.baseclass = pci_read_config(dev, PCIR_CLASS, 1);
3847 dinfo->cfg.subclass = pci_read_config(dev, PCIR_SUBCLASS, 1);
3848 dinfo->cfg.progif = pci_read_config(dev, PCIR_PROGIF, 1);
3849 dinfo->cfg.revid = pci_read_config(dev, PCIR_REVID, 1);
3852 * don't set the state for display devices, base peripherals and
3853 * memory devices since bad things happen when they are powered down.
3854 * We should (a) have drivers that can easily detach and (b) use
3855 * generic drivers for these devices so that some device actually
3856 * attaches. We need to make sure that when we implement (a) we don't
3857 * power the device down on a reattach.
3859 cls = pci_get_class(dev);
3862 switch (pci_do_power_nodriver)
3864 case 0: /* NO powerdown at all */
3866 case 1: /* Conservative about what to power down */
3867 if (cls == PCIC_STORAGE)
3870 case 2: /* Agressive about what to power down */
3871 if (cls == PCIC_DISPLAY || cls == PCIC_MEMORY ||
3872 cls == PCIC_BASEPERIPH)
3875 case 3: /* Power down everything */
3879 * PCI spec says we can only go into D3 state from D0 state.
3880 * Transition from D[12] into D0 before going to D3 state.
3882 ps = pci_get_powerstate(dev);
3883 if (ps != PCI_POWERSTATE_D0 && ps != PCI_POWERSTATE_D3)
3884 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
3885 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D3)
3886 pci_set_powerstate(dev, PCI_POWERSTATE_D3);