2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
41 #include <vm/vm_param.h>
43 #include <vm/vm_kern.h>
44 #include <vm/vm_extern.h>
46 #include <vm/vm_map.h>
52 #include <sys/mplock2.h>
54 #include <machine/smp.h>
55 #include <machine_base/apic/apicreg.h>
56 #include <machine/atomic.h>
57 #include <machine/cpufunc.h>
58 #include <machine/cputypes.h>
59 #include <machine_base/apic/mpapic.h>
60 #include <machine/psl.h>
61 #include <machine/segments.h>
62 #include <machine/tss.h>
63 #include <machine/specialreg.h>
64 #include <machine/globaldata.h>
65 #include <machine/pmap_inval.h>
67 #include <machine/md_var.h> /* setidt() */
68 #include <machine_base/icu/icu.h> /* IPIs */
69 #include <machine/intr_machdep.h> /* IPIs */
71 #define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
73 #define WARMBOOT_TARGET 0
74 #define WARMBOOT_OFF (KERNBASE + 0x0467)
75 #define WARMBOOT_SEG (KERNBASE + 0x0469)
77 #define BIOS_BASE (0xf0000)
78 #define BIOS_BASE2 (0xe0000)
79 #define BIOS_SIZE (0x10000)
80 #define BIOS_COUNT (BIOS_SIZE/4)
82 #define CMOS_REG (0x70)
83 #define CMOS_DATA (0x71)
84 #define BIOS_RESET (0x0f)
85 #define BIOS_WARM (0x0a)
87 #define PROCENTRY_FLAG_EN 0x01
88 #define PROCENTRY_FLAG_BP 0x02
89 #define IOAPICENTRY_FLAG_EN 0x01
92 /* MP Floating Pointer Structure */
93 typedef struct MPFPS {
106 /* MP Configuration Table Header */
107 typedef struct MPCTH {
109 u_short base_table_length;
113 u_char product_id[12];
114 void *oem_table_pointer;
115 u_short oem_table_size;
118 u_short extended_table_length;
119 u_char extended_table_checksum;
124 typedef struct PROCENTRY {
129 u_long cpu_signature;
130 u_long feature_flags;
135 typedef struct BUSENTRY {
141 typedef struct IOAPICENTRY {
147 } *io_apic_entry_ptr;
149 typedef struct INTENTRY {
159 /* descriptions of MP basetable entries */
160 typedef struct BASETABLE_ENTRY {
169 vm_size_t mp_cth_mapsz;
172 #define MPTABLE_POS_USE_DEFAULT(mpt) \
173 ((mpt)->mp_fps->mpfb1 != 0 || (mpt)->mp_cth == NULL)
177 int mb_type; /* MPTABLE_BUS_ */
178 TAILQ_ENTRY(mptable_bus) mb_link;
181 #define MPTABLE_BUS_ISA 0
182 #define MPTABLE_BUS_PCI 1
184 struct mptable_bus_info {
185 TAILQ_HEAD(, mptable_bus) mbi_list;
188 struct mptable_pci_int {
195 TAILQ_ENTRY(mptable_pci_int) mpci_link;
198 struct mptable_ioapic {
204 TAILQ_ENTRY(mptable_ioapic) mio_link;
207 typedef int (*mptable_iter_func)(void *, const void *, int);
210 * this code MUST be enabled here and in mpboot.s.
211 * it follows the very early stages of AP boot by placing values in CMOS ram.
212 * it NORMALLY will never be needed and thus the primitive method for enabling.
215 #if defined(CHECK_POINTS)
216 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
217 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
219 #define CHECK_INIT(D); \
220 CHECK_WRITE(0x34, (D)); \
221 CHECK_WRITE(0x35, (D)); \
222 CHECK_WRITE(0x36, (D)); \
223 CHECK_WRITE(0x37, (D)); \
224 CHECK_WRITE(0x38, (D)); \
225 CHECK_WRITE(0x39, (D));
227 #define CHECK_PRINT(S); \
228 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
237 #else /* CHECK_POINTS */
239 #define CHECK_INIT(D)
240 #define CHECK_PRINT(S)
242 #endif /* CHECK_POINTS */
245 * Values to send to the POST hardware.
247 #define MP_BOOTADDRESS_POST 0x10
248 #define MP_PROBE_POST 0x11
249 #define MPTABLE_PASS1_POST 0x12
251 #define MP_START_POST 0x13
252 #define MP_ENABLE_POST 0x14
253 #define MPTABLE_PASS2_POST 0x15
255 #define START_ALL_APS_POST 0x16
256 #define INSTALL_AP_TRAMP_POST 0x17
257 #define START_AP_POST 0x18
259 #define MP_ANNOUNCE_POST 0x19
261 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
262 int current_postcode;
264 /** XXX FIXME: what system files declare these??? */
265 extern struct region_descriptor r_gdt, r_idt;
267 int mp_naps; /* # of Applications processors */
268 #ifdef SMP /* APIC-IO */
269 static int mp_nbusses; /* # of busses */
270 int mp_napics; /* # of IO APICs */
271 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
272 u_int32_t *io_apic_versions;
276 u_int32_t cpu_apic_versions[MAXCPU];
278 extern int64_t tsc_offsets[];
280 extern u_long ebda_addr;
282 #ifdef SMP /* APIC-IO */
283 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
287 * APIC ID logical/physical mapping structures.
288 * We oversize these to simplify boot-time config.
290 int cpu_num_to_apic_id[NAPICID];
291 #ifdef SMP /* APIC-IO */
292 int io_num_to_apic_id[NAPICID];
294 int apic_id_to_logical[NAPICID];
296 /* AP uses this during bootstrap. Do not staticize. */
300 /* Hotwire a 0->4MB V==P mapping */
301 extern pt_entry_t *KPTphys;
304 * SMP page table page. Setup by locore to point to a page table
305 * page from which we allocate per-cpu privatespace areas io_apics,
309 #define IO_MAPPING_START_INDEX \
310 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
312 extern pt_entry_t *SMPpt;
313 static int SMPpt_alloc_index = IO_MAPPING_START_INDEX;
315 struct pcb stoppcbs[MAXCPU];
317 static basetable_entry basetable_entry_types[] =
319 {0, 20, "Processor"},
327 * Local data and functions.
330 static u_int boot_address;
331 static u_int base_memory;
332 static int mp_finish;
334 static void mp_enable(u_int boot_addr);
336 static int mptable_iterate_entries(const mpcth_t,
337 mptable_iter_func, void *);
338 static int mptable_search(void);
339 static int mptable_search_sig(u_int32_t target, int count);
340 static int mptable_hyperthread_fixup(cpumask_t, int);
341 #ifdef SMP /* APIC-IO */
342 static void mptable_pass1(struct mptable_pos *);
343 static void mptable_pass2(struct mptable_pos *);
344 static void mptable_default(int type);
345 static void mptable_fix(void);
347 static int mptable_map(struct mptable_pos *);
348 static void mptable_unmap(struct mptable_pos *);
349 static void mptable_imcr(struct mptable_pos *);
350 static void mptable_bus_info_alloc(const mpcth_t,
351 struct mptable_bus_info *);
352 static void mptable_bus_info_free(struct mptable_bus_info *);
354 static int mptable_lapic_probe(struct lapic_enumerator *);
355 static void mptable_lapic_enumerate(struct lapic_enumerator *);
356 static void mptable_lapic_default(void);
358 static int mptable_ioapic_probe(struct ioapic_enumerator *);
359 static void mptable_ioapic_enumerate(struct ioapic_enumerator *);
361 #ifdef SMP /* APIC-IO */
362 static void setup_apic_irq_mapping(void);
363 static int apic_int_is_bus_type(int intr, int bus_type);
365 static int start_all_aps(u_int boot_addr);
366 static void install_ap_tramp(u_int boot_addr);
367 static int start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest);
368 static int smitest(void);
370 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
371 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
372 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
374 static vm_paddr_t mptable_fps_phyaddr;
375 static int mptable_use_default;
376 static TAILQ_HEAD(mptable_pci_int_list, mptable_pci_int) mptable_pci_int_list =
377 TAILQ_HEAD_INITIALIZER(mptable_pci_int_list);
378 static TAILQ_HEAD(mptable_ioapic_list, mptable_ioapic) mptable_ioapic_list =
379 TAILQ_HEAD_INITIALIZER(mptable_ioapic_list);
382 * Calculate usable address in base memory for AP trampoline code.
385 mp_bootaddress(u_int basemem)
387 POSTCODE(MP_BOOTADDRESS_POST);
389 base_memory = basemem;
391 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
392 if ((base_memory - boot_address) < bootMP_size)
393 boot_address -= 4096; /* not enough, lower by 4k */
402 struct mptable_pos mpt;
405 KKASSERT(mptable_fps_phyaddr == 0);
407 mptable_fps_phyaddr = mptable_search();
408 if (mptable_fps_phyaddr == 0)
411 error = mptable_map(&mpt);
413 mptable_fps_phyaddr = 0;
417 if (MPTABLE_POS_USE_DEFAULT(&mpt)) {
418 kprintf("MPTABLE: use default configuration\n");
419 mptable_use_default = 1;
424 SYSINIT(mptable_probe, SI_BOOT2_PRESMP, SI_ORDER_FIRST, mptable_probe, 0);
427 * Look for an Intel MP spec table (ie, SMP capable hardware).
436 * Make sure our SMPpt[] page table is big enough to hold all the
439 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
441 POSTCODE(MP_PROBE_POST);
443 /* see if EBDA exists */
444 if (ebda_addr != 0) {
445 /* search first 1K of EBDA */
446 target = (u_int32_t)ebda_addr;
447 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
450 /* last 1K of base memory, effective 'top of base' passed in */
451 target = (u_int32_t)(base_memory - 0x400);
452 if ((x = mptable_search_sig(target, 1024 / 4)) > 0)
456 /* search the BIOS */
457 target = (u_int32_t)BIOS_BASE;
458 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
461 /* search the extended BIOS */
462 target = (u_int32_t)BIOS_BASE2;
463 if ((x = mptable_search_sig(target, BIOS_COUNT)) > 0)
471 mptable_iterate_entries(const mpcth_t cth, mptable_iter_func func, void *arg)
473 int count, total_size;
474 const void *position;
476 KKASSERT(cth->base_table_length >= sizeof(struct MPCTH));
477 total_size = cth->base_table_length - sizeof(struct MPCTH);
478 position = (const uint8_t *)cth + sizeof(struct MPCTH);
479 count = cth->entry_count;
484 KKASSERT(total_size >= 0);
485 if (total_size == 0) {
486 kprintf("invalid base MP table, "
487 "entry count and length mismatch\n");
491 type = *(const uint8_t *)position;
493 case 0: /* processor_entry */
494 case 1: /* bus_entry */
495 case 2: /* io_apic_entry */
496 case 3: /* int_entry */
497 case 4: /* int_entry */
500 kprintf("unknown base MP table entry type %d\n", type);
504 if (total_size < basetable_entry_types[type].length) {
505 kprintf("invalid base MP table length, "
506 "does not contain all entries\n");
509 total_size -= basetable_entry_types[type].length;
511 error = func(arg, position, type);
515 position = (const uint8_t *)position +
516 basetable_entry_types[type].length;
523 * Startup the SMP processors.
528 POSTCODE(MP_START_POST);
529 mp_enable(boot_address);
534 * Print various information about the SMP system hardware and setup.
541 POSTCODE(MP_ANNOUNCE_POST);
543 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
544 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
545 kprintf(", version: 0x%08x\n", cpu_apic_versions[0]);
546 for (x = 1; x <= mp_naps; ++x) {
547 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
548 kprintf(", version: 0x%08x\n", cpu_apic_versions[x]);
551 if (apic_io_enable) {
552 if (ioapic_use_old) {
553 for (x = 0; x < mp_napics; ++x) {
554 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
555 kprintf(", version: 0x%08x", io_apic_versions[x]);
556 kprintf(", at 0x%08lx\n", io_apic_address[x]);
560 kprintf(" Warning: APIC I/O disabled\n");
565 * AP cpu's call this to sync up protected mode.
567 * WARNING! We must ensure that the cpu is sufficiently initialized to
568 * be able to use to the FP for our optimized bzero/bcopy code before
569 * we enter more mainstream C code.
571 * WARNING! %fs is not set up on entry. This routine sets up %fs.
577 int x, myid = bootAP;
579 struct mdglobaldata *md;
580 struct privatespace *ps;
582 ps = &CPU_prvspace[myid];
584 gdt_segs[GPRIV_SEL].ssd_base = (int)ps;
585 gdt_segs[GPROC0_SEL].ssd_base =
586 (int) &ps->mdglobaldata.gd_common_tss;
587 ps->mdglobaldata.mi.gd_prvspace = ps;
589 for (x = 0; x < NGDT; x++) {
590 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
593 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
594 r_gdt.rd_base = (int) &gdt[myid * NGDT];
595 lgdt(&r_gdt); /* does magic intra-segment return */
600 mdcpu->gd_currentldt = _default_ldt;
602 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
603 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
605 md = mdcpu; /* loaded through %fs:0 (mdglobaldata.mi.gd_prvspace)*/
607 md->gd_common_tss.tss_esp0 = 0; /* not used until after switch */
608 md->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
609 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
610 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
611 md->gd_common_tssd = *md->gd_tss_gdt;
615 * Set to a known state:
616 * Set by mpboot.s: CR0_PG, CR0_PE
617 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
620 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
622 pmap_set_opt(); /* PSE/4MB pages, etc */
624 /* set up CPU registers and state */
627 /* set up FPU state on the AP */
628 npxinit(__INITIAL_NPXCW__);
630 /* set up SSE registers */
634 /*******************************************************************
635 * local functions and data
639 * start the SMP system
642 mp_enable(u_int boot_addr)
646 struct mptable_pos mpt;
648 POSTCODE(MP_ENABLE_POST);
655 if (mptable_fps_phyaddr) {
660 if (apic_io_enable && ioapic_use_old) {
662 if (!mptable_fps_phyaddr)
663 panic("no MP table, disable APIC_IO! (set hw.apic_io_enable=0)\n");
668 * Examine the MP table for needed info
675 /* Post scan cleanup */
678 setup_apic_irq_mapping();
680 /* fill the LOGICAL io_apic_versions table */
681 for (apic = 0; apic < mp_napics; ++apic) {
682 ux = ioapic_read(ioapic[apic], IOAPIC_VER);
683 io_apic_versions[apic] = ux;
684 io_apic_set_id(apic, IO_TO_ID(apic));
687 /* program each IO APIC in the system */
688 for (apic = 0; apic < mp_napics; ++apic)
689 if (io_apic_setup(apic) < 0)
690 panic("IO APIC setup failure");
695 * These are required for SMP operation
698 /* install a 'Spurious INTerrupt' vector */
699 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
700 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
702 /* install an inter-CPU IPI for TLB invalidation */
703 setidt(XINVLTLB_OFFSET, Xinvltlb,
704 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
706 /* install an inter-CPU IPI for IPIQ messaging */
707 setidt(XIPIQ_OFFSET, Xipiq,
708 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
710 /* install a timer vector */
711 setidt(XTIMER_OFFSET, Xtimer,
712 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
714 /* install an inter-CPU IPI for CPU stop/restart */
715 setidt(XCPUSTOP_OFFSET, Xcpustop,
716 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
718 /* start each Application Processor */
719 start_all_aps(boot_addr);
724 * look for the MP spec signature
727 /* string defined by the Intel MP Spec as identifying the MP table */
728 #define MP_SIG 0x5f504d5f /* _MP_ */
729 #define NEXT(X) ((X) += 4)
731 mptable_search_sig(u_int32_t target, int count)
737 KKASSERT(target != 0);
739 map_size = count * sizeof(u_int32_t);
740 addr = pmap_mapdev((vm_paddr_t)target, map_size);
743 for (x = 0; x < count; NEXT(x)) {
744 if (addr[x] == MP_SIG) {
745 /* make array index a byte index */
746 ret = target + (x * sizeof(u_int32_t));
751 pmap_unmapdev((vm_offset_t)addr, map_size);
756 typedef struct BUSDATA {
758 enum busTypes bus_type;
761 typedef struct INTDATA {
771 typedef struct BUSTYPENAME {
776 static bus_type_name bus_type_table[] =
782 {UNKNOWN_BUSTYPE, "---"},
785 {UNKNOWN_BUSTYPE, "---"},
786 {UNKNOWN_BUSTYPE, "---"},
787 {UNKNOWN_BUSTYPE, "---"},
788 {UNKNOWN_BUSTYPE, "---"},
789 {UNKNOWN_BUSTYPE, "---"},
791 {UNKNOWN_BUSTYPE, "---"},
792 {UNKNOWN_BUSTYPE, "---"},
793 {UNKNOWN_BUSTYPE, "---"},
794 {UNKNOWN_BUSTYPE, "---"},
796 {UNKNOWN_BUSTYPE, "---"}
798 /* from MP spec v1.4, table 5-1 */
799 static int default_data[7][5] =
801 /* nbus, id0, type0, id1, type1 */
802 {1, 0, ISA, 255, 255},
803 {1, 0, EISA, 255, 255},
804 {1, 0, EISA, 255, 255},
805 {1, 0, MCA, 255, 255},
807 {2, 0, EISA, 1, PCI},
813 static bus_datum *bus_data;
815 /* the IO INT data, one entry per possible APIC INTerrupt */
816 static io_int *io_apic_ints;
819 static int processor_entry (const struct PROCENTRY *entry, int cpu);
820 static int bus_entry (const struct BUSENTRY *entry, int bus);
821 static int io_apic_entry (const struct IOAPICENTRY *entry, int apic);
822 static int int_entry (const struct INTENTRY *entry, int intr);
823 static int lookup_bus_type (char *name);
826 mptable_ioapic_pass1_callback(void *xarg, const void *pos, int type)
828 const struct IOAPICENTRY *ioapic_ent;
831 case 1: /* bus_entry */
835 case 2: /* io_apic_entry */
837 if (ioapic_ent->apic_flags & IOAPICENTRY_FLAG_EN) {
838 io_apic_address[mp_napics++] =
839 (vm_offset_t)ioapic_ent->apic_address;
843 case 3: /* int_entry */
851 * 1st pass on motherboard's Intel MP specification table.
860 mptable_pass1(struct mptable_pos *mpt)
865 POSTCODE(MPTABLE_PASS1_POST);
868 KKASSERT(fps != NULL);
870 /* clear various tables */
871 for (x = 0; x < NAPICID; ++x)
872 io_apic_address[x] = ~0; /* IO APIC address table */
878 /* check for use of 'default' configuration */
879 if (fps->mpfb1 != 0) {
880 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
881 mp_nbusses = default_data[fps->mpfb1 - 1][0];
887 error = mptable_iterate_entries(mpt->mp_cth,
888 mptable_ioapic_pass1_callback, NULL);
890 panic("mptable_iterate_entries(ioapic_pass1) failed\n");
894 struct mptable_ioapic2_cbarg {
901 mptable_ioapic_pass2_callback(void *xarg, const void *pos, int type)
903 struct mptable_ioapic2_cbarg *arg = xarg;
907 if (bus_entry(pos, arg->bus))
912 if (io_apic_entry(pos, arg->apic))
917 if (int_entry(pos, arg->intr))
925 * 2nd pass on motherboard's Intel MP specification table.
928 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
929 * IO_TO_ID(N), logical IO to APIC ID table
934 mptable_pass2(struct mptable_pos *mpt)
936 struct mptable_ioapic2_cbarg arg;
940 POSTCODE(MPTABLE_PASS2_POST);
943 KKASSERT(fps != NULL);
945 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
947 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
948 M_DEVBUF, M_WAITOK | M_ZERO);
949 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
951 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
954 for (x = 0; x < mp_napics; x++)
955 ioapic[x] = ioapic_map(io_apic_address[x]);
957 /* clear various tables */
958 for (x = 0; x < NAPICID; ++x) {
959 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
960 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
963 /* clear bus data table */
964 for (x = 0; x < mp_nbusses; ++x)
965 bus_data[x].bus_id = 0xff;
967 /* clear IO APIC INT table */
968 for (x = 0; x < nintrs + FIXUP_EXTRA_APIC_INTS; ++x) {
969 io_apic_ints[x].int_type = 0xff;
970 io_apic_ints[x].int_vector = 0xff;
973 /* check for use of 'default' configuration */
974 if (fps->mpfb1 != 0) {
975 mptable_default(fps->mpfb1);
979 bzero(&arg, sizeof(arg));
980 error = mptable_iterate_entries(mpt->mp_cth,
981 mptable_ioapic_pass2_callback, &arg);
983 panic("mptable_iterate_entries(ioapic_pass2) failed\n");
987 * Check if we should perform a hyperthreading "fix-up" to
988 * enumerate any logical CPU's that aren't already listed
991 * XXX: We assume that all of the physical CPUs in the
992 * system have the same number of logical CPUs.
994 * XXX: We assume that APIC ID's are allocated such that
995 * the APIC ID's for a physical processor are aligned
996 * with the number of logical CPU's in the processor.
999 mptable_hyperthread_fixup(cpumask_t id_mask, int cpu_count)
1001 int i, id, lcpus_max, logical_cpus;
1003 if ((cpu_feature & CPUID_HTT) == 0)
1006 lcpus_max = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
1010 if (cpu_vendor_id == CPU_VENDOR_INTEL) {
1012 * INSTRUCTION SET REFERENCE, A-M (#253666)
1013 * Page 3-181, Table 3-20
1014 * "The nearest power-of-2 integer that is not smaller
1015 * than EBX[23:16] is the number of unique initial APIC
1016 * IDs reserved for addressing different logical
1017 * processors in a physical package."
1019 for (i = 0; ; ++i) {
1020 if ((1 << i) >= lcpus_max) {
1027 KKASSERT(cpu_count != 0);
1028 if (cpu_count == lcpus_max) {
1029 /* We have nothing to fix */
1031 } else if (cpu_count == 1) {
1032 /* XXX this may be incorrect */
1033 logical_cpus = lcpus_max;
1035 int cur, prev, dist;
1038 * Calculate the distances between two nearest
1039 * APIC IDs. If all such distances are same,
1040 * then it is the number of missing cpus that
1041 * we are going to fill later.
1043 dist = cur = prev = -1;
1044 for (id = 0; id < MAXCPU; ++id) {
1045 if ((id_mask & CPUMASK(id)) == 0)
1050 int new_dist = cur - prev;
1056 * Make sure that all distances
1057 * between two nearest APIC IDs
1060 if (dist != new_dist)
1068 /* Must be power of 2 */
1069 if (dist & (dist - 1))
1072 /* Can't exceed CPU package capacity */
1073 if (dist > lcpus_max)
1074 logical_cpus = lcpus_max;
1076 logical_cpus = dist;
1080 * For each APIC ID of a CPU that is set in the mask,
1081 * scan the other candidate APIC ID's for this
1082 * physical processor. If any of those ID's are
1083 * already in the table, then kill the fixup.
1085 for (id = 0; id < MAXCPU; id++) {
1086 if ((id_mask & CPUMASK(id)) == 0)
1088 /* First, make sure we are on a logical_cpus boundary. */
1089 if (id % logical_cpus != 0)
1091 for (i = id + 1; i < id + logical_cpus; i++)
1092 if ((id_mask & CPUMASK(i)) != 0)
1095 return logical_cpus;
1099 mptable_map(struct mptable_pos *mpt)
1103 vm_size_t cth_mapsz = 0;
1105 KKASSERT(mptable_fps_phyaddr != 0);
1107 bzero(mpt, sizeof(*mpt));
1109 fps = pmap_mapdev(mptable_fps_phyaddr, sizeof(*fps));
1110 if (fps->pap != 0) {
1112 * Map configuration table header to get
1113 * the base table size
1115 cth = pmap_mapdev(fps->pap, sizeof(*cth));
1116 cth_mapsz = cth->base_table_length;
1117 pmap_unmapdev((vm_offset_t)cth, sizeof(*cth));
1119 if (cth_mapsz < sizeof(*cth)) {
1120 kprintf("invalid base MP table length %d\n",
1122 pmap_unmapdev((vm_offset_t)fps, sizeof(*fps));
1127 * Map the base table
1129 cth = pmap_mapdev(fps->pap, cth_mapsz);
1134 mpt->mp_cth_mapsz = cth_mapsz;
1140 mptable_unmap(struct mptable_pos *mpt)
1142 if (mpt->mp_cth != NULL) {
1143 pmap_unmapdev((vm_offset_t)mpt->mp_cth, mpt->mp_cth_mapsz);
1145 mpt->mp_cth_mapsz = 0;
1147 if (mpt->mp_fps != NULL) {
1148 pmap_unmapdev((vm_offset_t)mpt->mp_fps, sizeof(*mpt->mp_fps));
1154 assign_apic_irq(int apic, int intpin, int irq)
1158 if (int_to_apicintpin[irq].ioapic != -1)
1159 panic("assign_apic_irq: inconsistent table");
1161 int_to_apicintpin[irq].ioapic = apic;
1162 int_to_apicintpin[irq].int_pin = intpin;
1163 int_to_apicintpin[irq].apic_address = ioapic[apic];
1164 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1166 for (x = 0; x < nintrs; x++) {
1167 if ((io_apic_ints[x].int_type == 0 ||
1168 io_apic_ints[x].int_type == 3) &&
1169 io_apic_ints[x].int_vector == 0xff &&
1170 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1171 io_apic_ints[x].dst_apic_int == intpin)
1172 io_apic_ints[x].int_vector = irq;
1177 revoke_apic_irq(int irq)
1183 if (int_to_apicintpin[irq].ioapic == -1)
1184 panic("revoke_apic_irq: inconsistent table");
1186 oldapic = int_to_apicintpin[irq].ioapic;
1187 oldintpin = int_to_apicintpin[irq].int_pin;
1189 int_to_apicintpin[irq].ioapic = -1;
1190 int_to_apicintpin[irq].int_pin = 0;
1191 int_to_apicintpin[irq].apic_address = NULL;
1192 int_to_apicintpin[irq].redirindex = 0;
1194 for (x = 0; x < nintrs; x++) {
1195 if ((io_apic_ints[x].int_type == 0 ||
1196 io_apic_ints[x].int_type == 3) &&
1197 io_apic_ints[x].int_vector != 0xff &&
1198 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1199 io_apic_ints[x].dst_apic_int == oldintpin)
1200 io_apic_ints[x].int_vector = 0xff;
1208 allocate_apic_irq(int intr)
1214 if (io_apic_ints[intr].int_vector != 0xff)
1215 return; /* Interrupt handler already assigned */
1217 if (io_apic_ints[intr].int_type != 0 &&
1218 (io_apic_ints[intr].int_type != 3 ||
1219 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1220 io_apic_ints[intr].dst_apic_int == 0)))
1221 return; /* Not INT or ExtInt on != (0, 0) */
1224 while (irq < APIC_INTMAPSIZE &&
1225 int_to_apicintpin[irq].ioapic != -1)
1228 if (irq >= APIC_INTMAPSIZE)
1229 return; /* No free interrupt handlers */
1231 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1232 intpin = io_apic_ints[intr].dst_apic_int;
1234 assign_apic_irq(apic, intpin, irq);
1239 swap_apic_id(int apic, int oldid, int newid)
1246 return; /* Nothing to do */
1248 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1249 apic, oldid, newid);
1251 /* Swap physical APIC IDs in interrupt entries */
1252 for (x = 0; x < nintrs; x++) {
1253 if (io_apic_ints[x].dst_apic_id == oldid)
1254 io_apic_ints[x].dst_apic_id = newid;
1255 else if (io_apic_ints[x].dst_apic_id == newid)
1256 io_apic_ints[x].dst_apic_id = oldid;
1259 /* Swap physical APIC IDs in IO_TO_ID mappings */
1260 for (oapic = 0; oapic < mp_napics; oapic++)
1261 if (IO_TO_ID(oapic) == newid)
1264 if (oapic < mp_napics) {
1265 kprintf("Changing APIC ID for IO APIC #%d from "
1266 "%d to %d in MP table\n",
1267 oapic, newid, oldid);
1268 IO_TO_ID(oapic) = oldid;
1270 IO_TO_ID(apic) = newid;
1275 fix_id_to_io_mapping(void)
1279 for (x = 0; x < NAPICID; x++)
1282 for (x = 0; x <= mp_naps; x++)
1283 if (CPU_TO_ID(x) < NAPICID)
1284 ID_TO_IO(CPU_TO_ID(x)) = x;
1286 for (x = 0; x < mp_napics; x++)
1287 if (IO_TO_ID(x) < NAPICID)
1288 ID_TO_IO(IO_TO_ID(x)) = x;
1293 first_free_apic_id(void)
1297 for (freeid = 0; freeid < NAPICID; freeid++) {
1298 for (x = 0; x <= mp_naps; x++)
1299 if (CPU_TO_ID(x) == freeid)
1303 for (x = 0; x < mp_napics; x++)
1304 if (IO_TO_ID(x) == freeid)
1315 io_apic_id_acceptable(int apic, int id)
1317 int cpu; /* Logical CPU number */
1318 int oapic; /* Logical IO APIC number for other IO APIC */
1321 return 0; /* Out of range */
1323 for (cpu = 0; cpu <= mp_naps; cpu++)
1324 if (CPU_TO_ID(cpu) == id)
1325 return 0; /* Conflict with CPU */
1327 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1328 if (IO_TO_ID(oapic) == id)
1329 return 0; /* Conflict with other APIC */
1331 return 1; /* ID is acceptable for IO APIC */
1336 io_apic_find_int_entry(int apic, int pin)
1340 /* search each of the possible INTerrupt sources */
1341 for (x = 0; x < nintrs; ++x) {
1342 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1343 (pin == io_apic_ints[x].dst_apic_int))
1344 return (&io_apic_ints[x]);
1350 * parse an Intel MP specification table
1357 int apic; /* IO APIC unit number */
1358 int freeid; /* Free physical APIC ID */
1359 int physid; /* Current physical IO APIC ID */
1361 int bus_0 = 0; /* Stop GCC warning */
1362 int bus_pci = 0; /* Stop GCC warning */
1366 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1367 * did it wrong. The MP spec says that when more than 1 PCI bus
1368 * exists the BIOS must begin with bus entries for the PCI bus and use
1369 * actual PCI bus numbering. This implies that when only 1 PCI bus
1370 * exists the BIOS can choose to ignore this ordering, and indeed many
1371 * MP motherboards do ignore it. This causes a problem when the PCI
1372 * sub-system makes requests of the MP sub-system based on PCI bus
1373 * numbers. So here we look for the situation and renumber the
1374 * busses and associated INTs in an effort to "make it right".
1377 /* find bus 0, PCI bus, count the number of PCI busses */
1378 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1379 if (bus_data[x].bus_id == 0) {
1382 if (bus_data[x].bus_type == PCI) {
1388 * bus_0 == slot of bus with ID of 0
1389 * bus_pci == slot of last PCI bus encountered
1392 /* check the 1 PCI bus case for sanity */
1393 /* if it is number 0 all is well */
1394 if (num_pci_bus == 1 &&
1395 bus_data[bus_pci].bus_id != 0) {
1397 /* mis-numbered, swap with whichever bus uses slot 0 */
1399 /* swap the bus entry types */
1400 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1401 bus_data[bus_0].bus_type = PCI;
1403 /* swap each relavant INTerrupt entry */
1404 id = bus_data[bus_pci].bus_id;
1405 for (x = 0; x < nintrs; ++x) {
1406 if (io_apic_ints[x].src_bus_id == id) {
1407 io_apic_ints[x].src_bus_id = 0;
1409 else if (io_apic_ints[x].src_bus_id == 0) {
1410 io_apic_ints[x].src_bus_id = id;
1415 /* Assign IO APIC IDs.
1417 * First try the existing ID. If a conflict is detected, try
1418 * the ID in the MP table. If a conflict is still detected, find
1421 * We cannot use the ID_TO_IO table before all conflicts has been
1422 * resolved and the table has been corrected.
1424 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1426 /* First try to use the value set by the BIOS */
1427 physid = io_apic_get_id(apic);
1428 if (io_apic_id_acceptable(apic, physid)) {
1429 if (IO_TO_ID(apic) != physid)
1430 swap_apic_id(apic, IO_TO_ID(apic), physid);
1434 /* Then check if the value in the MP table is acceptable */
1435 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1438 /* Last resort, find a free APIC ID and use it */
1439 freeid = first_free_apic_id();
1440 if (freeid >= NAPICID)
1441 panic("No free physical APIC IDs found");
1443 if (io_apic_id_acceptable(apic, freeid)) {
1444 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1447 panic("Free physical APIC ID not usable");
1449 fix_id_to_io_mapping();
1451 /* detect and fix broken Compaq MP table */
1452 if (apic_int_type(0, 0) == -1) {
1453 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1454 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1455 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1456 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1457 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1458 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1460 } else if (apic_int_type(0, 0) == 0) {
1461 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1462 for (x = 0; x < nintrs; ++x)
1463 if ((0 == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1464 (0 == io_apic_ints[x].dst_apic_int)) {
1465 io_apic_ints[x].int_type = 3;
1466 io_apic_ints[x].int_vector = 0xff;
1472 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1473 * controllers universally come in pairs. If IRQ 14 is specified
1474 * as an ISA interrupt, then IRQ 15 had better be too.
1476 * [ Shuttle XPC / AMD Athlon X2 ]
1477 * The MPTable is missing an entry for IRQ 15. Note that the
1478 * ACPI table has an entry for both 14 and 15.
1480 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
1481 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1482 io14 = io_apic_find_int_entry(0, 14);
1483 io_apic_ints[nintrs] = *io14;
1484 io_apic_ints[nintrs].src_bus_irq = 15;
1485 io_apic_ints[nintrs].dst_apic_int = 15;
1490 /* Assign low level interrupt handlers */
1492 setup_apic_irq_mapping(void)
1498 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1499 int_to_apicintpin[x].ioapic = -1;
1500 int_to_apicintpin[x].int_pin = 0;
1501 int_to_apicintpin[x].apic_address = NULL;
1502 int_to_apicintpin[x].redirindex = 0;
1504 /* Default to masked */
1505 int_to_apicintpin[x].flags = IOAPIC_IM_FLAG_MASKED;
1508 /* First assign ISA/EISA interrupts */
1509 for (x = 0; x < nintrs; x++) {
1510 int_vector = io_apic_ints[x].src_bus_irq;
1511 if (int_vector < APIC_INTMAPSIZE &&
1512 io_apic_ints[x].int_vector == 0xff &&
1513 int_to_apicintpin[int_vector].ioapic == -1 &&
1514 (apic_int_is_bus_type(x, ISA) ||
1515 apic_int_is_bus_type(x, EISA)) &&
1516 io_apic_ints[x].int_type == 0) {
1517 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1518 io_apic_ints[x].dst_apic_int,
1523 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1524 for (x = 0; x < nintrs; x++) {
1525 if (io_apic_ints[x].dst_apic_int == 0 &&
1526 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1527 io_apic_ints[x].int_vector == 0xff &&
1528 int_to_apicintpin[0].ioapic == -1 &&
1529 io_apic_ints[x].int_type == 3) {
1530 assign_apic_irq(0, 0, 0);
1535 /* Assign PCI interrupts */
1536 for (x = 0; x < nintrs; ++x) {
1537 if (io_apic_ints[x].int_type == 0 &&
1538 io_apic_ints[x].int_vector == 0xff &&
1539 apic_int_is_bus_type(x, PCI))
1540 allocate_apic_irq(x);
1545 mp_set_cpuids(int cpu_id, int apic_id)
1547 CPU_TO_ID(cpu_id) = apic_id;
1548 ID_TO_CPU(apic_id) = cpu_id;
1550 if (apic_id > lapic_id_max)
1551 lapic_id_max = apic_id;
1555 processor_entry(const struct PROCENTRY *entry, int cpu)
1559 /* check for usability */
1560 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1563 /* check for BSP flag */
1564 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1565 mp_set_cpuids(0, entry->apic_id);
1566 return 0; /* its already been counted */
1569 /* add another AP to list, if less than max number of CPUs */
1570 else if (cpu < MAXCPU) {
1571 mp_set_cpuids(cpu, entry->apic_id);
1579 bus_entry(const struct BUSENTRY *entry, int bus)
1584 /* encode the name into an index */
1585 for (x = 0; x < 6; ++x) {
1586 if ((c = entry->bus_type[x]) == ' ')
1592 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1593 panic("unknown bus type: '%s'", name);
1595 bus_data[bus].bus_id = entry->bus_id;
1596 bus_data[bus].bus_type = x;
1602 io_apic_entry(const struct IOAPICENTRY *entry, int apic)
1604 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1607 IO_TO_ID(apic) = entry->apic_id;
1608 ID_TO_IO(entry->apic_id) = apic;
1614 lookup_bus_type(char *name)
1618 for (x = 0; x < MAX_BUSTYPE; ++x)
1619 if (strcmp(bus_type_table[x].name, name) == 0)
1620 return bus_type_table[x].type;
1622 return UNKNOWN_BUSTYPE;
1626 int_entry(const struct INTENTRY *entry, int intr)
1630 io_apic_ints[intr].int_type = entry->int_type;
1631 io_apic_ints[intr].int_flags = entry->int_flags;
1632 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1633 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1634 if (entry->dst_apic_id == 255) {
1635 /* This signal goes to all IO APICS. Select an IO APIC
1636 with sufficient number of interrupt pins */
1637 for (apic = 0; apic < mp_napics; apic++)
1638 if (((ioapic_read(ioapic[apic], IOAPIC_VER) &
1639 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1640 entry->dst_apic_int)
1642 if (apic < mp_napics)
1643 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1645 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1647 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1648 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1654 apic_int_is_bus_type(int intr, int bus_type)
1658 for (bus = 0; bus < mp_nbusses; ++bus)
1659 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1660 && ((int) bus_data[bus].bus_type == bus_type))
1667 * Given a traditional ISA INT mask, return an APIC mask.
1670 isa_apic_mask(u_int isa_mask)
1675 #if defined(SKIP_IRQ15_REDIRECT)
1676 if (isa_mask == (1 << 15)) {
1677 kprintf("skipping ISA IRQ15 redirect\n");
1680 #endif /* SKIP_IRQ15_REDIRECT */
1682 isa_irq = ffs(isa_mask); /* find its bit position */
1683 if (isa_irq == 0) /* doesn't exist */
1685 --isa_irq; /* make it zero based */
1687 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1691 return (1 << apic_pin); /* convert pin# to a mask */
1695 * Determine which APIC pin an ISA/EISA INT is attached to.
1697 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1698 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1699 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1700 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1702 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1704 isa_apic_irq(int isa_irq)
1708 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1709 if (INTTYPE(intr) == 0) { /* standard INT */
1710 if (SRCBUSIRQ(intr) == isa_irq) {
1711 if (apic_int_is_bus_type(intr, ISA) ||
1712 apic_int_is_bus_type(intr, EISA)) {
1713 if (INTIRQ(intr) == 0xff)
1714 return -1; /* unassigned */
1715 return INTIRQ(intr); /* found */
1720 return -1; /* NOT found */
1725 * Determine which APIC pin a PCI INT is attached to.
1727 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1728 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1729 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1731 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1735 --pciInt; /* zero based */
1737 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1738 if ((INTTYPE(intr) == 0) /* standard INT */
1739 && (SRCBUSID(intr) == pciBus)
1740 && (SRCBUSDEVICE(intr) == pciDevice)
1741 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
1742 if (apic_int_is_bus_type(intr, PCI)) {
1743 if (INTIRQ(intr) == 0xff) {
1744 kprintf("IOAPIC: pci_apic_irq() "
1746 return -1; /* unassigned */
1748 return INTIRQ(intr); /* exact match */
1753 return -1; /* NOT found */
1757 next_apic_irq(int irq)
1764 for (intr = 0; intr < nintrs; intr++) {
1765 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1767 bus = SRCBUSID(intr);
1768 bustype = apic_bus_type(bus);
1769 if (bustype != ISA &&
1775 if (intr >= nintrs) {
1778 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1779 if (INTTYPE(ointr) != 0)
1781 if (bus != SRCBUSID(ointr))
1783 if (bustype == PCI) {
1784 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1786 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1789 if (bustype == ISA || bustype == EISA) {
1790 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1793 if (INTPIN(intr) == INTPIN(ointr))
1797 if (ointr >= nintrs) {
1800 return INTIRQ(ointr);
1813 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1816 * Exactly what this means is unclear at this point. It is a solution
1817 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1818 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1819 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1823 undirect_isa_irq(int rirq)
1827 kprintf("Freeing redirected ISA irq %d.\n", rirq);
1828 /** FIXME: tickle the MB redirector chip */
1832 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1839 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1842 undirect_pci_irq(int rirq)
1846 kprintf("Freeing redirected PCI irq %d.\n", rirq);
1848 /** FIXME: tickle the MB redirector chip */
1852 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1860 * given a bus ID, return:
1861 * the bus type if found
1865 apic_bus_type(int id)
1869 for (x = 0; x < mp_nbusses; ++x)
1870 if (bus_data[x].bus_id == id)
1871 return bus_data[x].bus_type;
1877 * given a LOGICAL APIC# and pin#, return:
1878 * the associated src bus ID if found
1882 apic_src_bus_id(int apic, int pin)
1886 /* search each of the possible INTerrupt sources */
1887 for (x = 0; x < nintrs; ++x)
1888 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1889 (pin == io_apic_ints[x].dst_apic_int))
1890 return (io_apic_ints[x].src_bus_id);
1892 return -1; /* NOT found */
1896 * given a LOGICAL APIC# and pin#, return:
1897 * the associated src bus IRQ if found
1901 apic_src_bus_irq(int apic, int pin)
1905 for (x = 0; x < nintrs; x++)
1906 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1907 (pin == io_apic_ints[x].dst_apic_int))
1908 return (io_apic_ints[x].src_bus_irq);
1910 return -1; /* NOT found */
1915 * given a LOGICAL APIC# and pin#, return:
1916 * the associated INTerrupt type if found
1920 apic_int_type(int apic, int pin)
1924 /* search each of the possible INTerrupt sources */
1925 for (x = 0; x < nintrs; ++x) {
1926 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1927 (pin == io_apic_ints[x].dst_apic_int))
1928 return (io_apic_ints[x].int_type);
1930 return -1; /* NOT found */
1934 * Return the IRQ associated with an APIC pin
1937 apic_irq(int apic, int pin)
1942 for (x = 0; x < nintrs; ++x) {
1943 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1944 (pin == io_apic_ints[x].dst_apic_int)) {
1945 res = io_apic_ints[x].int_vector;
1948 if (apic != int_to_apicintpin[res].ioapic)
1949 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
1950 if (pin != int_to_apicintpin[res].int_pin)
1951 panic("apic_irq inconsistent table (2)");
1960 * given a LOGICAL APIC# and pin#, return:
1961 * the associated trigger mode if found
1965 apic_trigger(int apic, int pin)
1969 /* search each of the possible INTerrupt sources */
1970 for (x = 0; x < nintrs; ++x)
1971 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1972 (pin == io_apic_ints[x].dst_apic_int))
1973 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1975 return -1; /* NOT found */
1980 * given a LOGICAL APIC# and pin#, return:
1981 * the associated 'active' level if found
1985 apic_polarity(int apic, int pin)
1989 /* search each of the possible INTerrupt sources */
1990 for (x = 0; x < nintrs; ++x)
1991 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1992 (pin == io_apic_ints[x].dst_apic_int))
1993 return (io_apic_ints[x].int_flags & 0x03);
1995 return -1; /* NOT found */
1999 * set data according to MP defaults
2000 * FIXME: probably not complete yet...
2003 mptable_default(int type)
2009 kprintf(" MP default config type: %d\n", type);
2012 kprintf(" bus: ISA, APIC: 82489DX\n");
2015 kprintf(" bus: EISA, APIC: 82489DX\n");
2018 kprintf(" bus: EISA, APIC: 82489DX\n");
2021 kprintf(" bus: MCA, APIC: 82489DX\n");
2024 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
2027 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
2030 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
2033 kprintf(" future type\n");
2039 /* one and only IO APIC */
2040 io_apic_id = (ioapic_read(ioapic[0], IOAPIC_ID) & APIC_ID_MASK) >> 24;
2043 * sanity check, refer to MP spec section 3.6.6, last paragraph
2044 * necessary as some hardware isn't properly setting up the IO APIC
2046 #if defined(REALLY_ANAL_IOAPICID_VALUE)
2047 if (io_apic_id != 2) {
2049 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
2050 #endif /* REALLY_ANAL_IOAPICID_VALUE */
2051 io_apic_set_id(0, 2);
2054 IO_TO_ID(0) = io_apic_id;
2055 ID_TO_IO(io_apic_id) = 0;
2057 /* fill out bus entries */
2066 bus_data[0].bus_id = default_data[type - 1][1];
2067 bus_data[0].bus_type = default_data[type - 1][2];
2068 bus_data[1].bus_id = default_data[type - 1][3];
2069 bus_data[1].bus_type = default_data[type - 1][4];
2072 /* case 4: case 7: MCA NOT supported */
2073 default: /* illegal/reserved */
2074 panic("BAD default MP config: %d", type);
2078 /* general cases from MP v1.4, table 5-2 */
2079 for (pin = 0; pin < 16; ++pin) {
2080 io_apic_ints[pin].int_type = 0;
2081 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
2082 io_apic_ints[pin].src_bus_id = 0;
2083 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
2084 io_apic_ints[pin].dst_apic_id = io_apic_id;
2085 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
2088 /* special cases from MP v1.4, table 5-2 */
2090 io_apic_ints[2].int_type = 0xff; /* N/C */
2091 io_apic_ints[13].int_type = 0xff; /* N/C */
2092 #if !defined(APIC_MIXED_MODE)
2094 panic("sorry, can't support type 2 default yet");
2095 #endif /* APIC_MIXED_MODE */
2098 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
2101 io_apic_ints[0].int_type = 0xff; /* N/C */
2103 io_apic_ints[0].int_type = 3; /* vectored 8259 */
2107 * Map a physical memory address representing I/O into KVA. The I/O
2108 * block is assumed not to cross a page boundary.
2111 ioapic_map(vm_paddr_t pa)
2117 KKASSERT(pa < 0x100000000LL);
2119 pgeflag = 0; /* not used for SMP yet */
2122 * If the requested physical address has already been incidently
2123 * mapped, just use the existing mapping. Otherwise create a new
2126 for (i = IO_MAPPING_START_INDEX; i < SMPpt_alloc_index; ++i) {
2127 if (((vm_offset_t)SMPpt[i] & PG_FRAME) ==
2128 ((vm_offset_t)pa & PG_FRAME)) {
2132 if (i == SMPpt_alloc_index) {
2133 if (i == NPTEPG - 2) {
2134 panic("permanent_io_mapping: We ran out of space"
2137 SMPpt[i] = (pt_entry_t)(PG_V | PG_RW | PG_N | pgeflag |
2138 ((vm_offset_t)pa & PG_FRAME));
2139 ++SMPpt_alloc_index;
2141 vaddr = (vm_offset_t)CPU_prvspace + (i * PAGE_SIZE) +
2142 ((vm_offset_t)pa & PAGE_MASK);
2143 return ((void *)vaddr);
2147 * start each AP in our list
2150 start_all_aps(u_int boot_addr)
2157 u_char mpbiosreason;
2158 u_long mpbioswarmvec;
2159 struct mdglobaldata *gd;
2160 struct privatespace *ps;
2164 POSTCODE(START_ALL_APS_POST);
2166 /* Initialize BSP's local APIC */
2167 apic_initialize(TRUE);
2170 MachIntrABI.finalize();
2172 /* install the AP 1st level boot code */
2173 install_ap_tramp(boot_addr);
2176 /* save the current value of the warm-start vector */
2177 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
2178 outb(CMOS_REG, BIOS_RESET);
2179 mpbiosreason = inb(CMOS_DATA);
2181 /* setup a vector to our boot code */
2182 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2183 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2184 outb(CMOS_REG, BIOS_RESET);
2185 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2188 * If we have a TSC we can figure out the SMI interrupt rate.
2189 * The SMI does not necessarily use a constant rate. Spend
2190 * up to 250ms trying to figure it out.
2193 if (cpu_feature & CPUID_TSC) {
2194 set_apic_timer(275000);
2195 smilast = read_apic_timer();
2196 for (x = 0; x < 20 && read_apic_timer(); ++x) {
2197 smicount = smitest();
2198 if (smibest == 0 || smilast - smicount < smibest)
2199 smibest = smilast - smicount;
2202 if (smibest > 250000)
2205 smibest = smibest * (int64_t)1000000 /
2206 get_apic_timer_frequency();
2210 kprintf("SMI Frequency (worst case): %d Hz (%d us)\n",
2211 1000000 / smibest, smibest);
2214 /* set up temporary P==V mapping for AP boot */
2215 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
2216 kptbase = (uintptr_t)(void *)KPTphys;
2217 for (x = 0; x < NKPT; x++) {
2218 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
2219 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
2224 for (x = 1; x <= mp_naps; ++x) {
2226 /* This is a bit verbose, it will go away soon. */
2228 /* first page of AP's private space */
2229 pg = x * i386_btop(sizeof(struct privatespace));
2231 /* allocate new private data page(s) */
2232 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
2233 MDGLOBALDATA_BASEALLOC_SIZE);
2234 /* wire it into the private page table page */
2235 for (i = 0; i < MDGLOBALDATA_BASEALLOC_SIZE; i += PAGE_SIZE) {
2236 SMPpt[pg + i / PAGE_SIZE] = (pt_entry_t)
2237 (PG_V | PG_RW | vtophys_pte((char *)gd + i));
2239 pg += MDGLOBALDATA_BASEALLOC_PAGES;
2241 SMPpt[pg + 0] = 0; /* *gd_CMAP1 */
2242 SMPpt[pg + 1] = 0; /* *gd_CMAP2 */
2243 SMPpt[pg + 2] = 0; /* *gd_CMAP3 */
2244 SMPpt[pg + 3] = 0; /* *gd_PMAP1 */
2246 /* allocate and set up an idle stack data page */
2247 stack = (char *)kmem_alloc(&kernel_map, UPAGES*PAGE_SIZE);
2248 for (i = 0; i < UPAGES; i++) {
2249 SMPpt[pg + 4 + i] = (pt_entry_t)
2250 (PG_V | PG_RW | vtophys_pte(PAGE_SIZE * i + stack));
2253 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2254 bzero(gd, sizeof(*gd));
2255 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2257 /* prime data page for it to use */
2258 mi_gdinit(&gd->mi, x);
2260 gd->gd_CMAP1 = &SMPpt[pg + 0];
2261 gd->gd_CMAP2 = &SMPpt[pg + 1];
2262 gd->gd_CMAP3 = &SMPpt[pg + 2];
2263 gd->gd_PMAP1 = &SMPpt[pg + 3];
2264 gd->gd_CADDR1 = ps->CPAGE1;
2265 gd->gd_CADDR2 = ps->CPAGE2;
2266 gd->gd_CADDR3 = ps->CPAGE3;
2267 gd->gd_PADDR1 = (unsigned *)ps->PPAGE1;
2270 * Per-cpu pmap for get_ptbase().
2272 gd->gd_GDADDR1= (unsigned *)
2273 kmem_alloc_nofault(&kernel_map, SEG_SIZE, SEG_SIZE);
2274 gd->gd_GDMAP1 = &PTD[(vm_offset_t)gd->gd_GDADDR1 >> PDRSHIFT];
2276 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2277 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2280 * Setup the AP boot stack
2282 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2285 /* attempt to start the Application Processor */
2286 CHECK_INIT(99); /* setup checkpoints */
2287 if (!start_ap(gd, boot_addr, smibest)) {
2288 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2289 CHECK_PRINT("trace"); /* show checkpoints */
2290 /* better panic as the AP may be running loose */
2291 kprintf("panic y/n? [y] ");
2292 if (cngetc() != 'n')
2295 CHECK_PRINT("trace"); /* show checkpoints */
2297 /* record its version info */
2298 cpu_apic_versions[x] = cpu_apic_versions[0];
2301 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2304 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2305 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2308 ncpus2_shift = shift;
2309 ncpus2 = 1 << shift;
2310 ncpus2_mask = ncpus2 - 1;
2312 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2313 if ((1 << shift) < ncpus)
2315 ncpus_fit = 1 << shift;
2316 ncpus_fit_mask = ncpus_fit - 1;
2318 /* build our map of 'other' CPUs */
2319 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
2320 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
2321 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2323 /* fill in our (BSP) APIC version */
2324 cpu_apic_versions[0] = lapic.version;
2326 /* restore the warmstart vector */
2327 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2328 outb(CMOS_REG, BIOS_RESET);
2329 outb(CMOS_DATA, mpbiosreason);
2332 * NOTE! The idlestack for the BSP was setup by locore. Finish
2333 * up, clean out the P==V mapping we did earlier.
2335 for (x = 0; x < NKPT; x++)
2339 /* number of APs actually started */
2344 * load the 1st level AP boot code into base memory.
2347 /* targets for relocation */
2348 extern void bigJump(void);
2349 extern void bootCodeSeg(void);
2350 extern void bootDataSeg(void);
2351 extern void MPentry(void);
2352 extern u_int MP_GDT;
2353 extern u_int mp_gdtbase;
2356 install_ap_tramp(u_int boot_addr)
2359 int size = *(int *) ((u_long) & bootMP_size);
2360 u_char *src = (u_char *) ((u_long) bootMP);
2361 u_char *dst = (u_char *) boot_addr + KERNBASE;
2362 u_int boot_base = (u_int) bootMP;
2367 POSTCODE(INSTALL_AP_TRAMP_POST);
2369 for (x = 0; x < size; ++x)
2373 * modify addresses in code we just moved to basemem. unfortunately we
2374 * need fairly detailed info about mpboot.s for this to work. changes
2375 * to mpboot.s might require changes here.
2378 /* boot code is located in KERNEL space */
2379 dst = (u_char *) boot_addr + KERNBASE;
2381 /* modify the lgdt arg */
2382 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2383 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2385 /* modify the ljmp target for MPentry() */
2386 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2387 *dst32 = ((u_int) MPentry - KERNBASE);
2389 /* modify the target for boot code segment */
2390 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2391 dst8 = (u_int8_t *) (dst16 + 1);
2392 *dst16 = (u_int) boot_addr & 0xffff;
2393 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2395 /* modify the target for boot data segment */
2396 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2397 dst8 = (u_int8_t *) (dst16 + 1);
2398 *dst16 = (u_int) boot_addr & 0xffff;
2399 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2404 * This function starts the AP (application processor) identified
2405 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2406 * to accomplish this. This is necessary because of the nuances
2407 * of the different hardware we might encounter. It ain't pretty,
2408 * but it seems to work.
2410 * NOTE: eventually an AP gets to ap_init(), which is called just
2411 * before the AP goes into the LWKT scheduler's idle loop.
2414 start_ap(struct mdglobaldata *gd, u_int boot_addr, int smibest)
2418 u_long icr_lo, icr_hi;
2420 POSTCODE(START_AP_POST);
2422 /* get the PHYSICAL APIC ID# */
2423 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2425 /* calculate the vector */
2426 vector = (boot_addr >> 12) & 0xff;
2428 /* We don't want anything interfering */
2431 /* Make sure the target cpu sees everything */
2435 * Try to detect when a SMI has occurred, wait up to 200ms.
2437 * If a SMI occurs during an AP reset but before we issue
2438 * the STARTUP command, the AP may brick. To work around
2439 * this problem we hold off doing the AP startup until
2440 * after we have detected the SMI. Hopefully another SMI
2441 * will not occur before we finish the AP startup.
2443 * Retries don't seem to help. SMIs have a window of opportunity
2444 * and if USB->legacy keyboard emulation is enabled in the BIOS
2445 * the interrupt rate can be quite high.
2447 * NOTE: Don't worry about the L1 cache load, it might bloat
2448 * ldelta a little but ndelta will be so huge when the SMI
2449 * occurs the detection logic will still work fine.
2452 set_apic_timer(200000);
2457 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2458 * and running the target CPU. OR this INIT IPI might be latched (P5
2459 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2462 * see apic/apicreg.h for icr bit definitions.
2464 * TIME CRITICAL CODE, DO NOT DO ANY KPRINTFS IN THE HOT PATH.
2468 * Setup the address for the target AP. We can setup
2469 * icr_hi once and then just trigger operations with
2472 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
2473 icr_hi |= (physical_cpu << 24);
2474 icr_lo = lapic.icr_lo & 0xfff00000;
2475 lapic.icr_hi = icr_hi;
2478 * Do an INIT IPI: assert RESET
2480 * Use edge triggered mode to assert INIT
2482 lapic.icr_lo = icr_lo | 0x0000c500;
2483 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2487 * The spec calls for a 10ms delay but we may have to use a
2488 * MUCH lower delay to avoid bricking an AP due to a fast SMI
2489 * interrupt. We have other loops here too and dividing by 2
2490 * doesn't seem to be enough even after subtracting 350us,
2491 * so we divide by 4.
2493 * Our minimum delay is 150uS, maximum is 10ms. If no SMI
2494 * interrupt was detected we use the full 10ms.
2498 else if (smibest < 150 * 4 + 350)
2500 else if ((smibest - 350) / 4 < 10000)
2501 u_sleep((smibest - 350) / 4);
2506 * Do an INIT IPI: deassert RESET
2508 * Use level triggered mode to deassert. It is unclear
2509 * why we need to do this.
2511 lapic.icr_lo = icr_lo | 0x00008500;
2512 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2514 u_sleep(150); /* wait 150us */
2517 * Next we do a STARTUP IPI: the previous INIT IPI might still be
2518 * latched, (P5 bug) this 1st STARTUP would then terminate
2519 * immediately, and the previously started INIT IPI would continue. OR
2520 * the previous INIT IPI has already run. and this STARTUP IPI will
2521 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2524 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2525 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2527 u_sleep(200); /* wait ~200uS */
2530 * Finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2531 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2532 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2533 * recognized after hardware RESET or INIT IPI.
2535 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2536 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2539 /* Resume normal operation */
2542 /* wait for it to start, see ap_init() */
2543 set_apic_timer(5000000);/* == 5 seconds */
2544 while (read_apic_timer()) {
2545 if (smp_startup_mask & CPUMASK(gd->mi.gd_cpuid))
2546 return 1; /* return SUCCESS */
2549 return 0; /* return FAILURE */
2564 while (read_apic_timer()) {
2566 for (count = 0; count < 100; ++count)
2567 ntsc = rdtsc(); /* force loop to occur */
2569 ndelta = ntsc - ltsc;
2570 if (ldelta > ndelta)
2572 if (ndelta > ldelta * 2)
2575 ldelta = ntsc - ltsc;
2578 return(read_apic_timer());
2582 * Lazy flush the TLB on all other CPU's. DEPRECATED.
2584 * If for some reason we were unable to start all cpus we cannot safely
2585 * use broadcast IPIs.
2588 static cpumask_t smp_invltlb_req;
2589 #define SMP_INVLTLB_DEBUG
2595 struct mdglobaldata *md = mdcpu;
2596 #ifdef SMP_INVLTLB_DEBUG
2601 crit_enter_gd(&md->mi);
2602 md->gd_invltlb_ret = 0;
2603 ++md->mi.gd_cnt.v_smpinvltlb;
2604 atomic_set_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
2605 #ifdef SMP_INVLTLB_DEBUG
2608 if (smp_startup_mask == smp_active_mask) {
2609 all_but_self_ipi(XINVLTLB_OFFSET);
2611 selected_apic_ipi(smp_active_mask & ~md->mi.gd_cpumask,
2612 XINVLTLB_OFFSET, APIC_DELMODE_FIXED);
2615 #ifdef SMP_INVLTLB_DEBUG
2617 kprintf("smp_invltlb: ipi sent\n");
2619 while ((md->gd_invltlb_ret & smp_active_mask & ~md->mi.gd_cpumask) !=
2620 (smp_active_mask & ~md->mi.gd_cpumask)) {
2623 #ifdef SMP_INVLTLB_DEBUG
2625 if (++count == 400000000) {
2626 print_backtrace(-1);
2627 kprintf("smp_invltlb: endless loop %08lx %08lx, "
2628 "rflags %016lx retry",
2629 (long)md->gd_invltlb_ret,
2630 (long)smp_invltlb_req,
2631 (long)read_eflags());
2632 __asm __volatile ("sti");
2635 lwkt_process_ipiq();
2637 int bcpu = BSFCPUMASK(~md->gd_invltlb_ret &
2638 ~md->mi.gd_cpumask &
2641 kprintf("bcpu %d\n", bcpu);
2642 xgd = globaldata_find(bcpu);
2643 kprintf("thread %p %s\n", xgd->gd_curthread, xgd->gd_curthread->td_comm);
2652 atomic_clear_cpumask(&smp_invltlb_req, md->mi.gd_cpumask);
2653 crit_exit_gd(&md->mi);
2660 * Called from Xinvltlb assembly with interrupts disabled. We didn't
2661 * bother to bump the critical section count or nested interrupt count
2662 * so only do very low level operations here.
2665 smp_invltlb_intr(void)
2667 struct mdglobaldata *md = mdcpu;
2668 struct mdglobaldata *omd;
2672 mask = smp_invltlb_req;
2676 cpu = BSFCPUMASK(mask);
2677 mask &= ~CPUMASK(cpu);
2678 omd = (struct mdglobaldata *)globaldata_find(cpu);
2679 atomic_set_cpumask(&omd->gd_invltlb_ret, md->mi.gd_cpumask);
2686 * When called the executing CPU will send an IPI to all other CPUs
2687 * requesting that they halt execution.
2689 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2691 * - Signals all CPUs in map to stop.
2692 * - Waits for each to stop.
2699 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2700 * from executing at same time.
2703 stop_cpus(cpumask_t map)
2705 map &= smp_active_mask;
2707 /* send the Xcpustop IPI to all CPUs in map */
2708 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2710 while ((stopped_cpus & map) != map)
2718 * Called by a CPU to restart stopped CPUs.
2720 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2722 * - Signals all CPUs in map to restart.
2723 * - Waits for each to restart.
2731 restart_cpus(cpumask_t map)
2733 /* signal other cpus to restart */
2734 started_cpus = map & smp_active_mask;
2736 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2743 * This is called once the mpboot code has gotten us properly relocated
2744 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2745 * and when it returns the scheduler will call the real cpu_idle() main
2746 * loop for the idlethread. Interrupts are disabled on entry and should
2747 * remain disabled at return.
2755 * Adjust smp_startup_mask to signal the BSP that we have started
2756 * up successfully. Note that we do not yet hold the BGL. The BSP
2757 * is waiting for our signal.
2759 * We can't set our bit in smp_active_mask yet because we are holding
2760 * interrupts physically disabled and remote cpus could deadlock
2761 * trying to send us an IPI.
2763 smp_startup_mask |= CPUMASK(mycpu->gd_cpuid);
2767 * Interlock for finalization. Wait until mp_finish is non-zero,
2768 * then get the MP lock.
2770 * Note: We are in a critical section.
2772 * Note: we are the idle thread, we can only spin.
2774 * Note: The load fence is memory volatile and prevents the compiler
2775 * from improperly caching mp_finish, and the cpu from improperly
2778 while (mp_finish == 0)
2780 while (try_mplock() == 0)
2783 if (cpu_feature & CPUID_TSC) {
2785 * The BSP is constantly updating tsc0_offset, figure out
2786 * the relative difference to synchronize ktrdump.
2788 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2791 /* BSP may have changed PTD while we're waiting for the lock */
2794 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2798 /* Build our map of 'other' CPUs. */
2799 mycpu->gd_other_cpus = smp_startup_mask & ~CPUMASK(mycpu->gd_cpuid);
2801 kprintf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
2803 /* A quick check from sanity claus */
2804 apic_id = (apic_id_to_logical[(lapic.id & 0xff000000) >> 24]);
2805 if (mycpu->gd_cpuid != apic_id) {
2806 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2807 kprintf("SMP: apic_id = %d\n", apic_id);
2808 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2809 panic("cpuid mismatch! boom!!");
2812 /* Initialize AP's local APIC for irq's */
2813 apic_initialize(FALSE);
2815 /* Set memory range attributes for this CPU to match the BSP */
2816 mem_range_AP_init();
2819 * Once we go active we must process any IPIQ messages that may
2820 * have been queued, because no actual IPI will occur until we
2821 * set our bit in the smp_active_mask. If we don't the IPI
2822 * message interlock could be left set which would also prevent
2825 * The idle loop doesn't expect the BGL to be held and while
2826 * lwkt_switch() normally cleans things up this is a special case
2827 * because we returning almost directly into the idle loop.
2829 * The idle thread is never placed on the runq, make sure
2830 * nothing we've done put it there.
2832 KKASSERT(get_mplock_count(curthread) == 1);
2833 smp_active_mask |= CPUMASK(mycpu->gd_cpuid);
2836 * Enable interrupts here. idle_restore will also do it, but
2837 * doing it here lets us clean up any strays that got posted to
2838 * the CPU during the AP boot while we are still in a critical
2841 __asm __volatile("sti; pause; pause"::);
2842 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
2844 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2845 lwkt_process_ipiq();
2848 * Releasing the mp lock lets the BSP finish up the SMP init
2851 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
2855 * Get SMP fully working before we start initializing devices.
2863 kprintf("Finish MP startup\n");
2864 if (cpu_feature & CPUID_TSC)
2865 tsc0_offset = rdtsc();
2868 while (smp_active_mask != smp_startup_mask) {
2870 if (cpu_feature & CPUID_TSC)
2871 tsc0_offset = rdtsc();
2873 while (try_mplock() == 0)
2876 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
2879 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
2882 cpu_send_ipiq(int dcpu)
2884 if (CPUMASK(dcpu) & smp_active_mask)
2885 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2888 #if 0 /* single_apic_ipi_passive() not working yet */
2890 * Returns 0 on failure, 1 on success
2893 cpu_send_ipiq_passive(int dcpu)
2896 if (CPUMASK(dcpu) & smp_active_mask) {
2897 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2898 APIC_DELMODE_FIXED);
2905 mptable_bus_info_callback(void *xarg, const void *pos, int type)
2907 struct mptable_bus_info *bus_info = xarg;
2908 const struct BUSENTRY *ent;
2909 struct mptable_bus *bus;
2915 TAILQ_FOREACH(bus, &bus_info->mbi_list, mb_link) {
2916 if (bus->mb_id == ent->bus_id) {
2917 kprintf("mptable_bus_info_alloc: duplicated bus id "
2918 "(%d)\n", bus->mb_id);
2924 if (strncmp(ent->bus_type, "PCI", 3) == 0) {
2925 bus = kmalloc(sizeof(*bus), M_TEMP, M_WAITOK | M_ZERO);
2926 bus->mb_type = MPTABLE_BUS_PCI;
2927 } else if (strncmp(ent->bus_type, "ISA", 3) == 0) {
2928 bus = kmalloc(sizeof(*bus), M_TEMP, M_WAITOK | M_ZERO);
2929 bus->mb_type = MPTABLE_BUS_ISA;
2933 bus->mb_id = ent->bus_id;
2934 TAILQ_INSERT_TAIL(&bus_info->mbi_list, bus, mb_link);
2940 mptable_bus_info_alloc(const mpcth_t cth, struct mptable_bus_info *bus_info)
2944 bzero(bus_info, sizeof(*bus_info));
2945 TAILQ_INIT(&bus_info->mbi_list);
2947 error = mptable_iterate_entries(cth, mptable_bus_info_callback, bus_info);
2949 mptable_bus_info_free(bus_info);
2953 mptable_bus_info_free(struct mptable_bus_info *bus_info)
2955 struct mptable_bus *bus;
2957 while ((bus = TAILQ_FIRST(&bus_info->mbi_list)) != NULL) {
2958 TAILQ_REMOVE(&bus_info->mbi_list, bus, mb_link);
2963 struct mptable_lapic_cbarg1 {
2966 u_int ht_apicid_mask;
2970 mptable_lapic_pass1_callback(void *xarg, const void *pos, int type)
2972 const struct PROCENTRY *ent;
2973 struct mptable_lapic_cbarg1 *arg = xarg;
2979 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
2983 if (ent->apic_id < 32) {
2984 arg->ht_apicid_mask |= 1 << ent->apic_id;
2985 } else if (arg->ht_fixup) {
2986 kprintf("MPTABLE: lapic id > 32, disable HTT fixup\n");
2992 struct mptable_lapic_cbarg2 {
2999 mptable_lapic_pass2_callback(void *xarg, const void *pos, int type)
3001 const struct PROCENTRY *ent;
3002 struct mptable_lapic_cbarg2 *arg = xarg;
3008 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
3009 KKASSERT(!arg->found_bsp);
3013 if (processor_entry(ent, arg->cpu))
3016 if (arg->logical_cpus) {
3017 struct PROCENTRY proc;
3021 * Create fake mptable processor entries
3022 * and feed them to processor_entry() to
3023 * enumerate the logical CPUs.
3025 bzero(&proc, sizeof(proc));
3027 proc.cpu_flags = PROCENTRY_FLAG_EN;
3028 proc.apic_id = ent->apic_id;
3030 for (i = 1; i < arg->logical_cpus; i++) {
3032 processor_entry(&proc, arg->cpu);
3040 mptable_imcr(struct mptable_pos *mpt)
3042 /* record whether PIC or virtual-wire mode */
3043 machintr_setvar_simple(MACHINTR_VAR_IMCR_PRESENT,
3044 mpt->mp_fps->mpfb2 & 0x80);
3048 mptable_lapic_default(void)
3050 int ap_apicid, bsp_apicid;
3052 mp_naps = 1; /* exclude BSP */
3054 /* Map local apic before the id field is accessed */
3055 lapic_map(DEFAULT_APIC_BASE);
3057 bsp_apicid = APIC_ID(lapic.id);
3058 ap_apicid = (bsp_apicid == 0) ? 1 : 0;
3061 mp_set_cpuids(0, bsp_apicid);
3062 /* one and only AP */
3063 mp_set_cpuids(1, ap_apicid);
3069 * ID_TO_CPU(N), APIC ID to logical CPU table
3070 * CPU_TO_ID(N), logical CPU to APIC ID table
3073 mptable_lapic_enumerate(struct lapic_enumerator *e)
3075 struct mptable_pos mpt;
3076 struct mptable_lapic_cbarg1 arg1;
3077 struct mptable_lapic_cbarg2 arg2;
3079 int error, logical_cpus = 0;
3080 vm_offset_t lapic_addr;
3082 if (mptable_use_default) {
3083 mptable_lapic_default();
3087 error = mptable_map(&mpt);
3089 panic("mptable_lapic_enumerate mptable_map failed\n");
3090 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
3094 /* Save local apic address */
3095 lapic_addr = (vm_offset_t)cth->apic_address;
3096 KKASSERT(lapic_addr != 0);
3099 * Find out how many CPUs do we have
3101 bzero(&arg1, sizeof(arg1));
3102 arg1.ht_fixup = 1; /* Apply ht fixup by default */
3104 error = mptable_iterate_entries(cth,
3105 mptable_lapic_pass1_callback, &arg1);
3107 panic("mptable_iterate_entries(lapic_pass1) failed\n");
3108 KKASSERT(arg1.cpu_count != 0);
3110 /* See if we need to fixup HT logical CPUs. */
3111 if (arg1.ht_fixup) {
3112 logical_cpus = mptable_hyperthread_fixup(arg1.ht_apicid_mask,
3114 if (logical_cpus != 0)
3115 arg1.cpu_count *= logical_cpus;
3117 mp_naps = arg1.cpu_count;
3119 /* Qualify the numbers again, after possible HT fixup */
3120 if (mp_naps > MAXCPU) {
3121 kprintf("Warning: only using %d of %d available CPUs!\n",
3126 --mp_naps; /* subtract the BSP */
3129 * Link logical CPU id to local apic id
3131 bzero(&arg2, sizeof(arg2));
3133 arg2.logical_cpus = logical_cpus;
3135 error = mptable_iterate_entries(cth,
3136 mptable_lapic_pass2_callback, &arg2);
3138 panic("mptable_iterate_entries(lapic_pass2) failed\n");
3139 KKASSERT(arg2.found_bsp);
3141 /* Map local apic */
3142 lapic_map(lapic_addr);
3144 mptable_unmap(&mpt);
3147 struct mptable_lapic_probe_cbarg {
3153 mptable_lapic_probe_callback(void *xarg, const void *pos, int type)
3155 const struct PROCENTRY *ent;
3156 struct mptable_lapic_probe_cbarg *arg = xarg;
3162 if ((ent->cpu_flags & PROCENTRY_FLAG_EN) == 0)
3166 if (ent->cpu_flags & PROCENTRY_FLAG_BP) {
3167 if (arg->found_bsp) {
3168 kprintf("more than one BSP in base MP table\n");
3177 mptable_lapic_probe(struct lapic_enumerator *e)
3179 struct mptable_pos mpt;
3180 struct mptable_lapic_probe_cbarg arg;
3184 if (mptable_fps_phyaddr == 0)
3187 if (mptable_use_default)
3190 error = mptable_map(&mpt);
3193 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
3198 if (cth->apic_address == 0)
3201 bzero(&arg, sizeof(arg));
3202 error = mptable_iterate_entries(cth,
3203 mptable_lapic_probe_callback, &arg);
3205 if (arg.cpu_count == 0) {
3206 kprintf("MP table contains no processor entries\n");
3208 } else if (!arg.found_bsp) {
3209 kprintf("MP table does not contains BSP entry\n");
3214 mptable_unmap(&mpt);
3218 static struct lapic_enumerator mptable_lapic_enumerator = {
3219 .lapic_prio = LAPIC_ENUM_PRIO_MPTABLE,
3220 .lapic_probe = mptable_lapic_probe,
3221 .lapic_enumerate = mptable_lapic_enumerate
3225 mptable_lapic_enum_register(void)
3227 lapic_enumerator_register(&mptable_lapic_enumerator);
3229 SYSINIT(mptable_lapic, SI_BOOT2_PRESMP, SI_ORDER_ANY,
3230 mptable_lapic_enum_register, 0);
3233 mptable_ioapic_list_callback(void *xarg, const void *pos, int type)
3235 const struct IOAPICENTRY *ent;
3236 struct mptable_ioapic *nioapic, *ioapic;
3242 if ((ent->apic_flags & IOAPICENTRY_FLAG_EN) == 0)
3245 if (ent->apic_address == 0) {
3246 kprintf("mptable_ioapic_create_list: zero IOAPIC addr\n");
3250 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
3251 if (ioapic->mio_apic_id == ent->apic_id) {
3252 kprintf("mptable_ioapic_create_list: duplicated "
3253 "apic id %d\n", ioapic->mio_apic_id);
3256 if (ioapic->mio_addr == (uint32_t)ent->apic_address) {
3257 kprintf("mptable_ioapic_create_list: overlapped "
3258 "IOAPIC addr 0x%08x", ioapic->mio_addr);
3263 nioapic = kmalloc(sizeof(*nioapic), M_DEVBUF, M_WAITOK | M_ZERO);
3264 nioapic->mio_apic_id = ent->apic_id;
3265 nioapic->mio_addr = (uint32_t)ent->apic_address;
3268 * Create IOAPIC list in ascending order of APIC ID
3270 TAILQ_FOREACH_REVERSE(ioapic, &mptable_ioapic_list,
3271 mptable_ioapic_list, mio_link) {
3272 if (nioapic->mio_apic_id > ioapic->mio_apic_id) {
3273 TAILQ_INSERT_AFTER(&mptable_ioapic_list,
3274 ioapic, nioapic, mio_link);
3279 TAILQ_INSERT_HEAD(&mptable_ioapic_list, nioapic, mio_link);
3285 mptable_ioapic_create_list(void)
3287 struct mptable_ioapic *ioapic;
3288 struct mptable_pos mpt;
3291 if (mptable_fps_phyaddr == 0)
3294 if (mptable_use_default) {
3295 ioapic = kmalloc(sizeof(*ioapic), M_DEVBUF, M_WAITOK | M_ZERO);
3296 ioapic->mio_idx = 0;
3297 ioapic->mio_apic_id = 0; /* NOTE: any value is ok here */
3298 ioapic->mio_addr = 0xfec00000; /* XXX magic number */
3300 TAILQ_INSERT_HEAD(&mptable_ioapic_list, ioapic, mio_link);
3304 error = mptable_map(&mpt);
3306 panic("mptable_ioapic_create_list: mptable_map failed\n");
3307 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
3309 error = mptable_iterate_entries(mpt.mp_cth,
3310 mptable_ioapic_list_callback, NULL);
3312 while ((ioapic = TAILQ_FIRST(&mptable_ioapic_list)) != NULL) {
3313 TAILQ_REMOVE(&mptable_ioapic_list, ioapic, mio_link);
3314 kfree(ioapic, M_DEVBUF);
3320 * Assign index number for each IOAPIC
3323 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
3324 ioapic->mio_idx = idx;
3328 mptable_unmap(&mpt);
3330 SYSINIT(mptable_ioapic_list, SI_BOOT2_PRESMP, SI_ORDER_SECOND,
3331 mptable_ioapic_create_list, 0);
3334 mptable_pci_int_callback(void *xarg, const void *pos, int type)
3336 const struct mptable_bus_info *bus_info = xarg;
3337 const struct mptable_ioapic *ioapic;
3338 const struct mptable_bus *bus;
3339 struct mptable_pci_int *pci_int;
3340 const struct INTENTRY *ent;
3341 int pci_pin, pci_dev;
3347 if (ent->int_type != 0)
3350 TAILQ_FOREACH(bus, &bus_info->mbi_list, mb_link) {
3351 if (bus->mb_type == MPTABLE_BUS_PCI &&
3352 bus->mb_id == ent->src_bus_id)
3358 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
3359 if (ioapic->mio_apic_id == ent->dst_apic_id)
3362 if (ioapic == NULL) {
3363 kprintf("MPTABLE: warning PCI int dst apic id %d "
3364 "does not exist\n", ent->dst_apic_id);
3368 pci_pin = ent->src_bus_irq & 0x3;
3369 pci_dev = (ent->src_bus_irq >> 2) & 0x1f;
3371 TAILQ_FOREACH(pci_int, &mptable_pci_int_list, mpci_link) {
3372 if (pci_int->mpci_bus == ent->src_bus_id &&
3373 pci_int->mpci_dev == pci_dev &&
3374 pci_int->mpci_pin == pci_pin) {
3375 if (pci_int->mpci_ioapic_idx == ioapic->mio_idx &&
3376 pci_int->mpci_ioapic_pin == ent->dst_apic_int) {
3377 kprintf("MPTABLE: warning duplicated "
3378 "PCI int entry for "
3379 "bus %d, dev %d, pin %d\n",
3385 kprintf("mptable_pci_int_register: "
3386 "conflict PCI int entry for "
3387 "bus %d, dev %d, pin %d, "
3388 "IOAPIC %d.%d -> %d.%d\n",
3392 pci_int->mpci_ioapic_idx,
3393 pci_int->mpci_ioapic_pin,
3401 pci_int = kmalloc(sizeof(*pci_int), M_DEVBUF, M_WAITOK | M_ZERO);
3403 pci_int->mpci_bus = ent->src_bus_id;
3404 pci_int->mpci_dev = pci_dev;
3405 pci_int->mpci_pin = pci_pin;
3406 pci_int->mpci_ioapic_idx = ioapic->mio_idx;
3407 pci_int->mpci_ioapic_pin = ent->dst_apic_int;
3409 TAILQ_INSERT_TAIL(&mptable_pci_int_list, pci_int, mpci_link);
3415 mptable_pci_int_register(void)
3417 struct mptable_bus_info bus_info;
3418 const struct mptable_bus *bus;
3419 struct mptable_pci_int *pci_int;
3420 struct mptable_pos mpt;
3421 int error, force_pci0, npcibus;
3424 if (mptable_fps_phyaddr == 0)
3427 if (mptable_use_default)
3430 if (TAILQ_EMPTY(&mptable_ioapic_list))
3433 error = mptable_map(&mpt);
3435 panic("mptable_pci_int_register: mptable_map failed\n");
3436 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
3440 mptable_bus_info_alloc(cth, &bus_info);
3441 if (TAILQ_EMPTY(&bus_info.mbi_list))
3445 TAILQ_FOREACH(bus, &bus_info.mbi_list, mb_link) {
3446 if (bus->mb_type == MPTABLE_BUS_PCI)
3450 mptable_bus_info_free(&bus_info);
3452 } else if (npcibus == 1) {
3456 error = mptable_iterate_entries(cth,
3457 mptable_pci_int_callback, &bus_info);
3459 mptable_bus_info_free(&bus_info);
3462 while ((pci_int = TAILQ_FIRST(&mptable_pci_int_list)) != NULL) {
3463 TAILQ_REMOVE(&mptable_pci_int_list, pci_int, mpci_link);
3464 kfree(pci_int, M_DEVBUF);
3470 TAILQ_FOREACH(pci_int, &mptable_pci_int_list, mpci_link)
3471 pci_int->mpci_bus = 0;
3474 mptable_unmap(&mpt);
3476 SYSINIT(mptable_pci, SI_BOOT2_PRESMP, SI_ORDER_ANY,
3477 mptable_pci_int_register, 0);
3479 struct mptable_ioapic_probe_cbarg {
3480 const struct mptable_bus_info *bus_info;
3484 mptable_ioapic_probe_callback(void *xarg, const void *pos, int type)
3486 struct mptable_ioapic_probe_cbarg *arg = xarg;
3487 const struct mptable_ioapic *ioapic;
3488 const struct mptable_bus *bus;
3489 const struct INTENTRY *ent;
3495 if (ent->int_type != 0)
3498 TAILQ_FOREACH(bus, &arg->bus_info->mbi_list, mb_link) {
3499 if (bus->mb_type == MPTABLE_BUS_ISA &&
3500 bus->mb_id == ent->src_bus_id)
3506 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
3507 if (ioapic->mio_apic_id == ent->dst_apic_id)
3510 if (ioapic == NULL) {
3511 kprintf("MPTABLE: warning ISA int dst apic id %d "
3512 "does not exist\n", ent->dst_apic_id);
3516 /* XXX magic number */
3517 if (ent->src_bus_irq >= 16) {
3518 kprintf("mptable_ioapic_probe: invalid ISA irq (%d)\n",
3526 mptable_ioapic_probe(struct ioapic_enumerator *e)
3528 struct mptable_ioapic_probe_cbarg arg;
3529 struct mptable_bus_info bus_info;
3530 struct mptable_pos mpt;
3534 if (mptable_fps_phyaddr == 0)
3537 if (mptable_use_default)
3540 if (TAILQ_EMPTY(&mptable_ioapic_list))
3543 error = mptable_map(&mpt);
3545 panic("mptable_ioapic_probe: mptable_map failed\n");
3546 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
3550 mptable_bus_info_alloc(cth, &bus_info);
3552 bzero(&arg, sizeof(arg));
3553 arg.bus_info = &bus_info;
3555 error = mptable_iterate_entries(cth,
3556 mptable_ioapic_probe_callback, &arg);
3558 mptable_bus_info_free(&bus_info);
3559 mptable_unmap(&mpt);
3564 struct mptable_ioapic_int_cbarg {
3565 const struct mptable_bus_info *bus_info;
3570 mptable_ioapic_int_callback(void *xarg, const void *pos, int type)
3572 struct mptable_ioapic_int_cbarg *arg = xarg;
3573 const struct mptable_bus *bus;
3574 const struct INTENTRY *ent;
3582 if (ent->int_type != 0)
3585 TAILQ_FOREACH(bus, &arg->bus_info->mbi_list, mb_link) {
3586 if (bus->mb_type == MPTABLE_BUS_ISA &&
3587 bus->mb_id == ent->src_bus_id)
3593 /* XXX rough estimation */
3594 if (ent->src_bus_irq != ent->dst_apic_int) {
3596 kprintf("MPTABLE: INTSRC irq %d -> GSI %d\n",
3597 ent->src_bus_irq, ent->dst_apic_int);
3604 mptable_ioapic_enumerate(struct ioapic_enumerator *e)
3606 struct mptable_bus_info bus_info;
3607 struct mptable_ioapic *ioapic;
3608 struct mptable_pos mpt;
3612 KKASSERT(mptable_fps_phyaddr != 0);
3613 KKASSERT(!TAILQ_EMPTY(&mptable_ioapic_list));
3615 TAILQ_FOREACH(ioapic, &mptable_ioapic_list, mio_link) {
3616 if (!ioapic_use_old) {
3617 const struct mptable_ioapic *prev_ioapic;
3621 addr = ioapic_map(ioapic->mio_addr);
3623 ver = ioapic_read(addr, IOAPIC_VER);
3624 ioapic->mio_npin = ((ver & IOART_VER_MAXREDIR)
3625 >> MAXREDIRSHIFT) + 1;
3627 prev_ioapic = TAILQ_PREV(ioapic,
3628 mptable_ioapic_list, mio_link);
3629 if (prev_ioapic == NULL) {
3630 ioapic->mio_gsi_base = 0;
3632 ioapic->mio_gsi_base =
3633 prev_ioapic->mio_gsi_base +
3634 prev_ioapic->mio_npin;
3639 kprintf("MPTABLE: IOAPIC addr 0x%08x, "
3640 "apic id %d, idx %d, gsi base %d, npin %d\n",
3642 ioapic->mio_apic_id,
3644 ioapic->mio_gsi_base,
3649 if (mptable_use_default) {
3651 kprintf("MPTABLE: INTSRC irq 0 -> GSI 2 (default)\n");
3652 /* TODO default intsrc */
3656 error = mptable_map(&mpt);
3658 panic("mptable_ioapic_probe: mptable_map failed\n");
3659 KKASSERT(!MPTABLE_POS_USE_DEFAULT(&mpt));
3663 mptable_bus_info_alloc(cth, &bus_info);
3665 if (TAILQ_EMPTY(&bus_info.mbi_list)) {
3667 kprintf("MPTABLE: INTSRC irq 0 -> GSI 2 (no bus)\n");
3668 /* TODO default intsrc */
3670 struct mptable_ioapic_int_cbarg arg;
3672 bzero(&arg, sizeof(arg));
3673 arg.bus_info = &bus_info;
3675 error = mptable_iterate_entries(cth,
3676 mptable_ioapic_int_callback, &arg);
3678 panic("mptable_ioapic_int failed\n");
3680 if (arg.ioapic_nint == 0) {
3682 kprintf("MPTABLE: INTSRC irq 0 -> GSI 2 "
3685 /* TODO default intsrc */
3689 mptable_bus_info_free(&bus_info);
3691 mptable_unmap(&mpt);
3694 static struct ioapic_enumerator mptable_ioapic_enumerator = {
3695 .ioapic_prio = IOAPIC_ENUM_PRIO_MPTABLE,
3696 .ioapic_probe = mptable_ioapic_probe,
3697 .ioapic_enumerate = mptable_ioapic_enumerate
3701 mptable_ioapic_enum_register(void)
3703 ioapic_enumerator_register(&mptable_ioapic_enumerator);
3705 SYSINIT(mptable_ioapic, SI_BOOT2_PRESMP, SI_ORDER_ANY,
3706 mptable_ioapic_enum_register, 0);