sys/dev/netif/bge/if_bge.c

   1 /*
   2  * Copyright (c) 2001 Wind River Systems
   3  * Copyright (c) 1997, 1998, 1999, 2001
   4  *      Bill Paul <wpaul@windriver.com>.  All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. All advertising materials mentioning features or use of this software
  15  *    must display the following acknowledgement:
  16  *      This product includes software developed by Bill Paul.
  17  * 4. Neither the name of the author nor the names of any co-contributors
  18  *    may be used to endorse or promote products derived from this software
  19  *    without specific prior written permission.
  20  *
  21  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
  22  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  23  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  24  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
  25  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  26  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  27  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  28  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  29  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  30  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  31  * THE POSSIBILITY OF SUCH DAMAGE.
  32  *
  33  * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.39 2005/07/03 03:41:18 silby Exp $
  34  * $DragonFly: src/sys/dev/netif/bge/if_bge.c,v 1.62 2007/03/31 06:07:16 sephe Exp $
  35  *
  36  */
  37
  38 /*
  39  * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
  40  *
  41  * Written by Bill Paul <wpaul@windriver.com>
  42  * Senior Engineer, Wind River Systems
  43  */
  44
  45 /*
  46  * The Broadcom BCM5700 is based on technology originally developed by
  47  * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
  48  * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
  49  * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
  50  * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
  51  * frames, highly configurable RX filtering, and 16 RX and TX queues
  52  * (which, along with RX filter rules, can be used for QOS applications).
  53  * Other features, such as TCP segmentation, may be available as part
  54  * of value-added firmware updates. Unlike the Tigon I and Tigon II,
  55  * firmware images can be stored in hardware and need not be compiled
  56  * into the driver.
  57  *
  58  * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
  59  * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
  60  *
  61  * The BCM5701 is a single-chip solution incorporating both the BCM5700
  62  * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
  63  * does not support external SSRAM.
  64  *
  65  * Broadcom also produces a variation of the BCM5700 under the "Altima"
  66  * brand name, which is functionally similar but lacks PCI-X support.
  67  *
  68  * Without external SSRAM, you can only have at most 4 TX rings,
  69  * and the use of the mini RX ring is disabled. This seems to imply
  70  * that these features are simply not available on the BCM5701. As a
  71  * result, this driver does not implement any support for the mini RX
  72  * ring.
  73  */
  74
  75 #include <sys/param.h>
  76 #include <sys/systm.h>
  77 #include <sys/sockio.h>
  78 #include <sys/mbuf.h>
  79 #include <sys/malloc.h>
  80 #include <sys/kernel.h>
  81 #include <sys/socket.h>
  82 #include <sys/queue.h>
  83 #include <sys/serialize.h>
  84 #include <sys/thread2.h>
  85
  86 #include <net/if.h>
  87 #include <net/ifq_var.h>
  88 #include <net/if_arp.h>
  89 #include <net/ethernet.h>
  90 #include <net/if_dl.h>
  91 #include <net/if_media.h>
  92
  93 #include <net/bpf.h>
  94
  95 #include <net/if_types.h>
  96 #include <net/vlan/if_vlan_var.h>
  97
  98 #include <netinet/in_systm.h>
  99 #include <netinet/in.h>
 100 #include <netinet/ip.h>
 101
 102 #include <vm/vm.h>              /* for vtophys */
 103 #include <vm/pmap.h>            /* for vtophys */
 104 #include <sys/bus.h>
 105 #include <sys/rman.h>
 106
 107 #include <dev/netif/mii_layer/mii.h>
 108 #include <dev/netif/mii_layer/miivar.h>
 109 #include <dev/netif/mii_layer/miidevs.h>
 110 #include <dev/netif/mii_layer/brgphyreg.h>
 111
 112 #include <bus/pci/pcidevs.h>
 113 #include <bus/pci/pcireg.h>
 114 #include <bus/pci/pcivar.h>
 115
 116 #include "if_bgereg.h"
 117
 118 #define BGE_CSUM_FEATURES       (CSUM_IP | CSUM_TCP | CSUM_UDP)
 119
 120 /* "controller miibus0" required.  See GENERIC if you get errors here. */
 121 #include "miibus_if.h"
 122
 123 /*
 124  * Various supported device vendors/types and their names. Note: the
 125  * spec seems to indicate that the hardware still has Alteon's vendor
 126  * ID burned into it, though it will always be overriden by the vendor
 127  * ID in the EEPROM. Just to be safe, we cover all possibilities.
 128  */
 129 #define BGE_DEVDESC_MAX         64      /* Maximum device description length */
 130
 131 static struct bge_type bge_devs[] = {
 132         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700,
 133                 "Alteon BCM5700 Gigabit Ethernet" },
 134         { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5701,
 135                 "Alteon BCM5701 Gigabit Ethernet" },
 136         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700,
 137                 "Broadcom BCM5700 Gigabit Ethernet" },
 138         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701,
 139                 "Broadcom BCM5701 Gigabit Ethernet" },
 140         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X,
 141                 "Broadcom BCM5702X Gigabit Ethernet" },
 142         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702_ALT,
 143                 "Broadcom BCM5702 Gigabit Ethernet" },
 144         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X,
 145                 "Broadcom BCM5703X Gigabit Ethernet" },
 146         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703A3,
 147                 "Broadcom BCM5703 Gigabit Ethernet" },
 148         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C,
 149                 "Broadcom BCM5704C Dual Gigabit Ethernet" },
 150         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S,
 151                 "Broadcom BCM5704S Dual Gigabit Ethernet" },
 152         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705,
 153                 "Broadcom BCM5705 Gigabit Ethernet" },
 154         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K,
 155                 "Broadcom BCM5705K Gigabit Ethernet" },
 156         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M,
 157                 "Broadcom BCM5705M Gigabit Ethernet" },
 158         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M_ALT,
 159                 "Broadcom BCM5705M Gigabit Ethernet" },
 160         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5714,
 161                 "Broadcom BCM5714C Gigabit Ethernet" },
 162         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721,
 163                 "Broadcom BCM5721 Gigabit Ethernet" },
 164         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750,
 165                 "Broadcom BCM5750 Gigabit Ethernet" },
 166         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M,
 167                 "Broadcom BCM5750M Gigabit Ethernet" },
 168         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751,
 169                 "Broadcom BCM5751 Gigabit Ethernet" },
 170         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751M,
 171                 "Broadcom BCM5751M Gigabit Ethernet" },
 172         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782,
 173                 "Broadcom BCM5782 Gigabit Ethernet" },
 174         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5788,
 175                 "Broadcom BCM5788 Gigabit Ethernet" },
 176         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5789,
 177                 "Broadcom BCM5789 Gigabit Ethernet" },
 178         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901,
 179                 "Broadcom BCM5901 Fast Ethernet" },
 180         { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2,
 181                 "Broadcom BCM5901A2 Fast Ethernet" },
 182         { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
 183                 "SysKonnect Gigabit Ethernet" },
 184         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000,
 185                 "Altima AC1000 Gigabit Ethernet" },
 186         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001,
 187                 "Altima AC1002 Gigabit Ethernet" },
 188         { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100,
 189                 "Altima AC9100 Gigabit Ethernet" },
 190         { 0, 0, NULL }
 191 };
 192
 193 static int      bge_probe(device_t);
 194 static int      bge_attach(device_t);
 195 static int      bge_detach(device_t);
 196 static void     bge_release_resources(struct bge_softc *);
 197 static void     bge_txeof(struct bge_softc *);
 198 static void     bge_rxeof(struct bge_softc *);
 199
 200 static void     bge_tick(void *);
 201 static void     bge_tick_serialized(void *);
 202 static void     bge_stats_update(struct bge_softc *);
 203 static void     bge_stats_update_regs(struct bge_softc *);
 204 static int      bge_encap(struct bge_softc *, struct mbuf *, uint32_t *);
 205
 206 static void     bge_intr(void *);
 207 static void     bge_start(struct ifnet *);
 208 static int      bge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 209 static void     bge_init(void *);
 210 static void     bge_stop(struct bge_softc *);
 211 static void     bge_watchdog(struct ifnet *);
 212 static void     bge_shutdown(device_t);
 213 static int      bge_suspend(device_t);
 214 static int      bge_resume(device_t);
 215 static int      bge_ifmedia_upd(struct ifnet *);
 216 static void     bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
 217
 218 static uint8_t  bge_eeprom_getbyte(struct bge_softc *, uint32_t, uint8_t *);
 219 static int      bge_read_eeprom(struct bge_softc *, caddr_t, uint32_t, size_t);
 220
 221 static void     bge_setmulti(struct bge_softc *);
 222
 223 static void     bge_handle_events(struct bge_softc *);
 224 static int      bge_alloc_jumbo_mem(struct bge_softc *);
 225 static void     bge_free_jumbo_mem(struct bge_softc *);
 226 static struct bge_jslot
 227                 *bge_jalloc(struct bge_softc *);
 228 static void     bge_jfree(void *);
 229 static void     bge_jref(void *);
 230 static int      bge_newbuf_std(struct bge_softc *, int, struct mbuf *);
 231 static int      bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *);
 232 static int      bge_init_rx_ring_std(struct bge_softc *);
 233 static void     bge_free_rx_ring_std(struct bge_softc *);
 234 static int      bge_init_rx_ring_jumbo(struct bge_softc *);
 235 static void     bge_free_rx_ring_jumbo(struct bge_softc *);
 236 static void     bge_free_tx_ring(struct bge_softc *);
 237 static int      bge_init_tx_ring(struct bge_softc *);
 238
 239 static int      bge_chipinit(struct bge_softc *);
 240 static int      bge_blockinit(struct bge_softc *);
 241
 242 #ifdef notdef
 243 static uint8_t  bge_vpd_readbyte(struct bge_softc *, uint32_t);
 244 static void     bge_vpd_read_res(struct bge_softc *, struct vpd_res *, uint32_t);
 245 static void     bge_vpd_read(struct bge_softc *);
 246 #endif
 247
 248 static uint32_t bge_readmem_ind(struct bge_softc *, uint32_t);
 249 static void     bge_writemem_ind(struct bge_softc *, uint32_t, uint32_t);
 250 #ifdef notdef
 251 static uint32_t bge_readreg_ind(struct bge_softc *, uint32_t);
 252 #endif
 253 static void     bge_writereg_ind(struct bge_softc *, uint32_t, uint32_t);
 254
 255 static int      bge_miibus_readreg(device_t, int, int);
 256 static int      bge_miibus_writereg(device_t, int, int, int);
 257 static void     bge_miibus_statchg(device_t);
 258
 259 static void     bge_reset(struct bge_softc *);
 260
 261 /*
 262  * Set following tunable to 1 for some IBM blade servers with the DNLK
 263  * switch module. Auto negotiation is broken for those configurations.
 264  */
 265 static int      bge_fake_autoneg = 0;
 266 TUNABLE_INT("hw.bge.fake_autoneg", &bge_fake_autoneg);
 267
 268 static device_method_t bge_methods[] = {
 269         /* Device interface */
 270         DEVMETHOD(device_probe,         bge_probe),
 271         DEVMETHOD(device_attach,        bge_attach),
 272         DEVMETHOD(device_detach,        bge_detach),
 273         DEVMETHOD(device_shutdown,      bge_shutdown),
 274         DEVMETHOD(device_suspend,       bge_suspend),
 275         DEVMETHOD(device_resume,        bge_resume),
 276
 277         /* bus interface */
 278         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 279         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 280
 281         /* MII interface */
 282         DEVMETHOD(miibus_readreg,       bge_miibus_readreg),
 283         DEVMETHOD(miibus_writereg,      bge_miibus_writereg),
 284         DEVMETHOD(miibus_statchg,       bge_miibus_statchg),
 285
 286         { 0, 0 }
 287 };
 288
 289 static DEFINE_CLASS_0(bge, bge_driver, bge_methods, sizeof(struct bge_softc));
 290 static devclass_t bge_devclass;
 291
 292 DECLARE_DUMMY_MODULE(if_bge);
 293 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, 0, 0);
 294 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
 295
 296 static uint32_t
 297 bge_readmem_ind(struct bge_softc *sc, uint32_t off)
 298 {
 299         device_t dev = sc->bge_dev;
 300
 301         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 302         return(pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4));
 303 }
 304
 305 static void
 306 bge_writemem_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
 307 {
 308         device_t dev = sc->bge_dev;
 309
 310         pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
 311         pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
 312 }
 313
 314 #ifdef notdef
 315 static uint32_t
 316 bge_readreg_ind(struct bge_softc *sc, uin32_t off)
 317 {
 318         device_t dev = sc->bge_dev;
 319
 320         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 321         return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
 322 }
 323 #endif
 324
 325 static void
 326 bge_writereg_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
 327 {
 328         device_t dev = sc->bge_dev;
 329
 330         pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
 331         pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
 332 }
 333
 334 #ifdef notdef
 335 static uint8_t
 336 bge_vpd_readbyte(struct bge_softc *sc, uint32_t addr)
 337 {
 338         device_t dev = sc->bge_dev;
 339         uint32_t val;
 340         int i;
 341
 342         pci_write_config(dev, BGE_PCI_VPD_ADDR, addr, 2);
 343         for (i = 0; i < BGE_TIMEOUT * 10; i++) {
 344                 DELAY(10);
 345                 if (pci_read_config(dev, BGE_PCI_VPD_ADDR, 2) & BGE_VPD_FLAG)
 346                         break;
 347         }
 348
 349         if (i == BGE_TIMEOUT) {
 350                 device_printf(sc->bge_dev, "VPD read timed out\n");
 351                 return(0);
 352         }
 353
 354         val = pci_read_config(dev, BGE_PCI_VPD_DATA, 4);
 355
 356         return((val >> ((addr % 4) * 8)) & 0xFF);
 357 }
 358
 359 static void
 360 bge_vpd_read_res(struct bge_softc *sc, struct vpd_res *res, uint32_t addr)
 361 {
 362         size_t i;
 363         uint8_t *ptr;
 364
 365         ptr = (uint8_t *)res;
 366         for (i = 0; i < sizeof(struct vpd_res); i++)
 367                 ptr[i] = bge_vpd_readbyte(sc, i + addr);
 368
 369         return;
 370 }
 371
 372 static void
 373 bge_vpd_read(struct bge_softc *sc)
 374 {
 375         int pos = 0, i;
 376         struct vpd_res res;
 377
 378         if (sc->bge_vpd_prodname != NULL)
 379                 kfree(sc->bge_vpd_prodname, M_DEVBUF);
 380         if (sc->bge_vpd_readonly != NULL)
 381                 kfree(sc->bge_vpd_readonly, M_DEVBUF);
 382         sc->bge_vpd_prodname = NULL;
 383         sc->bge_vpd_readonly = NULL;
 384
 385         bge_vpd_read_res(sc, &res, pos);
 386
 387         if (res.vr_id != VPD_RES_ID) {
 388                 device_printf(sc->bge_dev,
 389                               "bad VPD resource id: expected %x got %x\n",
 390                               VPD_RES_ID, res.vr_id);
 391                 return;
 392         }
 393
 394         pos += sizeof(res);
 395         sc->bge_vpd_prodname = kmalloc(res.vr_len + 1, M_DEVBUF, M_INTWAIT);
 396         for (i = 0; i < res.vr_len; i++)
 397                 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos);
 398         sc->bge_vpd_prodname[i] = '\0';
 399         pos += i;
 400
 401         bge_vpd_read_res(sc, &res, pos);
 402
 403         if (res.vr_id != VPD_RES_READ) {
 404                 device_printf(sc->bge_dev,
 405                               "bad VPD resource id: expected %x got %x\n",
 406                               VPD_RES_READ, res.vr_id);
 407                 return;
 408         }
 409
 410         pos += sizeof(res);
 411         sc->bge_vpd_readonly = kmalloc(res.vr_len, M_DEVBUF, M_INTWAIT);
 412         for (i = 0; i < res.vr_len + 1; i++)
 413                 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos);
 414 }
 415 #endif
 416
 417 /*
 418  * Read a byte of data stored in the EEPROM at address 'addr.' The
 419  * BCM570x supports both the traditional bitbang interface and an
 420  * auto access interface for reading the EEPROM. We use the auto
 421  * access method.
 422  */
 423 static uint8_t
 424 bge_eeprom_getbyte(struct bge_softc *sc, uint32_t addr, uint8_t *dest)
 425 {
 426         int i;
 427         uint32_t byte = 0;
 428
 429         /*
 430          * Enable use of auto EEPROM access so we can avoid
 431          * having to use the bitbang method.
 432          */
 433         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
 434
 435         /* Reset the EEPROM, load the clock period. */
 436         CSR_WRITE_4(sc, BGE_EE_ADDR,
 437             BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
 438         DELAY(20);
 439
 440         /* Issue the read EEPROM command. */
 441         CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
 442
 443         /* Wait for completion */
 444         for(i = 0; i < BGE_TIMEOUT * 10; i++) {
 445                 DELAY(10);
 446                 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
 447                         break;
 448         }
 449
 450         if (i == BGE_TIMEOUT) {
 451                 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
 452                 return(0);
 453         }
 454
 455         /* Get result. */
 456         byte = CSR_READ_4(sc, BGE_EE_DATA);
 457
 458         *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
 459
 460         return(0);
 461 }
 462
 463 /*
 464  * Read a sequence of bytes from the EEPROM.
 465  */
 466 static int
 467 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, uint32_t off, size_t len)
 468 {
 469         size_t i;
 470         int err;
 471         uint8_t byte;
 472
 473         for (byte = 0, err = 0, i = 0; i < len; i++) {
 474                 err = bge_eeprom_getbyte(sc, off + i, &byte);
 475                 if (err)
 476                         break;
 477                 *(dest + i) = byte;
 478         }
 479
 480         return(err ? 1 : 0);
 481 }
 482
 483 static int
 484 bge_miibus_readreg(device_t dev, int phy, int reg)
 485 {
 486         struct bge_softc *sc;
 487         struct ifnet *ifp;
 488         uint32_t val, autopoll;
 489         int i;
 490
 491         sc = device_get_softc(dev);
 492         ifp = &sc->arpcom.ac_if;
 493
 494         /*
 495          * Broadcom's own driver always assumes the internal
 496          * PHY is at GMII address 1. On some chips, the PHY responds
 497          * to accesses at all addresses, which could cause us to
 498          * bogusly attach the PHY 32 times at probe type. Always
 499          * restricting the lookup to address 1 is simpler than
 500          * trying to figure out which chips revisions should be
 501          * special-cased.
 502          */
 503         if (phy != 1)
 504                 return(0);
 505
 506         /* Reading with autopolling on may trigger PCI errors */
 507         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
 508         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 509                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 510                 DELAY(40);
 511         }
 512
 513         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY|
 514             BGE_MIPHY(phy)|BGE_MIREG(reg));
 515
 516         for (i = 0; i < BGE_TIMEOUT; i++) {
 517                 val = CSR_READ_4(sc, BGE_MI_COMM);
 518                 if (!(val & BGE_MICOMM_BUSY))
 519                         break;
 520         }
 521
 522         if (i == BGE_TIMEOUT) {
 523                 if_printf(ifp, "PHY read timed out\n");
 524                 val = 0;
 525                 goto done;
 526         }
 527
 528         val = CSR_READ_4(sc, BGE_MI_COMM);
 529
 530 done:
 531         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 532                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 533                 DELAY(40);
 534         }
 535
 536         if (val & BGE_MICOMM_READFAIL)
 537                 return(0);
 538
 539         return(val & 0xFFFF);
 540 }
 541
 542 static int
 543 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
 544 {
 545         struct bge_softc *sc;
 546         uint32_t autopoll;
 547         int i;
 548
 549         sc = device_get_softc(dev);
 550
 551         /* Reading with autopolling on may trigger PCI errors */
 552         autopoll = CSR_READ_4(sc, BGE_MI_MODE);
 553         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 554                 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 555                 DELAY(40);
 556         }
 557
 558         CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY|
 559             BGE_MIPHY(phy)|BGE_MIREG(reg)|val);
 560
 561         for (i = 0; i < BGE_TIMEOUT; i++) {
 562                 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY))
 563                         break;
 564         }
 565
 566         if (autopoll & BGE_MIMODE_AUTOPOLL) {
 567                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
 568                 DELAY(40);
 569         }
 570
 571         if (i == BGE_TIMEOUT) {
 572                 if_printf(&sc->arpcom.ac_if, "PHY read timed out\n");
 573                 return(0);
 574         }
 575
 576         return(0);
 577 }
 578
 579 static void
 580 bge_miibus_statchg(device_t dev)
 581 {
 582         struct bge_softc *sc;
 583         struct mii_data *mii;
 584
 585         sc = device_get_softc(dev);
 586         mii = device_get_softc(sc->bge_miibus);
 587
 588         BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
 589         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
 590                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
 591         } else {
 592                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
 593         }
 594
 595         if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
 596                 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 597         } else {
 598                 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
 599         }
 600 }
 601
 602 /*
 603  * Handle events that have triggered interrupts.
 604  */
 605 static void
 606 bge_handle_events(struct bge_softc *sc)
 607 {
 608 }
 609
 610 /*
 611  * Memory management for jumbo frames.
 612  */
 613 static int
 614 bge_alloc_jumbo_mem(struct bge_softc *sc)
 615 {
 616         struct bge_jslot *entry;
 617         caddr_t ptr;
 618         int i;
 619
 620         /* Grab a big chunk o' storage. */
 621         sc->bge_cdata.bge_jumbo_buf = contigmalloc(BGE_JMEM, M_DEVBUF,
 622                 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
 623
 624         if (sc->bge_cdata.bge_jumbo_buf == NULL) {
 625                 if_printf(&sc->arpcom.ac_if, "no memory for jumbo buffers!\n");
 626                 return(ENOBUFS);
 627         }
 628
 629         SLIST_INIT(&sc->bge_jfree_listhead);
 630
 631         /*
 632          * Now divide it up into 9K pieces and save the addresses
 633          * in an array. Note that we play an evil trick here by using
 634          * the first few bytes in the buffer to hold the the address
 635          * of the softc structure for this interface. This is because
 636          * bge_jfree() needs it, but it is called by the mbuf management
 637          * code which will not pass it to us explicitly.
 638          */
 639         ptr = sc->bge_cdata.bge_jumbo_buf;
 640         for (i = 0; i < BGE_JSLOTS; i++) {
 641                 entry = &sc->bge_cdata.bge_jslots[i];
 642                 entry->bge_sc = sc;
 643                 entry->bge_buf = ptr;
 644                 entry->bge_inuse = 0;
 645                 entry->bge_slot = i;
 646                 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link);
 647                 ptr += BGE_JLEN;
 648         }
 649
 650         return(0);
 651 }
 652
 653 static void
 654 bge_free_jumbo_mem(struct bge_softc *sc)
 655 {
 656         if (sc->bge_cdata.bge_jumbo_buf)
 657                 contigfree(sc->bge_cdata.bge_jumbo_buf, BGE_JMEM, M_DEVBUF);
 658 }
 659
 660 /*
 661  * Allocate a jumbo buffer.
 662  */
 663 static struct bge_jslot *
 664 bge_jalloc(struct bge_softc *sc)
 665 {
 666         struct bge_jslot *entry;
 667
 668         lwkt_serialize_enter(&sc->bge_jslot_serializer);
 669         entry = SLIST_FIRST(&sc->bge_jfree_listhead);
 670         if (entry) {
 671                 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jslot_link);
 672                 entry->bge_inuse = 1;
 673         } else {
 674                 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
 675         }
 676         lwkt_serialize_exit(&sc->bge_jslot_serializer);
 677         return(entry);
 678 }
 679
 680 /*
 681  * Adjust usage count on a jumbo buffer.
 682  */
 683 static void
 684 bge_jref(void *arg)
 685 {
 686         struct bge_jslot *entry = (struct bge_jslot *)arg;
 687         struct bge_softc *sc = entry->bge_sc;
 688
 689         if (sc == NULL)
 690                 panic("bge_jref: can't find softc pointer!");
 691
 692         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
 693                 panic("bge_jref: asked to reference buffer "
 694                     "that we don't manage!");
 695         } else if (entry->bge_inuse == 0) {
 696                 panic("bge_jref: buffer already free!");
 697         } else {
 698                 atomic_add_int(&entry->bge_inuse, 1);
 699         }
 700 }
 701
 702 /*
 703  * Release a jumbo buffer.
 704  */
 705 static void
 706 bge_jfree(void *arg)
 707 {
 708         struct bge_jslot *entry = (struct bge_jslot *)arg;
 709         struct bge_softc *sc = entry->bge_sc;
 710
 711         if (sc == NULL)
 712                 panic("bge_jfree: can't find softc pointer!");
 713
 714         if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
 715                 panic("bge_jfree: asked to free buffer that we don't manage!");
 716         } else if (entry->bge_inuse == 0) {
 717                 panic("bge_jfree: buffer already free!");
 718         } else {
 719                 /*
 720                  * Possible MP race to 0, use the serializer.  The atomic insn
 721                  * is still needed for races against bge_jref().
 722                  */
 723                 lwkt_serialize_enter(&sc->bge_jslot_serializer);
 724                 atomic_subtract_int(&entry->bge_inuse, 1);
 725                 if (entry->bge_inuse == 0) {
 726                         SLIST_INSERT_HEAD(&sc->bge_jfree_listhead,
 727                                           entry, jslot_link);
 728                 }
 729                 lwkt_serialize_exit(&sc->bge_jslot_serializer);
 730         }
 731 }
 732
 733
 734 /*
 735  * Intialize a standard receive ring descriptor.
 736  */
 737 static int
 738 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m)
 739 {
 740         struct mbuf *m_new = NULL;
 741         struct bge_rx_bd *r;
 742
 743         if (m == NULL) {
 744                 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
 745                 if (m_new == NULL)
 746                         return (ENOBUFS);
 747                 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 748         } else {
 749                 m_new = m;
 750                 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
 751                 m_new->m_data = m_new->m_ext.ext_buf;
 752         }
 753
 754         if (!sc->bge_rx_alignment_bug)
 755                 m_adj(m_new, ETHER_ALIGN);
 756         sc->bge_cdata.bge_rx_std_chain[i] = m_new;
 757         r = &sc->bge_rdata->bge_rx_std_ring[i];
 758         BGE_HOSTADDR(r->bge_addr, vtophys(mtod(m_new, caddr_t)));
 759         r->bge_flags = BGE_RXBDFLAG_END;
 760         r->bge_len = m_new->m_len;
 761         r->bge_idx = i;
 762
 763         return(0);
 764 }
 765
 766 /*
 767  * Initialize a jumbo receive ring descriptor. This allocates
 768  * a jumbo buffer from the pool managed internally by the driver.
 769  */
 770 static int
 771 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m)
 772 {
 773         struct mbuf *m_new = NULL;
 774         struct bge_rx_bd *r;
 775
 776         if (m == NULL) {
 777                 struct bge_jslot *buf;
 778
 779                 /* Allocate the mbuf. */
 780                 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
 781                 if (m_new == NULL)
 782                         return(ENOBUFS);
 783
 784                 /* Allocate the jumbo buffer */
 785                 buf = bge_jalloc(sc);
 786                 if (buf == NULL) {
 787                         m_freem(m_new);
 788                         if_printf(&sc->arpcom.ac_if, "jumbo allocation failed "
 789                             "-- packet dropped!\n");
 790                         return(ENOBUFS);
 791                 }
 792
 793                 /* Attach the buffer to the mbuf. */
 794                 m_new->m_ext.ext_arg = buf;
 795                 m_new->m_ext.ext_buf = buf->bge_buf;
 796                 m_new->m_ext.ext_free = bge_jfree;
 797                 m_new->m_ext.ext_ref = bge_jref;
 798                 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
 799
 800                 m_new->m_data = m_new->m_ext.ext_buf;
 801                 m_new->m_flags |= M_EXT;
 802                 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
 803         } else {
 804                 m_new = m;
 805                 m_new->m_data = m_new->m_ext.ext_buf;
 806                 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
 807         }
 808
 809         if (!sc->bge_rx_alignment_bug)
 810                 m_adj(m_new, ETHER_ALIGN);
 811         /* Set up the descriptor. */
 812         r = &sc->bge_rdata->bge_rx_jumbo_ring[i];
 813         sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new;
 814         BGE_HOSTADDR(r->bge_addr, vtophys(mtod(m_new, caddr_t)));
 815         r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
 816         r->bge_len = m_new->m_len;
 817         r->bge_idx = i;
 818
 819         return(0);
 820 }
 821
 822 /*
 823  * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
 824  * that's 1MB or memory, which is a lot. For now, we fill only the first
 825  * 256 ring entries and hope that our CPU is fast enough to keep up with
 826  * the NIC.
 827  */
 828 static int
 829 bge_init_rx_ring_std(struct bge_softc *sc)
 830 {
 831         int i;
 832
 833         for (i = 0; i < BGE_SSLOTS; i++) {
 834                 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS)
 835                         return(ENOBUFS);
 836         };
 837
 838         sc->bge_std = i - 1;
 839         CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
 840
 841         return(0);
 842 }
 843
 844 static void
 845 bge_free_rx_ring_std(struct bge_softc *sc)
 846 {
 847         int i;
 848
 849         for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
 850                 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
 851                         m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
 852                         sc->bge_cdata.bge_rx_std_chain[i] = NULL;
 853                 }
 854                 bzero(&sc->bge_rdata->bge_rx_std_ring[i],
 855                     sizeof(struct bge_rx_bd));
 856         }
 857 }
 858
 859 static int
 860 bge_init_rx_ring_jumbo(struct bge_softc *sc)
 861 {
 862         int i;
 863         struct bge_rcb *rcb;
 864
 865         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
 866                 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
 867                         return(ENOBUFS);
 868         };
 869
 870         sc->bge_jumbo = i - 1;
 871
 872         rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb;
 873         rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
 874         CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
 875
 876         CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
 877
 878         return(0);
 879 }
 880
 881 static void
 882 bge_free_rx_ring_jumbo(struct bge_softc *sc)
 883 {
 884         int i;
 885
 886         for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
 887                 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
 888                         m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
 889                         sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
 890                 }
 891                 bzero(&sc->bge_rdata->bge_rx_jumbo_ring[i],
 892                     sizeof(struct bge_rx_bd));
 893         }
 894 }
 895
 896 static void
 897 bge_free_tx_ring(struct bge_softc *sc)
 898 {
 899         int i;
 900
 901         if (sc->bge_rdata->bge_tx_ring == NULL)
 902                 return;
 903
 904         for (i = 0; i < BGE_TX_RING_CNT; i++) {
 905                 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
 906                         m_freem(sc->bge_cdata.bge_tx_chain[i]);
 907                         sc->bge_cdata.bge_tx_chain[i] = NULL;
 908                 }
 909                 bzero(&sc->bge_rdata->bge_tx_ring[i],
 910                     sizeof(struct bge_tx_bd));
 911         }
 912 }
 913
 914 static int
 915 bge_init_tx_ring(struct bge_softc *sc)
 916 {
 917         sc->bge_txcnt = 0;
 918         sc->bge_tx_saved_considx = 0;
 919
 920         CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0);
 921         /* 5700 b2 errata */
 922         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
 923                 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0);
 924
 925         CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
 926         /* 5700 b2 errata */
 927         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
 928                 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
 929
 930         return(0);
 931 }
 932
 933 static void
 934 bge_setmulti(struct bge_softc *sc)
 935 {
 936         struct ifnet *ifp;
 937         struct ifmultiaddr *ifma;
 938         uint32_t hashes[4] = { 0, 0, 0, 0 };
 939         int h, i;
 940
 941         ifp = &sc->arpcom.ac_if;
 942
 943         if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
 944                 for (i = 0; i < 4; i++)
 945                         CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
 946                 return;
 947         }
 948
 949         /* First, zot all the existing filters. */
 950         for (i = 0; i < 4; i++)
 951                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
 952
 953         /* Now program new ones. */
 954         LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
 955                 if (ifma->ifma_addr->sa_family != AF_LINK)
 956                         continue;
 957                 h = ether_crc32_le(
 958                     LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
 959                     ETHER_ADDR_LEN) & 0x7f;
 960                 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
 961         }
 962
 963         for (i = 0; i < 4; i++)
 964                 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
 965 }
 966
 967 /*
 968  * Do endian, PCI and DMA initialization. Also check the on-board ROM
 969  * self-test results.
 970  */
 971 static int
 972 bge_chipinit(struct bge_softc *sc)
 973 {
 974         int i;
 975         uint32_t dma_rw_ctl;
 976
 977         /* Set endianness before we access any non-PCI registers. */
 978 #if BYTE_ORDER == BIG_ENDIAN
 979         pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL,
 980             BGE_BIGENDIAN_INIT, 4);
 981 #else
 982         pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL,
 983             BGE_LITTLEENDIAN_INIT, 4);
 984 #endif
 985
 986         /*
 987          * Check the 'ROM failed' bit on the RX CPU to see if
 988          * self-tests passed.
 989          */
 990         if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) {
 991                 if_printf(&sc->arpcom.ac_if,
 992                           "RX CPU self-diagnostics failed!\n");
 993                 return(ENODEV);
 994         }
 995
 996         /* Clear the MAC control register */
 997         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
 998
 999         /*
1000          * Clear the MAC statistics block in the NIC's
1001          * internal memory.
1002          */
1003         for (i = BGE_STATS_BLOCK;
1004             i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
1005                 BGE_MEMWIN_WRITE(sc, i, 0);
1006
1007         for (i = BGE_STATUS_BLOCK;
1008             i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1009                 BGE_MEMWIN_WRITE(sc, i, 0);
1010
1011         /* Set up the PCI DMA control register. */
1012         if (sc->bge_pcie) {
1013                 /* PCI Express */
1014                 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1015                     (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1016                     (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1017         } else if (pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
1018                    BGE_PCISTATE_PCI_BUSMODE) {
1019                 /* Conventional PCI bus */
1020                 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1021                     (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1022                     (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1023                     (0x0F);
1024         } else {
1025                 /* PCI-X bus */
1026                 /*
1027                  * The 5704 uses a different encoding of read/write
1028                  * watermarks.
1029                  */
1030                 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1031                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1032                             (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1033                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1034                 else
1035                         dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1036                             (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1037                             (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1038                             (0x0F);
1039
1040                 /*
1041                  * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
1042                  * for hardware bugs.
1043                  */
1044                 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1045                     sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1046                         uint32_t tmp;
1047
1048                         tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
1049                         if (tmp == 0x6 || tmp == 0x7)
1050                                 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1051                 }
1052         }
1053
1054         if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1055             sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
1056             sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
1057             sc->bge_asicrev == BGE_ASICREV_BCM5750)
1058                 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1059         pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1060
1061         /*
1062          * Set up general mode register.
1063          */
1064         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_WORDSWAP_NONFRAME|
1065             BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA|
1066             BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1067             BGE_MODECTL_TX_NO_PHDR_CSUM|BGE_MODECTL_RX_NO_PHDR_CSUM);
1068
1069         /*
1070          * Disable memory write invalidate.  Apparently it is not supported
1071          * properly by these devices.
1072          */
1073         PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1074
1075         /* Set the timer prescaler (always 66Mhz) */
1076         CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1077
1078         return(0);
1079 }
1080
1081 static int
1082 bge_blockinit(struct bge_softc *sc)
1083 {
1084         struct bge_rcb *rcb;
1085         volatile struct bge_rcb *vrcb;
1086         int i;
1087
1088         /*
1089          * Initialize the memory window pointer register so that
1090          * we can access the first 32K of internal NIC RAM. This will
1091          * allow us to set up the TX send ring RCBs and the RX return
1092          * ring RCBs, plus other things which live in NIC memory.
1093          */
1094         CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1095
1096         /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1097
1098         if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1099             sc->bge_asicrev != BGE_ASICREV_BCM5750) {
1100                 /* Configure mbuf memory pool */
1101                 if (sc->bge_extram) {
1102                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR,
1103                             BGE_EXT_SSRAM);
1104                         if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1105                                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1106                         else
1107                                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1108                 } else {
1109                         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR,
1110                             BGE_BUFFPOOL_1);
1111                         if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1112                                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1113                         else
1114                                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1115                 }
1116
1117                 /* Configure DMA resource pool */
1118                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1119                     BGE_DMA_DESCRIPTORS);
1120                 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1121         }
1122
1123         /* Configure mbuf pool watermarks */
1124         if (sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
1125             sc->bge_asicrev == BGE_ASICREV_BCM5750) {
1126                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1127                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1128         } else {
1129                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1130                 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1131         }
1132         CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1133
1134         /* Configure DMA resource watermarks */
1135         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1136         CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1137
1138         /* Enable buffer manager */
1139         if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1140             sc->bge_asicrev != BGE_ASICREV_BCM5750) {
1141                 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1142                     BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
1143
1144                 /* Poll for buffer manager start indication */
1145                 for (i = 0; i < BGE_TIMEOUT; i++) {
1146                         if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1147                                 break;
1148                         DELAY(10);
1149                 }
1150
1151                 if (i == BGE_TIMEOUT) {
1152                         if_printf(&sc->arpcom.ac_if,
1153                                   "buffer manager failed to start\n");
1154                         return(ENXIO);
1155                 }
1156         }
1157
1158         /* Enable flow-through queues */
1159         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1160         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1161
1162         /* Wait until queue initialization is complete */
1163         for (i = 0; i < BGE_TIMEOUT; i++) {
1164                 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1165                         break;
1166                 DELAY(10);
1167         }
1168
1169         if (i == BGE_TIMEOUT) {
1170                 if_printf(&sc->arpcom.ac_if,
1171                           "flow-through queue init failed\n");
1172                 return(ENXIO);
1173         }
1174
1175         /* Initialize the standard RX ring control block */
1176         rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb;
1177         BGE_HOSTADDR(rcb->bge_hostaddr,
1178             vtophys(&sc->bge_rdata->bge_rx_std_ring));
1179         if (sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
1180             sc->bge_asicrev == BGE_ASICREV_BCM5750)
1181                 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1182         else
1183                 rcb->bge_maxlen_flags =
1184                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1185         if (sc->bge_extram)
1186                 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS;
1187         else
1188                 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1189         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1190         CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1191         CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1192         CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1193
1194         /*
1195          * Initialize the jumbo RX ring control block
1196          * We set the 'ring disabled' bit in the flags
1197          * field until we're actually ready to start
1198          * using this ring (i.e. once we set the MTU
1199          * high enough to require it).
1200          */
1201         if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1202             sc->bge_asicrev != BGE_ASICREV_BCM5750) {
1203                 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb;
1204                 BGE_HOSTADDR(rcb->bge_hostaddr,
1205                     vtophys(&sc->bge_rdata->bge_rx_jumbo_ring));
1206                 rcb->bge_maxlen_flags =
1207                     BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
1208                     BGE_RCB_FLAG_RING_DISABLED);
1209                 if (sc->bge_extram)
1210                         rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS;
1211                 else
1212                         rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1213                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1214                     rcb->bge_hostaddr.bge_addr_hi);
1215                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1216                     rcb->bge_hostaddr.bge_addr_lo);
1217                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1218                     rcb->bge_maxlen_flags);
1219                 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1220
1221                 /* Set up dummy disabled mini ring RCB */
1222                 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb;
1223                 rcb->bge_maxlen_flags =
1224                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1225                 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1226                     rcb->bge_maxlen_flags);
1227         }
1228
1229         /*
1230          * Set the BD ring replentish thresholds. The recommended
1231          * values are 1/8th the number of descriptors allocated to
1232          * each ring.
1233          */
1234         CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8);
1235         CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
1236
1237         /*
1238          * Disable all unused send rings by setting the 'ring disabled'
1239          * bit in the flags field of all the TX send ring control blocks.
1240          * These are located in NIC memory.
1241          */
1242         vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1243             BGE_SEND_RING_RCB);
1244         for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1245                 vrcb->bge_maxlen_flags =
1246                     BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1247                 vrcb->bge_nicaddr = 0;
1248                 vrcb++;
1249         }
1250
1251         /* Configure TX RCB 0 (we use only the first ring) */
1252         vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1253             BGE_SEND_RING_RCB);
1254         vrcb->bge_hostaddr.bge_addr_hi = 0;
1255         BGE_HOSTADDR(vrcb->bge_hostaddr, vtophys(&sc->bge_rdata->bge_tx_ring));
1256         vrcb->bge_nicaddr = BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT);
1257         if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1258             sc->bge_asicrev != BGE_ASICREV_BCM5750)
1259                 vrcb->bge_maxlen_flags =
1260                     BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0);
1261
1262         /* Disable all unused RX return rings */
1263         vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1264             BGE_RX_RETURN_RING_RCB);
1265         for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1266                 vrcb->bge_hostaddr.bge_addr_hi = 0;
1267                 vrcb->bge_hostaddr.bge_addr_lo = 0;
1268                 vrcb->bge_maxlen_flags =
1269                     BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
1270                     BGE_RCB_FLAG_RING_DISABLED);
1271                 vrcb->bge_nicaddr = 0;
1272                 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO +
1273                     (i * (sizeof(uint64_t))), 0);
1274                 vrcb++;
1275         }
1276
1277         /* Initialize RX ring indexes */
1278         CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1279         CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1280         CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1281
1282         /*
1283          * Set up RX return ring 0
1284          * Note that the NIC address for RX return rings is 0x00000000.
1285          * The return rings live entirely within the host, so the
1286          * nicaddr field in the RCB isn't used.
1287          */
1288         vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1289             BGE_RX_RETURN_RING_RCB);
1290         vrcb->bge_hostaddr.bge_addr_hi = 0;
1291         BGE_HOSTADDR(vrcb->bge_hostaddr,
1292             vtophys(&sc->bge_rdata->bge_rx_return_ring));
1293         vrcb->bge_nicaddr = 0x00000000;
1294         vrcb->bge_maxlen_flags =
1295             BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0);
1296
1297         /* Set random backoff seed for TX */
1298         CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1299             sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1300             sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1301             sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1302             BGE_TX_BACKOFF_SEED_MASK);
1303
1304         /* Set inter-packet gap */
1305         CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1306
1307         /*
1308          * Specify which ring to use for packets that don't match
1309          * any RX rules.
1310          */
1311         CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1312
1313         /*
1314          * Configure number of RX lists. One interrupt distribution
1315          * list, sixteen active lists, one bad frames class.
1316          */
1317         CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1318
1319         /* Inialize RX list placement stats mask. */
1320         CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1321         CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1322
1323         /* Disable host coalescing until we get it set up */
1324         CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1325
1326         /* Poll to make sure it's shut down. */
1327         for (i = 0; i < BGE_TIMEOUT; i++) {
1328                 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1329                         break;
1330                 DELAY(10);
1331         }
1332
1333         if (i == BGE_TIMEOUT) {
1334                 if_printf(&sc->arpcom.ac_if,
1335                           "host coalescing engine failed to idle\n");
1336                 return(ENXIO);
1337         }
1338
1339         /* Set up host coalescing defaults */
1340         CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1341         CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1342         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1343         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1344         if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1345             sc->bge_asicrev != BGE_ASICREV_BCM5750) {
1346                 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1347                 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1348         }
1349         CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0);
1350         CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0);
1351
1352         /* Set up address of statistics block */
1353         if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1354             sc->bge_asicrev != BGE_ASICREV_BCM5750) {
1355                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 0);
1356                 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1357                     vtophys(&sc->bge_rdata->bge_info.bge_stats));
1358
1359                 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1360                 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1361                 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1362         }
1363
1364         /* Set up address of status block */
1365         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 0);
1366         CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1367             vtophys(&sc->bge_rdata->bge_status_block));
1368
1369         sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0;
1370         sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0;
1371
1372         /* Turn on host coalescing state machine */
1373         CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
1374
1375         /* Turn on RX BD completion state machine and enable attentions */
1376         CSR_WRITE_4(sc, BGE_RBDC_MODE,
1377             BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1378
1379         /* Turn on RX list placement state machine */
1380         CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1381
1382         /* Turn on RX list selector state machine. */
1383         if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1384             sc->bge_asicrev != BGE_ASICREV_BCM5750)
1385                 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1386
1387         /* Turn on DMA, clear stats */
1388         CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB|
1389             BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR|
1390             BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB|
1391             BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB|
1392             (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII));
1393
1394         /* Set misc. local control, enable interrupts on attentions */
1395         CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1396
1397 #ifdef notdef
1398         /* Assert GPIO pins for PHY reset */
1399         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1400             BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1401         BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1402             BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1403 #endif
1404
1405         /* Turn on DMA completion state machine */
1406         if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1407             sc->bge_asicrev != BGE_ASICREV_BCM5750)
1408                 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1409
1410         /* Turn on write DMA state machine */
1411         CSR_WRITE_4(sc, BGE_WDMA_MODE,
1412             BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS);
1413
1414         /* Turn on read DMA state machine */
1415         CSR_WRITE_4(sc, BGE_RDMA_MODE,
1416             BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS);
1417
1418         /* Turn on RX data completion state machine */
1419         CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1420
1421         /* Turn on RX BD initiator state machine */
1422         CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1423
1424         /* Turn on RX data and RX BD initiator state machine */
1425         CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1426
1427         /* Turn on Mbuf cluster free state machine */
1428         if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1429             sc->bge_asicrev != BGE_ASICREV_BCM5750)
1430                 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1431
1432         /* Turn on send BD completion state machine */
1433         CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1434
1435         /* Turn on send data completion state machine */
1436         CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
1437
1438         /* Turn on send data initiator state machine */
1439         CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1440
1441         /* Turn on send BD initiator state machine */
1442         CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1443
1444         /* Turn on send BD selector state machine */
1445         CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1446
1447         CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1448         CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1449             BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1450
1451         /* ack/clear link change events */
1452         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1453             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1454             BGE_MACSTAT_LINK_CHANGED);
1455
1456         /* Enable PHY auto polling (for MII/GMII only) */
1457         if (sc->bge_tbi) {
1458                 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1459         } else {
1460                 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16);
1461                 if (sc->bge_asicrev == BGE_ASICREV_BCM5700)
1462                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1463                             BGE_EVTENB_MI_INTERRUPT);
1464         }
1465
1466         /* Enable link state change attentions. */
1467         BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1468
1469         return(0);
1470 }
1471
1472 /*
1473  * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1474  * against our list and return its name if we find a match. Note
1475  * that since the Broadcom controller contains VPD support, we
1476  * can get the device name string from the controller itself instead
1477  * of the compiled-in string. This is a little slow, but it guarantees
1478  * we'll always announce the right product name.
1479  */
1480 static int
1481 bge_probe(device_t dev)
1482 {
1483         struct bge_softc *sc;
1484         struct bge_type *t;
1485         char *descbuf;
1486         uint16_t product, vendor;
1487
1488         product = pci_get_device(dev);
1489         vendor = pci_get_vendor(dev);
1490
1491         for (t = bge_devs; t->bge_name != NULL; t++) {
1492                 if (vendor == t->bge_vid && product == t->bge_did)
1493                         break;
1494         }
1495
1496         if (t->bge_name == NULL)
1497                 return(ENXIO);
1498
1499         sc = device_get_softc(dev);
1500 #ifdef notdef
1501         sc->bge_dev = dev;
1502
1503         bge_vpd_read(sc);
1504         device_set_desc(dev, sc->bge_vpd_prodname);
1505 #endif
1506         descbuf = kmalloc(BGE_DEVDESC_MAX, M_TEMP, M_WAITOK);
1507         ksnprintf(descbuf, BGE_DEVDESC_MAX, "%s, ASIC rev. %#04x", t->bge_name,
1508             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 16);
1509         device_set_desc_copy(dev, descbuf);
1510         if (pci_get_subvendor(dev) == PCI_VENDOR_DELL)
1511                 sc->bge_no_3_led = 1;
1512         kfree(descbuf, M_TEMP);
1513         return(0);
1514 }
1515
1516 static int
1517 bge_attach(device_t dev)
1518 {
1519         struct ifnet *ifp;
1520         struct bge_softc *sc;
1521         uint32_t hwcfg = 0;
1522         uint32_t mac_addr = 0;
1523         int error = 0, rid;
1524         uint8_t ether_addr[ETHER_ADDR_LEN];
1525
1526         sc = device_get_softc(dev);
1527         sc->bge_dev = dev;
1528         callout_init(&sc->bge_stat_timer);
1529         lwkt_serialize_init(&sc->bge_jslot_serializer);
1530
1531         /*
1532          * Map control/status registers.
1533          */
1534         pci_enable_busmaster(dev);
1535
1536         rid = BGE_PCI_BAR0;
1537         sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1538             RF_ACTIVE);
1539
1540         if (sc->bge_res == NULL) {
1541                 device_printf(dev, "couldn't map memory\n");
1542                 error = ENXIO;
1543                 return(error);
1544         }
1545
1546         sc->bge_btag = rman_get_bustag(sc->bge_res);
1547         sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
1548         sc->bge_vhandle = (vm_offset_t)rman_get_virtual(sc->bge_res);
1549
1550         /* Allocate interrupt */
1551         rid = 0;
1552
1553         sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1554             RF_SHAREABLE | RF_ACTIVE);
1555
1556         if (sc->bge_irq == NULL) {
1557                 device_printf(dev, "couldn't map interrupt\n");
1558                 error = ENXIO;
1559                 goto fail;
1560         }
1561
1562         /* Save ASIC rev. */
1563         sc->bge_chipid =
1564             pci_read_config(dev, BGE_PCI_MISC_CTL, 4) &
1565             BGE_PCIMISCCTL_ASICREV;
1566         sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
1567         sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
1568
1569         /*
1570          * Treat the 5714 like the 5750 until we have more info
1571          * on this chip.
1572          */
1573         if (sc->bge_asicrev == BGE_ASICREV_BCM5714)
1574                 sc->bge_asicrev = BGE_ASICREV_BCM5750;
1575
1576         /*
1577          * XXX: Broadcom Linux driver.  Not in specs or eratta.
1578          * PCI-Express?
1579          */
1580         if (sc->bge_asicrev == BGE_ASICREV_BCM5750) {
1581                 uint32_t v;
1582
1583                 v = pci_read_config(dev, BGE_PCI_MSI_CAPID, 4);
1584                 if (((v >> 8) & 0xff) == BGE_PCIE_MSI_CAPID) {
1585                         v = pci_read_config(dev, BGE_PCIE_MSI_CAPID, 4);
1586                         if ((v & 0xff) == BGE_PCIE_MSI_CAPID_VAL)
1587                                 sc->bge_pcie = 1;
1588                 }
1589         }
1590
1591         ifp = &sc->arpcom.ac_if;
1592         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1593
1594         /* Try to reset the chip. */
1595         bge_reset(sc);
1596
1597         if (bge_chipinit(sc)) {
1598                 device_printf(dev, "chip initialization failed\n");
1599                 error = ENXIO;
1600                 goto fail;
1601         }
1602
1603         /*
1604          * Get station address from the EEPROM.
1605          */
1606         mac_addr = bge_readmem_ind(sc, 0x0c14);
1607         if ((mac_addr >> 16) == 0x484b) {
1608                 ether_addr[0] = (uint8_t)(mac_addr >> 8);
1609                 ether_addr[1] = (uint8_t)mac_addr;
1610                 mac_addr = bge_readmem_ind(sc, 0x0c18);
1611                 ether_addr[2] = (uint8_t)(mac_addr >> 24);
1612                 ether_addr[3] = (uint8_t)(mac_addr >> 16);
1613                 ether_addr[4] = (uint8_t)(mac_addr >> 8);
1614                 ether_addr[5] = (uint8_t)mac_addr;
1615         } else if (bge_read_eeprom(sc, ether_addr,
1616             BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
1617                 device_printf(dev, "failed to read station address\n");
1618                 error = ENXIO;
1619                 goto fail;
1620         }
1621
1622         /* Allocate the general information block and ring buffers. */
1623         sc->bge_rdata = contigmalloc(sizeof(struct bge_ring_data), M_DEVBUF,
1624             M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
1625
1626         if (sc->bge_rdata == NULL) {
1627                 error = ENXIO;
1628                 device_printf(dev, "no memory for list buffers!\n");
1629                 goto fail;
1630         }
1631
1632         bzero(sc->bge_rdata, sizeof(struct bge_ring_data));
1633
1634         /*
1635          * Try to allocate memory for jumbo buffers.
1636          * The 5705/5750 does not appear to support jumbo frames.
1637          */
1638         if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1639             sc->bge_asicrev != BGE_ASICREV_BCM5750) {
1640                 if (bge_alloc_jumbo_mem(sc)) {
1641                         device_printf(dev, "jumbo buffer allocation failed\n");
1642                         error = ENXIO;
1643                         goto fail;
1644                 }
1645         }
1646
1647         /* Set default tuneable values. */
1648         sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
1649         sc->bge_rx_coal_ticks = 150;
1650         sc->bge_tx_coal_ticks = 150;
1651         sc->bge_rx_max_coal_bds = 64;
1652         sc->bge_tx_max_coal_bds = 128;
1653
1654         /* 5705/5750 limits RX return ring to 512 entries. */
1655         if (sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
1656             sc->bge_asicrev == BGE_ASICREV_BCM5750)
1657                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
1658         else
1659                 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
1660
1661         /* Set up ifnet structure */
1662         ifp->if_softc = sc;
1663         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1664         ifp->if_ioctl = bge_ioctl;
1665         ifp->if_start = bge_start;
1666         ifp->if_watchdog = bge_watchdog;
1667         ifp->if_init = bge_init;
1668         ifp->if_mtu = ETHERMTU;
1669         ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
1670         ifq_set_ready(&ifp->if_snd);
1671         ifp->if_hwassist = BGE_CSUM_FEATURES;
1672         ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING |
1673             IFCAP_VLAN_MTU;
1674         ifp->if_capenable = ifp->if_capabilities;
1675
1676         /*
1677          * Figure out what sort of media we have by checking the
1678          * hardware config word in the first 32k of NIC internal memory,
1679          * or fall back to examining the EEPROM if necessary.
1680          * Note: on some BCM5700 cards, this value appears to be unset.
1681          * If that's the case, we have to rely on identifying the NIC
1682          * by its PCI subsystem ID, as we do below for the SysKonnect
1683          * SK-9D41.
1684          */
1685         if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
1686                 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
1687         else {
1688                 bge_read_eeprom(sc, (caddr_t)&hwcfg,
1689                                 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg));
1690                 hwcfg = ntohl(hwcfg);
1691         }
1692
1693         if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
1694                 sc->bge_tbi = 1;
1695
1696         /* The SysKonnect SK-9D41 is a 1000baseSX card. */
1697         if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41)
1698                 sc->bge_tbi = 1;
1699
1700         if (sc->bge_tbi) {
1701                 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
1702                     bge_ifmedia_upd, bge_ifmedia_sts);
1703                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
1704                 ifmedia_add(&sc->bge_ifmedia,
1705                     IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
1706                 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
1707                 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
1708                 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
1709         } else {
1710                 /*
1711                  * Do transceiver setup.
1712                  */
1713                 if (mii_phy_probe(dev, &sc->bge_miibus,
1714                     bge_ifmedia_upd, bge_ifmedia_sts)) {
1715                         device_printf(dev, "MII without any PHY!\n");
1716                         error = ENXIO;
1717                         goto fail;
1718                 }
1719         }
1720
1721         /*
1722          * When using the BCM5701 in PCI-X mode, data corruption has
1723          * been observed in the first few bytes of some received packets.
1724          * Aligning the packet buffer in memory eliminates the corruption.
1725          * Unfortunately, this misaligns the packet payloads.  On platforms
1726          * which do not support unaligned accesses, we will realign the
1727          * payloads by copying the received packets.
1728          */
1729         switch (sc->bge_chipid) {
1730         case BGE_CHIPID_BCM5701_A0:
1731         case BGE_CHIPID_BCM5701_B0:
1732         case BGE_CHIPID_BCM5701_B2:
1733         case BGE_CHIPID_BCM5701_B5:
1734                 /* If in PCI-X mode, work around the alignment bug. */
1735                 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) &
1736                     (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) ==
1737                     BGE_PCISTATE_PCI_BUSSPEED)
1738                         sc->bge_rx_alignment_bug = 1;
1739                 break;
1740         }
1741
1742         /*
1743          * Call MI attach routine.
1744          */
1745         ether_ifattach(ifp, ether_addr, NULL);
1746
1747         error = bus_setup_intr(dev, sc->bge_irq, INTR_NETSAFE,
1748                                bge_intr, sc, &sc->bge_intrhand,
1749                                ifp->if_serializer);
1750         if (error) {
1751                 ether_ifdetach(ifp);
1752                 device_printf(dev, "couldn't set up irq\n");
1753                 goto fail;
1754         }
1755
1756         return(0);
1757
1758 fail:
1759         bge_detach(dev);
1760
1761         return(error);
1762 }
1763
1764 static int
1765 bge_detach(device_t dev)
1766 {
1767         struct bge_softc *sc = device_get_softc(dev);
1768         struct ifnet *ifp = &sc->arpcom.ac_if;
1769
1770         if (device_is_attached(dev)) {
1771                 lwkt_serialize_enter(ifp->if_serializer);
1772                 bge_stop(sc);
1773                 bge_reset(sc);
1774                 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
1775                 lwkt_serialize_exit(ifp->if_serializer);
1776
1777                 ether_ifdetach(ifp);
1778         }
1779         if (sc->bge_tbi)
1780                 ifmedia_removeall(&sc->bge_ifmedia);
1781         if (sc->bge_miibus)
1782                 device_delete_child(dev, sc->bge_miibus);
1783         bus_generic_detach(dev);
1784
1785         bge_release_resources(sc);
1786
1787         if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1788             sc->bge_asicrev != BGE_ASICREV_BCM5750)
1789                 bge_free_jumbo_mem(sc);
1790
1791         return(0);
1792 }
1793
1794 static void
1795 bge_release_resources(struct bge_softc *sc)
1796 {
1797         device_t dev;
1798
1799         dev = sc->bge_dev;
1800
1801         if (sc->bge_vpd_prodname != NULL)
1802                 kfree(sc->bge_vpd_prodname, M_DEVBUF);
1803
1804         if (sc->bge_vpd_readonly != NULL)
1805                 kfree(sc->bge_vpd_readonly, M_DEVBUF);
1806
1807         if (sc->bge_irq != NULL)
1808                 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq);
1809
1810         if (sc->bge_res != NULL)
1811                 bus_release_resource(dev, SYS_RES_MEMORY,
1812                     BGE_PCI_BAR0, sc->bge_res);
1813
1814         if (sc->bge_rdata != NULL)
1815                 contigfree(sc->bge_rdata, sizeof(struct bge_ring_data),
1816                            M_DEVBUF);
1817
1818         return;
1819 }
1820
1821 static void
1822 bge_reset(struct bge_softc *sc)
1823 {
1824         device_t dev;
1825         uint32_t cachesize, command, pcistate, reset;
1826         int i, val = 0;
1827
1828         dev = sc->bge_dev;
1829
1830         /* Save some important PCI state. */
1831         cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
1832         command = pci_read_config(dev, BGE_PCI_CMD, 4);
1833         pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
1834
1835         pci_write_config(dev, BGE_PCI_MISC_CTL,
1836             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
1837             BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4);
1838
1839         reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
1840
1841         /* XXX: Broadcom Linux driver. */
1842         if (sc->bge_pcie) {
1843                 if (CSR_READ_4(sc, 0x7e2c) == 0x60)     /* PCIE 1.0 */
1844                         CSR_WRITE_4(sc, 0x7e2c, 0x20);
1845                 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
1846                         /* Prevent PCIE link training during global reset */
1847                         CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
1848                         reset |= (1<<29);
1849                 }
1850         }
1851
1852         /* Issue global reset */
1853         bge_writereg_ind(sc, BGE_MISC_CFG, reset);
1854
1855         DELAY(1000);
1856
1857         /* XXX: Broadcom Linux driver. */
1858         if (sc->bge_pcie) {
1859                 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
1860                         uint32_t v;
1861
1862                         DELAY(500000); /* wait for link training to complete */
1863                         v = pci_read_config(dev, 0xc4, 4);
1864                         pci_write_config(dev, 0xc4, v | (1<<15), 4);
1865                 }
1866                 /* Set PCIE max payload size and clear error status. */
1867                 pci_write_config(dev, 0xd8, 0xf5000, 4);
1868         }
1869
1870         /* Reset some of the PCI state that got zapped by reset */
1871         pci_write_config(dev, BGE_PCI_MISC_CTL,
1872             BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
1873             BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4);
1874         pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
1875         pci_write_config(dev, BGE_PCI_CMD, command, 4);
1876         bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1));
1877
1878         /* Enable memory arbiter. */
1879         if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
1880                 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
1881
1882         /*
1883          * Prevent PXE restart: write a magic number to the
1884          * general communications memory at 0xB50.
1885          */
1886         bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
1887         /*
1888          * Poll the value location we just wrote until
1889          * we see the 1's complement of the magic number.
1890          * This indicates that the firmware initialization
1891          * is complete.
1892          */
1893         for (i = 0; i < BGE_TIMEOUT; i++) {
1894                 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
1895                 if (val == ~BGE_MAGIC_NUMBER)
1896                         break;
1897                 DELAY(10);
1898         }
1899
1900         if (i == BGE_TIMEOUT) {
1901                 if_printf(&sc->arpcom.ac_if, "firmware handshake timed out\n");
1902                 return;
1903         }
1904
1905         /*
1906          * XXX Wait for the value of the PCISTATE register to
1907          * return to its original pre-reset state. This is a
1908          * fairly good indicator of reset completion. If we don't
1909          * wait for the reset to fully complete, trying to read
1910          * from the device's non-PCI registers may yield garbage
1911          * results.
1912          */
1913         for (i = 0; i < BGE_TIMEOUT; i++) {
1914                 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
1915                         break;
1916                 DELAY(10);
1917         }
1918
1919         /* Fix up byte swapping */
1920         CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_BYTESWAP_NONFRAME|
1921             BGE_MODECTL_BYTESWAP_DATA);
1922
1923         CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1924
1925         /*
1926          * The 5704 in TBI mode apparently needs some special
1927          * adjustment to insure the SERDES drive level is set
1928          * to 1.2V.
1929          */
1930         if (sc->bge_asicrev == BGE_ASICREV_BCM5704 && sc->bge_tbi) {
1931                 uint32_t serdescfg;
1932
1933                 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
1934                 serdescfg = (serdescfg & ~0xFFF) | 0x880;
1935                 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
1936         }
1937
1938         /* XXX: Broadcom Linux driver. */
1939         if (sc->bge_pcie && sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
1940                 uint32_t v;
1941
1942                 v = CSR_READ_4(sc, 0x7c00);
1943                 CSR_WRITE_4(sc, 0x7c00, v | (1<<25));
1944         }
1945
1946         DELAY(10000);
1947 }
1948
1949 /*
1950  * Frame reception handling. This is called if there's a frame
1951  * on the receive return list.
1952  *
1953  * Note: we have to be able to handle two possibilities here:
1954  * 1) the frame is from the jumbo recieve ring
1955  * 2) the frame is from the standard receive ring
1956  */
1957
1958 static void
1959 bge_rxeof(struct bge_softc *sc)
1960 {
1961         struct ifnet *ifp;
1962         int stdcnt = 0, jumbocnt = 0;
1963
1964         ifp = &sc->arpcom.ac_if;
1965
1966         while(sc->bge_rx_saved_considx !=
1967             sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) {
1968                 struct bge_rx_bd        *cur_rx;
1969                 uint32_t                rxidx;
1970                 struct mbuf             *m = NULL;
1971                 uint16_t                vlan_tag = 0;
1972                 int                     have_tag = 0;
1973
1974                 cur_rx =
1975             &sc->bge_rdata->bge_rx_return_ring[sc->bge_rx_saved_considx];
1976
1977                 rxidx = cur_rx->bge_idx;
1978                 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
1979
1980                 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
1981                         have_tag = 1;
1982                         vlan_tag = cur_rx->bge_vlan_tag;
1983                 }
1984
1985                 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
1986                         BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
1987                         m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
1988                         sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL;
1989                         jumbocnt++;
1990                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
1991                                 ifp->if_ierrors++;
1992                                 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
1993                                 continue;
1994                         }
1995                         if (bge_newbuf_jumbo(sc,
1996                             sc->bge_jumbo, NULL) == ENOBUFS) {
1997                                 ifp->if_ierrors++;
1998                                 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
1999                                 continue;
2000                         }
2001                 } else {
2002                         BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
2003                         m = sc->bge_cdata.bge_rx_std_chain[rxidx];
2004                         sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL;
2005                         stdcnt++;
2006                         if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2007                                 ifp->if_ierrors++;
2008                                 bge_newbuf_std(sc, sc->bge_std, m);
2009                                 continue;
2010                         }
2011                         if (bge_newbuf_std(sc, sc->bge_std,
2012                             NULL) == ENOBUFS) {
2013                                 ifp->if_ierrors++;
2014                                 bge_newbuf_std(sc, sc->bge_std, m);
2015                                 continue;
2016                         }
2017                 }
2018
2019                 ifp->if_ipackets++;
2020 #ifndef __i386__
2021                 /*
2022                  * The i386 allows unaligned accesses, but for other
2023                  * platforms we must make sure the payload is aligned.
2024                  */
2025                 if (sc->bge_rx_alignment_bug) {
2026                         bcopy(m->m_data, m->m_data + ETHER_ALIGN,
2027                             cur_rx->bge_len);
2028                         m->m_data += ETHER_ALIGN;
2029                 }
2030 #endif
2031                 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2032                 m->m_pkthdr.rcvif = ifp;
2033
2034 #if 0 /* currently broken for some packets, possibly related to TCP options */
2035                 if (ifp->if_hwassist) {
2036                         m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2037                         if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
2038                                 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2039                         if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
2040                                 m->m_pkthdr.csum_data =
2041                                     cur_rx->bge_tcp_udp_csum;
2042                                 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID;
2043                         }
2044                 }
2045 #endif
2046
2047                 /*
2048                  * If we received a packet with a vlan tag, pass it
2049                  * to vlan_input() instead of ether_input().
2050                  */
2051                 if (have_tag) {
2052                         VLAN_INPUT_TAG(m, vlan_tag);
2053                         have_tag = vlan_tag = 0;
2054                 } else {
2055                         ifp->if_input(ifp, m);
2056                 }
2057         }
2058
2059         CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
2060         if (stdcnt)
2061                 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
2062         if (jumbocnt)
2063                 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
2064 }
2065
2066 static void
2067 bge_txeof(struct bge_softc *sc)
2068 {
2069         struct bge_tx_bd *cur_tx = NULL;
2070         struct ifnet *ifp;
2071
2072         ifp = &sc->arpcom.ac_if;
2073
2074         /*
2075          * Go through our tx ring and free mbufs for those
2076          * frames that have been sent.
2077          */
2078         while (sc->bge_tx_saved_considx !=
2079             sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) {
2080                 uint32_t                idx = 0;
2081
2082                 idx = sc->bge_tx_saved_considx;
2083                 cur_tx = &sc->bge_rdata->bge_tx_ring[idx];
2084                 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
2085                         ifp->if_opackets++;
2086                 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
2087                         m_freem(sc->bge_cdata.bge_tx_chain[idx]);
2088                         sc->bge_cdata.bge_tx_chain[idx] = NULL;
2089                 }
2090                 sc->bge_txcnt--;
2091                 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
2092                 ifp->if_timer = 0;
2093         }
2094
2095         if (cur_tx != NULL)
2096                 ifp->if_flags &= ~IFF_OACTIVE;
2097 }
2098
2099 static void
2100 bge_intr(void *xsc)
2101 {
2102         struct bge_softc *sc = xsc;
2103         struct ifnet *ifp = &sc->arpcom.ac_if;
2104         uint32_t status, statusword, mimode;
2105
2106         /* XXX */
2107         statusword = loadandclear(&sc->bge_rdata->bge_status_block.bge_status);
2108
2109 #ifdef notdef
2110         /* Avoid this for now -- checking this register is expensive. */
2111         /* Make sure this is really our interrupt. */
2112         if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE))
2113                 return;
2114 #endif
2115         /* Ack interrupt and stop others from occuring. */
2116         CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
2117
2118         /*
2119          * Process link state changes.
2120          * Grrr. The link status word in the status block does
2121          * not work correctly on the BCM5700 rev AX and BX chips,
2122          * according to all available information. Hence, we have
2123          * to enable MII interrupts in order to properly obtain
2124          * async link changes. Unfortunately, this also means that
2125          * we have to read the MAC status register to detect link
2126          * changes, thereby adding an additional register access to
2127          * the interrupt handler.
2128          */
2129
2130         if (sc->bge_asicrev == BGE_ASICREV_BCM5700) {
2131                 status = CSR_READ_4(sc, BGE_MAC_STS);
2132                 if (status & BGE_MACSTAT_MI_INTERRUPT) {
2133                         sc->bge_link = 0;
2134                         callout_stop(&sc->bge_stat_timer);
2135                         bge_tick_serialized(sc);
2136                         /* Clear the interrupt */
2137                         CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
2138                             BGE_EVTENB_MI_INTERRUPT);
2139                         bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
2140                         bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR,
2141                             BRGPHY_INTRS);
2142                 }
2143         } else {
2144                 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED) {
2145                         /*
2146                          * Sometimes PCS encoding errors are detected in
2147                          * TBI mode (on fiber NICs), and for some reason
2148                          * the chip will signal them as link changes.
2149                          * If we get a link change event, but the 'PCS
2150                          * encoding error' bit in the MAC status register
2151                          * is set, don't bother doing a link check.
2152                          * This avoids spurious "gigabit link up" messages
2153                          * that sometimes appear on fiber NICs during
2154                          * periods of heavy traffic. (There should be no
2155                          * effect on copper NICs.)
2156                          *
2157                          * If we do have a copper NIC (bge_tbi == 0) then
2158                          * check that the AUTOPOLL bit is set before
2159                          * processing the event as a real link change.
2160                          * Turning AUTOPOLL on and off in the MII read/write
2161                          * functions will often trigger a link status
2162                          * interrupt for no reason.
2163                          */
2164                         status = CSR_READ_4(sc, BGE_MAC_STS);
2165                         mimode = CSR_READ_4(sc, BGE_MI_MODE);
2166                         if (!(status & (BGE_MACSTAT_PORT_DECODE_ERROR |
2167                                         BGE_MACSTAT_MI_COMPLETE)) &&
2168                             (!sc->bge_tbi && (mimode & BGE_MIMODE_AUTOPOLL))) {
2169                                 sc->bge_link = 0;
2170                                 callout_stop(&sc->bge_stat_timer);
2171                                 bge_tick_serialized(sc);
2172                         }
2173                         sc->bge_link = 0;
2174                         callout_stop(&sc->bge_stat_timer);
2175                         bge_tick_serialized(sc);
2176                         /* Clear the interrupt */
2177                         CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
2178                             BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
2179                             BGE_MACSTAT_LINK_CHANGED);
2180
2181                         /* Force flush the status block cached by PCI bridge */
2182                         CSR_READ_4(sc, BGE_MBX_IRQ0_LO);
2183                 }
2184         }
2185
2186         if (ifp->if_flags & IFF_RUNNING) {
2187                 /* Check RX return ring producer/consumer */
2188                 bge_rxeof(sc);
2189
2190                 /* Check TX ring producer/consumer */
2191                 bge_txeof(sc);
2192         }
2193
2194         bge_handle_events(sc);
2195
2196         /* Re-enable interrupts. */
2197         CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
2198
2199         if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd))
2200                 (*ifp->if_start)(ifp);
2201 }
2202
2203 static void
2204 bge_tick(void *xsc)
2205 {
2206         struct bge_softc *sc = xsc;
2207         struct ifnet *ifp = &sc->arpcom.ac_if;
2208
2209         lwkt_serialize_enter(ifp->if_serializer);
2210         bge_tick_serialized(xsc);
2211         lwkt_serialize_exit(ifp->if_serializer);
2212 }
2213
2214 static void
2215 bge_tick_serialized(void *xsc)
2216 {
2217         struct bge_softc *sc = xsc;
2218         struct ifnet *ifp = &sc->arpcom.ac_if;
2219         struct mii_data *mii = NULL;
2220         struct ifmedia *ifm = NULL;
2221
2222         if (sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
2223             sc->bge_asicrev == BGE_ASICREV_BCM5750)
2224                 bge_stats_update_regs(sc);
2225         else
2226                 bge_stats_update(sc);
2227
2228         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2229
2230         if (sc->bge_link) {
2231                 return;
2232         }
2233
2234         if (sc->bge_tbi) {
2235                 ifm = &sc->bge_ifmedia;
2236                 if (CSR_READ_4(sc, BGE_MAC_STS) &
2237                     BGE_MACSTAT_TBI_PCS_SYNCHED) {
2238                         sc->bge_link++;
2239                         if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
2240                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
2241                                            BGE_MACMODE_TBI_SEND_CFGS);
2242                         }
2243                         CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
2244                         if_printf(ifp, "gigabit link up\n");
2245                         if (!ifq_is_empty(&ifp->if_snd))
2246                                 (*ifp->if_start)(ifp);
2247                 }
2248                 return;
2249         }
2250
2251         mii = device_get_softc(sc->bge_miibus);
2252         mii_tick(mii);
2253
2254         if (!sc->bge_link) {
2255                 mii_pollstat(mii);
2256                 if (mii->mii_media_status & IFM_ACTIVE &&
2257                     IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
2258                         sc->bge_link++;
2259                         if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
2260                             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
2261                                 if_printf(ifp, "gigabit link up\n");
2262                         if (!ifq_is_empty(&ifp->if_snd))
2263                                 (*ifp->if_start)(ifp);
2264                 }
2265         }
2266 }
2267
2268 static void
2269 bge_stats_update_regs(struct bge_softc *sc)
2270 {
2271         struct ifnet *ifp = &sc->arpcom.ac_if;
2272         struct bge_mac_stats_regs stats;
2273         uint32_t *s;
2274         int i;
2275
2276         s = (uint32_t *)&stats;
2277         for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
2278                 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
2279                 s++;
2280         }
2281
2282         ifp->if_collisions +=
2283            (stats.dot3StatsSingleCollisionFrames +
2284            stats.dot3StatsMultipleCollisionFrames +
2285            stats.dot3StatsExcessiveCollisions +
2286            stats.dot3StatsLateCollisions) -
2287            ifp->if_collisions;
2288 }
2289
2290 static void
2291 bge_stats_update(struct bge_softc *sc)
2292 {
2293         struct ifnet *ifp = &sc->arpcom.ac_if;
2294         struct bge_stats *stats;
2295
2296         stats = (struct bge_stats *)(sc->bge_vhandle +
2297             BGE_MEMWIN_START + BGE_STATS_BLOCK);
2298
2299         ifp->if_collisions +=
2300            (stats->txstats.dot3StatsSingleCollisionFrames.bge_addr_lo +
2301            stats->txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo +
2302            stats->txstats.dot3StatsExcessiveCollisions.bge_addr_lo +
2303            stats->txstats.dot3StatsLateCollisions.bge_addr_lo) -
2304            ifp->if_collisions;
2305
2306 #ifdef notdef
2307         ifp->if_collisions +=
2308            (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
2309            sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
2310            sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
2311            sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
2312            ifp->if_collisions;
2313 #endif
2314 }
2315
2316 /*
2317  * Encapsulate an mbuf chain in the tx ring  by coupling the mbuf data
2318  * pointers to descriptors.
2319  */
2320 static int
2321 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx)
2322 {
2323         struct bge_tx_bd *f = NULL;
2324         struct mbuf *m;
2325         uint32_t frag, cur, cnt = 0;
2326         uint16_t csum_flags = 0;
2327         struct ifvlan *ifv = NULL;
2328
2329         if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
2330             m_head->m_pkthdr.rcvif != NULL &&
2331             m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN)
2332                 ifv = m_head->m_pkthdr.rcvif->if_softc;
2333
2334         m = m_head;
2335         cur = frag = *txidx;
2336
2337         if (m_head->m_pkthdr.csum_flags) {
2338                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2339                         csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2340                 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2341                         csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2342                 if (m_head->m_flags & M_LASTFRAG)
2343                         csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
2344                 else if (m_head->m_flags & M_FRAG)
2345                         csum_flags |= BGE_TXBDFLAG_IP_FRAG;
2346         }
2347         /*
2348          * Start packing the mbufs in this chain into
2349          * the fragment pointers. Stop when we run out
2350          * of fragments or hit the end of the mbuf chain.
2351          */
2352         for (m = m_head; m != NULL; m = m->m_next) {
2353                 if (m->m_len != 0) {
2354                         f = &sc->bge_rdata->bge_tx_ring[frag];
2355                         if (sc->bge_cdata.bge_tx_chain[frag] != NULL)
2356                                 break;
2357                         BGE_HOSTADDR(f->bge_addr,
2358                             vtophys(mtod(m, vm_offset_t)));
2359                         f->bge_len = m->m_len;
2360                         f->bge_flags = csum_flags;
2361                         if (ifv != NULL) {
2362                                 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
2363                                 f->bge_vlan_tag = ifv->ifv_tag;
2364                         } else {
2365                                 f->bge_vlan_tag = 0;
2366                         }
2367                         /*
2368                          * Sanity check: avoid coming within 16 descriptors
2369                          * of the end of the ring.
2370                          */
2371                         if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16)
2372                                 return(ENOBUFS);
2373                         cur = frag;
2374                         BGE_INC(frag, BGE_TX_RING_CNT);
2375                         cnt++;
2376                 }
2377         }
2378
2379         if (m != NULL)
2380                 return(ENOBUFS);
2381
2382         if (frag == sc->bge_tx_saved_considx)
2383                 return(ENOBUFS);
2384
2385         sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END;
2386         sc->bge_cdata.bge_tx_chain[cur] = m_head;
2387         sc->bge_txcnt += cnt;
2388
2389         *txidx = frag;
2390
2391         return(0);
2392 }
2393
2394 /*
2395  * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2396  * to the mbuf data regions directly in the transmit descriptors.
2397  */
2398 static void
2399 bge_start(struct ifnet *ifp)
2400 {
2401         struct bge_softc *sc;
2402         struct mbuf *m_head = NULL;
2403         uint32_t prodidx = 0;
2404         int need_trans;
2405
2406         sc = ifp->if_softc;
2407
2408         if (!sc->bge_link)
2409                 return;
2410
2411         prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO);
2412
2413         need_trans = 0;
2414         while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
2415                 m_head = ifq_poll(&ifp->if_snd);
2416                 if (m_head == NULL)
2417                         break;
2418
2419                 /*
2420                  * XXX
2421                  * safety overkill.  If this is a fragmented packet chain
2422                  * with delayed TCP/UDP checksums, then only encapsulate
2423                  * it if we have enough descriptors to handle the entire
2424                  * chain at once.
2425                  * (paranoia -- may not actually be needed)
2426                  */
2427                 if (m_head->m_flags & M_FIRSTFRAG &&
2428                     m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
2429                         if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
2430                             m_head->m_pkthdr.csum_data + 16) {
2431                                 ifp->if_flags |= IFF_OACTIVE;
2432                                 break;
2433                         }
2434                 }
2435
2436                 /*
2437                  * Pack the data into the transmit ring. If we
2438                  * don't have room, set the OACTIVE flag and wait
2439                  * for the NIC to drain the ring.
2440                  */
2441                 if (bge_encap(sc, m_head, &prodidx)) {
2442                         ifp->if_flags |= IFF_OACTIVE;
2443                         break;
2444                 }
2445                 ifq_dequeue(&ifp->if_snd, m_head);
2446                 need_trans = 1;
2447
2448                 BPF_MTAP(ifp, m_head);
2449         }
2450
2451         if (!need_trans)
2452                 return;
2453
2454         /* Transmit */
2455         CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2456         /* 5700 b2 errata */
2457         if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
2458                 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2459
2460         /*
2461          * Set a timeout in case the chip goes out to lunch.
2462          */
2463         ifp->if_timer = 5;
2464 }
2465
2466 static void
2467 bge_init(void *xsc)
2468 {
2469         struct bge_softc *sc = xsc;
2470         struct ifnet *ifp = &sc->arpcom.ac_if;
2471         uint16_t *m;
2472
2473         ASSERT_SERIALIZED(ifp->if_serializer);
2474
2475         if (ifp->if_flags & IFF_RUNNING)
2476                 return;
2477
2478         /* Cancel pending I/O and flush buffers. */
2479         bge_stop(sc);
2480         bge_reset(sc);
2481         bge_chipinit(sc);
2482
2483         /*
2484          * Init the various state machines, ring
2485          * control blocks and firmware.
2486          */
2487         if (bge_blockinit(sc)) {
2488                 if_printf(ifp, "initialization failure\n");
2489                 return;
2490         }
2491
2492         /* Specify MTU. */
2493         CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
2494             ETHER_HDR_LEN + ETHER_CRC_LEN + EVL_ENCAPLEN);
2495
2496         /* Load our MAC address. */
2497         m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
2498         CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
2499         CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
2500
2501         /* Enable or disable promiscuous mode as needed. */
2502         if (ifp->if_flags & IFF_PROMISC) {
2503                 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
2504         } else {
2505                 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
2506         }
2507
2508         /* Program multicast filter. */
2509         bge_setmulti(sc);
2510
2511         /* Init RX ring. */
2512         bge_init_rx_ring_std(sc);
2513
2514         /*
2515          * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
2516          * memory to insure that the chip has in fact read the first
2517          * entry of the ring.
2518          */
2519         if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
2520                 uint32_t                v, i;
2521                 for (i = 0; i < 10; i++) {
2522                         DELAY(20);
2523                         v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
2524                         if (v == (MCLBYTES - ETHER_ALIGN))
2525                                 break;
2526                 }
2527                 if (i == 10)
2528                         if_printf(ifp, "5705 A0 chip failed to load RX ring\n");
2529         }
2530
2531         /* Init jumbo RX ring. */
2532         if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2533                 bge_init_rx_ring_jumbo(sc);
2534
2535         /* Init our RX return ring index */
2536         sc->bge_rx_saved_considx = 0;
2537
2538         /* Init TX ring. */
2539         bge_init_tx_ring(sc);
2540
2541         /* Turn on transmitter */
2542         BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
2543
2544         /* Turn on receiver */
2545         BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
2546
2547         /* Tell firmware we're alive. */
2548         BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2549
2550         /* Enable host interrupts. */
2551         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
2552         BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
2553         CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
2554
2555         bge_ifmedia_upd(ifp);
2556
2557         ifp->if_flags |= IFF_RUNNING;
2558         ifp->if_flags &= ~IFF_OACTIVE;
2559
2560         callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2561 }
2562
2563 /*
2564  * Set media options.
2565  */
2566 static int
2567 bge_ifmedia_upd(struct ifnet *ifp)
2568 {
2569         struct bge_softc *sc = ifp->if_softc;
2570         struct ifmedia *ifm = &sc->bge_ifmedia;
2571         struct mii_data *mii;
2572
2573         /* If this is a 1000baseX NIC, enable the TBI port. */
2574         if (sc->bge_tbi) {
2575                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2576                         return(EINVAL);
2577                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
2578                 case IFM_AUTO:
2579                         /*
2580                          * The BCM5704 ASIC appears to have a special
2581                          * mechanism for programming the autoneg
2582                          * advertisement registers in TBI mode.
2583                          */
2584                         if (!bge_fake_autoneg &&
2585                             sc->bge_asicrev == BGE_ASICREV_BCM5704) {
2586                                 uint32_t sgdig;
2587
2588                                 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
2589                                 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
2590                                 sgdig |= BGE_SGDIGCFG_AUTO |
2591                                          BGE_SGDIGCFG_PAUSE_CAP |
2592                                          BGE_SGDIGCFG_ASYM_PAUSE;
2593                                 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
2594                                             sgdig | BGE_SGDIGCFG_SEND);
2595                                 DELAY(5);
2596                                 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
2597                         }
2598                         break;
2599                 case IFM_1000_SX:
2600                         if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
2601                                 BGE_CLRBIT(sc, BGE_MAC_MODE,
2602                                     BGE_MACMODE_HALF_DUPLEX);
2603                         } else {
2604                                 BGE_SETBIT(sc, BGE_MAC_MODE,
2605                                     BGE_MACMODE_HALF_DUPLEX);
2606                         }
2607                         break;
2608                 default:
2609                         return(EINVAL);
2610                 }
2611                 return(0);
2612         }
2613
2614         mii = device_get_softc(sc->bge_miibus);
2615         sc->bge_link = 0;
2616         if (mii->mii_instance) {
2617                 struct mii_softc *miisc;
2618                 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
2619                         mii_phy_reset(miisc);
2620         }
2621         mii_mediachg(mii);
2622
2623         return(0);
2624 }
2625
2626 /*
2627  * Report current media status.
2628  */
2629 static void
2630 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2631 {
2632         struct bge_softc *sc = ifp->if_softc;
2633         struct mii_data *mii;
2634
2635         if (sc->bge_tbi) {
2636                 ifmr->ifm_status = IFM_AVALID;
2637                 ifmr->ifm_active = IFM_ETHER;
2638                 if (CSR_READ_4(sc, BGE_MAC_STS) &
2639                     BGE_MACSTAT_TBI_PCS_SYNCHED)
2640                         ifmr->ifm_status |= IFM_ACTIVE;
2641                 ifmr->ifm_active |= IFM_1000_SX;
2642                 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
2643                         ifmr->ifm_active |= IFM_HDX;
2644                 else
2645                         ifmr->ifm_active |= IFM_FDX;
2646                 return;
2647         }
2648
2649         mii = device_get_softc(sc->bge_miibus);
2650         mii_pollstat(mii);
2651         ifmr->ifm_active = mii->mii_media_active;
2652         ifmr->ifm_status = mii->mii_media_status;
2653 }
2654
2655 static int
2656 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2657 {
2658         struct bge_softc *sc = ifp->if_softc;
2659         struct ifreq *ifr = (struct ifreq *) data;
2660         int mask, error = 0;
2661         struct mii_data *mii;
2662
2663         ASSERT_SERIALIZED(ifp->if_serializer);
2664
2665         switch(command) {
2666         case SIOCSIFMTU:
2667                 /* Disallow jumbo frames on 5705/5750. */
2668                 if (((sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
2669                       sc->bge_asicrev == BGE_ASICREV_BCM5750) &&
2670                      ifr->ifr_mtu > ETHERMTU) || ifr->ifr_mtu > BGE_JUMBO_MTU)
2671                         error = EINVAL;
2672                 else {
2673                         ifp->if_mtu = ifr->ifr_mtu;
2674                         ifp->if_flags &= ~IFF_RUNNING;
2675                         bge_init(sc);
2676                 }
2677                 break;
2678         case SIOCSIFFLAGS:
2679                 if (ifp->if_flags & IFF_UP) {
2680                         /*
2681                          * If only the state of the PROMISC flag changed,
2682                          * then just use the 'set promisc mode' command
2683                          * instead of reinitializing the entire NIC. Doing
2684                          * a full re-init means reloading the firmware and
2685                          * waiting for it to start up, which may take a
2686                          * second or two.
2687                          */
2688                         if (ifp->if_flags & IFF_RUNNING &&
2689                             ifp->if_flags & IFF_PROMISC &&
2690                             !(sc->bge_if_flags & IFF_PROMISC)) {
2691                                 BGE_SETBIT(sc, BGE_RX_MODE,
2692                                     BGE_RXMODE_RX_PROMISC);
2693                         } else if (ifp->if_flags & IFF_RUNNING &&
2694                             !(ifp->if_flags & IFF_PROMISC) &&
2695                             sc->bge_if_flags & IFF_PROMISC) {
2696                                 BGE_CLRBIT(sc, BGE_RX_MODE,
2697                                     BGE_RXMODE_RX_PROMISC);
2698                         } else
2699                                 bge_init(sc);
2700                 } else {
2701                         if (ifp->if_flags & IFF_RUNNING)
2702                                 bge_stop(sc);
2703                 }
2704                 sc->bge_if_flags = ifp->if_flags;
2705                 error = 0;
2706                 break;
2707         case SIOCADDMULTI:
2708         case SIOCDELMULTI:
2709                 if (ifp->if_flags & IFF_RUNNING) {
2710                         bge_setmulti(sc);
2711                         error = 0;
2712                 }
2713                 break;
2714         case SIOCSIFMEDIA:
2715         case SIOCGIFMEDIA:
2716                 if (sc->bge_tbi) {
2717                         error = ifmedia_ioctl(ifp, ifr,
2718                             &sc->bge_ifmedia, command);
2719                 } else {
2720                         mii = device_get_softc(sc->bge_miibus);
2721                         error = ifmedia_ioctl(ifp, ifr,
2722                             &mii->mii_media, command);
2723                 }
2724                 break;
2725         case SIOCSIFCAP:
2726                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2727                 if (mask & IFCAP_HWCSUM) {
2728                         if (IFCAP_HWCSUM & ifp->if_capenable)
2729                                 ifp->if_capenable &= ~IFCAP_HWCSUM;
2730                         else
2731                                 ifp->if_capenable |= IFCAP_HWCSUM;
2732                 }
2733                 error = 0;
2734                 break;
2735         default:
2736                 error = ether_ioctl(ifp, command, data);
2737                 break;
2738         }
2739         return(error);
2740 }
2741
2742 static void
2743 bge_watchdog(struct ifnet *ifp)
2744 {
2745         struct bge_softc *sc = ifp->if_softc;
2746
2747         if_printf(ifp, "watchdog timeout -- resetting\n");
2748
2749         ifp->if_flags &= ~IFF_RUNNING;
2750         bge_init(sc);
2751
2752         ifp->if_oerrors++;
2753
2754         if (!ifq_is_empty(&ifp->if_snd))
2755                 ifp->if_start(ifp);
2756 }
2757
2758 /*
2759  * Stop the adapter and free any mbufs allocated to the
2760  * RX and TX lists.
2761  */
2762 static void
2763 bge_stop(struct bge_softc *sc)
2764 {
2765         struct ifnet *ifp = &sc->arpcom.ac_if;
2766         struct ifmedia_entry *ifm;
2767         struct mii_data *mii = NULL;
2768         int mtmp, itmp;
2769
2770         ASSERT_SERIALIZED(ifp->if_serializer);
2771
2772         if (!sc->bge_tbi)
2773                 mii = device_get_softc(sc->bge_miibus);
2774
2775         callout_stop(&sc->bge_stat_timer);
2776
2777         /*
2778          * Disable all of the receiver blocks
2779          */
2780         BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
2781         BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
2782         BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
2783         if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
2784             sc->bge_asicrev != BGE_ASICREV_BCM5750)
2785                 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
2786         BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
2787         BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
2788         BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
2789
2790         /*
2791          * Disable all of the transmit blocks
2792          */
2793         BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
2794         BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
2795         BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
2796         BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
2797         BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
2798         if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
2799             sc->bge_asicrev != BGE_ASICREV_BCM5750)
2800                 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
2801         BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
2802
2803         /*
2804          * Shut down all of the memory managers and related
2805          * state machines.
2806          */
2807         BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
2808         BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
2809         if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
2810             sc->bge_asicrev != BGE_ASICREV_BCM5750)
2811                 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
2812         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
2813         CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
2814         if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
2815             sc->bge_asicrev != BGE_ASICREV_BCM5750) {
2816                 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
2817                 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2818         }
2819
2820         /* Disable host interrupts. */
2821         BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
2822         CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
2823
2824         /*
2825          * Tell firmware we're shutting down.
2826          */
2827         BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2828
2829         /* Free the RX lists. */
2830         bge_free_rx_ring_std(sc);
2831
2832         /* Free jumbo RX list. */
2833         if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
2834             sc->bge_asicrev != BGE_ASICREV_BCM5750)
2835                 bge_free_rx_ring_jumbo(sc);
2836
2837         /* Free TX buffers. */
2838         bge_free_tx_ring(sc);
2839
2840         /*
2841          * Isolate/power down the PHY, but leave the media selection
2842          * unchanged so that things will be put back to normal when
2843          * we bring the interface back up.
2844          */
2845         if (!sc->bge_tbi) {
2846                 itmp = ifp->if_flags;
2847                 ifp->if_flags |= IFF_UP;
2848                 ifm = mii->mii_media.ifm_cur;
2849                 mtmp = ifm->ifm_media;
2850                 ifm->ifm_media = IFM_ETHER|IFM_NONE;
2851                 mii_mediachg(mii);
2852                 ifm->ifm_media = mtmp;
2853                 ifp->if_flags = itmp;
2854         }
2855
2856         sc->bge_link = 0;
2857
2858         sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
2859
2860         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2861 }
2862
2863 /*
2864  * Stop all chip I/O so that the kernel's probe routines don't
2865  * get confused by errant DMAs when rebooting.
2866  */
2867 static void
2868 bge_shutdown(device_t dev)
2869 {
2870         struct bge_softc *sc = device_get_softc(dev);
2871         struct ifnet *ifp = &sc->arpcom.ac_if;
2872
2873         lwkt_serialize_enter(ifp->if_serializer);
2874         bge_stop(sc);
2875         bge_reset(sc);
2876         lwkt_serialize_exit(ifp->if_serializer);
2877 }
2878
2879 static int
2880 bge_suspend(device_t dev)
2881 {
2882         struct bge_softc *sc = device_get_softc(dev);
2883         struct ifnet *ifp = &sc->arpcom.ac_if;
2884
2885         lwkt_serialize_enter(ifp->if_serializer);
2886         bge_stop(sc);
2887         lwkt_serialize_exit(ifp->if_serializer);
2888
2889         return 0;
2890 }
2891
2892 static int
2893 bge_resume(device_t dev)
2894 {
2895         struct bge_softc *sc = device_get_softc(dev);
2896         struct ifnet *ifp = &sc->arpcom.ac_if;
2897
2898         lwkt_serialize_enter(ifp->if_serializer);
2899
2900         if (ifp->if_flags & IFF_UP) {
2901                 bge_init(sc);
2902
2903                 if (ifp->if_flags & IFF_RUNNING)
2904                         ifp->if_start(ifp);
2905         }
2906
2907         lwkt_serialize_exit(ifp->if_serializer);
2908
2909         return 0;
2910 }