2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
4 * Copyright (c) 2001-2008, Intel Corporation
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * 3. Neither the name of the Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived from
19 * this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
34 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
36 * This code is derived from software contributed to The DragonFly Project
37 * by Matthew Dillon <dillon@backplane.com>
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
43 * 1. Redistributions of source code must retain the above copyright
44 * notice, this list of conditions and the following disclaimer.
45 * 2. Redistributions in binary form must reproduce the above copyright
46 * notice, this list of conditions and the following disclaimer in
47 * the documentation and/or other materials provided with the
49 * 3. Neither the name of The DragonFly Project nor the names of its
50 * contributors may be used to endorse or promote products derived
51 * from this software without specific, prior written permission.
53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
67 #include "opt_polling.h"
68 #include "opt_serializer.h"
72 #include <sys/param.h>
74 #include <sys/endian.h>
75 #include <sys/interrupt.h>
76 #include <sys/kernel.h>
78 #include <sys/malloc.h>
82 #include <sys/serialize.h>
83 #include <sys/socket.h>
84 #include <sys/sockio.h>
85 #include <sys/sysctl.h>
86 #include <sys/systm.h>
89 #include <net/ethernet.h>
91 #include <net/if_arp.h>
92 #include <net/if_dl.h>
93 #include <net/if_media.h>
94 #include <net/ifq_var.h>
95 #include <net/toeplitz.h>
96 #include <net/toeplitz2.h>
97 #include <net/vlan/if_vlan_var.h>
98 #include <net/vlan/if_vlan_ether.h>
100 #include <netinet/in_systm.h>
101 #include <netinet/in.h>
102 #include <netinet/ip.h>
103 #include <netinet/tcp.h>
104 #include <netinet/udp.h>
106 #include <bus/pci/pcivar.h>
107 #include <bus/pci/pcireg.h>
109 #include <dev/netif/ig_hal/e1000_api.h>
110 #include <dev/netif/ig_hal/e1000_82571.h>
111 #include <dev/netif/emx/if_emx.h>
114 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) \
116 if (sc->rss_debug >= lvl) \
117 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
119 #else /* !EMX_RSS_DEBUG */
120 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
121 #endif /* EMX_RSS_DEBUG */
123 #define EMX_NAME "Intel(R) PRO/1000 "
125 #define EMX_DEVICE(id) \
126 { EMX_VENDOR_ID, E1000_DEV_ID_##id, EMX_NAME #id }
127 #define EMX_DEVICE_NULL { 0, 0, NULL }
129 static const struct emx_device {
134 EMX_DEVICE(82571EB_COPPER),
135 EMX_DEVICE(82571EB_FIBER),
136 EMX_DEVICE(82571EB_SERDES),
137 EMX_DEVICE(82571EB_SERDES_DUAL),
138 EMX_DEVICE(82571EB_SERDES_QUAD),
139 EMX_DEVICE(82571EB_QUAD_COPPER),
140 EMX_DEVICE(82571EB_QUAD_COPPER_BP),
141 EMX_DEVICE(82571EB_QUAD_COPPER_LP),
142 EMX_DEVICE(82571EB_QUAD_FIBER),
143 EMX_DEVICE(82571PT_QUAD_COPPER),
145 EMX_DEVICE(82572EI_COPPER),
146 EMX_DEVICE(82572EI_FIBER),
147 EMX_DEVICE(82572EI_SERDES),
151 EMX_DEVICE(82573E_IAMT),
154 EMX_DEVICE(80003ES2LAN_COPPER_SPT),
155 EMX_DEVICE(80003ES2LAN_SERDES_SPT),
156 EMX_DEVICE(80003ES2LAN_COPPER_DPT),
157 EMX_DEVICE(80003ES2LAN_SERDES_DPT),
161 /* required last entry */
165 static int emx_probe(device_t);
166 static int emx_attach(device_t);
167 static int emx_detach(device_t);
168 static int emx_shutdown(device_t);
169 static int emx_suspend(device_t);
170 static int emx_resume(device_t);
172 static void emx_init(void *);
173 static void emx_stop(struct emx_softc *);
174 static int emx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
175 static void emx_start(struct ifnet *);
176 #ifdef DEVICE_POLLING
177 static void emx_poll(struct ifnet *, enum poll_cmd, int);
179 static void emx_watchdog(struct ifnet *);
180 static void emx_media_status(struct ifnet *, struct ifmediareq *);
181 static int emx_media_change(struct ifnet *);
182 static void emx_timer(void *);
183 static void emx_serialize(struct ifnet *, enum ifnet_serialize);
184 static void emx_deserialize(struct ifnet *, enum ifnet_serialize);
185 static int emx_tryserialize(struct ifnet *, enum ifnet_serialize);
187 static void emx_serialize_assert(struct ifnet *, enum ifnet_serialize,
191 static void emx_intr(void *);
192 static void emx_rxeof(struct emx_softc *, int, int);
193 static void emx_txeof(struct emx_softc *);
194 static void emx_tx_collect(struct emx_softc *);
195 static void emx_tx_purge(struct emx_softc *);
196 static void emx_enable_intr(struct emx_softc *);
197 static void emx_disable_intr(struct emx_softc *);
199 static int emx_dma_alloc(struct emx_softc *);
200 static void emx_dma_free(struct emx_softc *);
201 static void emx_init_tx_ring(struct emx_softc *);
202 static int emx_init_rx_ring(struct emx_softc *, struct emx_rxdata *);
203 static void emx_free_rx_ring(struct emx_softc *, struct emx_rxdata *);
204 static int emx_create_tx_ring(struct emx_softc *);
205 static int emx_create_rx_ring(struct emx_softc *, struct emx_rxdata *);
206 static void emx_destroy_tx_ring(struct emx_softc *, int);
207 static void emx_destroy_rx_ring(struct emx_softc *,
208 struct emx_rxdata *, int);
209 static int emx_newbuf(struct emx_softc *, struct emx_rxdata *, int, int);
210 static int emx_encap(struct emx_softc *, struct mbuf **);
211 static int emx_txcsum_pullup(struct emx_softc *, struct mbuf **);
212 static int emx_txcsum(struct emx_softc *, struct mbuf *,
213 uint32_t *, uint32_t *);
215 static int emx_is_valid_eaddr(const uint8_t *);
216 static int emx_hw_init(struct emx_softc *);
217 static void emx_setup_ifp(struct emx_softc *);
218 static void emx_init_tx_unit(struct emx_softc *);
219 static void emx_init_rx_unit(struct emx_softc *);
220 static void emx_update_stats(struct emx_softc *);
221 static void emx_set_promisc(struct emx_softc *);
222 static void emx_disable_promisc(struct emx_softc *);
223 static void emx_set_multi(struct emx_softc *);
224 static void emx_update_link_status(struct emx_softc *);
225 static void emx_smartspeed(struct emx_softc *);
227 static void emx_print_debug_info(struct emx_softc *);
228 static void emx_print_nvm_info(struct emx_softc *);
229 static void emx_print_hw_stats(struct emx_softc *);
231 static int emx_sysctl_stats(SYSCTL_HANDLER_ARGS);
232 static int emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
233 static int emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS);
234 static int emx_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS);
235 static void emx_add_sysctl(struct emx_softc *);
237 static void emx_serialize_skipmain(struct emx_softc *);
238 static void emx_deserialize_skipmain(struct emx_softc *);
239 static int emx_tryserialize_skipmain(struct emx_softc *);
241 /* Management and WOL Support */
242 static void emx_get_mgmt(struct emx_softc *);
243 static void emx_rel_mgmt(struct emx_softc *);
244 static void emx_get_hw_control(struct emx_softc *);
245 static void emx_rel_hw_control(struct emx_softc *);
246 static void emx_enable_wol(device_t);
248 static device_method_t emx_methods[] = {
249 /* Device interface */
250 DEVMETHOD(device_probe, emx_probe),
251 DEVMETHOD(device_attach, emx_attach),
252 DEVMETHOD(device_detach, emx_detach),
253 DEVMETHOD(device_shutdown, emx_shutdown),
254 DEVMETHOD(device_suspend, emx_suspend),
255 DEVMETHOD(device_resume, emx_resume),
259 static driver_t emx_driver = {
262 sizeof(struct emx_softc),
265 static devclass_t emx_devclass;
267 DECLARE_DUMMY_MODULE(if_emx);
268 MODULE_DEPEND(emx, ig_hal, 1, 1, 1);
269 DRIVER_MODULE(if_emx, pci, emx_driver, emx_devclass, 0, 0);
274 static int emx_int_throttle_ceil = EMX_DEFAULT_ITR;
275 static int emx_rxd = EMX_DEFAULT_RXD;
276 static int emx_txd = EMX_DEFAULT_TXD;
277 static int emx_smart_pwr_down = FALSE;
279 /* Controls whether promiscuous also shows bad packets */
280 static int emx_debug_sbp = FALSE;
282 static int emx_82573_workaround = TRUE;
284 TUNABLE_INT("hw.emx.int_throttle_ceil", &emx_int_throttle_ceil);
285 TUNABLE_INT("hw.emx.rxd", &emx_rxd);
286 TUNABLE_INT("hw.emx.txd", &emx_txd);
287 TUNABLE_INT("hw.emx.smart_pwr_down", &emx_smart_pwr_down);
288 TUNABLE_INT("hw.emx.sbp", &emx_debug_sbp);
289 TUNABLE_INT("hw.emx.82573_workaround", &emx_82573_workaround);
291 /* Global used in WOL setup with multiport cards */
292 static int emx_global_quad_port_a = 0;
294 /* Set this to one to display debug statistics */
295 static int emx_display_debug_stats = 0;
297 #if !defined(KTR_IF_EMX)
298 #define KTR_IF_EMX KTR_ALL
300 KTR_INFO_MASTER(if_emx);
301 KTR_INFO(KTR_IF_EMX, if_emx, intr_beg, 0, "intr begin", 0);
302 KTR_INFO(KTR_IF_EMX, if_emx, intr_end, 1, "intr end", 0);
303 KTR_INFO(KTR_IF_EMX, if_emx, pkt_receive, 4, "rx packet", 0);
304 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txqueue, 5, "tx packet", 0);
305 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txclean, 6, "tx clean", 0);
306 #define logif(name) KTR_LOG(if_emx_ ## name)
309 emx_setup_rxdesc(emx_rxdesc_t *rxd, const struct emx_rxbuf *rxbuf)
311 rxd->rxd_bufaddr = htole64(rxbuf->paddr);
312 /* DD bit must be cleared */
313 rxd->rxd_staterr = 0;
317 emx_rxcsum(uint32_t staterr, struct mbuf *mp)
319 /* Ignore Checksum bit is set */
320 if (staterr & E1000_RXD_STAT_IXSM)
323 if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
325 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
327 if ((staterr & (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
328 E1000_RXD_STAT_TCPCS) {
329 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
331 CSUM_FRAG_NOT_CHECKED;
332 mp->m_pkthdr.csum_data = htons(0xffff);
336 static __inline struct pktinfo *
337 emx_rssinfo(struct mbuf *m, struct pktinfo *pi,
338 uint32_t mrq, uint32_t hash, uint32_t staterr)
340 switch (mrq & EMX_RXDMRQ_RSSTYPE_MASK) {
341 case EMX_RXDMRQ_IPV4_TCP:
342 pi->pi_netisr = NETISR_IP;
344 pi->pi_l3proto = IPPROTO_TCP;
347 case EMX_RXDMRQ_IPV6_TCP:
348 pi->pi_netisr = NETISR_IPV6;
350 pi->pi_l3proto = IPPROTO_TCP;
353 case EMX_RXDMRQ_IPV4:
354 if (staterr & E1000_RXD_STAT_IXSM)
358 (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
359 E1000_RXD_STAT_TCPCS) {
360 pi->pi_netisr = NETISR_IP;
362 pi->pi_l3proto = IPPROTO_UDP;
370 m->m_flags |= M_HASH;
371 m->m_pkthdr.hash = toeplitz_hash(hash);
376 emx_probe(device_t dev)
378 const struct emx_device *d;
381 vid = pci_get_vendor(dev);
382 did = pci_get_device(dev);
384 for (d = emx_devices; d->desc != NULL; ++d) {
385 if (vid == d->vid && did == d->did) {
386 device_set_desc(dev, d->desc);
387 device_set_async_attach(dev, TRUE);
395 emx_attach(device_t dev)
397 struct emx_softc *sc = device_get_softc(dev);
398 struct ifnet *ifp = &sc->arpcom.ac_if;
400 uint16_t eeprom_data, device_id;
402 lwkt_serialize_init(&sc->main_serialize);
403 lwkt_serialize_init(&sc->tx_serialize);
404 for (i = 0; i < EMX_NRX_RING; ++i)
405 lwkt_serialize_init(&sc->rx_data[i].rx_serialize);
407 lwkt_serialize_init(&sc->panic_serialize);
408 lwkt_serialize_enter(&sc->panic_serialize);
411 sc->serializes[i++] = &sc->main_serialize;
412 sc->serializes[i++] = &sc->tx_serialize;
413 sc->serializes[i++] = &sc->rx_data[0].rx_serialize;
414 sc->serializes[i++] = &sc->rx_data[1].rx_serialize;
415 KKASSERT(i == EMX_NSERIALIZE);
417 callout_init(&sc->timer);
419 sc->dev = sc->osdep.dev = dev;
422 * Determine hardware and mac type
424 sc->hw.vendor_id = pci_get_vendor(dev);
425 sc->hw.device_id = pci_get_device(dev);
426 sc->hw.revision_id = pci_get_revid(dev);
427 sc->hw.subsystem_vendor_id = pci_get_subvendor(dev);
428 sc->hw.subsystem_device_id = pci_get_subdevice(dev);
430 if (e1000_set_mac_type(&sc->hw))
433 /* Enable bus mastering */
434 pci_enable_busmaster(dev);
439 sc->memory_rid = EMX_BAR_MEM;
440 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
441 &sc->memory_rid, RF_ACTIVE);
442 if (sc->memory == NULL) {
443 device_printf(dev, "Unable to allocate bus resource: memory\n");
447 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory);
448 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->memory);
450 /* XXX This is quite goofy, it is not actually used */
451 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
457 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid,
458 RF_SHAREABLE | RF_ACTIVE);
459 if (sc->intr_res == NULL) {
460 device_printf(dev, "Unable to allocate bus resource: "
466 /* Save PCI command register for Shared Code */
467 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
468 sc->hw.back = &sc->osdep;
470 /* Do Shared Code initialization */
471 if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
472 device_printf(dev, "Setup of Shared code failed\n");
476 e1000_get_bus_info(&sc->hw);
478 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
479 sc->hw.phy.autoneg_wait_to_complete = FALSE;
480 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
483 * Interrupt throttle rate
485 if (emx_int_throttle_ceil == 0) {
486 sc->int_throttle_ceil = 0;
488 int throttle = emx_int_throttle_ceil;
491 throttle = EMX_DEFAULT_ITR;
493 /* Recalculate the tunable value to get the exact frequency. */
494 throttle = 1000000000 / 256 / throttle;
496 /* Upper 16bits of ITR is reserved and should be zero */
497 if (throttle & 0xffff0000)
498 throttle = 1000000000 / 256 / EMX_DEFAULT_ITR;
500 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
503 e1000_init_script_state_82541(&sc->hw, TRUE);
504 e1000_set_tbi_compatibility_82543(&sc->hw, TRUE);
507 if (sc->hw.phy.media_type == e1000_media_type_copper) {
508 sc->hw.phy.mdix = EMX_AUTO_ALL_MODES;
509 sc->hw.phy.disable_polarity_correction = FALSE;
510 sc->hw.phy.ms_type = EMX_MASTER_SLAVE;
513 /* Set the frame limits assuming standard ethernet sized frames. */
514 sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
515 sc->min_frame_size = ETHER_MIN_LEN;
517 /* This controls when hardware reports transmit completion status. */
518 sc->hw.mac.report_tx_early = 1;
521 /* Calculate # of RX rings */
523 sc->rx_ring_cnt = EMX_NRX_RING;
527 sc->rx_ring_inuse = sc->rx_ring_cnt;
529 /* Allocate RX/TX rings' busdma(9) stuffs */
530 error = emx_dma_alloc(sc);
534 /* Make sure we have a good EEPROM before we read from it */
535 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
537 * Some PCI-E parts fail the first check due to
538 * the link being in sleep state, call it again,
539 * if it fails a second time its a real issue.
541 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
543 "The EEPROM Checksum Is Not Valid\n");
549 /* Initialize the hardware */
550 error = emx_hw_init(sc);
552 device_printf(dev, "Unable to initialize the hardware\n");
556 /* Copy the permanent MAC address out of the EEPROM */
557 if (e1000_read_mac_addr(&sc->hw) < 0) {
558 device_printf(dev, "EEPROM read error while reading MAC"
563 if (!emx_is_valid_eaddr(sc->hw.mac.addr)) {
564 device_printf(dev, "Invalid MAC address\n");
569 /* Manually turn off all interrupts */
570 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
572 /* Setup OS specific network interface */
575 /* Add sysctl tree, must after emx_setup_ifp() */
578 /* Initialize statistics */
579 emx_update_stats(sc);
581 sc->hw.mac.get_link_status = 1;
582 emx_update_link_status(sc);
584 /* Indicate SOL/IDER usage */
585 if (e1000_check_reset_block(&sc->hw)) {
587 "PHY reset is blocked due to SOL/IDER session.\n");
590 /* Determine if we have to control management hardware */
591 sc->has_manage = e1000_enable_mng_pass_thru(&sc->hw);
596 switch (sc->hw.mac.type) {
598 case e1000_80003es2lan:
599 if (sc->hw.bus.func == 1) {
600 e1000_read_nvm(&sc->hw,
601 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
603 e1000_read_nvm(&sc->hw,
604 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
606 eeprom_data &= EMX_EEPROM_APME;
610 /* APME bit in EEPROM is mapped to WUC.APME */
612 E1000_READ_REG(&sc->hw, E1000_WUC) & E1000_WUC_APME;
616 sc->wol = E1000_WUFC_MAG;
618 * We have the eeprom settings, now apply the special cases
619 * where the eeprom may be wrong or the board won't support
620 * wake on lan on a particular port
622 device_id = pci_get_device(dev);
624 case E1000_DEV_ID_82571EB_FIBER:
626 * Wake events only supported on port A for dual fiber
627 * regardless of eeprom setting
629 if (E1000_READ_REG(&sc->hw, E1000_STATUS) &
634 case E1000_DEV_ID_82571EB_QUAD_COPPER:
635 case E1000_DEV_ID_82571EB_QUAD_FIBER:
636 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
637 /* if quad port sc, disable WoL on all but port A */
638 if (emx_global_quad_port_a != 0)
640 /* Reset for multiple quad port adapters */
641 if (++emx_global_quad_port_a == 4)
642 emx_global_quad_port_a = 0;
646 /* XXX disable wol */
649 sc->spare_tx_desc = EMX_TX_SPARE;
652 * Keep following relationship between spare_tx_desc, oact_tx_desc
654 * (spare_tx_desc + EMX_TX_RESERVED) <=
655 * oact_tx_desc <= EMX_TX_OACTIVE_MAX <= tx_int_nsegs
657 sc->oact_tx_desc = sc->num_tx_desc / 8;
658 if (sc->oact_tx_desc > EMX_TX_OACTIVE_MAX)
659 sc->oact_tx_desc = EMX_TX_OACTIVE_MAX;
660 if (sc->oact_tx_desc < sc->spare_tx_desc + EMX_TX_RESERVED)
661 sc->oact_tx_desc = sc->spare_tx_desc + EMX_TX_RESERVED;
663 sc->tx_int_nsegs = sc->num_tx_desc / 16;
664 if (sc->tx_int_nsegs < sc->oact_tx_desc)
665 sc->tx_int_nsegs = sc->oact_tx_desc;
667 error = bus_setup_intr(dev, sc->intr_res, INTR_MPSAFE, emx_intr, sc,
668 &sc->intr_tag, &sc->main_serialize);
670 device_printf(dev, "Failed to register interrupt handler");
671 ether_ifdetach(&sc->arpcom.ac_if);
675 ifp->if_cpuid = ithread_cpuid(rman_get_start(sc->intr_res));
676 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
684 emx_detach(device_t dev)
686 struct emx_softc *sc = device_get_softc(dev);
688 if (device_is_attached(dev)) {
689 struct ifnet *ifp = &sc->arpcom.ac_if;
691 ifnet_serialize_all(ifp);
695 e1000_phy_hw_reset(&sc->hw);
699 if (sc->hw.mac.type == e1000_82573 &&
700 e1000_check_mng_mode(&sc->hw))
701 emx_rel_hw_control(sc);
704 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
705 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
709 bus_teardown_intr(dev, sc->intr_res, sc->intr_tag);
711 ifnet_deserialize_all(ifp);
715 bus_generic_detach(dev);
717 if (sc->intr_res != NULL) {
718 bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid,
722 if (sc->memory != NULL) {
723 bus_release_resource(dev, SYS_RES_MEMORY, sc->memory_rid,
729 /* Free sysctl tree */
730 if (sc->sysctl_tree != NULL)
731 sysctl_ctx_free(&sc->sysctl_ctx);
737 emx_shutdown(device_t dev)
739 return emx_suspend(dev);
743 emx_suspend(device_t dev)
745 struct emx_softc *sc = device_get_softc(dev);
746 struct ifnet *ifp = &sc->arpcom.ac_if;
748 ifnet_serialize_all(ifp);
754 if (sc->hw.mac.type == e1000_82573 &&
755 e1000_check_mng_mode(&sc->hw))
756 emx_rel_hw_control(sc);
759 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
760 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
764 ifnet_deserialize_all(ifp);
766 return bus_generic_suspend(dev);
770 emx_resume(device_t dev)
772 struct emx_softc *sc = device_get_softc(dev);
773 struct ifnet *ifp = &sc->arpcom.ac_if;
775 ifnet_serialize_all(ifp);
781 ifnet_deserialize_all(ifp);
783 return bus_generic_resume(dev);
787 emx_start(struct ifnet *ifp)
789 struct emx_softc *sc = ifp->if_softc;
792 ASSERT_SERIALIZED(&sc->tx_serialize);
794 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
797 if (!sc->link_active) {
798 ifq_purge(&ifp->if_snd);
802 while (!ifq_is_empty(&ifp->if_snd)) {
803 /* Now do we at least have a minimal? */
804 if (EMX_IS_OACTIVE(sc)) {
806 if (EMX_IS_OACTIVE(sc)) {
807 ifp->if_flags |= IFF_OACTIVE;
808 sc->no_tx_desc_avail1++;
814 m_head = ifq_dequeue(&ifp->if_snd, NULL);
818 if (emx_encap(sc, &m_head)) {
824 /* Send a copy of the frame to the BPF listener */
825 ETHER_BPF_MTAP(ifp, m_head);
827 /* Set timeout in case hardware has problems transmitting. */
828 ifp->if_timer = EMX_TX_TIMEOUT;
833 emx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
835 struct emx_softc *sc = ifp->if_softc;
836 struct ifreq *ifr = (struct ifreq *)data;
837 uint16_t eeprom_data = 0;
838 int max_frame_size, mask, reinit;
841 ASSERT_IFNET_SERIALIZED_ALL(ifp);
845 switch (sc->hw.mac.type) {
848 * 82573 only supports jumbo frames
849 * if ASPM is disabled.
851 e1000_read_nvm(&sc->hw, NVM_INIT_3GIO_3, 1,
853 if (eeprom_data & NVM_WORD1A_ASPM_MASK) {
854 max_frame_size = ETHER_MAX_LEN;
859 /* Limit Jumbo Frame size */
863 case e1000_80003es2lan:
864 max_frame_size = 9234;
868 max_frame_size = MAX_JUMBO_FRAME_SIZE;
871 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
877 ifp->if_mtu = ifr->ifr_mtu;
878 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
881 if (ifp->if_flags & IFF_RUNNING)
886 if (ifp->if_flags & IFF_UP) {
887 if ((ifp->if_flags & IFF_RUNNING)) {
888 if ((ifp->if_flags ^ sc->if_flags) &
889 (IFF_PROMISC | IFF_ALLMULTI)) {
890 emx_disable_promisc(sc);
896 } else if (ifp->if_flags & IFF_RUNNING) {
899 sc->if_flags = ifp->if_flags;
904 if (ifp->if_flags & IFF_RUNNING) {
905 emx_disable_intr(sc);
907 #ifdef DEVICE_POLLING
908 if (!(ifp->if_flags & IFF_POLLING))
915 /* Check SOL/IDER usage */
916 if (e1000_check_reset_block(&sc->hw)) {
917 device_printf(sc->dev, "Media change is"
918 " blocked due to SOL/IDER session.\n");
924 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
929 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
930 if (mask & IFCAP_HWCSUM) {
931 ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
934 if (mask & IFCAP_VLAN_HWTAGGING) {
935 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
938 if (mask & IFCAP_RSS) {
939 ifp->if_capenable ^= IFCAP_RSS;
942 if (reinit && (ifp->if_flags & IFF_RUNNING))
947 error = ether_ioctl(ifp, command, data);
954 emx_watchdog(struct ifnet *ifp)
956 struct emx_softc *sc = ifp->if_softc;
958 ASSERT_IFNET_SERIALIZED_ALL(ifp);
961 * The timer is set to 5 every time start queues a packet.
962 * Then txeof keeps resetting it as long as it cleans at
963 * least one descriptor.
964 * Finally, anytime all descriptors are clean the timer is
968 if (E1000_READ_REG(&sc->hw, E1000_TDT(0)) ==
969 E1000_READ_REG(&sc->hw, E1000_TDH(0))) {
971 * If we reach here, all TX jobs are completed and
972 * the TX engine should have been idled for some time.
973 * We don't need to call if_devstart() here.
975 ifp->if_flags &= ~IFF_OACTIVE;
981 * If we are in this routine because of pause frames, then
982 * don't reset the hardware.
984 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_TXOFF) {
985 ifp->if_timer = EMX_TX_TIMEOUT;
989 if (e1000_check_for_link(&sc->hw) == 0)
990 if_printf(ifp, "watchdog timeout -- resetting\n");
993 sc->watchdog_events++;
997 if (!ifq_is_empty(&ifp->if_snd))
1004 struct emx_softc *sc = xsc;
1005 struct ifnet *ifp = &sc->arpcom.ac_if;
1006 device_t dev = sc->dev;
1010 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1015 * Packet Buffer Allocation (PBA)
1016 * Writing PBA sets the receive portion of the buffer
1017 * the remainder is used for the transmit buffer.
1019 switch (sc->hw.mac.type) {
1020 /* Total Packet Buffer on these is 48K */
1023 case e1000_80003es2lan:
1024 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1027 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
1028 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
1032 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
1036 /* Devices before 82547 had a Packet Buffer of 64K. */
1037 if (sc->max_frame_size > 8192)
1038 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
1040 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
1042 E1000_WRITE_REG(&sc->hw, E1000_PBA, pba);
1044 /* Get the latest mac address, User can use a LAA */
1045 bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
1047 /* Put the address into the Receive Address Array */
1048 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1051 * With the 82571 sc, RAR[0] may be overwritten
1052 * when the other port is reset, we make a duplicate
1053 * in RAR[14] for that eventuality, this assures
1054 * the interface continues to function.
1056 if (sc->hw.mac.type == e1000_82571) {
1057 e1000_set_laa_state_82571(&sc->hw, TRUE);
1058 e1000_rar_set(&sc->hw, sc->hw.mac.addr,
1059 E1000_RAR_ENTRIES - 1);
1062 /* Initialize the hardware */
1063 if (emx_hw_init(sc)) {
1064 device_printf(dev, "Unable to initialize the hardware\n");
1065 /* XXX emx_stop()? */
1068 emx_update_link_status(sc);
1070 /* Setup VLAN support, basic and offload if available */
1071 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1073 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) {
1076 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL);
1077 ctrl |= E1000_CTRL_VME;
1078 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl);
1081 /* Set hardware offload abilities */
1082 if (ifp->if_capenable & IFCAP_TXCSUM)
1083 ifp->if_hwassist = EMX_CSUM_FEATURES;
1085 ifp->if_hwassist = 0;
1087 /* Configure for OS presence */
1090 /* Prepare transmit descriptors and buffers */
1091 emx_init_tx_ring(sc);
1092 emx_init_tx_unit(sc);
1094 /* Setup Multicast table */
1098 * Adjust # of RX ring to be used based on IFCAP_RSS
1100 if (ifp->if_capenable & IFCAP_RSS)
1101 sc->rx_ring_inuse = sc->rx_ring_cnt;
1103 sc->rx_ring_inuse = 1;
1105 /* Prepare receive descriptors and buffers */
1106 for (i = 0; i < sc->rx_ring_inuse; ++i) {
1107 if (emx_init_rx_ring(sc, &sc->rx_data[i])) {
1109 "Could not setup receive structures\n");
1114 emx_init_rx_unit(sc);
1116 /* Don't lose promiscuous settings */
1117 emx_set_promisc(sc);
1119 ifp->if_flags |= IFF_RUNNING;
1120 ifp->if_flags &= ~IFF_OACTIVE;
1122 callout_reset(&sc->timer, hz, emx_timer, sc);
1123 e1000_clear_hw_cntrs_base_generic(&sc->hw);
1125 /* MSI/X configuration for 82574 */
1126 if (sc->hw.mac.type == e1000_82574) {
1129 tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
1130 tmp |= E1000_CTRL_EXT_PBA_CLR;
1131 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp);
1133 * Set the IVAR - interrupt vector routing.
1134 * Each nibble represents a vector, high bit
1135 * is enable, other 3 bits are the MSIX table
1136 * entry, we map RXQ0 to 0, TXQ0 to 1, and
1137 * Link (other) to 2, hence the magic number.
1139 E1000_WRITE_REG(&sc->hw, E1000_IVAR, 0x800A0908);
1142 #ifdef DEVICE_POLLING
1144 * Only enable interrupts if we are not polling, make sure
1145 * they are off otherwise.
1147 if (ifp->if_flags & IFF_POLLING)
1148 emx_disable_intr(sc);
1150 #endif /* DEVICE_POLLING */
1151 emx_enable_intr(sc);
1153 /* Don't reset the phy next time init gets called */
1154 sc->hw.phy.reset_disable = TRUE;
1157 #ifdef DEVICE_POLLING
1160 emx_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
1162 struct emx_softc *sc = ifp->if_softc;
1165 ASSERT_IFNET_SERIALIZED_MAIN(ifp);
1169 emx_disable_intr(sc);
1172 case POLL_DEREGISTER:
1173 emx_enable_intr(sc);
1176 case POLL_AND_CHECK_STATUS:
1177 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
1178 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1179 if (emx_tryserialize_skipmain(sc)) {
1180 callout_stop(&sc->timer);
1181 sc->hw.mac.get_link_status = 1;
1182 emx_update_link_status(sc);
1183 callout_reset(&sc->timer, hz, emx_timer, sc);
1184 emx_deserialize_skipmain(sc);
1189 if (ifp->if_flags & IFF_RUNNING) {
1192 for (i = 0; i < sc->rx_ring_inuse; ++i) {
1193 if (lwkt_serialize_try(
1194 &sc->rx_data[i].rx_serialize)) {
1195 emx_rxeof(sc, i, count);
1196 lwkt_serialize_exit(
1197 &sc->rx_data[i].rx_serialize);
1201 if (lwkt_serialize_try(&sc->tx_serialize)) {
1203 if (!ifq_is_empty(&ifp->if_snd))
1205 lwkt_serialize_exit(&sc->tx_serialize);
1212 #endif /* DEVICE_POLLING */
1217 struct emx_softc *sc = xsc;
1218 struct ifnet *ifp = &sc->arpcom.ac_if;
1222 ASSERT_SERIALIZED(&sc->main_serialize);
1224 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
1226 if ((reg_icr & E1000_ICR_INT_ASSERTED) == 0) {
1232 * XXX: some laptops trigger several spurious interrupts
1233 * on emx(4) when in the resume cycle. The ICR register
1234 * reports all-ones value in this case. Processing such
1235 * interrupts would lead to a freeze. I don't know why.
1237 if (reg_icr == 0xffffffff) {
1242 if (ifp->if_flags & IFF_RUNNING) {
1244 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
1247 for (i = 0; i < sc->rx_ring_inuse; ++i) {
1248 lwkt_serialize_enter(
1249 &sc->rx_data[i].rx_serialize);
1250 emx_rxeof(sc, i, -1);
1251 lwkt_serialize_exit(
1252 &sc->rx_data[i].rx_serialize);
1255 if (reg_icr & E1000_ICR_TXDW) {
1256 lwkt_serialize_enter(&sc->tx_serialize);
1258 if (!ifq_is_empty(&ifp->if_snd))
1260 lwkt_serialize_exit(&sc->tx_serialize);
1264 /* Link status change */
1265 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1266 emx_serialize_skipmain(sc);
1268 callout_stop(&sc->timer);
1269 sc->hw.mac.get_link_status = 1;
1270 emx_update_link_status(sc);
1272 /* Deal with TX cruft when link lost */
1275 callout_reset(&sc->timer, hz, emx_timer, sc);
1277 emx_deserialize_skipmain(sc);
1280 if (reg_icr & E1000_ICR_RXO)
1287 emx_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1289 struct emx_softc *sc = ifp->if_softc;
1291 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1293 emx_update_link_status(sc);
1295 ifmr->ifm_status = IFM_AVALID;
1296 ifmr->ifm_active = IFM_ETHER;
1298 if (!sc->link_active)
1301 ifmr->ifm_status |= IFM_ACTIVE;
1303 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1304 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1305 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
1307 switch (sc->link_speed) {
1309 ifmr->ifm_active |= IFM_10_T;
1312 ifmr->ifm_active |= IFM_100_TX;
1316 ifmr->ifm_active |= IFM_1000_T;
1319 if (sc->link_duplex == FULL_DUPLEX)
1320 ifmr->ifm_active |= IFM_FDX;
1322 ifmr->ifm_active |= IFM_HDX;
1327 emx_media_change(struct ifnet *ifp)
1329 struct emx_softc *sc = ifp->if_softc;
1330 struct ifmedia *ifm = &sc->media;
1332 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1334 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1337 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1339 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1340 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
1346 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1347 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1351 sc->hw.mac.autoneg = FALSE;
1352 sc->hw.phy.autoneg_advertised = 0;
1353 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1354 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1356 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1360 sc->hw.mac.autoneg = FALSE;
1361 sc->hw.phy.autoneg_advertised = 0;
1362 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1363 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1365 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1369 if_printf(ifp, "Unsupported media type\n");
1374 * As the speed/duplex settings my have changed we need to
1377 sc->hw.phy.reset_disable = FALSE;
1385 emx_encap(struct emx_softc *sc, struct mbuf **m_headp)
1387 bus_dma_segment_t segs[EMX_MAX_SCATTER];
1389 struct emx_txbuf *tx_buffer, *tx_buffer_mapped;
1390 struct e1000_tx_desc *ctxd = NULL;
1391 struct mbuf *m_head = *m_headp;
1392 uint32_t txd_upper, txd_lower, cmd = 0;
1393 int maxsegs, nsegs, i, j, first, last = 0, error;
1395 if (m_head->m_len < EMX_TXCSUM_MINHL &&
1396 (m_head->m_flags & EMX_CSUM_FEATURES)) {
1398 * Make sure that ethernet header and ip.ip_hl are in
1399 * contiguous memory, since if TXCSUM is enabled, later
1400 * TX context descriptor's setup need to access ip.ip_hl.
1402 error = emx_txcsum_pullup(sc, m_headp);
1404 KKASSERT(*m_headp == NULL);
1410 txd_upper = txd_lower = 0;
1413 * Capture the first descriptor index, this descriptor
1414 * will have the index of the EOP which is the only one
1415 * that now gets a DONE bit writeback.
1417 first = sc->next_avail_tx_desc;
1418 tx_buffer = &sc->tx_buf[first];
1419 tx_buffer_mapped = tx_buffer;
1420 map = tx_buffer->map;
1422 maxsegs = sc->num_tx_desc_avail - EMX_TX_RESERVED;
1423 KASSERT(maxsegs >= sc->spare_tx_desc, ("not enough spare TX desc\n"));
1424 if (maxsegs > EMX_MAX_SCATTER)
1425 maxsegs = EMX_MAX_SCATTER;
1427 error = bus_dmamap_load_mbuf_defrag(sc->txtag, map, m_headp,
1428 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1430 if (error == ENOBUFS)
1431 sc->mbuf_alloc_failed++;
1433 sc->no_tx_dma_setup++;
1439 bus_dmamap_sync(sc->txtag, map, BUS_DMASYNC_PREWRITE);
1442 sc->tx_nsegs += nsegs;
1444 if (m_head->m_pkthdr.csum_flags & EMX_CSUM_FEATURES) {
1445 /* TX csum offloading will consume one TX desc */
1446 sc->tx_nsegs += emx_txcsum(sc, m_head, &txd_upper, &txd_lower);
1448 i = sc->next_avail_tx_desc;
1450 /* Set up our transmit descriptors */
1451 for (j = 0; j < nsegs; j++) {
1452 tx_buffer = &sc->tx_buf[i];
1453 ctxd = &sc->tx_desc_base[i];
1455 ctxd->buffer_addr = htole64(segs[j].ds_addr);
1456 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS |
1457 txd_lower | segs[j].ds_len);
1458 ctxd->upper.data = htole32(txd_upper);
1461 if (++i == sc->num_tx_desc)
1465 sc->next_avail_tx_desc = i;
1467 KKASSERT(sc->num_tx_desc_avail > nsegs);
1468 sc->num_tx_desc_avail -= nsegs;
1470 /* Handle VLAN tag */
1471 if (m_head->m_flags & M_VLANTAG) {
1472 /* Set the vlan id. */
1473 ctxd->upper.fields.special =
1474 htole16(m_head->m_pkthdr.ether_vlantag);
1476 /* Tell hardware to add tag */
1477 ctxd->lower.data |= htole32(E1000_TXD_CMD_VLE);
1480 tx_buffer->m_head = m_head;
1481 tx_buffer_mapped->map = tx_buffer->map;
1482 tx_buffer->map = map;
1484 if (sc->tx_nsegs >= sc->tx_int_nsegs) {
1488 * Report Status (RS) is turned on
1489 * every tx_int_nsegs descriptors.
1491 cmd = E1000_TXD_CMD_RS;
1494 * Keep track of the descriptor, which will
1495 * be written back by hardware.
1497 sc->tx_dd[sc->tx_dd_tail] = last;
1498 EMX_INC_TXDD_IDX(sc->tx_dd_tail);
1499 KKASSERT(sc->tx_dd_tail != sc->tx_dd_head);
1503 * Last Descriptor of Packet needs End Of Packet (EOP)
1505 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd);
1508 * Advance the Transmit Descriptor Tail (TDT), this tells
1509 * the E1000 that this frame is available to transmit.
1511 E1000_WRITE_REG(&sc->hw, E1000_TDT(0), i);
1517 emx_set_promisc(struct emx_softc *sc)
1519 struct ifnet *ifp = &sc->arpcom.ac_if;
1522 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1524 if (ifp->if_flags & IFF_PROMISC) {
1525 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1526 /* Turn this on if you want to see bad packets */
1528 reg_rctl |= E1000_RCTL_SBP;
1529 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1530 } else if (ifp->if_flags & IFF_ALLMULTI) {
1531 reg_rctl |= E1000_RCTL_MPE;
1532 reg_rctl &= ~E1000_RCTL_UPE;
1533 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1538 emx_disable_promisc(struct emx_softc *sc)
1542 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1544 reg_rctl &= ~E1000_RCTL_UPE;
1545 reg_rctl &= ~E1000_RCTL_MPE;
1546 reg_rctl &= ~E1000_RCTL_SBP;
1547 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1551 emx_set_multi(struct emx_softc *sc)
1553 struct ifnet *ifp = &sc->arpcom.ac_if;
1554 struct ifmultiaddr *ifma;
1555 uint32_t reg_rctl = 0;
1556 uint8_t mta[512]; /* Largest MTS is 4096 bits */
1559 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1560 if (ifma->ifma_addr->sa_family != AF_LINK)
1563 if (mcnt == EMX_MCAST_ADDR_MAX)
1566 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1567 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
1571 if (mcnt >= EMX_MCAST_ADDR_MAX) {
1572 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1573 reg_rctl |= E1000_RCTL_MPE;
1574 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1576 e1000_update_mc_addr_list(&sc->hw, mta,
1577 mcnt, 1, sc->hw.mac.rar_entry_count);
1582 * This routine checks for link status and updates statistics.
1585 emx_timer(void *xsc)
1587 struct emx_softc *sc = xsc;
1588 struct ifnet *ifp = &sc->arpcom.ac_if;
1590 ifnet_serialize_all(ifp);
1592 emx_update_link_status(sc);
1593 emx_update_stats(sc);
1595 /* Reset LAA into RAR[0] on 82571 */
1596 if (e1000_get_laa_state_82571(&sc->hw) == TRUE)
1597 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1599 if (emx_display_debug_stats && (ifp->if_flags & IFF_RUNNING))
1600 emx_print_hw_stats(sc);
1604 callout_reset(&sc->timer, hz, emx_timer, sc);
1606 ifnet_deserialize_all(ifp);
1610 emx_update_link_status(struct emx_softc *sc)
1612 struct e1000_hw *hw = &sc->hw;
1613 struct ifnet *ifp = &sc->arpcom.ac_if;
1614 device_t dev = sc->dev;
1615 uint32_t link_check = 0;
1617 /* Get the cached link value or read phy for real */
1618 switch (hw->phy.media_type) {
1619 case e1000_media_type_copper:
1620 if (hw->mac.get_link_status) {
1621 /* Do the work to read phy */
1622 e1000_check_for_link(hw);
1623 link_check = !hw->mac.get_link_status;
1624 if (link_check) /* ESB2 fix */
1625 e1000_cfg_on_link_up(hw);
1631 case e1000_media_type_fiber:
1632 e1000_check_for_link(hw);
1633 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1636 case e1000_media_type_internal_serdes:
1637 e1000_check_for_link(hw);
1638 link_check = sc->hw.mac.serdes_has_link;
1641 case e1000_media_type_unknown:
1646 /* Now check for a transition */
1647 if (link_check && sc->link_active == 0) {
1648 e1000_get_speed_and_duplex(hw, &sc->link_speed,
1652 * Check if we should enable/disable SPEED_MODE bit on
1655 if (hw->mac.type == e1000_82571 ||
1656 hw->mac.type == e1000_82572) {
1659 tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
1660 if (sc->link_speed != SPEED_1000)
1661 tarc0 &= ~EMX_TARC_SPEED_MODE;
1663 tarc0 |= EMX_TARC_SPEED_MODE;
1664 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
1667 device_printf(dev, "Link is up %d Mbps %s\n",
1669 ((sc->link_duplex == FULL_DUPLEX) ?
1670 "Full Duplex" : "Half Duplex"));
1672 sc->link_active = 1;
1674 ifp->if_baudrate = sc->link_speed * 1000000;
1675 ifp->if_link_state = LINK_STATE_UP;
1676 if_link_state_change(ifp);
1677 } else if (!link_check && sc->link_active == 1) {
1678 ifp->if_baudrate = sc->link_speed = 0;
1679 sc->link_duplex = 0;
1681 device_printf(dev, "Link is Down\n");
1682 sc->link_active = 0;
1684 /* Link down, disable watchdog */
1687 ifp->if_link_state = LINK_STATE_DOWN;
1688 if_link_state_change(ifp);
1693 emx_stop(struct emx_softc *sc)
1695 struct ifnet *ifp = &sc->arpcom.ac_if;
1698 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1700 emx_disable_intr(sc);
1702 callout_stop(&sc->timer);
1704 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1708 * Disable multiple receive queues.
1711 * We should disable multiple receive queues before
1712 * resetting the hardware.
1714 E1000_WRITE_REG(&sc->hw, E1000_MRQC, 0);
1716 e1000_reset_hw(&sc->hw);
1717 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1719 for (i = 0; i < sc->num_tx_desc; i++) {
1720 struct emx_txbuf *tx_buffer = &sc->tx_buf[i];
1722 if (tx_buffer->m_head != NULL) {
1723 bus_dmamap_unload(sc->txtag, tx_buffer->map);
1724 m_freem(tx_buffer->m_head);
1725 tx_buffer->m_head = NULL;
1729 for (i = 0; i < sc->rx_ring_inuse; ++i)
1730 emx_free_rx_ring(sc, &sc->rx_data[i]);
1734 sc->csum_iphlen = 0;
1742 emx_hw_init(struct emx_softc *sc)
1744 device_t dev = sc->dev;
1745 uint16_t rx_buffer_size;
1747 /* Issue a global reset */
1748 e1000_reset_hw(&sc->hw);
1750 /* Get control from any management/hw control */
1751 if (sc->hw.mac.type == e1000_82573 &&
1752 e1000_check_mng_mode(&sc->hw))
1753 emx_get_hw_control(sc);
1755 /* Set up smart power down as default off on newer adapters. */
1756 if (!emx_smart_pwr_down &&
1757 (sc->hw.mac.type == e1000_82571 ||
1758 sc->hw.mac.type == e1000_82572)) {
1759 uint16_t phy_tmp = 0;
1761 /* Speed up time to link by disabling smart power down. */
1762 e1000_read_phy_reg(&sc->hw,
1763 IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
1764 phy_tmp &= ~IGP02E1000_PM_SPD;
1765 e1000_write_phy_reg(&sc->hw,
1766 IGP02E1000_PHY_POWER_MGMT, phy_tmp);
1770 * These parameters control the automatic generation (Tx) and
1771 * response (Rx) to Ethernet PAUSE frames.
1772 * - High water mark should allow for at least two frames to be
1773 * received after sending an XOFF.
1774 * - Low water mark works best when it is very near the high water mark.
1775 * This allows the receiver to restart by sending XON when it has
1776 * drained a bit. Here we use an arbitary value of 1500 which will
1777 * restart after one full frame is pulled from the buffer. There
1778 * could be several smaller frames in the buffer and if so they will
1779 * not trigger the XON until their total number reduces the buffer
1781 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1783 rx_buffer_size = (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) << 10;
1785 sc->hw.fc.high_water = rx_buffer_size -
1786 roundup2(sc->max_frame_size, 1024);
1787 sc->hw.fc.low_water = sc->hw.fc.high_water - 1500;
1789 if (sc->hw.mac.type == e1000_80003es2lan)
1790 sc->hw.fc.pause_time = 0xFFFF;
1792 sc->hw.fc.pause_time = EMX_FC_PAUSE_TIME;
1793 sc->hw.fc.send_xon = TRUE;
1794 sc->hw.fc.requested_mode = e1000_fc_full;
1796 if (e1000_init_hw(&sc->hw) < 0) {
1797 device_printf(dev, "Hardware Initialization Failed\n");
1801 e1000_check_for_link(&sc->hw);
1807 emx_setup_ifp(struct emx_softc *sc)
1809 struct ifnet *ifp = &sc->arpcom.ac_if;
1811 if_initname(ifp, device_get_name(sc->dev),
1812 device_get_unit(sc->dev));
1814 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1815 ifp->if_init = emx_init;
1816 ifp->if_ioctl = emx_ioctl;
1817 ifp->if_start = emx_start;
1818 #ifdef DEVICE_POLLING
1819 ifp->if_poll = emx_poll;
1821 ifp->if_watchdog = emx_watchdog;
1822 ifp->if_serialize = emx_serialize;
1823 ifp->if_deserialize = emx_deserialize;
1824 ifp->if_tryserialize = emx_tryserialize;
1826 ifp->if_serialize_assert = emx_serialize_assert;
1828 ifq_set_maxlen(&ifp->if_snd, sc->num_tx_desc - 1);
1829 ifq_set_ready(&ifp->if_snd);
1831 ether_ifattach(ifp, sc->hw.mac.addr, &sc->panic_serialize);
1833 ifp->if_capabilities = IFCAP_HWCSUM |
1834 IFCAP_VLAN_HWTAGGING |
1836 if (sc->rx_ring_cnt > 1)
1837 ifp->if_capabilities |= IFCAP_RSS;
1838 ifp->if_capenable = ifp->if_capabilities;
1839 ifp->if_hwassist = EMX_CSUM_FEATURES;
1842 * Tell the upper layer(s) we support long frames.
1844 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1847 * Specify the media types supported by this sc and register
1848 * callbacks to update media and link information
1850 ifmedia_init(&sc->media, IFM_IMASK,
1851 emx_media_change, emx_media_status);
1852 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1853 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1854 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1856 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1858 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1859 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1861 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1862 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1864 if (sc->hw.phy.type != e1000_phy_ife) {
1865 ifmedia_add(&sc->media,
1866 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1867 ifmedia_add(&sc->media,
1868 IFM_ETHER | IFM_1000_T, 0, NULL);
1871 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1872 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1876 * Workaround for SmartSpeed on 82541 and 82547 controllers
1879 emx_smartspeed(struct emx_softc *sc)
1883 if (sc->link_active || sc->hw.phy.type != e1000_phy_igp ||
1884 sc->hw.mac.autoneg == 0 ||
1885 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
1888 if (sc->smartspeed == 0) {
1890 * If Master/Slave config fault is asserted twice,
1891 * we assume back-to-back
1893 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
1894 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
1896 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
1897 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
1898 e1000_read_phy_reg(&sc->hw,
1899 PHY_1000T_CTRL, &phy_tmp);
1900 if (phy_tmp & CR_1000T_MS_ENABLE) {
1901 phy_tmp &= ~CR_1000T_MS_ENABLE;
1902 e1000_write_phy_reg(&sc->hw,
1903 PHY_1000T_CTRL, phy_tmp);
1905 if (sc->hw.mac.autoneg &&
1906 !e1000_phy_setup_autoneg(&sc->hw) &&
1907 !e1000_read_phy_reg(&sc->hw,
1908 PHY_CONTROL, &phy_tmp)) {
1909 phy_tmp |= MII_CR_AUTO_NEG_EN |
1910 MII_CR_RESTART_AUTO_NEG;
1911 e1000_write_phy_reg(&sc->hw,
1912 PHY_CONTROL, phy_tmp);
1917 } else if (sc->smartspeed == EMX_SMARTSPEED_DOWNSHIFT) {
1918 /* If still no link, perhaps using 2/3 pair cable */
1919 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp);
1920 phy_tmp |= CR_1000T_MS_ENABLE;
1921 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp);
1922 if (sc->hw.mac.autoneg &&
1923 !e1000_phy_setup_autoneg(&sc->hw) &&
1924 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) {
1925 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
1926 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp);
1930 /* Restart process after EMX_SMARTSPEED_MAX iterations */
1931 if (sc->smartspeed++ == EMX_SMARTSPEED_MAX)
1936 emx_create_tx_ring(struct emx_softc *sc)
1938 device_t dev = sc->dev;
1939 struct emx_txbuf *tx_buffer;
1940 int error, i, tsize;
1943 * Validate number of transmit descriptors. It must not exceed
1944 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
1946 if ((emx_txd * sizeof(struct e1000_tx_desc)) % EMX_DBA_ALIGN != 0 ||
1947 emx_txd > EMX_MAX_TXD || emx_txd < EMX_MIN_TXD) {
1948 device_printf(dev, "Using %d TX descriptors instead of %d!\n",
1949 EMX_DEFAULT_TXD, emx_txd);
1950 sc->num_tx_desc = EMX_DEFAULT_TXD;
1952 sc->num_tx_desc = emx_txd;
1956 * Allocate Transmit Descriptor ring
1958 tsize = roundup2(sc->num_tx_desc * sizeof(struct e1000_tx_desc),
1960 sc->tx_desc_base = bus_dmamem_coherent_any(sc->parent_dtag,
1961 EMX_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
1962 &sc->tx_desc_dtag, &sc->tx_desc_dmap,
1963 &sc->tx_desc_paddr);
1964 if (sc->tx_desc_base == NULL) {
1965 device_printf(dev, "Unable to allocate tx_desc memory\n");
1969 sc->tx_buf = kmalloc(sizeof(struct emx_txbuf) * sc->num_tx_desc,
1970 M_DEVBUF, M_WAITOK | M_ZERO);
1973 * Create DMA tags for tx buffers
1975 error = bus_dma_tag_create(sc->parent_dtag, /* parent */
1976 1, 0, /* alignment, bounds */
1977 BUS_SPACE_MAXADDR, /* lowaddr */
1978 BUS_SPACE_MAXADDR, /* highaddr */
1979 NULL, NULL, /* filter, filterarg */
1980 EMX_TSO_SIZE, /* maxsize */
1981 EMX_MAX_SCATTER, /* nsegments */
1982 EMX_MAX_SEGSIZE, /* maxsegsize */
1983 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
1984 BUS_DMA_ONEBPAGE, /* flags */
1987 device_printf(dev, "Unable to allocate TX DMA tag\n");
1988 kfree(sc->tx_buf, M_DEVBUF);
1994 * Create DMA maps for tx buffers
1996 for (i = 0; i < sc->num_tx_desc; i++) {
1997 tx_buffer = &sc->tx_buf[i];
1999 error = bus_dmamap_create(sc->txtag,
2000 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2003 device_printf(dev, "Unable to create TX DMA map\n");
2004 emx_destroy_tx_ring(sc, i);
2012 emx_init_tx_ring(struct emx_softc *sc)
2014 /* Clear the old ring contents */
2015 bzero(sc->tx_desc_base,
2016 sizeof(struct e1000_tx_desc) * sc->num_tx_desc);
2019 sc->next_avail_tx_desc = 0;
2020 sc->next_tx_to_clean = 0;
2021 sc->num_tx_desc_avail = sc->num_tx_desc;
2025 emx_init_tx_unit(struct emx_softc *sc)
2027 uint32_t tctl, tarc, tipg = 0;
2030 /* Setup the Base and Length of the Tx Descriptor Ring */
2031 bus_addr = sc->tx_desc_paddr;
2032 E1000_WRITE_REG(&sc->hw, E1000_TDLEN(0),
2033 sc->num_tx_desc * sizeof(struct e1000_tx_desc));
2034 E1000_WRITE_REG(&sc->hw, E1000_TDBAH(0),
2035 (uint32_t)(bus_addr >> 32));
2036 E1000_WRITE_REG(&sc->hw, E1000_TDBAL(0),
2037 (uint32_t)bus_addr);
2038 /* Setup the HW Tx Head and Tail descriptor pointers */
2039 E1000_WRITE_REG(&sc->hw, E1000_TDT(0), 0);
2040 E1000_WRITE_REG(&sc->hw, E1000_TDH(0), 0);
2042 /* Set the default values for the Tx Inter Packet Gap timer */
2043 switch (sc->hw.mac.type) {
2044 case e1000_80003es2lan:
2045 tipg = DEFAULT_82543_TIPG_IPGR1;
2046 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
2047 E1000_TIPG_IPGR2_SHIFT;
2051 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
2052 sc->hw.phy.media_type == e1000_media_type_internal_serdes)
2053 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
2055 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
2056 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2057 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2061 E1000_WRITE_REG(&sc->hw, E1000_TIPG, tipg);
2063 /* NOTE: 0 is not allowed for TIDV */
2064 E1000_WRITE_REG(&sc->hw, E1000_TIDV, 1);
2065 E1000_WRITE_REG(&sc->hw, E1000_TADV, 0);
2067 if (sc->hw.mac.type == e1000_82571 ||
2068 sc->hw.mac.type == e1000_82572) {
2069 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2070 tarc |= EMX_TARC_SPEED_MODE;
2071 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2072 } else if (sc->hw.mac.type == e1000_80003es2lan) {
2073 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2075 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2076 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1));
2078 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc);
2081 /* Program the Transmit Control Register */
2082 tctl = E1000_READ_REG(&sc->hw, E1000_TCTL);
2083 tctl &= ~E1000_TCTL_CT;
2084 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2085 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2086 tctl |= E1000_TCTL_MULR;
2088 /* This write will effectively turn on the transmit unit. */
2089 E1000_WRITE_REG(&sc->hw, E1000_TCTL, tctl);
2093 emx_destroy_tx_ring(struct emx_softc *sc, int ndesc)
2095 struct emx_txbuf *tx_buffer;
2098 /* Free Transmit Descriptor ring */
2099 if (sc->tx_desc_base) {
2100 bus_dmamap_unload(sc->tx_desc_dtag, sc->tx_desc_dmap);
2101 bus_dmamem_free(sc->tx_desc_dtag, sc->tx_desc_base,
2103 bus_dma_tag_destroy(sc->tx_desc_dtag);
2105 sc->tx_desc_base = NULL;
2108 if (sc->tx_buf == NULL)
2111 for (i = 0; i < ndesc; i++) {
2112 tx_buffer = &sc->tx_buf[i];
2114 KKASSERT(tx_buffer->m_head == NULL);
2115 bus_dmamap_destroy(sc->txtag, tx_buffer->map);
2117 bus_dma_tag_destroy(sc->txtag);
2119 kfree(sc->tx_buf, M_DEVBUF);
2124 * The offload context needs to be set when we transfer the first
2125 * packet of a particular protocol (TCP/UDP). This routine has been
2126 * enhanced to deal with inserted VLAN headers.
2128 * If the new packet's ether header length, ip header length and
2129 * csum offloading type are same as the previous packet, we should
2130 * avoid allocating a new csum context descriptor; mainly to take
2131 * advantage of the pipeline effect of the TX data read request.
2133 * This function returns number of TX descrptors allocated for
2137 emx_txcsum(struct emx_softc *sc, struct mbuf *mp,
2138 uint32_t *txd_upper, uint32_t *txd_lower)
2140 struct e1000_context_desc *TXD;
2141 struct emx_txbuf *tx_buffer;
2142 struct ether_vlan_header *eh;
2144 int curr_txd, ehdrlen, csum_flags;
2145 uint32_t cmd, hdr_len, ip_hlen;
2149 * Determine where frame payload starts.
2150 * Jump over vlan headers if already present,
2151 * helpful for QinQ too.
2153 KASSERT(mp->m_len >= ETHER_HDR_LEN,
2154 ("emx_txcsum_pullup is not called (eh)?\n"));
2155 eh = mtod(mp, struct ether_vlan_header *);
2156 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
2157 KASSERT(mp->m_len >= ETHER_HDR_LEN + EVL_ENCAPLEN,
2158 ("emx_txcsum_pullup is not called (evh)?\n"));
2159 etype = ntohs(eh->evl_proto);
2160 ehdrlen = ETHER_HDR_LEN + EVL_ENCAPLEN;
2162 etype = ntohs(eh->evl_encap_proto);
2163 ehdrlen = ETHER_HDR_LEN;
2167 * We only support TCP/UDP for IPv4 for the moment.
2168 * TODO: Support SCTP too when it hits the tree.
2170 if (etype != ETHERTYPE_IP)
2173 KASSERT(mp->m_len >= ehdrlen + EMX_IPVHL_SIZE,
2174 ("emx_txcsum_pullup is not called (eh+ip_vhl)?\n"));
2176 /* NOTE: We could only safely access ip.ip_vhl part */
2177 ip = (struct ip *)(mp->m_data + ehdrlen);
2178 ip_hlen = ip->ip_hl << 2;
2180 csum_flags = mp->m_pkthdr.csum_flags & EMX_CSUM_FEATURES;
2182 if (sc->csum_ehlen == ehdrlen && sc->csum_iphlen == ip_hlen &&
2183 sc->csum_flags == csum_flags) {
2185 * Same csum offload context as the previous packets;
2188 *txd_upper = sc->csum_txd_upper;
2189 *txd_lower = sc->csum_txd_lower;
2194 * Setup a new csum offload context.
2197 curr_txd = sc->next_avail_tx_desc;
2198 tx_buffer = &sc->tx_buf[curr_txd];
2199 TXD = (struct e1000_context_desc *)&sc->tx_desc_base[curr_txd];
2203 /* Setup of IP header checksum. */
2204 if (csum_flags & CSUM_IP) {
2206 * Start offset for header checksum calculation.
2207 * End offset for header checksum calculation.
2208 * Offset of place to put the checksum.
2210 TXD->lower_setup.ip_fields.ipcss = ehdrlen;
2211 TXD->lower_setup.ip_fields.ipcse =
2212 htole16(ehdrlen + ip_hlen - 1);
2213 TXD->lower_setup.ip_fields.ipcso =
2214 ehdrlen + offsetof(struct ip, ip_sum);
2215 cmd |= E1000_TXD_CMD_IP;
2216 *txd_upper |= E1000_TXD_POPTS_IXSM << 8;
2218 hdr_len = ehdrlen + ip_hlen;
2220 if (csum_flags & CSUM_TCP) {
2222 * Start offset for payload checksum calculation.
2223 * End offset for payload checksum calculation.
2224 * Offset of place to put the checksum.
2226 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2227 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2228 TXD->upper_setup.tcp_fields.tucso =
2229 hdr_len + offsetof(struct tcphdr, th_sum);
2230 cmd |= E1000_TXD_CMD_TCP;
2231 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2232 } else if (csum_flags & CSUM_UDP) {
2234 * Start offset for header checksum calculation.
2235 * End offset for header checksum calculation.
2236 * Offset of place to put the checksum.
2238 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2239 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2240 TXD->upper_setup.tcp_fields.tucso =
2241 hdr_len + offsetof(struct udphdr, uh_sum);
2242 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2245 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
2246 E1000_TXD_DTYP_D; /* Data descr */
2248 /* Save the information for this csum offloading context */
2249 sc->csum_ehlen = ehdrlen;
2250 sc->csum_iphlen = ip_hlen;
2251 sc->csum_flags = csum_flags;
2252 sc->csum_txd_upper = *txd_upper;
2253 sc->csum_txd_lower = *txd_lower;
2255 TXD->tcp_seg_setup.data = htole32(0);
2256 TXD->cmd_and_length =
2257 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd);
2259 if (++curr_txd == sc->num_tx_desc)
2262 KKASSERT(sc->num_tx_desc_avail > 0);
2263 sc->num_tx_desc_avail--;
2265 sc->next_avail_tx_desc = curr_txd;
2270 emx_txcsum_pullup(struct emx_softc *sc, struct mbuf **m0)
2272 struct mbuf *m = *m0;
2273 struct ether_header *eh;
2276 sc->tx_csum_try_pullup++;
2278 len = ETHER_HDR_LEN + EMX_IPVHL_SIZE;
2280 if (__predict_false(!M_WRITABLE(m))) {
2281 if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
2282 sc->tx_csum_drop1++;
2287 eh = mtod(m, struct ether_header *);
2289 if (eh->ether_type == htons(ETHERTYPE_VLAN))
2290 len += EVL_ENCAPLEN;
2292 if (m->m_len < len) {
2293 sc->tx_csum_drop2++;
2301 if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
2302 sc->tx_csum_pullup1++;
2303 m = m_pullup(m, ETHER_HDR_LEN);
2305 sc->tx_csum_pullup1_failed++;
2311 eh = mtod(m, struct ether_header *);
2313 if (eh->ether_type == htons(ETHERTYPE_VLAN))
2314 len += EVL_ENCAPLEN;
2316 if (m->m_len < len) {
2317 sc->tx_csum_pullup2++;
2318 m = m_pullup(m, len);
2320 sc->tx_csum_pullup2_failed++;
2330 emx_txeof(struct emx_softc *sc)
2332 struct ifnet *ifp = &sc->arpcom.ac_if;
2333 struct emx_txbuf *tx_buffer;
2334 int first, num_avail;
2336 if (sc->tx_dd_head == sc->tx_dd_tail)
2339 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2342 num_avail = sc->num_tx_desc_avail;
2343 first = sc->next_tx_to_clean;
2345 while (sc->tx_dd_head != sc->tx_dd_tail) {
2346 int dd_idx = sc->tx_dd[sc->tx_dd_head];
2347 struct e1000_tx_desc *tx_desc;
2349 tx_desc = &sc->tx_desc_base[dd_idx];
2350 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) {
2351 EMX_INC_TXDD_IDX(sc->tx_dd_head);
2353 if (++dd_idx == sc->num_tx_desc)
2356 while (first != dd_idx) {
2361 tx_buffer = &sc->tx_buf[first];
2362 if (tx_buffer->m_head) {
2364 bus_dmamap_unload(sc->txtag,
2366 m_freem(tx_buffer->m_head);
2367 tx_buffer->m_head = NULL;
2370 if (++first == sc->num_tx_desc)
2377 sc->next_tx_to_clean = first;
2378 sc->num_tx_desc_avail = num_avail;
2380 if (sc->tx_dd_head == sc->tx_dd_tail) {
2385 if (!EMX_IS_OACTIVE(sc)) {
2386 ifp->if_flags &= ~IFF_OACTIVE;
2388 /* All clean, turn off the timer */
2389 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2395 emx_tx_collect(struct emx_softc *sc)
2397 struct ifnet *ifp = &sc->arpcom.ac_if;
2398 struct emx_txbuf *tx_buffer;
2399 int tdh, first, num_avail, dd_idx = -1;
2401 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2404 tdh = E1000_READ_REG(&sc->hw, E1000_TDH(0));
2405 if (tdh == sc->next_tx_to_clean)
2408 if (sc->tx_dd_head != sc->tx_dd_tail)
2409 dd_idx = sc->tx_dd[sc->tx_dd_head];
2411 num_avail = sc->num_tx_desc_avail;
2412 first = sc->next_tx_to_clean;
2414 while (first != tdh) {
2419 tx_buffer = &sc->tx_buf[first];
2420 if (tx_buffer->m_head) {
2422 bus_dmamap_unload(sc->txtag,
2424 m_freem(tx_buffer->m_head);
2425 tx_buffer->m_head = NULL;
2428 if (first == dd_idx) {
2429 EMX_INC_TXDD_IDX(sc->tx_dd_head);
2430 if (sc->tx_dd_head == sc->tx_dd_tail) {
2435 dd_idx = sc->tx_dd[sc->tx_dd_head];
2439 if (++first == sc->num_tx_desc)
2442 sc->next_tx_to_clean = first;
2443 sc->num_tx_desc_avail = num_avail;
2445 if (!EMX_IS_OACTIVE(sc)) {
2446 ifp->if_flags &= ~IFF_OACTIVE;
2448 /* All clean, turn off the timer */
2449 if (sc->num_tx_desc_avail == sc->num_tx_desc)
2455 * When Link is lost sometimes there is work still in the TX ring
2456 * which will result in a watchdog, rather than allow that do an
2457 * attempted cleanup and then reinit here. Note that this has been
2458 * seens mostly with fiber adapters.
2461 emx_tx_purge(struct emx_softc *sc)
2463 struct ifnet *ifp = &sc->arpcom.ac_if;
2465 if (!sc->link_active && ifp->if_timer) {
2467 if (ifp->if_timer) {
2468 if_printf(ifp, "Link lost, TX pending, reinit\n");
2476 emx_newbuf(struct emx_softc *sc, struct emx_rxdata *rdata, int i, int init)
2479 bus_dma_segment_t seg;
2481 struct emx_rxbuf *rx_buffer;
2484 m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2486 rdata->mbuf_cluster_failed++;
2488 if_printf(&sc->arpcom.ac_if,
2489 "Unable to allocate RX mbuf\n");
2493 m->m_len = m->m_pkthdr.len = MCLBYTES;
2495 if (sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2496 m_adj(m, ETHER_ALIGN);
2498 error = bus_dmamap_load_mbuf_segment(rdata->rxtag,
2499 rdata->rx_sparemap, m,
2500 &seg, 1, &nseg, BUS_DMA_NOWAIT);
2504 if_printf(&sc->arpcom.ac_if,
2505 "Unable to load RX mbuf\n");
2510 rx_buffer = &rdata->rx_buf[i];
2511 if (rx_buffer->m_head != NULL)
2512 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
2514 map = rx_buffer->map;
2515 rx_buffer->map = rdata->rx_sparemap;
2516 rdata->rx_sparemap = map;
2518 rx_buffer->m_head = m;
2519 rx_buffer->paddr = seg.ds_addr;
2521 emx_setup_rxdesc(&rdata->rx_desc[i], rx_buffer);
2526 emx_create_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata)
2528 device_t dev = sc->dev;
2529 struct emx_rxbuf *rx_buffer;
2530 int i, error, rsize;
2533 * Validate number of receive descriptors. It must not exceed
2534 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
2536 if ((emx_rxd * sizeof(emx_rxdesc_t)) % EMX_DBA_ALIGN != 0 ||
2537 emx_rxd > EMX_MAX_RXD || emx_rxd < EMX_MIN_RXD) {
2538 device_printf(dev, "Using %d RX descriptors instead of %d!\n",
2539 EMX_DEFAULT_RXD, emx_rxd);
2540 rdata->num_rx_desc = EMX_DEFAULT_RXD;
2542 rdata->num_rx_desc = emx_rxd;
2546 * Allocate Receive Descriptor ring
2548 rsize = roundup2(rdata->num_rx_desc * sizeof(emx_rxdesc_t),
2550 rdata->rx_desc = bus_dmamem_coherent_any(sc->parent_dtag,
2551 EMX_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
2552 &rdata->rx_desc_dtag, &rdata->rx_desc_dmap,
2553 &rdata->rx_desc_paddr);
2554 if (rdata->rx_desc == NULL) {
2555 device_printf(dev, "Unable to allocate rx_desc memory\n");
2559 rdata->rx_buf = kmalloc(sizeof(struct emx_rxbuf) * rdata->num_rx_desc,
2560 M_DEVBUF, M_WAITOK | M_ZERO);
2563 * Create DMA tag for rx buffers
2565 error = bus_dma_tag_create(sc->parent_dtag, /* parent */
2566 1, 0, /* alignment, bounds */
2567 BUS_SPACE_MAXADDR, /* lowaddr */
2568 BUS_SPACE_MAXADDR, /* highaddr */
2569 NULL, NULL, /* filter, filterarg */
2570 MCLBYTES, /* maxsize */
2572 MCLBYTES, /* maxsegsize */
2573 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
2576 device_printf(dev, "Unable to allocate RX DMA tag\n");
2577 kfree(rdata->rx_buf, M_DEVBUF);
2578 rdata->rx_buf = NULL;
2583 * Create spare DMA map for rx buffers
2585 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
2586 &rdata->rx_sparemap);
2588 device_printf(dev, "Unable to create spare RX DMA map\n");
2589 bus_dma_tag_destroy(rdata->rxtag);
2590 kfree(rdata->rx_buf, M_DEVBUF);
2591 rdata->rx_buf = NULL;
2596 * Create DMA maps for rx buffers
2598 for (i = 0; i < rdata->num_rx_desc; i++) {
2599 rx_buffer = &rdata->rx_buf[i];
2601 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
2604 device_printf(dev, "Unable to create RX DMA map\n");
2605 emx_destroy_rx_ring(sc, rdata, i);
2613 emx_free_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata)
2617 for (i = 0; i < rdata->num_rx_desc; i++) {
2618 struct emx_rxbuf *rx_buffer = &rdata->rx_buf[i];
2620 if (rx_buffer->m_head != NULL) {
2621 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
2622 m_freem(rx_buffer->m_head);
2623 rx_buffer->m_head = NULL;
2627 if (rdata->fmp != NULL)
2628 m_freem(rdata->fmp);
2634 emx_init_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata)
2638 /* Reset descriptor ring */
2639 bzero(rdata->rx_desc, sizeof(emx_rxdesc_t) * rdata->num_rx_desc);
2641 /* Allocate new ones. */
2642 for (i = 0; i < rdata->num_rx_desc; i++) {
2643 error = emx_newbuf(sc, rdata, i, 1);
2648 /* Setup our descriptor pointers */
2649 rdata->next_rx_desc_to_check = 0;
2655 emx_init_rx_unit(struct emx_softc *sc)
2657 struct ifnet *ifp = &sc->arpcom.ac_if;
2659 uint32_t rctl, rxcsum, rfctl;
2663 * Make sure receives are disabled while setting
2664 * up the descriptor ring
2666 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
2667 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2670 * Set the interrupt throttling rate. Value is calculated
2671 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns)
2673 if (sc->int_throttle_ceil) {
2674 E1000_WRITE_REG(&sc->hw, E1000_ITR,
2675 1000000000 / 256 / sc->int_throttle_ceil);
2677 E1000_WRITE_REG(&sc->hw, E1000_ITR, 0);
2680 /* Use extended RX descriptor */
2681 rfctl = E1000_RFCTL_EXTEN;
2683 /* Disable accelerated ackknowledge */
2684 if (sc->hw.mac.type == e1000_82574)
2685 rfctl |= E1000_RFCTL_ACK_DIS;
2687 E1000_WRITE_REG(&sc->hw, E1000_RFCTL, rfctl);
2689 /* Setup the Base and Length of the Rx Descriptor Ring */
2690 for (i = 0; i < sc->rx_ring_inuse; ++i) {
2691 struct emx_rxdata *rdata = &sc->rx_data[i];
2693 bus_addr = rdata->rx_desc_paddr;
2694 E1000_WRITE_REG(&sc->hw, E1000_RDLEN(i),
2695 rdata->num_rx_desc * sizeof(emx_rxdesc_t));
2696 E1000_WRITE_REG(&sc->hw, E1000_RDBAH(i),
2697 (uint32_t)(bus_addr >> 32));
2698 E1000_WRITE_REG(&sc->hw, E1000_RDBAL(i),
2699 (uint32_t)bus_addr);
2702 /* Setup the Receive Control Register */
2703 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2704 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2705 E1000_RCTL_RDMTS_HALF | E1000_RCTL_SECRC |
2706 (sc->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2708 /* Make sure VLAN Filters are off */
2709 rctl &= ~E1000_RCTL_VFE;
2711 /* Don't store bad paket */
2712 rctl &= ~E1000_RCTL_SBP;
2715 rctl |= E1000_RCTL_SZ_2048;
2717 if (ifp->if_mtu > ETHERMTU)
2718 rctl |= E1000_RCTL_LPE;
2720 rctl &= ~E1000_RCTL_LPE;
2723 * Receive Checksum Offload for TCP and UDP
2725 * Checksum offloading is also enabled if multiple receive
2726 * queue is to be supported, since we need it to figure out
2729 if (ifp->if_capenable & (IFCAP_RSS | IFCAP_RXCSUM)) {
2730 rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
2734 * PCSD must be enabled to enable multiple
2737 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2739 E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2743 * Configure multiple receive queue (RSS)
2745 if (ifp->if_capenable & IFCAP_RSS) {
2746 uint8_t key[EMX_NRSSRK * EMX_RSSRK_SIZE];
2749 KASSERT(sc->rx_ring_inuse == EMX_NRX_RING,
2750 ("invalid number of RX ring (%d)",
2751 sc->rx_ring_inuse));
2755 * When we reach here, RSS has already been disabled
2756 * in emx_stop(), so we could safely configure RSS key
2757 * and redirect table.
2763 toeplitz_get_key(key, sizeof(key));
2764 for (i = 0; i < EMX_NRSSRK; ++i) {
2767 rssrk = EMX_RSSRK_VAL(key, i);
2768 EMX_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2770 E1000_WRITE_REG(&sc->hw, E1000_RSSRK(i), rssrk);
2774 * Configure RSS redirect table in following fashion:
2775 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2778 for (i = 0; i < EMX_RETA_SIZE; ++i) {
2781 q = (i % sc->rx_ring_inuse) << EMX_RETA_RINGIDX_SHIFT;
2782 reta |= q << (8 * i);
2784 EMX_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2786 for (i = 0; i < EMX_NRETA; ++i)
2787 E1000_WRITE_REG(&sc->hw, E1000_RETA(i), reta);
2790 * Enable multiple receive queues.
2791 * Enable IPv4 RSS standard hash functions.
2792 * Disable RSS interrupt.
2794 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
2795 E1000_MRQC_ENABLE_RSS_2Q |
2796 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2797 E1000_MRQC_RSS_FIELD_IPV4);
2801 * XXX TEMPORARY WORKAROUND: on some systems with 82573
2802 * long latencies are observed, like Lenovo X60. This
2803 * change eliminates the problem, but since having positive
2804 * values in RDTR is a known source of problems on other
2805 * platforms another solution is being sought.
2807 if (emx_82573_workaround && sc->hw.mac.type == e1000_82573) {
2808 E1000_WRITE_REG(&sc->hw, E1000_RADV, EMX_RADV_82573);
2809 E1000_WRITE_REG(&sc->hw, E1000_RDTR, EMX_RDTR_82573);
2813 * Setup the HW Rx Head and Tail Descriptor Pointers
2815 for (i = 0; i < sc->rx_ring_inuse; ++i) {
2816 E1000_WRITE_REG(&sc->hw, E1000_RDH(i), 0);
2817 E1000_WRITE_REG(&sc->hw, E1000_RDT(i),
2818 sc->rx_data[i].num_rx_desc - 1);
2821 /* Enable Receives */
2822 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl);
2826 emx_destroy_rx_ring(struct emx_softc *sc, struct emx_rxdata *rdata, int ndesc)
2828 struct emx_rxbuf *rx_buffer;
2831 /* Free Receive Descriptor ring */
2832 if (rdata->rx_desc) {
2833 bus_dmamap_unload(rdata->rx_desc_dtag, rdata->rx_desc_dmap);
2834 bus_dmamem_free(rdata->rx_desc_dtag, rdata->rx_desc,
2835 rdata->rx_desc_dmap);
2836 bus_dma_tag_destroy(rdata->rx_desc_dtag);
2838 rdata->rx_desc = NULL;
2841 if (rdata->rx_buf == NULL)
2844 for (i = 0; i < ndesc; i++) {
2845 rx_buffer = &rdata->rx_buf[i];
2847 KKASSERT(rx_buffer->m_head == NULL);
2848 bus_dmamap_destroy(rdata->rxtag, rx_buffer->map);
2850 bus_dmamap_destroy(rdata->rxtag, rdata->rx_sparemap);
2851 bus_dma_tag_destroy(rdata->rxtag);
2853 kfree(rdata->rx_buf, M_DEVBUF);
2854 rdata->rx_buf = NULL;
2858 emx_rxeof(struct emx_softc *sc, int ring_idx, int count)
2860 struct emx_rxdata *rdata = &sc->rx_data[ring_idx];
2861 struct ifnet *ifp = &sc->arpcom.ac_if;
2863 emx_rxdesc_t *current_desc;
2866 struct mbuf_chain chain[MAXCPU];
2868 i = rdata->next_rx_desc_to_check;
2869 current_desc = &rdata->rx_desc[i];
2870 staterr = le32toh(current_desc->rxd_staterr);
2872 if (!(staterr & E1000_RXD_STAT_DD))
2875 ether_input_chain_init(chain);
2877 while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
2878 struct pktinfo *pi = NULL, pi0;
2879 struct emx_rxbuf *rx_buf = &rdata->rx_buf[i];
2880 struct mbuf *m = NULL;
2885 mp = rx_buf->m_head;
2888 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT
2889 * needs to access the last received byte in the mbuf.
2891 bus_dmamap_sync(rdata->rxtag, rx_buf->map,
2892 BUS_DMASYNC_POSTREAD);
2894 len = le16toh(current_desc->rxd_length);
2895 if (staterr & E1000_RXD_STAT_EOP) {
2902 if (!(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
2904 uint32_t mrq, rss_hash;
2907 * Save several necessary information,
2908 * before emx_newbuf() destroy it.
2910 if ((staterr & E1000_RXD_STAT_VP) && eop)
2911 vlan = le16toh(current_desc->rxd_vlan);
2913 mrq = le32toh(current_desc->rxd_mrq);
2914 rss_hash = le32toh(current_desc->rxd_rss);
2916 EMX_RSS_DPRINTF(sc, 10,
2917 "ring%d, mrq 0x%08x, rss_hash 0x%08x\n",
2918 ring_idx, mrq, rss_hash);
2920 if (emx_newbuf(sc, rdata, i, 0) != 0) {
2925 /* Assign correct length to the current fragment */
2928 if (rdata->fmp == NULL) {
2929 mp->m_pkthdr.len = len;
2930 rdata->fmp = mp; /* Store the first mbuf */
2934 * Chain mbuf's together
2936 rdata->lmp->m_next = mp;
2937 rdata->lmp = rdata->lmp->m_next;
2938 rdata->fmp->m_pkthdr.len += len;
2942 rdata->fmp->m_pkthdr.rcvif = ifp;
2945 if (ifp->if_capenable & IFCAP_RXCSUM)
2946 emx_rxcsum(staterr, rdata->fmp);
2948 if (staterr & E1000_RXD_STAT_VP) {
2949 rdata->fmp->m_pkthdr.ether_vlantag =
2951 rdata->fmp->m_flags |= M_VLANTAG;
2957 if (ifp->if_capenable & IFCAP_RSS) {
2958 pi = emx_rssinfo(m, &pi0, mrq,
2961 #ifdef EMX_RSS_DEBUG
2968 emx_setup_rxdesc(current_desc, rx_buf);
2969 if (rdata->fmp != NULL) {
2970 m_freem(rdata->fmp);
2978 ether_input_chain(ifp, m, pi, chain);
2980 /* Advance our pointers to the next descriptor. */
2981 if (++i == rdata->num_rx_desc)
2984 current_desc = &rdata->rx_desc[i];
2985 staterr = le32toh(current_desc->rxd_staterr);
2987 rdata->next_rx_desc_to_check = i;
2989 ether_input_dispatch(chain);
2991 /* Advance the E1000's Receive Queue "Tail Pointer". */
2993 i = rdata->num_rx_desc - 1;
2994 E1000_WRITE_REG(&sc->hw, E1000_RDT(ring_idx), i);
2998 emx_enable_intr(struct emx_softc *sc)
3000 lwkt_serialize_handler_enable(&sc->main_serialize);
3001 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
3005 emx_disable_intr(struct emx_softc *sc)
3007 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
3008 lwkt_serialize_handler_disable(&sc->main_serialize);
3012 * Bit of a misnomer, what this really means is
3013 * to enable OS management of the system... aka
3014 * to disable special hardware management features
3017 emx_get_mgmt(struct emx_softc *sc)
3019 /* A shared code workaround */
3020 if (sc->has_manage) {
3021 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
3022 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3024 /* disable hardware interception of ARP */
3025 manc &= ~(E1000_MANC_ARP_EN);
3027 /* enable receiving management packets to the host */
3028 manc |= E1000_MANC_EN_MNG2HOST;
3029 #define E1000_MNG2HOST_PORT_623 (1 << 5)
3030 #define E1000_MNG2HOST_PORT_664 (1 << 6)
3031 manc2h |= E1000_MNG2HOST_PORT_623;
3032 manc2h |= E1000_MNG2HOST_PORT_664;
3033 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
3035 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3040 * Give control back to hardware management
3041 * controller if there is one.
3044 emx_rel_mgmt(struct emx_softc *sc)
3046 if (sc->has_manage) {
3047 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3049 /* re-enable hardware interception of ARP */
3050 manc |= E1000_MANC_ARP_EN;
3051 manc &= ~E1000_MANC_EN_MNG2HOST;
3053 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3058 * emx_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3059 * For ASF and Pass Through versions of f/w this means that
3060 * the driver is loaded. For AMT version (only with 82573)
3061 * of the f/w this means that the network i/f is open.
3064 emx_get_hw_control(struct emx_softc *sc)
3066 uint32_t ctrl_ext, swsm;
3068 /* Let firmware know the driver has taken over */
3069 switch (sc->hw.mac.type) {
3071 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3072 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3073 swsm | E1000_SWSM_DRV_LOAD);
3078 case e1000_80003es2lan:
3079 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3080 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3081 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
3090 * emx_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3091 * For ASF and Pass Through versions of f/w this means that the
3092 * driver is no longer loaded. For AMT version (only with 82573)
3093 * of the f/w this means that the network i/f is closed.
3096 emx_rel_hw_control(struct emx_softc *sc)
3098 uint32_t ctrl_ext, swsm;
3100 /* Let firmware taken over control of h/w */
3101 switch (sc->hw.mac.type) {
3103 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3104 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3105 swsm & ~E1000_SWSM_DRV_LOAD);
3110 case e1000_80003es2lan:
3111 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3112 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3113 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
3122 emx_is_valid_eaddr(const uint8_t *addr)
3124 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
3126 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
3133 * Enable PCI Wake On Lan capability
3136 emx_enable_wol(device_t dev)
3138 uint16_t cap, status;
3141 /* First find the capabilities pointer*/
3142 cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
3144 /* Read the PM Capabilities */
3145 id = pci_read_config(dev, cap, 1);
3146 if (id != PCIY_PMG) /* Something wrong */
3150 * OK, we have the power capabilities,
3151 * so now get the status register
3153 cap += PCIR_POWER_STATUS;
3154 status = pci_read_config(dev, cap, 2);
3155 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3156 pci_write_config(dev, cap, status, 2);
3160 emx_update_stats(struct emx_softc *sc)
3162 struct ifnet *ifp = &sc->arpcom.ac_if;
3164 if (sc->hw.phy.media_type == e1000_media_type_copper ||
3165 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) {
3166 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS);
3167 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC);
3169 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS);
3170 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC);
3171 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC);
3172 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL);
3174 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC);
3175 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL);
3176 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC);
3177 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC);
3178 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC);
3179 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC);
3180 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC);
3181 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC);
3182 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC);
3183 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC);
3184 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64);
3185 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127);
3186 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255);
3187 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511);
3188 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023);
3189 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522);
3190 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC);
3191 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC);
3192 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC);
3193 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC);
3195 /* For the 64-bit byte counters the low dword must be read first. */
3196 /* Both registers clear on the read of the high dword */
3198 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCH);
3199 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCH);
3201 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC);
3202 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC);
3203 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC);
3204 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC);
3205 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC);
3207 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH);
3208 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH);
3210 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR);
3211 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT);
3212 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64);
3213 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127);
3214 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255);
3215 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511);
3216 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023);
3217 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522);
3218 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC);
3219 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC);
3221 sc->stats.algnerrc += E1000_READ_REG(&sc->hw, E1000_ALGNERRC);
3222 sc->stats.rxerrc += E1000_READ_REG(&sc->hw, E1000_RXERRC);
3223 sc->stats.tncrs += E1000_READ_REG(&sc->hw, E1000_TNCRS);
3224 sc->stats.cexterr += E1000_READ_REG(&sc->hw, E1000_CEXTERR);
3225 sc->stats.tsctc += E1000_READ_REG(&sc->hw, E1000_TSCTC);
3226 sc->stats.tsctfc += E1000_READ_REG(&sc->hw, E1000_TSCTFC);
3228 ifp->if_collisions = sc->stats.colc;
3231 ifp->if_ierrors = sc->dropped_pkts + sc->stats.rxerrc +
3232 sc->stats.crcerrs + sc->stats.algnerrc +
3233 sc->stats.ruc + sc->stats.roc +
3234 sc->stats.mpc + sc->stats.cexterr;
3237 ifp->if_oerrors = sc->stats.ecol + sc->stats.latecol +
3238 sc->watchdog_events;
3242 emx_print_debug_info(struct emx_softc *sc)
3244 device_t dev = sc->dev;
3245 uint8_t *hw_addr = sc->hw.hw_addr;
3247 device_printf(dev, "Adapter hardware address = %p \n", hw_addr);
3248 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n",
3249 E1000_READ_REG(&sc->hw, E1000_CTRL),
3250 E1000_READ_REG(&sc->hw, E1000_RCTL));
3251 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n",
3252 ((E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff0000) >> 16),\
3253 (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) );
3254 device_printf(dev, "Flow control watermarks high = %d low = %d\n",
3255 sc->hw.fc.high_water, sc->hw.fc.low_water);
3256 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n",
3257 E1000_READ_REG(&sc->hw, E1000_TIDV),
3258 E1000_READ_REG(&sc->hw, E1000_TADV));
3259 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n",
3260 E1000_READ_REG(&sc->hw, E1000_RDTR),
3261 E1000_READ_REG(&sc->hw, E1000_RADV));
3262 device_printf(dev, "hw tdh = %d, hw tdt = %d\n",
3263 E1000_READ_REG(&sc->hw, E1000_TDH(0)),
3264 E1000_READ_REG(&sc->hw, E1000_TDT(0)));
3265 device_printf(dev, "hw rdh = %d, hw rdt = %d\n",
3266 E1000_READ_REG(&sc->hw, E1000_RDH(0)),
3267 E1000_READ_REG(&sc->hw, E1000_RDT(0)));
3268 device_printf(dev, "Num Tx descriptors avail = %d\n",
3269 sc->num_tx_desc_avail);
3270 device_printf(dev, "Tx Descriptors not avail1 = %ld\n",
3271 sc->no_tx_desc_avail1);
3272 device_printf(dev, "Tx Descriptors not avail2 = %ld\n",
3273 sc->no_tx_desc_avail2);
3274 device_printf(dev, "Std mbuf failed = %ld\n",
3275 sc->mbuf_alloc_failed);
3276 device_printf(dev, "Std mbuf cluster failed = %ld\n",
3277 sc->rx_data[0].mbuf_cluster_failed);
3278 device_printf(dev, "Driver dropped packets = %ld\n",
3280 device_printf(dev, "Driver tx dma failure in encap = %ld\n",
3281 sc->no_tx_dma_setup);
3283 device_printf(dev, "TXCSUM try pullup = %lu\n",
3284 sc->tx_csum_try_pullup);
3285 device_printf(dev, "TXCSUM m_pullup(eh) called = %lu\n",
3286 sc->tx_csum_pullup1);
3287 device_printf(dev, "TXCSUM m_pullup(eh) failed = %lu\n",
3288 sc->tx_csum_pullup1_failed);
3289 device_printf(dev, "TXCSUM m_pullup(eh+ip) called = %lu\n",
3290 sc->tx_csum_pullup2);
3291 device_printf(dev, "TXCSUM m_pullup(eh+ip) failed = %lu\n",
3292 sc->tx_csum_pullup2_failed);
3293 device_printf(dev, "TXCSUM non-writable(eh) droped = %lu\n",
3295 device_printf(dev, "TXCSUM non-writable(eh+ip) droped = %lu\n",
3300 emx_print_hw_stats(struct emx_softc *sc)
3302 device_t dev = sc->dev;
3304 device_printf(dev, "Excessive collisions = %lld\n",
3305 (long long)sc->stats.ecol);
3306 #if (DEBUG_HW > 0) /* Dont output these errors normally */
3307 device_printf(dev, "Symbol errors = %lld\n",
3308 (long long)sc->stats.symerrs);
3310 device_printf(dev, "Sequence errors = %lld\n",
3311 (long long)sc->stats.sec);
3312 device_printf(dev, "Defer count = %lld\n",
3313 (long long)sc->stats.dc);
3314 device_printf(dev, "Missed Packets = %lld\n",
3315 (long long)sc->stats.mpc);
3316 device_printf(dev, "Receive No Buffers = %lld\n",
3317 (long long)sc->stats.rnbc);
3318 /* RLEC is inaccurate on some hardware, calculate our own. */
3319 device_printf(dev, "Receive Length Errors = %lld\n",
3320 ((long long)sc->stats.roc + (long long)sc->stats.ruc));
3321 device_printf(dev, "Receive errors = %lld\n",
3322 (long long)sc->stats.rxerrc);
3323 device_printf(dev, "Crc errors = %lld\n",
3324 (long long)sc->stats.crcerrs);
3325 device_printf(dev, "Alignment errors = %lld\n",
3326 (long long)sc->stats.algnerrc);
3327 device_printf(dev, "Collision/Carrier extension errors = %lld\n",
3328 (long long)sc->stats.cexterr);
3329 device_printf(dev, "RX overruns = %ld\n", sc->rx_overruns);
3330 device_printf(dev, "watchdog timeouts = %ld\n",
3331 sc->watchdog_events);
3332 device_printf(dev, "XON Rcvd = %lld\n",
3333 (long long)sc->stats.xonrxc);
3334 device_printf(dev, "XON Xmtd = %lld\n",
3335 (long long)sc->stats.xontxc);
3336 device_printf(dev, "XOFF Rcvd = %lld\n",
3337 (long long)sc->stats.xoffrxc);
3338 device_printf(dev, "XOFF Xmtd = %lld\n",
3339 (long long)sc->stats.xofftxc);
3340 device_printf(dev, "Good Packets Rcvd = %lld\n",
3341 (long long)sc->stats.gprc);
3342 device_printf(dev, "Good Packets Xmtd = %lld\n",
3343 (long long)sc->stats.gptc);
3347 emx_print_nvm_info(struct emx_softc *sc)
3349 uint16_t eeprom_data;
3352 /* Its a bit crude, but it gets the job done */
3353 kprintf("\nInterface EEPROM Dump:\n");
3354 kprintf("Offset\n0x0000 ");
3355 for (i = 0, j = 0; i < 32; i++, j++) {
3356 if (j == 8) { /* Make the offset block */
3358 kprintf("\n0x00%x0 ",row);
3360 e1000_read_nvm(&sc->hw, i, 1, &eeprom_data);
3361 kprintf("%04x ", eeprom_data);
3367 emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
3369 struct emx_softc *sc;
3374 error = sysctl_handle_int(oidp, &result, 0, req);
3375 if (error || !req->newptr)
3378 sc = (struct emx_softc *)arg1;
3379 ifp = &sc->arpcom.ac_if;
3381 ifnet_serialize_all(ifp);
3384 emx_print_debug_info(sc);
3387 * This value will cause a hex dump of the
3388 * first 32 16-bit words of the EEPROM to
3392 emx_print_nvm_info(sc);
3394 ifnet_deserialize_all(ifp);
3400 emx_sysctl_stats(SYSCTL_HANDLER_ARGS)
3405 error = sysctl_handle_int(oidp, &result, 0, req);
3406 if (error || !req->newptr)
3410 struct emx_softc *sc = (struct emx_softc *)arg1;
3411 struct ifnet *ifp = &sc->arpcom.ac_if;
3413 ifnet_serialize_all(ifp);
3414 emx_print_hw_stats(sc);
3415 ifnet_deserialize_all(ifp);
3421 emx_add_sysctl(struct emx_softc *sc)
3423 #ifdef PROFILE_SERIALIZER
3424 struct ifnet *ifp = &sc->arpcom.ac_if;
3426 #ifdef EMX_RSS_DEBUG
3431 sysctl_ctx_init(&sc->sysctl_ctx);
3432 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
3433 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
3434 device_get_nameunit(sc->dev),
3436 if (sc->sysctl_tree == NULL) {
3437 device_printf(sc->dev, "can't add sysctl node\n");
3441 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3442 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3443 emx_sysctl_debug_info, "I", "Debug Information");
3445 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3446 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3447 emx_sysctl_stats, "I", "Statistics");
3449 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3450 OID_AUTO, "rxd", CTLFLAG_RD,
3451 &sc->rx_data[0].num_rx_desc, 0, NULL);
3452 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3453 OID_AUTO, "txd", CTLFLAG_RD, &sc->num_tx_desc, 0, NULL);
3456 #ifdef PROFILE_SERIALIZER
3457 SYSCTL_ADD_UINT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3458 OID_AUTO, "serializer_sleep", CTLFLAG_RW,
3459 &ifp->if_serializer->sleep_cnt, 0, NULL);
3460 SYSCTL_ADD_UINT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3461 OID_AUTO, "serializer_tryfail", CTLFLAG_RW,
3462 &ifp->if_serializer->tryfail_cnt, 0, NULL);
3463 SYSCTL_ADD_UINT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3464 OID_AUTO, "serializer_enter", CTLFLAG_RW,
3465 &ifp->if_serializer->enter_cnt, 0, NULL);
3466 SYSCTL_ADD_UINT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3467 OID_AUTO, "serializer_try", CTLFLAG_RW,
3468 &ifp->if_serializer->try_cnt, 0, NULL);
3472 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3473 OID_AUTO, "int_throttle_ceil", CTLTYPE_INT|CTLFLAG_RW,
3474 sc, 0, emx_sysctl_int_throttle, "I",
3475 "interrupt throttling rate");
3476 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3477 OID_AUTO, "int_tx_nsegs", CTLTYPE_INT|CTLFLAG_RW,
3478 sc, 0, emx_sysctl_int_tx_nsegs, "I",
3479 "# segments per TX interrupt");
3481 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3482 OID_AUTO, "rx_ring_inuse", CTLFLAG_RD,
3483 &sc->rx_ring_inuse, 0, "RX ring in use");
3485 #ifdef EMX_RSS_DEBUG
3486 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
3487 OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug,
3488 0, "RSS debug level");
3489 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3490 ksnprintf(rx_pkt, sizeof(rx_pkt), "rx%d_pkt", i);
3491 SYSCTL_ADD_UINT(&sc->sysctl_ctx,
3492 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO,
3494 &sc->rx_data[i].rx_pkts, 0, "RXed packets");
3500 emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS)
3502 struct emx_softc *sc = (void *)arg1;
3503 struct ifnet *ifp = &sc->arpcom.ac_if;
3504 int error, throttle;
3506 throttle = sc->int_throttle_ceil;
3507 error = sysctl_handle_int(oidp, &throttle, 0, req);
3508 if (error || req->newptr == NULL)
3510 if (throttle < 0 || throttle > 1000000000 / 256)
3515 * Set the interrupt throttling rate in 256ns increments,
3516 * recalculate sysctl value assignment to get exact frequency.
3518 throttle = 1000000000 / 256 / throttle;
3520 /* Upper 16bits of ITR is reserved and should be zero */
3521 if (throttle & 0xffff0000)
3525 ifnet_serialize_all(ifp);
3528 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
3530 sc->int_throttle_ceil = 0;
3532 if (ifp->if_flags & IFF_RUNNING)
3533 E1000_WRITE_REG(&sc->hw, E1000_ITR, throttle);
3535 ifnet_deserialize_all(ifp);
3538 if_printf(ifp, "Interrupt moderation set to %d/sec\n",
3539 sc->int_throttle_ceil);
3545 emx_sysctl_int_tx_nsegs(SYSCTL_HANDLER_ARGS)
3547 struct emx_softc *sc = (void *)arg1;
3548 struct ifnet *ifp = &sc->arpcom.ac_if;
3551 segs = sc->tx_int_nsegs;
3552 error = sysctl_handle_int(oidp, &segs, 0, req);
3553 if (error || req->newptr == NULL)
3558 ifnet_serialize_all(ifp);
3561 * Don't allow int_tx_nsegs to become:
3562 * o Less the oact_tx_desc
3563 * o Too large that no TX desc will cause TX interrupt to
3564 * be generated (OACTIVE will never recover)
3565 * o Too small that will cause tx_dd[] overflow
3567 if (segs < sc->oact_tx_desc ||
3568 segs >= sc->num_tx_desc - sc->oact_tx_desc ||
3569 segs < sc->num_tx_desc / EMX_TXDD_SAFE) {
3573 sc->tx_int_nsegs = segs;
3576 ifnet_deserialize_all(ifp);
3582 emx_dma_alloc(struct emx_softc *sc)
3587 * Create top level busdma tag
3589 error = bus_dma_tag_create(NULL, 1, 0,
3590 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3592 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
3593 0, &sc->parent_dtag);
3595 device_printf(sc->dev, "could not create top level DMA tag\n");
3600 * Allocate transmit descriptors ring and buffers
3602 error = emx_create_tx_ring(sc);
3604 device_printf(sc->dev, "Could not setup transmit structures\n");
3609 * Allocate receive descriptors ring and buffers
3611 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3612 error = emx_create_rx_ring(sc, &sc->rx_data[i]);
3614 device_printf(sc->dev,
3615 "Could not setup receive structures\n");
3623 emx_dma_free(struct emx_softc *sc)
3627 emx_destroy_tx_ring(sc, sc->num_tx_desc);
3629 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3630 emx_destroy_rx_ring(sc, &sc->rx_data[i],
3631 sc->rx_data[i].num_rx_desc);
3634 /* Free top level busdma tag */
3635 if (sc->parent_dtag != NULL)
3636 bus_dma_tag_destroy(sc->parent_dtag);
3640 emx_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3642 struct emx_softc *sc = ifp->if_softc;
3645 case IFNET_SERIALIZE_ALL:
3646 lwkt_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, 0);
3649 case IFNET_SERIALIZE_MAIN:
3650 lwkt_serialize_enter(&sc->main_serialize);
3653 case IFNET_SERIALIZE_TX:
3654 lwkt_serialize_enter(&sc->tx_serialize);
3657 case IFNET_SERIALIZE_RX(0):
3658 lwkt_serialize_enter(&sc->rx_data[0].rx_serialize);
3661 case IFNET_SERIALIZE_RX(1):
3662 lwkt_serialize_enter(&sc->rx_data[1].rx_serialize);
3666 panic("%s unsupported serialize type\n", ifp->if_xname);
3671 emx_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3673 struct emx_softc *sc = ifp->if_softc;
3676 case IFNET_SERIALIZE_ALL:
3677 lwkt_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, 0);
3680 case IFNET_SERIALIZE_MAIN:
3681 lwkt_serialize_exit(&sc->main_serialize);
3684 case IFNET_SERIALIZE_TX:
3685 lwkt_serialize_exit(&sc->tx_serialize);
3688 case IFNET_SERIALIZE_RX(0):
3689 lwkt_serialize_exit(&sc->rx_data[0].rx_serialize);
3692 case IFNET_SERIALIZE_RX(1):
3693 lwkt_serialize_exit(&sc->rx_data[1].rx_serialize);
3697 panic("%s unsupported serialize type\n", ifp->if_xname);
3702 emx_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3704 struct emx_softc *sc = ifp->if_softc;
3707 case IFNET_SERIALIZE_ALL:
3708 return lwkt_serialize_array_try(sc->serializes,
3711 case IFNET_SERIALIZE_MAIN:
3712 return lwkt_serialize_try(&sc->main_serialize);
3714 case IFNET_SERIALIZE_TX:
3715 return lwkt_serialize_try(&sc->tx_serialize);
3717 case IFNET_SERIALIZE_RX(0):
3718 return lwkt_serialize_try(&sc->rx_data[0].rx_serialize);
3720 case IFNET_SERIALIZE_RX(1):
3721 return lwkt_serialize_try(&sc->rx_data[1].rx_serialize);
3724 panic("%s unsupported serialize type\n", ifp->if_xname);
3729 emx_serialize_skipmain(struct emx_softc *sc)
3731 lwkt_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, 1);
3735 emx_tryserialize_skipmain(struct emx_softc *sc)
3737 return lwkt_serialize_array_try(sc->serializes, EMX_NSERIALIZE, 1);
3741 emx_deserialize_skipmain(struct emx_softc *sc)
3743 lwkt_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, 1);
3749 emx_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3750 boolean_t serialized)
3752 struct emx_softc *sc = ifp->if_softc;
3756 case IFNET_SERIALIZE_ALL:
3758 for (i = 0; i < EMX_NSERIALIZE; ++i)
3759 ASSERT_SERIALIZED(sc->serializes[i]);
3761 for (i = 0; i < EMX_NSERIALIZE; ++i)
3762 ASSERT_NOT_SERIALIZED(sc->serializes[i]);
3766 case IFNET_SERIALIZE_MAIN:
3768 ASSERT_SERIALIZED(&sc->main_serialize);
3770 ASSERT_NOT_SERIALIZED(&sc->main_serialize);
3773 case IFNET_SERIALIZE_TX:
3775 ASSERT_SERIALIZED(&sc->tx_serialize);
3777 ASSERT_NOT_SERIALIZED(&sc->tx_serialize);
3780 case IFNET_SERIALIZE_RX(0):
3782 ASSERT_SERIALIZED(&sc->rx_data[0].rx_serialize);
3784 ASSERT_NOT_SERIALIZED(&sc->rx_data[0].rx_serialize);
3787 case IFNET_SERIALIZE_RX(1):
3789 ASSERT_SERIALIZED(&sc->rx_data[1].rx_serialize);
3791 ASSERT_NOT_SERIALIZED(&sc->rx_data[1].rx_serialize);
3795 panic("%s unsupported serialize type\n", ifp->if_xname);
3799 #endif /* INVARIANTS */