2 * Copyright (c) 2001 Scott Long <scottl@freebsd.org>
3 * Copyright (c) 2001 Darrell Anderson <anderson@cs.duke.edu>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * $FreeBSD: src/sys/dev/sound/pci/maestro3.c,v 1.2.2.11 2002/09/16 19:52:33 scottl Exp $
28 * $DragonFly: src/sys/dev/sound/pci/maestro3.c,v 1.4 2003/08/15 08:32:31 dillon Exp $
32 * Maestro-3/Allegro FreeBSD pcm sound driver
34 * executive status summary:
35 * (+) /dev/dsp multiple concurrent play channels.
36 * (+) /dev/dsp config (speed, mono/stereo, 8/16 bit).
37 * (+) /dev/mixer sets left/right volumes.
38 * (+) /dev/dsp recording works. Tested successfully with the cdrom channel
39 * (+) apm suspend/resume works, and works properly!.
40 * (-) hardware volme controls don't work =-(
41 * (-) setblocksize() does nothing.
43 * The real credit goes to:
45 * Zach Brown for his Linux driver core and helpful technical comments.
46 * <zab@zabbo.net>, http://www.zabbo.net/maestro3
48 * Cameron Grant created the pcm framework used here nearly verbatim.
49 * <cg@freebsd.org>, http://people.freebsd.org/~cg/template.c
51 * Taku YAMAMOTO for his Maestro-1/2 FreeBSD driver and sanity reference.
52 * <taku@cent.saitama-u.ac.jp>
54 * ESS docs explained a few magic registers and numbers.
55 * http://virgo.caltech.edu/~dmoore/maestro3.pdf.gz
58 #include <dev/sound/pcm/sound.h>
59 #include <dev/sound/pcm/ac97.h>
61 #include <bus/pci/pcireg.h>
62 #include <bus/pci/pcivar.h>
64 #include "gnu/maestro3_reg.h"
65 #include "gnu/maestro3_dsp.h"
67 SND_DECLARE_FILE("$DragonFly: src/sys/dev/sound/pci/maestro3.c,v 1.4 2003/08/15 08:32:31 dillon Exp $");
69 /* -------------------------------------------------------------------- */
71 enum {CHANGE=0, CALL=1, INTR=2, BORING=3, NONE=-1};
72 #ifndef M3_DEBUG_LEVEL
73 #define M3_DEBUG_LEVEL NONE
75 #define M3_DEBUG(level, _msg) {if ((level) <= M3_DEBUG_LEVEL) {printf _msg;}}
77 /* -------------------------------------------------------------------- */
83 static struct m3_card_type {
84 u_int32_t pci_id; int which; int delay1; int delay2; char *name;
86 { 0x1988125d, ESS_ALLEGRO_1, 50, 800, "ESS Technology Allegro-1" },
87 { 0x1998125d, ESS_MAESTRO3, 20, 500, "ESS Technology Maestro3" },
88 { 0x199a125d, ESS_MAESTRO3, 20, 500, "ESS Technology Maestro3" },
92 #define M3_BUFSIZE_DEFAULT 4096
93 #define M3_PCHANS 4 /* create /dev/dsp0.[0-N] to use more than one */
95 #define M3_MAXADDR ((1 << 27) - 1)
102 struct snd_dbuf *buffer;
103 struct pcm_channel *channel;
104 struct sc_info *parent;
114 struct snd_dbuf *buffer;
115 struct pcm_channel *channel;
116 struct sc_info *parent;
131 bus_space_handle_t sh;
132 bus_dma_tag_t parent_dmat;
134 struct resource *reg;
135 struct resource *irq;
141 struct sc_pchinfo pch[M3_PCHANS];
142 struct sc_rchinfo rch[M3_RCHANS];
150 /* -------------------------------------------------------------------- */
152 /* play channel interface */
153 static void *m3_pchan_init(kobj_t, void *, struct snd_dbuf *, struct pcm_channel *, int);
154 static int m3_pchan_free(kobj_t, void *);
155 static int m3_pchan_setformat(kobj_t, void *, u_int32_t);
156 static int m3_pchan_setspeed(kobj_t, void *, u_int32_t);
157 static int m3_pchan_setblocksize(kobj_t, void *, u_int32_t);
158 static int m3_pchan_trigger(kobj_t, void *, int);
159 static int m3_pchan_getptr(kobj_t, void *);
160 static struct pcmchan_caps *m3_pchan_getcaps(kobj_t, void *);
162 /* record channel interface */
163 static void *m3_rchan_init(kobj_t, void *, struct snd_dbuf *, struct pcm_channel *, int);
164 static int m3_rchan_free(kobj_t, void *);
165 static int m3_rchan_setformat(kobj_t, void *, u_int32_t);
166 static int m3_rchan_setspeed(kobj_t, void *, u_int32_t);
167 static int m3_rchan_setblocksize(kobj_t, void *, u_int32_t);
168 static int m3_rchan_trigger(kobj_t, void *, int);
169 static int m3_rchan_getptr(kobj_t, void *);
170 static struct pcmchan_caps *m3_rchan_getcaps(kobj_t, void *);
172 /* talk to the codec - called from ac97.c */
173 static int m3_initcd(kobj_t, void *);
174 static int m3_rdcd(kobj_t, void *, int);
175 static int m3_wrcd(kobj_t, void *, int, u_int32_t);
178 static void m3_intr(void *);
179 static int m3_power(struct sc_info *, int);
180 static int m3_init(struct sc_info *);
181 static int m3_uninit(struct sc_info *);
182 static u_int8_t m3_assp_halt(struct sc_info *);
183 static void m3_config(struct sc_info *);
184 static void m3_amp_enable(struct sc_info *);
185 static void m3_enable_ints(struct sc_info *);
186 static void m3_codec_reset(struct sc_info *);
188 /* -------------------------------------------------------------------- */
189 /* Codec descriptor */
190 static kobj_method_t m3_codec_methods[] = {
191 KOBJMETHOD(ac97_init, m3_initcd),
192 KOBJMETHOD(ac97_read, m3_rdcd),
193 KOBJMETHOD(ac97_write, m3_wrcd),
196 AC97_DECLARE(m3_codec);
198 /* -------------------------------------------------------------------- */
199 /* channel descriptors */
201 static u_int32_t m3_playfmt[] = {
203 AFMT_STEREO | AFMT_U8,
205 AFMT_STEREO | AFMT_S16_LE,
208 static struct pcmchan_caps m3_playcaps = {8000, 48000, m3_playfmt, 0};
210 static kobj_method_t m3_pch_methods[] = {
211 KOBJMETHOD(channel_init, m3_pchan_init),
212 KOBJMETHOD(channel_setformat, m3_pchan_setformat),
213 KOBJMETHOD(channel_setspeed, m3_pchan_setspeed),
214 KOBJMETHOD(channel_setblocksize, m3_pchan_setblocksize),
215 KOBJMETHOD(channel_trigger, m3_pchan_trigger),
216 KOBJMETHOD(channel_getptr, m3_pchan_getptr),
217 KOBJMETHOD(channel_getcaps, m3_pchan_getcaps),
218 KOBJMETHOD(channel_free, m3_pchan_free),
221 CHANNEL_DECLARE(m3_pch);
223 static u_int32_t m3_recfmt[] = {
225 AFMT_STEREO | AFMT_U8,
227 AFMT_STEREO | AFMT_S16_LE,
230 static struct pcmchan_caps m3_reccaps = {8000, 48000, m3_recfmt, 0};
232 static kobj_method_t m3_rch_methods[] = {
233 KOBJMETHOD(channel_init, m3_rchan_init),
234 KOBJMETHOD(channel_setformat, m3_rchan_setformat),
235 KOBJMETHOD(channel_setspeed, m3_rchan_setspeed),
236 KOBJMETHOD(channel_setblocksize, m3_rchan_setblocksize),
237 KOBJMETHOD(channel_trigger, m3_rchan_trigger),
238 KOBJMETHOD(channel_getptr, m3_rchan_getptr),
239 KOBJMETHOD(channel_getcaps, m3_rchan_getcaps),
240 KOBJMETHOD(channel_free, m3_rchan_free),
243 CHANNEL_DECLARE(m3_rch);
245 /* -------------------------------------------------------------------- */
246 /* some i/o convenience functions */
248 #define m3_rd_1(sc, regno) bus_space_read_1(sc->st, sc->sh, regno)
249 #define m3_rd_2(sc, regno) bus_space_read_2(sc->st, sc->sh, regno)
250 #define m3_rd_4(sc, regno) bus_space_read_4(sc->st, sc->sh, regno)
251 #define m3_wr_1(sc, regno, data) bus_space_write_1(sc->st, sc->sh, regno, data)
252 #define m3_wr_2(sc, regno, data) bus_space_write_2(sc->st, sc->sh, regno, data)
253 #define m3_wr_4(sc, regno, data) bus_space_write_4(sc->st, sc->sh, regno, data)
254 #define m3_rd_assp_code(sc, index) \
255 m3_rd_assp(sc, MEMTYPE_INTERNAL_CODE, index)
256 #define m3_wr_assp_code(sc, index, data) \
257 m3_wr_assp(sc, MEMTYPE_INTERNAL_CODE, index, data)
258 #define m3_rd_assp_data(sc, index) \
259 m3_rd_assp(sc, MEMTYPE_INTERNAL_DATA, index)
260 #define m3_wr_assp_data(sc, index, data) \
261 m3_wr_assp(sc, MEMTYPE_INTERNAL_DATA, index, data)
263 static __inline u_int16_t
264 m3_rd_assp(struct sc_info *sc, u_int16_t region, u_int16_t index)
266 m3_wr_2(sc, DSP_PORT_MEMORY_TYPE, region & MEMTYPE_MASK);
267 m3_wr_2(sc, DSP_PORT_MEMORY_INDEX, index);
268 return m3_rd_2(sc, DSP_PORT_MEMORY_DATA);
272 m3_wr_assp(struct sc_info *sc, u_int16_t region, u_int16_t index,
275 m3_wr_2(sc, DSP_PORT_MEMORY_TYPE, region & MEMTYPE_MASK);
276 m3_wr_2(sc, DSP_PORT_MEMORY_INDEX, index);
277 m3_wr_2(sc, DSP_PORT_MEMORY_DATA, data);
281 m3_wait(struct sc_info *sc)
285 for (i=0 ; i<20 ; i++) {
286 if ((m3_rd_1(sc, CODEC_STATUS) & 1) == 0) {
294 /* -------------------------------------------------------------------- */
298 m3_initcd(kobj_t kobj, void *devinfo)
300 struct sc_info *sc = (struct sc_info *)devinfo;
303 M3_DEBUG(CALL, ("m3_initcd\n"));
307 data = m3_rd_1(sc, CODEC_COMMAND);
308 return ((data & 0x1) ? 0 : 1);
312 m3_rdcd(kobj_t kobj, void *devinfo, int regno)
314 struct sc_info *sc = (struct sc_info *)devinfo;
318 device_printf(sc->dev, "m3_rdcd timed out.\n");
321 m3_wr_1(sc, CODEC_COMMAND, (regno & 0x7f) | 0x80);
322 DELAY(50); /* ac97 cycle = 20.8 usec */
324 device_printf(sc->dev, "m3_rdcd timed out.\n");
327 data = m3_rd_2(sc, CODEC_DATA);
332 m3_wrcd(kobj_t kobj, void *devinfo, int regno, u_int32_t data)
334 struct sc_info *sc = (struct sc_info *)devinfo;
336 device_printf(sc->dev, "m3_wrcd timed out.\n");
339 m3_wr_2(sc, CODEC_DATA, data);
340 m3_wr_1(sc, CODEC_COMMAND, regno & 0x7f);
341 DELAY(50); /* ac97 cycle = 20.8 usec */
345 /* -------------------------------------------------------------------- */
346 /* play channel interface */
348 #define LO(x) (((x) & 0x0000ffff) )
349 #define HI(x) (((x) & 0xffff0000) >> 16)
352 m3_pchan_init(kobj_t kobj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
354 struct sc_info *sc = devinfo;
355 struct sc_pchinfo *ch;
356 u_int32_t bus_addr, i;
358 int idx = sc->pch_cnt; /* dac instance number, no active reuse! */
359 int data_bytes = (((MINISRC_TMP_BUFFER_SIZE & ~1) +
360 (MINISRC_IN_BUFFER_SIZE & ~1) +
361 (MINISRC_OUT_BUFFER_SIZE & ~1) + 4) + 255) &~ 255;
362 int dac_data = 0x1100 + (data_bytes * idx);
364 int dsp_in_size = MINISRC_IN_BUFFER_SIZE - (0x20 * 2);
365 int dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x20 * 2);
366 int dsp_in_buf = dac_data + (MINISRC_TMP_BUFFER_SIZE/2);
367 int dsp_out_buf = dsp_in_buf + (dsp_in_size/2) + 1;
369 M3_DEBUG(CHANGE, ("m3_pchan_init(dac=%d)\n", idx));
371 if (dir != PCMDIR_PLAY) {
372 device_printf(sc->dev, "m3_pchan_init not PCMDIR_PLAY\n");
378 ch->dac_data = dac_data;
379 if (ch->dac_data + data_bytes/2 >= 0x1c00) {
380 device_printf(sc->dev, "m3_pchan_init: revb mem exhausted\n");
388 ch->spd = DSP_DEFAULT_SPEED;
389 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, sc->bufsz) == -1) {
390 device_printf(sc->dev, "m3_pchan_init chn_allocbuf failed\n");
393 ch->bufsize = sndbuf_getsize(ch->buffer);
395 /* host dma buffer pointers */
396 bus_addr = vtophys(sndbuf_getbuf(ch->buffer));
398 device_printf(sc->dev, "m3_pchan_init unaligned bus_addr\n");
399 bus_addr = (bus_addr + 4) & ~3;
401 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_ADDRL, LO(bus_addr));
402 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_ADDRH, HI(bus_addr));
403 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_END_PLUS_1L,
404 LO(bus_addr + ch->bufsize));
405 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_END_PLUS_1H,
406 HI(bus_addr + ch->bufsize));
407 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTL,
409 m3_wr_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTH,
413 m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_BEGIN, dsp_in_buf);
414 m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_END_PLUS_1,
415 dsp_in_buf + dsp_in_size/2);
416 m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_HEAD, dsp_in_buf);
417 m3_wr_assp_data(sc, ch->dac_data + CDATA_IN_BUF_TAIL, dsp_in_buf);
418 m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_BEGIN, dsp_out_buf);
419 m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_END_PLUS_1,
420 dsp_out_buf + dsp_out_size/2);
421 m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_HEAD, dsp_out_buf);
422 m3_wr_assp_data(sc, ch->dac_data + CDATA_OUT_BUF_TAIL, dsp_out_buf);
424 /* some per client initializers */
425 m3_wr_assp_data(sc, ch->dac_data + SRC3_DIRECTION_OFFSET + 12,
426 ch->dac_data + 40 + 8);
427 m3_wr_assp_data(sc, ch->dac_data + SRC3_DIRECTION_OFFSET + 19,
428 0x400 + MINISRC_COEF_LOC);
429 /* enable or disable low pass filter? (0xff if rate> 45000) */
430 m3_wr_assp_data(sc, ch->dac_data + SRC3_DIRECTION_OFFSET + 22, 0);
431 /* tell it which way dma is going? */
432 m3_wr_assp_data(sc, ch->dac_data + CDATA_DMA_CONTROL,
433 DMACONTROL_AUTOREPEAT + DMAC_PAGE3_SELECTOR +
434 DMAC_BLOCKF_SELECTOR);
436 /* set an armload of static initializers */
437 for(i = 0 ; i < (sizeof(pv) / sizeof(pv[0])) ; i++) {
438 m3_wr_assp_data(sc, ch->dac_data + pv[i].addr, pv[i].val);
441 /* put us in the packed task lists */
442 m3_wr_assp_data(sc, KDATA_INSTANCE0_MINISRC +
443 (sc->pch_cnt + sc->rch_cnt),
444 ch->dac_data >> DP_SHIFT_COUNT);
445 m3_wr_assp_data(sc, KDATA_DMA_XFER0 + (sc->pch_cnt + sc->rch_cnt),
446 ch->dac_data >> DP_SHIFT_COUNT);
447 m3_wr_assp_data(sc, KDATA_MIXER_XFER0 + sc->pch_cnt,
448 ch->dac_data >> DP_SHIFT_COUNT);
450 m3_pchan_trigger(NULL, ch, PCMTRIG_START); /* gotta start before stop */
451 m3_pchan_trigger(NULL, ch, PCMTRIG_STOP); /* silence noise on load */
458 m3_pchan_free(kobj_t kobj, void *chdata)
460 struct sc_pchinfo *ch = chdata;
461 struct sc_info *sc = ch->parent;
463 M3_DEBUG(CHANGE, ("m3_pchan_free(dac=%d)\n", ch->dac_idx));
466 * should remove this exact instance from the packed lists, but all
467 * are released at once (and in a stopped state) so this is ok.
469 m3_wr_assp_data(sc, KDATA_INSTANCE0_MINISRC +
470 (sc->pch_cnt - 1) + sc->rch_cnt, 0);
471 m3_wr_assp_data(sc, KDATA_DMA_XFER0 +
472 (sc->pch_cnt - 1) + sc->rch_cnt, 0);
473 m3_wr_assp_data(sc, KDATA_MIXER_XFER0 + (sc->pch_cnt-1), 0);
480 m3_pchan_setformat(kobj_t kobj, void *chdata, u_int32_t format)
482 struct sc_pchinfo *ch = chdata;
483 struct sc_info *sc = ch->parent;
487 ("m3_pchan_setformat(dac=%d, format=0x%x{%s-%s})\n",
489 format & (AFMT_U8|AFMT_S8) ? "8bit":"16bit",
490 format & AFMT_STEREO ? "STEREO":"MONO"));
493 data = (format & AFMT_STEREO) ? 0 : 1;
494 m3_wr_assp_data(sc, ch->dac_data + SRC3_MODE_OFFSET, data);
497 data = ((format & AFMT_U8) || (format & AFMT_S8)) ? 1 : 0;
498 m3_wr_assp_data(sc, ch->dac_data + SRC3_WORD_LENGTH_OFFSET, data);
505 m3_pchan_setspeed(kobj_t kobj, void *chdata, u_int32_t speed)
507 struct sc_pchinfo *ch = chdata;
508 struct sc_info *sc = ch->parent;
511 M3_DEBUG(CHANGE, ("m3_pchan_setspeed(dac=%d, speed=%d)\n",
512 ch->dac_idx, speed));
514 if ((freq = ((speed << 15) + 24000) / 48000) != 0) {
518 m3_wr_assp_data(sc, ch->dac_data + CDATA_FREQUENCY, freq);
521 return speed; /* return closest possible speed */
525 m3_pchan_setblocksize(kobj_t kobj, void *chdata, u_int32_t blocksize)
527 struct sc_pchinfo *ch = chdata;
529 M3_DEBUG(CHANGE, ("m3_pchan_setblocksize(dac=%d, blocksize=%d)\n",
530 ch->dac_idx, blocksize));
536 m3_pchan_trigger(kobj_t kobj, void *chdata, int go)
538 struct sc_pchinfo *ch = chdata;
539 struct sc_info *sc = ch->parent;
542 M3_DEBUG(go == PCMTRIG_START ? CHANGE :
543 go == PCMTRIG_STOP ? CHANGE :
544 go == PCMTRIG_ABORT ? CHANGE :
546 ("m3_pchan_trigger(dac=%d, go=0x%x{%s})\n", ch->dac_idx, go,
547 go == PCMTRIG_START ? "PCMTRIG_START" :
548 go == PCMTRIG_STOP ? "PCMTRIG_STOP" :
549 go == PCMTRIG_ABORT ? "PCMTRIG_ABORT" : "ignore"));
557 sc->pch_active_cnt++;
559 /*[[inc_timer_users]]*/
560 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_RELOAD, 240);
561 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_CURRENT, 240);
562 data = m3_rd_2(sc, HOST_INT_CTRL);
563 m3_wr_2(sc, HOST_INT_CTRL, data | CLKRUN_GEN_ENABLE);
565 m3_wr_assp_data(sc, ch->dac_data + CDATA_INSTANCE_READY, 1);
566 m3_wr_assp_data(sc, KDATA_MIXER_TASK_NUMBER,
572 if (ch->active == 0) {
576 sc->pch_active_cnt--;
578 /* XXX should the channel be drained? */
579 /*[[dec_timer_users]]*/
580 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_RELOAD, 0);
581 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_CURRENT, 0);
582 data = m3_rd_2(sc, HOST_INT_CTRL);
583 m3_wr_2(sc, HOST_INT_CTRL, data & ~CLKRUN_GEN_ENABLE);
585 m3_wr_assp_data(sc, ch->dac_data + CDATA_INSTANCE_READY, 0);
586 m3_wr_assp_data(sc, KDATA_MIXER_TASK_NUMBER,
590 case PCMTRIG_EMLDMAWR:
591 /* got play irq, transfer next buffer - ignore if using dma */
592 case PCMTRIG_EMLDMARD:
593 /* got rec irq, transfer next buffer - ignore if using dma */
601 m3_pchan_getptr(kobj_t kobj, void *chdata)
603 struct sc_pchinfo *ch = chdata;
604 struct sc_info *sc = ch->parent;
605 u_int32_t hi, lo, bus_crnt;
606 u_int32_t bus_base = vtophys(sndbuf_getbuf(ch->buffer));
608 hi = m3_rd_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTH);
609 lo = m3_rd_assp_data(sc, ch->dac_data + CDATA_HOST_SRC_CURRENTL);
610 bus_crnt = lo | (hi << 16);
612 M3_DEBUG(CALL, ("m3_pchan_getptr(dac=%d) result=%d\n",
613 ch->dac_idx, bus_crnt - bus_base));
615 return (bus_crnt - bus_base); /* current byte offset of channel */
618 static struct pcmchan_caps *
619 m3_pchan_getcaps(kobj_t kobj, void *chdata)
621 struct sc_pchinfo *ch = chdata;
623 M3_DEBUG(CALL, ("m3_pchan_getcaps(dac=%d)\n", ch->dac_idx));
628 /* -------------------------------------------------------------------- */
629 /* rec channel interface */
632 m3_rchan_init(kobj_t kobj, void *devinfo, struct snd_dbuf *b, struct pcm_channel *c, int dir)
634 struct sc_info *sc = devinfo;
635 struct sc_rchinfo *ch;
636 u_int32_t bus_addr, i;
638 int idx = sc->rch_cnt; /* adc instance number, no active reuse! */
639 int data_bytes = (((MINISRC_TMP_BUFFER_SIZE & ~1) +
640 (MINISRC_IN_BUFFER_SIZE & ~1) +
641 (MINISRC_OUT_BUFFER_SIZE & ~1) + 4) + 255) &~ 255;
642 int adc_data = 0x1100 + (data_bytes * idx) + data_bytes/2;
644 int dsp_in_size = MINISRC_IN_BUFFER_SIZE + (0x10 * 2);
645 int dsp_out_size = MINISRC_OUT_BUFFER_SIZE - (0x10 * 2);
646 int dsp_in_buf = adc_data + (MINISRC_TMP_BUFFER_SIZE / 2);
647 int dsp_out_buf = dsp_in_buf + (dsp_in_size / 2) + 1;
649 M3_DEBUG(CHANGE, ("m3_rchan_init(adc=%d)\n", idx));
651 if (dir != PCMDIR_REC) {
652 device_printf(sc->dev, "m3_pchan_init not PCMDIR_REC\n");
658 ch->adc_data = adc_data;
659 if (ch->adc_data + data_bytes/2 >= 0x1c00) {
660 device_printf(sc->dev, "m3_rchan_init: revb mem exhausted\n");
668 ch->spd = DSP_DEFAULT_SPEED;
669 if (sndbuf_alloc(ch->buffer, sc->parent_dmat, sc->bufsz) == -1) {
670 device_printf(sc->dev, "m3_rchan_init chn_allocbuf failed\n");
673 ch->bufsize = sndbuf_getsize(ch->buffer);
675 /* host dma buffer pointers */
676 bus_addr = vtophys(sndbuf_getbuf(ch->buffer));
678 device_printf(sc->dev, "m3_rchan_init unaligned bus_addr\n");
679 bus_addr = (bus_addr + 4) & ~3;
681 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_ADDRL, LO(bus_addr));
682 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_ADDRH, HI(bus_addr));
683 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_END_PLUS_1L,
684 LO(bus_addr + ch->bufsize));
685 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_END_PLUS_1H,
686 HI(bus_addr + ch->bufsize));
687 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTL,
689 m3_wr_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTH,
693 m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_BEGIN, dsp_in_buf);
694 m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_END_PLUS_1,
695 dsp_in_buf + dsp_in_size/2);
696 m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_HEAD, dsp_in_buf);
697 m3_wr_assp_data(sc, ch->adc_data + CDATA_IN_BUF_TAIL, dsp_in_buf);
698 m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_BEGIN, dsp_out_buf);
699 m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_END_PLUS_1,
700 dsp_out_buf + dsp_out_size/2);
701 m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_HEAD, dsp_out_buf);
702 m3_wr_assp_data(sc, ch->adc_data + CDATA_OUT_BUF_TAIL, dsp_out_buf);
704 /* some per client initializers */
705 m3_wr_assp_data(sc, ch->adc_data + SRC3_DIRECTION_OFFSET + 12,
706 ch->adc_data + 40 + 8);
707 m3_wr_assp_data(sc, ch->adc_data + CDATA_DMA_CONTROL,
708 DMACONTROL_DIRECTION + DMACONTROL_AUTOREPEAT +
709 DMAC_PAGE3_SELECTOR + DMAC_BLOCKF_SELECTOR);
711 /* set an armload of static initializers */
712 for(i = 0 ; i < (sizeof(rv) / sizeof(rv[0])) ; i++) {
713 m3_wr_assp_data(sc, ch->adc_data + rv[i].addr, rv[i].val);
716 /* put us in the packed task lists */
717 m3_wr_assp_data(sc, KDATA_INSTANCE0_MINISRC +
718 (sc->pch_cnt + sc->rch_cnt),
719 ch->adc_data >> DP_SHIFT_COUNT);
720 m3_wr_assp_data(sc, KDATA_DMA_XFER0 + (sc->pch_cnt + sc->rch_cnt),
721 ch->adc_data >> DP_SHIFT_COUNT);
722 m3_wr_assp_data(sc, KDATA_ADC1_XFER0 + sc->rch_cnt,
723 ch->adc_data >> DP_SHIFT_COUNT);
725 m3_rchan_trigger(NULL, ch, PCMTRIG_START); /* gotta start before stop */
726 m3_rchan_trigger(NULL, ch, PCMTRIG_STOP); /* stop on init */
733 m3_rchan_free(kobj_t kobj, void *chdata)
735 struct sc_rchinfo *ch = chdata;
736 struct sc_info *sc = ch->parent;
738 M3_DEBUG(CHANGE, ("m3_rchan_free(adc=%d)\n", ch->adc_idx));
741 * should remove this exact instance from the packed lists, but all
742 * are released at once (and in a stopped state) so this is ok.
744 m3_wr_assp_data(sc, KDATA_INSTANCE0_MINISRC +
745 (sc->rch_cnt - 1) + sc->pch_cnt, 0);
746 m3_wr_assp_data(sc, KDATA_DMA_XFER0 +
747 (sc->rch_cnt - 1) + sc->pch_cnt, 0);
748 m3_wr_assp_data(sc, KDATA_ADC1_XFER0 + (sc->rch_cnt - 1), 0);
755 m3_rchan_setformat(kobj_t kobj, void *chdata, u_int32_t format)
757 struct sc_rchinfo *ch = chdata;
758 struct sc_info *sc = ch->parent;
762 ("m3_rchan_setformat(dac=%d, format=0x%x{%s-%s})\n",
764 format & (AFMT_U8|AFMT_S8) ? "8bit":"16bit",
765 format & AFMT_STEREO ? "STEREO":"MONO"));
768 data = (format & AFMT_STEREO) ? 0 : 1;
769 m3_wr_assp_data(sc, ch->adc_data + SRC3_MODE_OFFSET, data);
772 data = ((format & AFMT_U8) || (format & AFMT_S8)) ? 1 : 0;
773 m3_wr_assp_data(sc, ch->adc_data + SRC3_WORD_LENGTH_OFFSET, data);
780 m3_rchan_setspeed(kobj_t kobj, void *chdata, u_int32_t speed)
782 struct sc_rchinfo *ch = chdata;
783 struct sc_info *sc = ch->parent;
786 M3_DEBUG(CHANGE, ("m3_rchan_setspeed(adc=%d, speed=%d)\n",
787 ch->adc_idx, speed));
789 if ((freq = ((speed << 15) + 24000) / 48000) != 0) {
793 m3_wr_assp_data(sc, ch->adc_data + CDATA_FREQUENCY, freq);
796 return speed; /* return closest possible speed */
800 m3_rchan_setblocksize(kobj_t kobj, void *chdata, u_int32_t blocksize)
802 struct sc_rchinfo *ch = chdata;
804 M3_DEBUG(CHANGE, ("m3_rchan_setblocksize(adc=%d, blocksize=%d)\n",
805 ch->adc_idx, blocksize));
811 m3_rchan_trigger(kobj_t kobj, void *chdata, int go)
813 struct sc_rchinfo *ch = chdata;
814 struct sc_info *sc = ch->parent;
817 M3_DEBUG(go == PCMTRIG_START ? CHANGE :
818 go == PCMTRIG_STOP ? CHANGE :
819 go == PCMTRIG_ABORT ? CHANGE :
821 ("m3_rchan_trigger(adc=%d, go=0x%x{%s})\n", ch->adc_idx, go,
822 go == PCMTRIG_START ? "PCMTRIG_START" :
823 go == PCMTRIG_STOP ? "PCMTRIG_STOP" :
824 go == PCMTRIG_ABORT ? "PCMTRIG_ABORT" : "ignore"));
833 /*[[inc_timer_users]]*/
834 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_RELOAD, 240);
835 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_CURRENT, 240);
836 data = m3_rd_2(sc, HOST_INT_CTRL);
837 m3_wr_2(sc, HOST_INT_CTRL, data | CLKRUN_GEN_ENABLE);
839 m3_wr_assp_data(sc, KDATA_ADC1_REQUEST, 1);
840 m3_wr_assp_data(sc, ch->adc_data + CDATA_INSTANCE_READY, 1);
845 if (ch->active == 0) {
850 /*[[dec_timer_users]]*/
851 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_RELOAD, 0);
852 m3_wr_assp_data(sc, KDATA_TIMER_COUNT_CURRENT, 0);
853 data = m3_rd_2(sc, HOST_INT_CTRL);
854 m3_wr_2(sc, HOST_INT_CTRL, data & ~CLKRUN_GEN_ENABLE);
856 m3_wr_assp_data(sc, ch->adc_data + CDATA_INSTANCE_READY, 0);
857 m3_wr_assp_data(sc, KDATA_ADC1_REQUEST, 0);
860 case PCMTRIG_EMLDMAWR:
861 /* got play irq, transfer next buffer - ignore if using dma */
862 case PCMTRIG_EMLDMARD:
863 /* got rec irq, transfer next buffer - ignore if using dma */
871 m3_rchan_getptr(kobj_t kobj, void *chdata)
873 struct sc_rchinfo *ch = chdata;
874 struct sc_info *sc = ch->parent;
875 u_int32_t hi, lo, bus_crnt;
876 u_int32_t bus_base = vtophys(sndbuf_getbuf(ch->buffer));
878 hi = m3_rd_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTH);
879 lo = m3_rd_assp_data(sc, ch->adc_data + CDATA_HOST_SRC_CURRENTL);
880 bus_crnt = lo | (hi << 16);
882 M3_DEBUG(CALL, ("m3_rchan_getptr(adc=%d) result=%d\n",
883 ch->adc_idx, bus_crnt - bus_base));
885 return (bus_crnt - bus_base); /* current byte offset of channel */
888 static struct pcmchan_caps *
889 m3_rchan_getcaps(kobj_t kobj, void *chdata)
891 struct sc_rchinfo *ch = chdata;
893 M3_DEBUG(CALL, ("m3_rchan_getcaps(adc=%d)\n", ch->adc_idx));
898 /* -------------------------------------------------------------------- */
899 /* The interrupt handler */
904 struct sc_info *sc = (struct sc_info *)p;
905 u_int32_t status, ctl, i;
907 M3_DEBUG(INTR, ("m3_intr\n"));
909 status = m3_rd_1(sc, HOST_INT_STATUS);
913 m3_wr_1(sc, HOST_INT_STATUS, 0xff); /* ack the int? */
915 if (status & HV_INT_PENDING) {
918 event = m3_rd_1(sc, HW_VOL_COUNTER_MASTER);
921 mixer_hwvol_mute(sc->dev);
924 mixer_hwvol_step(sc->dev, 1, 1);
927 mixer_hwvol_step(sc->dev, -1, -1);
932 device_printf(sc->dev, "Unknown HWVOL event\n");
934 m3_wr_1(sc, HW_VOL_COUNTER_MASTER, 0x88);
938 if (status & ASSP_INT_PENDING) {
939 ctl = m3_rd_1(sc, ASSP_CONTROL_B);
940 if (!(ctl & STOP_ASSP_CLOCK)) {
941 ctl = m3_rd_1(sc, ASSP_HOST_INT_STATUS);
942 if (ctl & DSP2HOST_REQ_TIMER) {
943 m3_wr_1(sc, ASSP_HOST_INT_STATUS,
945 /*[[ess_update_ptr]]*/
950 for (i=0 ; i<sc->pch_cnt ; i++) {
951 if (sc->pch[i].active) {
952 chn_intr(sc->pch[i].channel);
955 for (i=0 ; i<sc->rch_cnt ; i++) {
956 if (sc->rch[i].active) {
957 chn_intr(sc->rch[i].channel);
962 /* -------------------------------------------------------------------- */
966 m3_power(struct sc_info *sc, int state)
970 M3_DEBUG(CHANGE, ("m3_power(%d)\n", state));
972 data = pci_read_config(sc->dev, 0x34, 1);
973 if (pci_read_config(sc->dev, data, 1) == 1) {
974 pci_write_config(sc->dev, data + 4, state, 1);
981 m3_init(struct sc_info *sc)
983 u_int32_t data, i, size;
984 u_int8_t reset_state;
986 M3_DEBUG(CHANGE, ("m3_init\n"));
988 /* diable legacy emulations. */
989 data = pci_read_config(sc->dev, PCI_LEGACY_AUDIO_CTRL, 2);
990 data |= DISABLE_LEGACY;
991 pci_write_config(sc->dev, PCI_LEGACY_AUDIO_CTRL, data, 2);
995 reset_state = m3_assp_halt(sc);
1000 /* zero kernel data */
1001 size = REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA;
1002 for(i = 0 ; i < size / 2 ; i++) {
1003 m3_wr_assp_data(sc, KDATA_BASE_ADDR + i, 0);
1005 /* zero mixer data? */
1006 size = REV_B_DATA_MEMORY_UNIT_LENGTH * NUM_UNITS_KERNEL_DATA;
1007 for(i = 0 ; i < size / 2 ; i++) {
1008 m3_wr_assp_data(sc, KDATA_BASE_ADDR2 + i, 0);
1010 /* init dma pointer */
1011 m3_wr_assp_data(sc, KDATA_CURRENT_DMA,
1013 /* write kernel into code memory */
1014 size = sizeof(assp_kernel_image);
1015 for(i = 0 ; i < size / 2; i++) {
1016 m3_wr_assp_code(sc, REV_B_CODE_MEMORY_BEGIN + i,
1017 assp_kernel_image[i]);
1020 * We only have this one client and we know that 0x400 is free in
1021 * our kernel's mem map, so lets just drop it there. It seems that
1022 * the minisrc doesn't need vectors, so we won't bother with them..
1024 size = sizeof(assp_minisrc_image);
1025 for(i = 0 ; i < size / 2; i++) {
1026 m3_wr_assp_code(sc, 0x400 + i, assp_minisrc_image[i]);
1028 /* write the coefficients for the low pass filter? */
1029 size = sizeof(minisrc_lpf_image);
1030 for(i = 0; i < size / 2 ; i++) {
1031 m3_wr_assp_code(sc,0x400 + MINISRC_COEF_LOC + i,
1032 minisrc_lpf_image[i]);
1034 m3_wr_assp_code(sc, 0x400 + MINISRC_COEF_LOC + size, 0x8000);
1035 /* the minisrc is the only thing on our task list */
1036 m3_wr_assp_data(sc, KDATA_TASK0, 0x400);
1037 /* init the mixer number */
1038 m3_wr_assp_data(sc, KDATA_MIXER_TASK_NUMBER, 0);
1039 /* extreme kernel master volume */
1040 m3_wr_assp_data(sc, KDATA_DAC_LEFT_VOLUME, ARB_VOLUME);
1041 m3_wr_assp_data(sc, KDATA_DAC_RIGHT_VOLUME, ARB_VOLUME);
1045 /* [m3_assp_client_init] (only one client at index 0) */
1046 for (i=0x1100 ; i<0x1c00 ; i++) {
1047 m3_wr_assp_data(sc, i, 0); /* zero entire dac/adc area */
1050 /* [m3_assp_continue] */
1051 m3_wr_1(sc, DSP_PORT_CONTROL_REG_B, reset_state | REGB_ENABLE_RESET);
1057 m3_uninit(struct sc_info *sc)
1059 M3_DEBUG(CHANGE, ("m3_uninit\n"));
1063 /* -------------------------------------------------------------------- */
1064 /* Probe and attach the card */
1067 m3_pci_probe(device_t dev)
1069 struct m3_card_type *card;
1071 M3_DEBUG(CALL, ("m3_pci_probe(0x%x)\n", pci_get_devid(dev)));
1073 for (card = m3_card_types ; card->pci_id ; card++) {
1074 if (pci_get_devid(dev) == card->pci_id) {
1075 device_set_desc(dev, card->name);
1083 m3_pci_attach(device_t dev)
1086 struct ac97_info *codec = NULL;
1088 char status[SND_STATUSLEN];
1089 struct m3_card_type *card;
1092 M3_DEBUG(CALL, ("m3_pci_attach\n"));
1094 if ((sc = malloc(sizeof(*sc), M_DEVBUF, M_NOWAIT | M_ZERO)) == NULL) {
1095 device_printf(dev, "cannot allocate softc\n");
1100 sc->type = pci_get_devid(dev);
1102 for (card = m3_card_types ; card->pci_id ; card++) {
1103 if (sc->type == card->pci_id) {
1104 sc->which = card->which;
1105 sc->delay1 = card->delay1;
1106 sc->delay2 = card->delay2;
1111 data = pci_read_config(dev, PCIR_COMMAND, 2);
1112 data |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
1113 pci_write_config(dev, PCIR_COMMAND, data, 2);
1115 sc->regid = PCIR_MAPS;
1116 sc->regtype = SYS_RES_MEMORY;
1117 sc->reg = bus_alloc_resource(dev, sc->regtype, &sc->regid,
1118 0, ~0, 1, RF_ACTIVE);
1120 sc->regtype = SYS_RES_IOPORT;
1121 sc->reg = bus_alloc_resource(dev, sc->regtype, &sc->regid,
1122 0, ~0, 1, RF_ACTIVE);
1125 device_printf(dev, "unable to allocate register space\n");
1128 sc->st = rman_get_bustag(sc->reg);
1129 sc->sh = rman_get_bushandle(sc->reg);
1132 sc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &sc->irqid,
1133 0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
1135 device_printf(dev, "unable to allocate interrupt\n");
1139 if (snd_setup_intr(dev, sc->irq, 0, m3_intr, sc, &sc->ih)) {
1140 device_printf(dev, "unable to setup interrupt\n");
1144 sc->bufsz = pcm_getbuffersize(dev, 1024, M3_BUFSIZE_DEFAULT, 65536);
1146 if (bus_dma_tag_create(/*parent*/NULL, /*alignment*/2, /*boundary*/0,
1147 /*lowaddr*/M3_MAXADDR,
1148 /*highaddr*/BUS_SPACE_MAXADDR,
1149 /*filter*/NULL, /*filterarg*/NULL,
1150 /*maxsize*/sc->bufsz, /*nsegments*/1,
1152 /*flags*/0, &sc->parent_dmat) != 0) {
1153 device_printf(dev, "unable to create dma tag\n");
1157 m3_power(sc, 0); /* power up */
1160 if (m3_init(sc) == -1) {
1161 device_printf(dev, "unable to initialize the card\n");
1165 /* create/init mixer */
1166 codec = AC97_CREATE(dev, sc, m3_codec);
1167 if (codec == NULL) {
1168 device_printf(dev, "ac97_create error\n");
1171 if (mixer_init(dev, ac97_getmixerclass(), codec)) {
1172 device_printf(dev, "mixer_init error\n");
1178 if (pcm_register(dev, sc, M3_PCHANS, M3_RCHANS)) {
1179 device_printf(dev, "pcm_register error\n");
1182 for (i=0 ; i<M3_PCHANS ; i++) {
1183 if (pcm_addchan(dev, PCMDIR_PLAY, &m3_pch_class, sc)) {
1184 device_printf(dev, "pcm_addchan (play) error\n");
1188 for (i=0 ; i<M3_RCHANS ; i++) {
1189 if (pcm_addchan(dev, PCMDIR_REC, &m3_rch_class, sc)) {
1190 device_printf(dev, "pcm_addchan (rec) error\n");
1194 snprintf(status, SND_STATUSLEN, "at %s 0x%lx irq %ld",
1195 (sc->regtype == SYS_RES_IOPORT)? "io" : "memory",
1196 rman_get_start(sc->reg), rman_get_start(sc->irq));
1197 if (pcm_setstatus(dev, status)) {
1198 device_printf(dev, "attach: pcm_setstatus error\n");
1202 mixer_hwvol_init(dev);
1204 /* Create the buffer for saving the card state during suspend */
1205 len = sizeof(u_int16_t) * (REV_B_CODE_MEMORY_LENGTH +
1206 REV_B_DATA_MEMORY_LENGTH);
1207 sc->savemem = (u_int16_t*)malloc(len, M_DEVBUF, M_NOWAIT | M_ZERO);
1208 if (sc->savemem == NULL) {
1209 device_printf(dev, "Failed to create suspend buffer\n");
1217 ac97_destroy(codec);
1220 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg);
1223 bus_teardown_intr(dev, sc->irq, sc->ih);
1226 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
1228 if (sc->parent_dmat) {
1229 bus_dma_tag_destroy(sc->parent_dmat);
1236 m3_pci_detach(device_t dev)
1238 struct sc_info *sc = pcm_getdevinfo(dev);
1241 M3_DEBUG(CALL, ("m3_pci_detach\n"));
1243 if ((r = pcm_unregister(dev)) != 0) {
1246 m3_uninit(sc); /* shutdown chip */
1247 m3_power(sc, 3); /* power off */
1249 bus_release_resource(dev, sc->regtype, sc->regid, sc->reg);
1250 bus_teardown_intr(dev, sc->irq, sc->ih);
1251 bus_release_resource(dev, SYS_RES_IRQ, sc->irqid, sc->irq);
1252 bus_dma_tag_destroy(sc->parent_dmat);
1254 free(sc->savemem, M_DEVBUF);
1260 m3_pci_suspend(device_t dev)
1262 struct sc_info *sc = pcm_getdevinfo(dev);
1265 M3_DEBUG(CHANGE, ("m3_pci_suspend\n"));
1267 for (i=0 ; i<sc->pch_cnt ; i++) {
1268 if (sc->pch[i].active) {
1269 m3_pchan_trigger(NULL, &sc->pch[i], PCMTRIG_STOP);
1272 for (i=0 ; i<sc->rch_cnt ; i++) {
1273 if (sc->rch[i].active) {
1274 m3_rchan_trigger(NULL, &sc->rch[i], PCMTRIG_STOP);
1277 DELAY(10 * 1000); /* give things a chance to stop */
1279 /* Disable interrupts */
1280 m3_wr_2(sc, HOST_INT_CTRL, 0);
1281 m3_wr_1(sc, ASSP_CONTROL_C, 0);
1285 /* Save the state of the ASSP */
1286 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
1287 sc->savemem[index++] = m3_rd_assp_code(sc, i);
1288 for (i = REV_B_DATA_MEMORY_BEGIN; i <= REV_B_DATA_MEMORY_END; i++)
1289 sc->savemem[index++] = m3_rd_assp_data(sc, i);
1291 /* Power down the card to D3 state */
1298 m3_pci_resume(device_t dev)
1300 struct sc_info *sc = pcm_getdevinfo(dev);
1302 u_int8_t reset_state;
1304 M3_DEBUG(CHANGE, ("m3_pci_resume\n"));
1306 /* Power the card back to D0 */
1311 reset_state = m3_assp_halt(sc);
1315 /* Restore the ASSP state */
1316 for (i = REV_B_CODE_MEMORY_BEGIN; i <= REV_B_CODE_MEMORY_END; i++)
1317 m3_wr_assp_code(sc, i, sc->savemem[index++]);
1318 for (i = REV_B_DATA_MEMORY_BEGIN; i <= REV_B_DATA_MEMORY_END; i++)
1319 m3_wr_assp_data(sc, i, sc->savemem[index++]);
1321 /* Restart the DMA engine */
1322 m3_wr_assp_data(sc, KDATA_DMA_ACTIVE, 0);
1324 /* [m3_assp_continue] */
1325 m3_wr_1(sc, DSP_PORT_CONTROL_REG_B, reset_state | REGB_ENABLE_RESET);
1331 if (mixer_reinit(dev) == -1) {
1332 device_printf(dev, "unable to reinitialize the mixer\n");
1336 /* Turn the channels back on */
1337 for (i=0 ; i<sc->pch_cnt ; i++) {
1338 if (sc->pch[i].active) {
1339 m3_pchan_trigger(NULL, &sc->pch[i], PCMTRIG_START);
1342 for (i=0 ; i<sc->rch_cnt ; i++) {
1343 if (sc->rch[i].active) {
1344 m3_rchan_trigger(NULL, &sc->rch[i], PCMTRIG_START);
1352 m3_pci_shutdown(device_t dev)
1354 struct sc_info *sc = pcm_getdevinfo(dev);
1356 M3_DEBUG(CALL, ("m3_pci_shutdown\n"));
1358 m3_power(sc, 3); /* power off */
1363 m3_assp_halt(struct sc_info *sc)
1365 u_int8_t data, reset_state;
1367 data = m3_rd_1(sc, DSP_PORT_CONTROL_REG_B);
1368 reset_state = data & ~REGB_STOP_CLOCK; /* remember for continue */
1370 m3_wr_1(sc, DSP_PORT_CONTROL_REG_B, reset_state & ~REGB_ENABLE_RESET);
1371 DELAY(10 * 1000); /* necessary? */
1377 m3_config(struct sc_info *sc)
1379 u_int32_t data, hv_cfg;
1383 * The volume buttons can be wired up via two different sets of pins.
1384 * This presents a problem since we can't tell which way it's
1385 * configured. Allow the user to set a hint in order to twiddle
1388 if (resource_int_value(device_get_name(sc->dev),
1389 device_get_unit(sc->dev),
1390 "hwvol_config", &hint) == 0)
1391 hv_cfg = (hint > 0) ? HV_BUTTON_FROM_GD : 0;
1393 hv_cfg = HV_BUTTON_FROM_GD;
1395 data = pci_read_config(sc->dev, PCI_ALLEGRO_CONFIG, 4);
1396 data &= ~HV_BUTTON_FROM_GD;
1397 data |= REDUCED_DEBOUNCE | HV_CTRL_ENABLE | hv_cfg;
1398 data |= PM_CTRL_ENABLE | CLK_DIV_BY_49 | USE_PCI_TIMING;
1399 pci_write_config(sc->dev, PCI_ALLEGRO_CONFIG, data, 4);
1401 m3_wr_1(sc, ASSP_CONTROL_B, RESET_ASSP);
1402 data = pci_read_config(sc->dev, PCI_ALLEGRO_CONFIG, 4);
1403 data &= ~INT_CLK_SELECT;
1404 if (sc->which == ESS_MAESTRO3) {
1405 data &= ~INT_CLK_MULT_ENABLE;
1406 data |= INT_CLK_SRC_NOT_PCI;
1408 data &= ~(CLK_MULT_MODE_SELECT | CLK_MULT_MODE_SELECT_2);
1409 pci_write_config(sc->dev, PCI_ALLEGRO_CONFIG, data, 4);
1411 if (sc->which == ESS_ALLEGRO_1) {
1412 data = pci_read_config(sc->dev, PCI_USER_CONFIG, 4);
1413 data |= IN_CLK_12MHZ_SELECT;
1414 pci_write_config(sc->dev, PCI_USER_CONFIG, data, 4);
1417 data = m3_rd_1(sc, ASSP_CONTROL_A);
1418 data &= ~(DSP_CLK_36MHZ_SELECT | ASSP_CLK_49MHZ_SELECT);
1419 data |= ASSP_CLK_49MHZ_SELECT; /*XXX assumes 49MHZ dsp XXX*/
1420 data |= ASSP_0_WS_ENABLE;
1421 m3_wr_1(sc, ASSP_CONTROL_A, data);
1423 m3_wr_1(sc, ASSP_CONTROL_B, RUN_ASSP);
1427 m3_enable_ints(struct sc_info *sc)
1431 m3_wr_2(sc, HOST_INT_CTRL, ASSP_INT_ENABLE | HV_INT_ENABLE);
1432 data = m3_rd_1(sc, ASSP_CONTROL_C);
1433 m3_wr_1(sc, ASSP_CONTROL_C, data | ASSP_HOST_INT_ENABLE);
1437 m3_amp_enable(struct sc_info *sc)
1439 u_int32_t gpo, polarity_port, polarity;
1442 switch (sc->which) {
1444 polarity_port = 0x1800;
1447 polarity_port = 0x1100;
1450 panic("bad sc->which");
1452 gpo = (polarity_port >> 8) & 0x0f;
1453 polarity = polarity_port >> 12;
1454 polarity = !polarity; /* enable */
1455 polarity = polarity << gpo;
1457 m3_wr_2(sc, GPIO_MASK, ~gpo);
1458 data = m3_rd_2(sc, GPIO_DIRECTION);
1459 m3_wr_2(sc, GPIO_DIRECTION, data | gpo);
1460 data = GPO_SECONDARY_AC97 | GPO_PRIMARY_AC97 | polarity;
1461 m3_wr_2(sc, GPIO_DATA, data);
1462 m3_wr_2(sc, GPIO_MASK, ~0);
1466 m3_codec_reset(struct sc_info *sc)
1468 u_int16_t data, dir;
1472 data = m3_rd_2(sc, GPIO_DIRECTION);
1473 dir = data | 0x10; /* assuming pci bus master? */
1475 /* [[remote_codec_config]] */
1476 data = m3_rd_2(sc, RING_BUS_CTRL_B);
1477 m3_wr_2(sc, RING_BUS_CTRL_B, data & ~SECOND_CODEC_ID_MASK);
1478 data = m3_rd_2(sc, SDO_OUT_DEST_CTRL);
1479 m3_wr_2(sc, SDO_OUT_DEST_CTRL, data & ~COMMAND_ADDR_OUT);
1480 data = m3_rd_2(sc, SDO_IN_DEST_CTRL);
1481 m3_wr_2(sc, SDO_IN_DEST_CTRL, data & ~STATUS_ADDR_IN);
1483 m3_wr_2(sc, RING_BUS_CTRL_A, IO_SRAM_ENABLE);
1486 m3_wr_2(sc, GPIO_DIRECTION, dir & ~GPO_PRIMARY_AC97);
1487 m3_wr_2(sc, GPIO_MASK, ~GPO_PRIMARY_AC97);
1488 m3_wr_2(sc, GPIO_DATA, 0);
1489 m3_wr_2(sc, GPIO_DIRECTION, dir | GPO_PRIMARY_AC97);
1490 DELAY(sc->delay1 * 1000); /*delay1 (ALLEGRO:50, MAESTRO3:20)*/
1491 m3_wr_2(sc, GPIO_DATA, GPO_PRIMARY_AC97);
1493 m3_wr_2(sc, RING_BUS_CTRL_A, IO_SRAM_ENABLE |
1494 SERIAL_AC_LINK_ENABLE);
1495 m3_wr_2(sc, GPIO_MASK, ~0);
1496 DELAY(sc->delay2 * 1000); /*delay2 (ALLEGRO:800, MAESTRO3:500)*/
1498 /* [[try read vendor]] */
1499 data = m3_rdcd(NULL, sc, 0x7c);
1500 if ((data == 0) || (data == 0xffff)) {
1503 device_printf(sc->dev, "Codec reset failed\n");
1506 device_printf(sc->dev, "Codec reset retry\n");
1511 static device_method_t m3_methods[] = {
1512 DEVMETHOD(device_probe, m3_pci_probe),
1513 DEVMETHOD(device_attach, m3_pci_attach),
1514 DEVMETHOD(device_detach, m3_pci_detach),
1515 DEVMETHOD(device_suspend, m3_pci_suspend),
1516 DEVMETHOD(device_resume, m3_pci_resume),
1517 DEVMETHOD(device_shutdown, m3_pci_shutdown),
1521 static driver_t m3_driver = {
1527 DRIVER_MODULE(snd_maestro3, pci, m3_driver, pcm_devclass, 0, 0);
1528 MODULE_DEPEND(snd_maestro3, snd_pcm, PCM_MINVER, PCM_PREFVER, PCM_MAXVER);
1529 MODULE_VERSION(snd_maestro3, 1);