sys/dev/netif/age/if_age.c

   1 /*-
   2  * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice unmodified, this list of conditions, and the following
  10  *    disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  *
  27  * $FreeBSD: src/sys/dev/age/if_age.c,v 1.6 2008/11/07 07:02:28 yongari Exp $
  28  */
  29
  30 /* Driver for Attansic Technology Corp. L1 Gigabit Ethernet. */
  31
  32 #include <sys/param.h>
  33 #include <sys/endian.h>
  34 #include <sys/kernel.h>
  35 #include <sys/bus.h>
  36 #include <sys/interrupt.h>
  37 #include <sys/malloc.h>
  38 #include <sys/proc.h>
  39 #include <sys/rman.h>
  40 #include <sys/serialize.h>
  41 #include <sys/socket.h>
  42 #include <sys/sockio.h>
  43 #include <sys/sysctl.h>
  44
  45 #include <net/ethernet.h>
  46 #include <net/if.h>
  47 #include <net/bpf.h>
  48 #include <net/if_arp.h>
  49 #include <net/if_dl.h>
  50 #include <net/if_media.h>
  51 #include <net/ifq_var.h>
  52 #include <net/vlan/if_vlan_var.h>
  53 #include <net/vlan/if_vlan_ether.h>
  54
  55 #include <dev/netif/mii_layer/miivar.h>
  56 #include <dev/netif/mii_layer/jmphyreg.h>
  57
  58 #include <bus/pci/pcireg.h>
  59 #include <bus/pci/pcivar.h>
  60 #include <bus/pci/pcidevs.h>
  61
  62 #include <dev/netif/age/if_agereg.h>
  63 #include <dev/netif/age/if_agevar.h>
  64
  65 /* "device miibus" required.  See GENERIC if you get errors here. */
  66 #include "miibus_if.h"
  67
  68 #define AGE_CSUM_FEATURES       (CSUM_TCP | CSUM_UDP)
  69
  70 struct age_dmamap_ctx {
  71         int                     nsegs;
  72         bus_dma_segment_t       *segs;
  73 };
  74
  75 static int      age_probe(device_t);
  76 static int      age_attach(device_t);
  77 static int      age_detach(device_t);
  78 static int      age_shutdown(device_t);
  79 static int      age_suspend(device_t);
  80 static int      age_resume(device_t);
  81
  82 static int      age_miibus_readreg(device_t, int, int);
  83 static int      age_miibus_writereg(device_t, int, int, int);
  84 static void     age_miibus_statchg(device_t);
  85
  86 static void     age_init(void *);
  87 static int      age_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
  88 static void     age_start(struct ifnet *, struct ifaltq_subque *);
  89 static void     age_watchdog(struct ifnet *);
  90 static void     age_mediastatus(struct ifnet *, struct ifmediareq *);
  91 static int      age_mediachange(struct ifnet *);
  92
  93 static void     age_intr(void *);
  94 static void     age_txintr(struct age_softc *, int);
  95 static void     age_rxintr(struct age_softc *, int);
  96 static void     age_rxeof(struct age_softc *sc, struct rx_rdesc *);
  97
  98 static int      age_dma_alloc(struct age_softc *);
  99 static void     age_dma_free(struct age_softc *);
 100 static void     age_dmamap_cb(void *, bus_dma_segment_t *, int, int);
 101 static void     age_dmamap_buf_cb(void *, bus_dma_segment_t *, int,
 102                     bus_size_t, int);
 103 static int      age_check_boundary(struct age_softc *);
 104 static int      age_newbuf(struct age_softc *, struct age_rxdesc *, int);
 105 static int      age_encap(struct age_softc *, struct mbuf **);
 106 static void     age_init_tx_ring(struct age_softc *);
 107 static int      age_init_rx_ring(struct age_softc *);
 108 static void     age_init_rr_ring(struct age_softc *);
 109 static void     age_init_cmb_block(struct age_softc *);
 110 static void     age_init_smb_block(struct age_softc *);
 111
 112 static void     age_tick(void *);
 113 static void     age_stop(struct age_softc *);
 114 static void     age_reset(struct age_softc *);
 115 static int      age_read_vpd_word(struct age_softc *, uint32_t, uint32_t,
 116                     uint32_t *);
 117 static void     age_get_macaddr(struct age_softc *);
 118 static void     age_phy_reset(struct age_softc *);
 119 static void     age_mac_config(struct age_softc *);
 120 static void     age_stats_update(struct age_softc *);
 121 static void     age_stop_txmac(struct age_softc *);
 122 static void     age_stop_rxmac(struct age_softc *);
 123 static void     age_rxvlan(struct age_softc *);
 124 static void     age_rxfilter(struct age_softc *);
 125 #ifdef wol_notyet
 126 static void age_setwol(struct age_softc *);
 127 #endif
 128
 129 static void     age_sysctl_node(struct age_softc *);
 130 static int      sysctl_age_stats(SYSCTL_HANDLER_ARGS);
 131 static int      sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS);
 132
 133 /*
 134  * Devices supported by this driver.
 135  */
 136 static struct age_dev {
 137         uint16_t        age_vendorid;
 138         uint16_t        age_deviceid;
 139         const char      *age_name;
 140 } age_devs[] = {
 141         { VENDORID_ATTANSIC, DEVICEID_ATTANSIC_L1,
 142             "Attansic Technology Corp, L1 Gigabit Ethernet" },
 143 };
 144
 145 static device_method_t age_methods[] = {
 146         /* Device interface. */
 147         DEVMETHOD(device_probe,         age_probe),
 148         DEVMETHOD(device_attach,        age_attach),
 149         DEVMETHOD(device_detach,        age_detach),
 150         DEVMETHOD(device_shutdown,      age_shutdown),
 151         DEVMETHOD(device_suspend,       age_suspend),
 152         DEVMETHOD(device_resume,        age_resume),
 153
 154         /* Bus interface. */
 155         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 156         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 157
 158         /* MII interface. */
 159         DEVMETHOD(miibus_readreg,       age_miibus_readreg),
 160         DEVMETHOD(miibus_writereg,      age_miibus_writereg),
 161         DEVMETHOD(miibus_statchg,       age_miibus_statchg),
 162
 163         { NULL, NULL }
 164 };
 165
 166 static driver_t age_driver = {
 167         "age",
 168         age_methods,
 169         sizeof(struct age_softc)
 170 };
 171
 172 static devclass_t age_devclass;
 173
 174 DECLARE_DUMMY_MODULE(if_age);
 175 MODULE_DEPEND(if_age, miibus, 1, 1, 1);
 176 DRIVER_MODULE(if_age, pci, age_driver, age_devclass, NULL, NULL);
 177 DRIVER_MODULE(miibus, age, miibus_driver, miibus_devclass, NULL, NULL);
 178
 179 /*
 180  *      Read a PHY register on the MII of the L1.
 181  */
 182 static int
 183 age_miibus_readreg(device_t dev, int phy, int reg)
 184 {
 185         struct age_softc *sc;
 186         uint32_t v;
 187         int i;
 188
 189         sc = device_get_softc(dev);
 190         if (phy != sc->age_phyaddr)
 191                 return (0);
 192
 193         CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
 194             MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
 195         for (i = AGE_PHY_TIMEOUT; i > 0; i--) {
 196                 DELAY(1);
 197                 v = CSR_READ_4(sc, AGE_MDIO);
 198                 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
 199                         break;
 200         }
 201
 202         if (i == 0) {
 203                 device_printf(sc->age_dev, "phy read timeout : %d\n", reg);
 204                 return (0);
 205         }
 206
 207         return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT);
 208 }
 209
 210 /*
 211  *      Write a PHY register on the MII of the L1.
 212  */
 213 static int
 214 age_miibus_writereg(device_t dev, int phy, int reg, int val)
 215 {
 216         struct age_softc *sc;
 217         uint32_t v;
 218         int i;
 219
 220         sc = device_get_softc(dev);
 221         if (phy != sc->age_phyaddr)
 222                 return (0);
 223
 224         CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
 225             (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT |
 226             MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
 227         for (i = AGE_PHY_TIMEOUT; i > 0; i--) {
 228                 DELAY(1);
 229                 v = CSR_READ_4(sc, AGE_MDIO);
 230                 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
 231                         break;
 232         }
 233
 234         if (i == 0)
 235                 device_printf(sc->age_dev, "phy write timeout : %d\n", reg);
 236
 237         return (0);
 238 }
 239
 240 /*
 241  *      Callback from MII layer when media changes.
 242  */
 243 static void
 244 age_miibus_statchg(device_t dev)
 245 {
 246         struct age_softc *sc = device_get_softc(dev);
 247         struct ifnet *ifp = &sc->arpcom.ac_if;
 248         struct mii_data *mii;
 249
 250         ASSERT_SERIALIZED(ifp->if_serializer);
 251
 252         if ((ifp->if_flags & IFF_RUNNING) == 0)
 253                 return;
 254
 255         mii = device_get_softc(sc->age_miibus);
 256
 257         sc->age_flags &= ~AGE_FLAG_LINK;
 258         if ((mii->mii_media_status & IFM_AVALID) != 0) {
 259                 switch (IFM_SUBTYPE(mii->mii_media_active)) {
 260                 case IFM_10_T:
 261                 case IFM_100_TX:
 262                 case IFM_1000_T:
 263                         sc->age_flags |= AGE_FLAG_LINK;
 264                         break;
 265                 default:
 266                         break;
 267                 }
 268         }
 269
 270         /* Stop Rx/Tx MACs. */
 271         age_stop_rxmac(sc);
 272         age_stop_txmac(sc);
 273
 274         /* Program MACs with resolved speed/duplex/flow-control. */
 275         if ((sc->age_flags & AGE_FLAG_LINK) != 0) {
 276                 uint32_t reg;
 277
 278                 age_mac_config(sc);
 279
 280                 reg = CSR_READ_4(sc, AGE_MAC_CFG);
 281                 /* Restart DMA engine and Tx/Rx MAC. */
 282                 CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) |
 283                     DMA_CFG_RD_ENB | DMA_CFG_WR_ENB);
 284                 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
 285                 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
 286         }
 287 }
 288
 289 /*
 290  *      Get the current interface media status.
 291  */
 292 static void
 293 age_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
 294 {
 295         struct age_softc *sc = ifp->if_softc;
 296         struct mii_data *mii = device_get_softc(sc->age_miibus);
 297
 298         ASSERT_SERIALIZED(ifp->if_serializer);
 299
 300         mii_pollstat(mii);
 301         ifmr->ifm_status = mii->mii_media_status;
 302         ifmr->ifm_active = mii->mii_media_active;
 303 }
 304
 305 /*
 306  *      Set hardware to newly-selected media.
 307  */
 308 static int
 309 age_mediachange(struct ifnet *ifp)
 310 {
 311         struct age_softc *sc = ifp->if_softc;
 312         struct mii_data *mii = device_get_softc(sc->age_miibus);
 313         int error;
 314
 315         ASSERT_SERIALIZED(ifp->if_serializer);
 316
 317         if (mii->mii_instance != 0) {
 318                 struct mii_softc *miisc;
 319
 320                 LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
 321                         mii_phy_reset(miisc);
 322         }
 323         error = mii_mediachg(mii);
 324
 325         return (error);
 326 }
 327
 328 static int
 329 age_read_vpd_word(struct age_softc *sc, uint32_t vpdc, uint32_t offset,
 330     uint32_t *word)
 331 {
 332         int i;
 333
 334         pci_write_config(sc->age_dev, vpdc + PCIR_VPD_ADDR, offset, 2);
 335         for (i = AGE_TIMEOUT; i > 0; i--) {
 336                 DELAY(10);
 337                 if ((pci_read_config(sc->age_dev, vpdc + PCIR_VPD_ADDR, 2) &
 338                     0x8000) == 0x8000)
 339                         break;
 340         }
 341         if (i == 0) {
 342                 device_printf(sc->age_dev, "VPD read timeout!\n");
 343                 *word = 0;
 344                 return (ETIMEDOUT);
 345         }
 346
 347         *word = pci_read_config(sc->age_dev, vpdc + PCIR_VPD_DATA, 4);
 348         return (0);
 349 }
 350
 351 static int
 352 age_probe(device_t dev)
 353 {
 354         struct age_dev *sp;
 355         int i;
 356         uint16_t vendor, devid;
 357
 358         vendor = pci_get_vendor(dev);
 359         devid = pci_get_device(dev);
 360         sp = age_devs;
 361         for (i = 0; i < NELEM(age_devs); i++, sp++) {
 362                 if (vendor == sp->age_vendorid &&
 363                     devid == sp->age_deviceid) {
 364                         device_set_desc(dev, sp->age_name);
 365                         return (0);
 366                 }
 367         }
 368         return (ENXIO);
 369 }
 370
 371 static void
 372 age_get_macaddr(struct age_softc *sc)
 373 {
 374         uint32_t ea[2], off, reg, word;
 375         int vpd_error, match, vpdc;
 376
 377         reg = CSR_READ_4(sc, AGE_SPI_CTRL);
 378         if ((reg & SPI_VPD_ENB) != 0) {
 379                 /* Get VPD stored in TWSI EEPROM. */
 380                 reg &= ~SPI_VPD_ENB;
 381                 CSR_WRITE_4(sc, AGE_SPI_CTRL, reg);
 382         }
 383
 384         ea[0] = ea[1] = 0;
 385         vpdc = pci_get_vpdcap_ptr(sc->age_dev);
 386         if (vpdc) {
 387                 vpd_error = 0;
 388
 389                 /*
 390                  * PCI VPD capability exists, but it seems that it's
 391                  * not in the standard form as stated in PCI VPD
 392                  * specification such that driver could not use
 393                  * pci_get_vpd_readonly(9) with keyword 'NA'.
 394                  * Search VPD data starting at address 0x0100. The data
 395                  * should be used as initializers to set AGE_PAR0,
 396                  * AGE_PAR1 register including other PCI configuration
 397                  * registers.
 398                  */
 399                 word = 0;
 400                 match = 0;
 401                 reg = 0;
 402                 for (off = AGE_VPD_REG_CONF_START; off < AGE_VPD_REG_CONF_END;
 403                     off += sizeof(uint32_t)) {
 404                         vpd_error = age_read_vpd_word(sc, vpdc, off, &word);
 405                         if (vpd_error != 0)
 406                                 break;
 407                         if (match != 0) {
 408                                 switch (reg) {
 409                                 case AGE_PAR0:
 410                                         ea[0] = word;
 411                                         break;
 412                                 case AGE_PAR1:
 413                                         ea[1] = word;
 414                                         break;
 415                                 default:
 416                                         break;
 417                                 }
 418                                 match = 0;
 419                         } else if ((word & 0xFF) == AGE_VPD_REG_CONF_SIG) {
 420                                 match = 1;
 421                                 reg = word >> 16;
 422                         } else
 423                                 break;
 424                 }
 425                 if (off >= AGE_VPD_REG_CONF_END)
 426                         vpd_error = ENOENT;
 427                 if (vpd_error == 0) {
 428                         /*
 429                          * Don't blindly trust ethernet address obtained
 430                          * from VPD. Check whether ethernet address is
 431                          * valid one. Otherwise fall-back to reading
 432                          * PAR register.
 433                          */
 434                         ea[1] &= 0xFFFF;
 435                         if ((ea[0] == 0 && ea[1] == 0) ||
 436                             (ea[0] == 0xFFFFFFFF && ea[1] == 0xFFFF)) {
 437                                 if (bootverbose)
 438                                         device_printf(sc->age_dev,
 439                                             "invalid ethernet address "
 440                                             "returned from VPD.\n");
 441                                 vpd_error = EINVAL;
 442                         }
 443                 }
 444                 if (vpd_error != 0 && (bootverbose))
 445                         device_printf(sc->age_dev, "VPD access failure!\n");
 446         } else {
 447                 vpd_error = ENOENT;
 448                 if (bootverbose)
 449                         device_printf(sc->age_dev,
 450                             "PCI VPD capability not found!\n");
 451         }
 452
 453         /*
 454          * It seems that L1 also provides a way to extract ethernet
 455          * address via SPI flash interface. Because SPI flash memory
 456          * device of different vendors vary in their instruction
 457          * codes for read ID instruction, it's very hard to get
 458          * instructions codes without detailed information for the
 459          * flash memory device used on ethernet controller. To simplify
 460          * code, just read AGE_PAR0/AGE_PAR1 register to get ethernet
 461          * address which is supposed to be set by hardware during
 462          * power on reset.
 463          */
 464         if (vpd_error != 0) {
 465                 /*
 466                  * VPD is mapped to SPI flash memory or BIOS set it.
 467                  */
 468                 ea[0] = CSR_READ_4(sc, AGE_PAR0);
 469                 ea[1] = CSR_READ_4(sc, AGE_PAR1);
 470         }
 471
 472         ea[1] &= 0xFFFF;
 473         if ((ea[0] == 0 && ea[1]  == 0) ||
 474             (ea[0] == 0xFFFFFFFF && ea[1] == 0xFFFF)) {
 475                 device_printf(sc->age_dev,
 476                     "generating fake ethernet address.\n");
 477                 ea[0] = karc4random();
 478                 /* Set OUI to ASUSTek COMPUTER INC. */
 479                 sc->age_eaddr[0] = 0x00;
 480                 sc->age_eaddr[1] = 0x1B;
 481                 sc->age_eaddr[2] = 0xFC;
 482                 sc->age_eaddr[3] = (ea[0] >> 16) & 0xFF;
 483                 sc->age_eaddr[4] = (ea[0] >> 8) & 0xFF;
 484                 sc->age_eaddr[5] = (ea[0] >> 0) & 0xFF;
 485         } else {
 486                 sc->age_eaddr[0] = (ea[1] >> 8) & 0xFF;
 487                 sc->age_eaddr[1] = (ea[1] >> 0) & 0xFF;
 488                 sc->age_eaddr[2] = (ea[0] >> 24) & 0xFF;
 489                 sc->age_eaddr[3] = (ea[0] >> 16) & 0xFF;
 490                 sc->age_eaddr[4] = (ea[0] >> 8) & 0xFF;
 491                 sc->age_eaddr[5] = (ea[0] >> 0) & 0xFF;
 492         }
 493 }
 494
 495 static void
 496 age_phy_reset(struct age_softc *sc)
 497 {
 498         /* Reset PHY. */
 499         CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST);
 500         DELAY(1000);
 501         CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR);
 502         DELAY(1000);
 503 }
 504
 505 static int
 506 age_attach(device_t dev)
 507 {
 508         struct age_softc *sc = device_get_softc(dev);
 509         struct ifnet *ifp = &sc->arpcom.ac_if;
 510         uint8_t pcie_ptr;
 511         int error;
 512
 513         error = 0;
 514         sc->age_dev = dev;
 515         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
 516
 517         callout_init(&sc->age_tick_ch);
 518
 519 #ifndef BURN_BRIDGES
 520         if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) {
 521                 uint32_t irq, mem;
 522
 523                 irq = pci_read_config(dev, PCIR_INTLINE, 4);
 524                 mem = pci_read_config(dev, AGE_PCIR_BAR, 4);
 525
 526                 device_printf(dev, "chip is in D%d power mode "
 527                     "-- setting to D0\n", pci_get_powerstate(dev));
 528
 529                 pci_set_powerstate(dev, PCI_POWERSTATE_D0);
 530
 531                 pci_write_config(dev, PCIR_INTLINE, irq, 4);
 532                 pci_write_config(dev, AGE_PCIR_BAR, mem, 4);
 533         }
 534 #endif  /* !BURN_BRIDGE */
 535
 536         /* Enable bus mastering */
 537         pci_enable_busmaster(dev);
 538
 539         /*
 540          * Allocate memory mapped IO
 541          */
 542         sc->age_mem_rid = AGE_PCIR_BAR;
 543         sc->age_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
 544                                                  &sc->age_mem_rid, RF_ACTIVE);
 545         if (sc->age_mem_res == NULL) {
 546                 device_printf(dev, "can't allocate IO memory\n");
 547                 return ENXIO;
 548         }
 549         sc->age_mem_bt = rman_get_bustag(sc->age_mem_res);
 550         sc->age_mem_bh = rman_get_bushandle(sc->age_mem_res);
 551
 552         /*
 553          * Allocate IRQ
 554          */
 555         sc->age_irq_rid = 0;
 556         sc->age_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
 557                                                  &sc->age_irq_rid,
 558                                                  RF_SHAREABLE | RF_ACTIVE);
 559         if (sc->age_irq_res == NULL) {
 560                 device_printf(dev, "can't allocate irq\n");
 561                 error = ENXIO;
 562                 goto fail;
 563         }
 564
 565         /* Set PHY address. */
 566         sc->age_phyaddr = AGE_PHY_ADDR;
 567
 568         /* Reset PHY. */
 569         age_phy_reset(sc);
 570
 571         /* Reset the ethernet controller. */
 572         age_reset(sc);
 573
 574         /* Get PCI and chip id/revision. */
 575         sc->age_rev = pci_get_revid(dev);
 576         sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >>
 577             MASTER_CHIP_REV_SHIFT;
 578         if (bootverbose) {
 579                 device_printf(dev, "PCI device revision : 0x%04x\n", sc->age_rev);
 580                 device_printf(dev, "Chip id/revision : 0x%04x\n",
 581                     sc->age_chip_rev);
 582         }
 583
 584         /*
 585          * XXX
 586          * Unintialized hardware returns an invalid chip id/revision
 587          * as well as 0xFFFFFFFF for Tx/Rx fifo length. It seems that
 588          * unplugged cable results in putting hardware into automatic
 589          * power down mode which in turn returns invalld chip revision.
 590          */
 591         if (sc->age_chip_rev == 0xFFFF) {
 592                 device_printf(dev,"invalid chip revision : 0x%04x -- "
 593                     "not initialized?\n", sc->age_chip_rev);
 594                 error = ENXIO;
 595                 goto fail;
 596         }
 597         device_printf(dev, "%d Tx FIFO, %d Rx FIFO\n",
 598             CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN),
 599             CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN));
 600
 601         /* Get DMA parameters from PCIe device control register. */
 602         pcie_ptr = pci_get_pciecap_ptr(dev);
 603         if (pcie_ptr) {
 604                 uint16_t devctl;
 605
 606                 sc->age_flags |= AGE_FLAG_PCIE;
 607                 devctl = pci_read_config(dev, pcie_ptr + PCIER_DEVCTRL, 2);
 608                 /* Max read request size. */
 609                 sc->age_dma_rd_burst = ((devctl >> 12) & 0x07) <<
 610                     DMA_CFG_RD_BURST_SHIFT;
 611                 /* Max payload size. */
 612                 sc->age_dma_wr_burst = ((devctl >> 5) & 0x07) <<
 613                     DMA_CFG_WR_BURST_SHIFT;
 614                 if (bootverbose) {
 615                         device_printf(dev, "Read request size : %d bytes.\n",
 616                             128 << ((devctl >> 12) & 0x07));
 617                         device_printf(dev, "TLP payload size : %d bytes.\n",
 618                             128 << ((devctl >> 5) & 0x07));
 619                 }
 620         } else {
 621                 sc->age_dma_rd_burst = DMA_CFG_RD_BURST_128;
 622                 sc->age_dma_wr_burst = DMA_CFG_WR_BURST_128;
 623         }
 624
 625         /* Create device sysctl node. */
 626         age_sysctl_node(sc);
 627
 628         if ((error = age_dma_alloc(sc) != 0))
 629                 goto fail;
 630
 631         /* Load station address. */
 632         age_get_macaddr(sc);
 633
 634         ifp->if_softc = sc;
 635         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
 636         ifp->if_ioctl = age_ioctl;
 637         ifp->if_start = age_start;
 638         ifp->if_init = age_init;
 639         ifp->if_watchdog = age_watchdog;
 640         ifq_set_maxlen(&ifp->if_snd, AGE_TX_RING_CNT - 1);
 641         ifq_set_ready(&ifp->if_snd);
 642
 643         ifp->if_capabilities = IFCAP_HWCSUM |
 644                                IFCAP_VLAN_MTU |
 645                                IFCAP_VLAN_HWTAGGING;
 646         ifp->if_hwassist = AGE_CSUM_FEATURES;
 647         ifp->if_capenable = ifp->if_capabilities;
 648
 649         /* Set up MII bus. */
 650         if ((error = mii_phy_probe(dev, &sc->age_miibus, age_mediachange,
 651             age_mediastatus)) != 0) {
 652                 device_printf(dev, "no PHY found!\n");
 653                 goto fail;
 654         }
 655
 656         ether_ifattach(ifp, sc->age_eaddr, NULL);
 657
 658         /* Tell the upper layer(s) we support long frames. */
 659         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
 660
 661         ifq_set_cpuid(&ifp->if_snd, rman_get_cpuid(sc->age_irq_res));
 662
 663         error = bus_setup_intr(dev, sc->age_irq_res, INTR_MPSAFE, age_intr, sc,
 664                                &sc->age_irq_handle, ifp->if_serializer);
 665         if (error) {
 666                 device_printf(dev, "could not set up interrupt handler.\n");
 667                 ether_ifdetach(ifp);
 668                 goto fail;
 669         }
 670
 671         return 0;
 672 fail:
 673         age_detach(dev);
 674         return (error);
 675 }
 676
 677 static int
 678 age_detach(device_t dev)
 679 {
 680         struct age_softc *sc = device_get_softc(dev);
 681
 682         if (device_is_attached(dev)) {
 683                 struct ifnet *ifp = &sc->arpcom.ac_if;
 684
 685                 lwkt_serialize_enter(ifp->if_serializer);
 686                 sc->age_flags |= AGE_FLAG_DETACH;
 687                 age_stop(sc);
 688                 bus_teardown_intr(dev, sc->age_irq_res, sc->age_irq_handle);
 689                 lwkt_serialize_exit(ifp->if_serializer);
 690
 691                 ether_ifdetach(ifp);
 692         }
 693
 694         if (sc->age_sysctl_tree != NULL)
 695                 sysctl_ctx_free(&sc->age_sysctl_ctx);
 696
 697         if (sc->age_miibus != NULL)
 698                 device_delete_child(dev, sc->age_miibus);
 699         bus_generic_detach(dev);
 700
 701         if (sc->age_irq_res != NULL) {
 702                 bus_release_resource(dev, SYS_RES_IRQ, sc->age_irq_rid,
 703                                      sc->age_irq_res);
 704         }
 705         if (sc->age_mem_res != NULL) {
 706                 bus_release_resource(dev, SYS_RES_MEMORY, sc->age_mem_rid,
 707                                      sc->age_mem_res);
 708         }
 709
 710         age_dma_free(sc);
 711
 712         return (0);
 713 }
 714
 715 static void
 716 age_sysctl_node(struct age_softc *sc)
 717 {
 718         int error;
 719
 720         sysctl_ctx_init(&sc->age_sysctl_ctx);
 721         sc->age_sysctl_tree = SYSCTL_ADD_NODE(&sc->age_sysctl_ctx,
 722                                 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
 723                                 device_get_nameunit(sc->age_dev),
 724                                 CTLFLAG_RD, 0, "");
 725         if (sc->age_sysctl_tree == NULL) {
 726                 device_printf(sc->age_dev, "can't add sysctl node\n");
 727                 return;
 728         }
 729
 730         SYSCTL_ADD_PROC(&sc->age_sysctl_ctx,
 731             SYSCTL_CHILDREN(sc->age_sysctl_tree), OID_AUTO,
 732             "stats", CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_age_stats,
 733             "I", "Statistics");
 734
 735         SYSCTL_ADD_PROC(&sc->age_sysctl_ctx,
 736             SYSCTL_CHILDREN(sc->age_sysctl_tree), OID_AUTO,
 737             "int_mod", CTLTYPE_INT | CTLFLAG_RW, &sc->age_int_mod, 0,
 738             sysctl_hw_age_int_mod, "I", "age interrupt moderation");
 739
 740         /* Pull in device tunables. */
 741         sc->age_int_mod = AGE_IM_TIMER_DEFAULT;
 742         error = resource_int_value(device_get_name(sc->age_dev),
 743             device_get_unit(sc->age_dev), "int_mod", &sc->age_int_mod);
 744         if (error == 0) {
 745                 if (sc->age_int_mod < AGE_IM_TIMER_MIN ||
 746                     sc->age_int_mod > AGE_IM_TIMER_MAX) {
 747                         device_printf(sc->age_dev,
 748                             "int_mod value out of range; using default: %d\n",
 749                             AGE_IM_TIMER_DEFAULT);
 750                         sc->age_int_mod = AGE_IM_TIMER_DEFAULT;
 751                 }
 752         }
 753 }
 754
 755 struct age_dmamap_arg {
 756         bus_addr_t      age_busaddr;
 757 };
 758
 759 static void
 760 age_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
 761 {
 762         struct age_dmamap_arg *ctx;
 763
 764         if (error != 0)
 765                 return;
 766
 767         KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
 768
 769         ctx = (struct age_dmamap_arg *)arg;
 770         ctx->age_busaddr = segs[0].ds_addr;
 771 }
 772
 773 /*
 774  * Attansic L1 controller have single register to specify high
 775  * address part of DMA blocks. So all descriptor structures and
 776  * DMA memory blocks should have the same high address of given
 777  * 4GB address space(i.e. crossing 4GB boundary is not allowed).
 778  */
 779 static int
 780 age_check_boundary(struct age_softc *sc)
 781 {
 782         bus_addr_t rx_ring_end, rr_ring_end, tx_ring_end;
 783         bus_addr_t cmb_block_end, smb_block_end;
 784
 785         /* Tx/Rx descriptor queue should reside within 4GB boundary. */
 786         tx_ring_end = sc->age_rdata.age_tx_ring_paddr + AGE_TX_RING_SZ;
 787         rx_ring_end = sc->age_rdata.age_rx_ring_paddr + AGE_RX_RING_SZ;
 788         rr_ring_end = sc->age_rdata.age_rr_ring_paddr + AGE_RR_RING_SZ;
 789         cmb_block_end = sc->age_rdata.age_cmb_block_paddr + AGE_CMB_BLOCK_SZ;
 790         smb_block_end = sc->age_rdata.age_smb_block_paddr + AGE_SMB_BLOCK_SZ;
 791
 792         if ((AGE_ADDR_HI(tx_ring_end) !=
 793             AGE_ADDR_HI(sc->age_rdata.age_tx_ring_paddr)) ||
 794             (AGE_ADDR_HI(rx_ring_end) !=
 795             AGE_ADDR_HI(sc->age_rdata.age_rx_ring_paddr)) ||
 796             (AGE_ADDR_HI(rr_ring_end) !=
 797             AGE_ADDR_HI(sc->age_rdata.age_rr_ring_paddr)) ||
 798             (AGE_ADDR_HI(cmb_block_end) !=
 799             AGE_ADDR_HI(sc->age_rdata.age_cmb_block_paddr)) ||
 800             (AGE_ADDR_HI(smb_block_end) !=
 801             AGE_ADDR_HI(sc->age_rdata.age_smb_block_paddr)))
 802                 return (EFBIG);
 803
 804         if ((AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rx_ring_end)) ||
 805             (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rr_ring_end)) ||
 806             (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(cmb_block_end)) ||
 807             (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(smb_block_end)))
 808                 return (EFBIG);
 809
 810         return (0);
 811 }
 812
 813 static int
 814 age_dma_alloc(struct age_softc *sc)
 815 {
 816         struct age_txdesc *txd;
 817         struct age_rxdesc *rxd;
 818         bus_addr_t lowaddr;
 819         struct age_dmamap_arg ctx;
 820         int error, i;
 821
 822         lowaddr = BUS_SPACE_MAXADDR;
 823 again:
 824         /* Create parent ring/DMA block tag. */
 825         error = bus_dma_tag_create(
 826             NULL,                       /* parent */
 827             1, 0,                       /* alignment, boundary */
 828             lowaddr,                    /* lowaddr */
 829             BUS_SPACE_MAXADDR,          /* highaddr */
 830             NULL, NULL,                 /* filter, filterarg */
 831             BUS_SPACE_MAXSIZE_32BIT,    /* maxsize */
 832             0,                          /* nsegments */
 833             BUS_SPACE_MAXSIZE_32BIT,    /* maxsegsize */
 834             0,                          /* flags */
 835             &sc->age_cdata.age_parent_tag);
 836         if (error != 0) {
 837                 device_printf(sc->age_dev,
 838                     "could not create parent DMA tag.\n");
 839                 goto fail;
 840         }
 841
 842         /* Create tag for Tx ring. */
 843         error = bus_dma_tag_create(
 844             sc->age_cdata.age_parent_tag, /* parent */
 845             AGE_TX_RING_ALIGN, 0,       /* alignment, boundary */
 846             BUS_SPACE_MAXADDR,          /* lowaddr */
 847             BUS_SPACE_MAXADDR,          /* highaddr */
 848             NULL, NULL,                 /* filter, filterarg */
 849             AGE_TX_RING_SZ,             /* maxsize */
 850             1,                          /* nsegments */
 851             AGE_TX_RING_SZ,             /* maxsegsize */
 852             0,                          /* flags */
 853             &sc->age_cdata.age_tx_ring_tag);
 854         if (error != 0) {
 855                 device_printf(sc->age_dev,
 856                     "could not create Tx ring DMA tag.\n");
 857                 goto fail;
 858         }
 859
 860         /* Create tag for Rx ring. */
 861         error = bus_dma_tag_create(
 862             sc->age_cdata.age_parent_tag, /* parent */
 863             AGE_RX_RING_ALIGN, 0,       /* alignment, boundary */
 864             BUS_SPACE_MAXADDR,          /* lowaddr */
 865             BUS_SPACE_MAXADDR,          /* highaddr */
 866             NULL, NULL,                 /* filter, filterarg */
 867             AGE_RX_RING_SZ,             /* maxsize */
 868             1,                          /* nsegments */
 869             AGE_RX_RING_SZ,             /* maxsegsize */
 870             0,                          /* flags */
 871             &sc->age_cdata.age_rx_ring_tag);
 872         if (error != 0) {
 873                 device_printf(sc->age_dev,
 874                     "could not create Rx ring DMA tag.\n");
 875                 goto fail;
 876         }
 877
 878         /* Create tag for Rx return ring. */
 879         error = bus_dma_tag_create(
 880             sc->age_cdata.age_parent_tag, /* parent */
 881             AGE_RR_RING_ALIGN, 0,       /* alignment, boundary */
 882             BUS_SPACE_MAXADDR,          /* lowaddr */
 883             BUS_SPACE_MAXADDR,          /* highaddr */
 884             NULL, NULL,                 /* filter, filterarg */
 885             AGE_RR_RING_SZ,             /* maxsize */
 886             1,                          /* nsegments */
 887             AGE_RR_RING_SZ,             /* maxsegsize */
 888             0,                          /* flags */
 889             &sc->age_cdata.age_rr_ring_tag);
 890         if (error != 0) {
 891                 device_printf(sc->age_dev,
 892                     "could not create Rx return ring DMA tag.\n");
 893                 goto fail;
 894         }
 895
 896         /* Create tag for coalesing message block. */
 897         error = bus_dma_tag_create(
 898             sc->age_cdata.age_parent_tag, /* parent */
 899             AGE_CMB_ALIGN, 0,           /* alignment, boundary */
 900             BUS_SPACE_MAXADDR,          /* lowaddr */
 901             BUS_SPACE_MAXADDR,          /* highaddr */
 902             NULL, NULL,                 /* filter, filterarg */
 903             AGE_CMB_BLOCK_SZ,           /* maxsize */
 904             1,                          /* nsegments */
 905             AGE_CMB_BLOCK_SZ,           /* maxsegsize */
 906             0,                          /* flags */
 907             &sc->age_cdata.age_cmb_block_tag);
 908         if (error != 0) {
 909                 device_printf(sc->age_dev,
 910                     "could not create CMB DMA tag.\n");
 911                 goto fail;
 912         }
 913
 914         /* Create tag for statistics message block. */
 915         error = bus_dma_tag_create(
 916             sc->age_cdata.age_parent_tag, /* parent */
 917             AGE_SMB_ALIGN, 0,           /* alignment, boundary */
 918             BUS_SPACE_MAXADDR,          /* lowaddr */
 919             BUS_SPACE_MAXADDR,          /* highaddr */
 920             NULL, NULL,                 /* filter, filterarg */
 921             AGE_SMB_BLOCK_SZ,           /* maxsize */
 922             1,                          /* nsegments */
 923             AGE_SMB_BLOCK_SZ,           /* maxsegsize */
 924             0,                          /* flags */
 925             &sc->age_cdata.age_smb_block_tag);
 926         if (error != 0) {
 927                 device_printf(sc->age_dev,
 928                     "could not create SMB DMA tag.\n");
 929                 goto fail;
 930         }
 931
 932         /* Allocate DMA'able memory and load the DMA map. */
 933         error = bus_dmamem_alloc(sc->age_cdata.age_tx_ring_tag,
 934             (void **)&sc->age_rdata.age_tx_ring,
 935             BUS_DMA_WAITOK | BUS_DMA_ZERO,
 936             &sc->age_cdata.age_tx_ring_map);
 937         if (error != 0) {
 938                 device_printf(sc->age_dev,
 939                     "could not allocate DMA'able memory for Tx ring.\n");
 940                 goto fail;
 941         }
 942         ctx.age_busaddr = 0;
 943         error = bus_dmamap_load(sc->age_cdata.age_tx_ring_tag,
 944             sc->age_cdata.age_tx_ring_map, sc->age_rdata.age_tx_ring,
 945             AGE_TX_RING_SZ, age_dmamap_cb, &ctx, 0);
 946         if (error != 0 || ctx.age_busaddr == 0) {
 947                 device_printf(sc->age_dev,
 948                     "could not load DMA'able memory for Tx ring.\n");
 949                 goto fail;
 950         }
 951         sc->age_rdata.age_tx_ring_paddr = ctx.age_busaddr;
 952         /* Rx ring */
 953         error = bus_dmamem_alloc(sc->age_cdata.age_rx_ring_tag,
 954             (void **)&sc->age_rdata.age_rx_ring,
 955             BUS_DMA_WAITOK | BUS_DMA_ZERO,
 956             &sc->age_cdata.age_rx_ring_map);
 957         if (error != 0) {
 958                 device_printf(sc->age_dev,
 959                     "could not allocate DMA'able memory for Rx ring.\n");
 960                 goto fail;
 961         }
 962         ctx.age_busaddr = 0;
 963         error = bus_dmamap_load(sc->age_cdata.age_rx_ring_tag,
 964             sc->age_cdata.age_rx_ring_map, sc->age_rdata.age_rx_ring,
 965             AGE_RX_RING_SZ, age_dmamap_cb, &ctx, 0);
 966         if (error != 0 || ctx.age_busaddr == 0) {
 967                 device_printf(sc->age_dev,
 968                     "could not load DMA'able memory for Rx ring.\n");
 969                 goto fail;
 970         }
 971         sc->age_rdata.age_rx_ring_paddr = ctx.age_busaddr;
 972         /* Rx return ring */
 973         error = bus_dmamem_alloc(sc->age_cdata.age_rr_ring_tag,
 974             (void **)&sc->age_rdata.age_rr_ring,
 975             BUS_DMA_WAITOK | BUS_DMA_ZERO,
 976             &sc->age_cdata.age_rr_ring_map);
 977         if (error != 0) {
 978                 device_printf(sc->age_dev,
 979                     "could not allocate DMA'able memory for Rx return ring.\n");
 980                 goto fail;
 981         }
 982         ctx.age_busaddr = 0;
 983         error = bus_dmamap_load(sc->age_cdata.age_rr_ring_tag,
 984             sc->age_cdata.age_rr_ring_map, sc->age_rdata.age_rr_ring,
 985             AGE_RR_RING_SZ, age_dmamap_cb, &ctx, 0);
 986         if (error != 0 || ctx.age_busaddr == 0) {
 987                 device_printf(sc->age_dev,
 988                     "could not load DMA'able memory for Rx return ring.\n");
 989                 goto fail;
 990         }
 991         sc->age_rdata.age_rr_ring_paddr = ctx.age_busaddr;
 992         /* CMB block */
 993         error = bus_dmamem_alloc(sc->age_cdata.age_cmb_block_tag,
 994             (void **)&sc->age_rdata.age_cmb_block,
 995             BUS_DMA_WAITOK | BUS_DMA_ZERO,
 996             &sc->age_cdata.age_cmb_block_map);
 997         if (error != 0) {
 998                 device_printf(sc->age_dev,
 999                     "could not allocate DMA'able memory for CMB block.\n");
1000                 goto fail;
1001         }
1002         ctx.age_busaddr = 0;
1003         error = bus_dmamap_load(sc->age_cdata.age_cmb_block_tag,
1004             sc->age_cdata.age_cmb_block_map, sc->age_rdata.age_cmb_block,
1005             AGE_CMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0);
1006         if (error != 0 || ctx.age_busaddr == 0) {
1007                 device_printf(sc->age_dev,
1008                     "could not load DMA'able memory for CMB block.\n");
1009                 goto fail;
1010         }
1011         sc->age_rdata.age_cmb_block_paddr = ctx.age_busaddr;
1012         /* SMB block */
1013         error = bus_dmamem_alloc(sc->age_cdata.age_smb_block_tag,
1014             (void **)&sc->age_rdata.age_smb_block,
1015             BUS_DMA_WAITOK | BUS_DMA_ZERO,
1016             &sc->age_cdata.age_smb_block_map);
1017         if (error != 0) {
1018                 device_printf(sc->age_dev,
1019                     "could not allocate DMA'able memory for SMB block.\n");
1020                 goto fail;
1021         }
1022         ctx.age_busaddr = 0;
1023         error = bus_dmamap_load(sc->age_cdata.age_smb_block_tag,
1024             sc->age_cdata.age_smb_block_map, sc->age_rdata.age_smb_block,
1025             AGE_SMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0);
1026         if (error != 0 || ctx.age_busaddr == 0) {
1027                 device_printf(sc->age_dev,
1028                     "could not load DMA'able memory for SMB block.\n");
1029                 goto fail;
1030         }
1031         sc->age_rdata.age_smb_block_paddr = ctx.age_busaddr;
1032
1033         /*
1034          * All ring buffer and DMA blocks should have the same
1035          * high address part of 64bit DMA address space.
1036          */
1037         if (lowaddr != BUS_SPACE_MAXADDR_32BIT &&
1038             (error = age_check_boundary(sc)) != 0) {
1039                 device_printf(sc->age_dev, "4GB boundary crossed, "
1040                     "switching to 32bit DMA addressing mode.\n");
1041                 age_dma_free(sc);
1042                 /* Limit DMA address space to 32bit and try again. */
1043                 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1044                 goto again;
1045         }
1046
1047         /*
1048          * Create Tx/Rx buffer parent tag.
1049          * L1 supports full 64bit DMA addressing in Tx/Rx buffers
1050          * so it needs separate parent DMA tag.
1051          */
1052         error = bus_dma_tag_create(
1053             NULL,                       /* parent */
1054             1, 0,                       /* alignment, boundary */
1055             BUS_SPACE_MAXADDR,          /* lowaddr */
1056             BUS_SPACE_MAXADDR,          /* highaddr */
1057             NULL, NULL,                 /* filter, filterarg */
1058             BUS_SPACE_MAXSIZE_32BIT,    /* maxsize */
1059             0,                          /* nsegments */
1060             BUS_SPACE_MAXSIZE_32BIT,    /* maxsegsize */
1061             0,                          /* flags */
1062             &sc->age_cdata.age_buffer_tag);
1063         if (error != 0) {
1064                 device_printf(sc->age_dev,
1065                     "could not create parent buffer DMA tag.\n");
1066                 goto fail;
1067         }
1068
1069         /* Create tag for Tx buffers. */
1070         error = bus_dma_tag_create(
1071             sc->age_cdata.age_buffer_tag, /* parent */
1072             1, 0,                       /* alignment, boundary */
1073             BUS_SPACE_MAXADDR,          /* lowaddr */
1074             BUS_SPACE_MAXADDR,          /* highaddr */
1075             NULL, NULL,                 /* filter, filterarg */
1076             AGE_TSO_MAXSIZE,            /* maxsize */
1077             AGE_MAXTXSEGS,              /* nsegments */
1078             AGE_TSO_MAXSEGSIZE,         /* maxsegsize */
1079             0,                          /* flags */
1080             &sc->age_cdata.age_tx_tag);
1081         if (error != 0) {
1082                 device_printf(sc->age_dev, "could not create Tx DMA tag.\n");
1083                 goto fail;
1084         }
1085
1086         /* Create tag for Rx buffers. */
1087         error = bus_dma_tag_create(
1088             sc->age_cdata.age_buffer_tag, /* parent */
1089             1, 0,                       /* alignment, boundary */
1090             BUS_SPACE_MAXADDR,          /* lowaddr */
1091             BUS_SPACE_MAXADDR,          /* highaddr */
1092             NULL, NULL,                 /* filter, filterarg */
1093             MCLBYTES,                   /* maxsize */
1094             1,                          /* nsegments */
1095             MCLBYTES,                   /* maxsegsize */
1096             0,                          /* flags */
1097             &sc->age_cdata.age_rx_tag);
1098         if (error != 0) {
1099                 device_printf(sc->age_dev, "could not create Rx DMA tag.\n");
1100                 goto fail;
1101         }
1102
1103         /* Create DMA maps for Tx buffers. */
1104         for (i = 0; i < AGE_TX_RING_CNT; i++) {
1105                 txd = &sc->age_cdata.age_txdesc[i];
1106                 txd->tx_m = NULL;
1107                 txd->tx_dmamap = NULL;
1108                 error = bus_dmamap_create(sc->age_cdata.age_tx_tag, 0,
1109                     &txd->tx_dmamap);
1110                 if (error != 0) {
1111                         device_printf(sc->age_dev,
1112                             "could not create Tx dmamap.\n");
1113                         goto fail;
1114                 }
1115         }
1116         /* Create DMA maps for Rx buffers. */
1117         if ((error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0,
1118             &sc->age_cdata.age_rx_sparemap)) != 0) {
1119                 device_printf(sc->age_dev,
1120                     "could not create spare Rx dmamap.\n");
1121                 goto fail;
1122         }
1123         for (i = 0; i < AGE_RX_RING_CNT; i++) {
1124                 rxd = &sc->age_cdata.age_rxdesc[i];
1125                 rxd->rx_m = NULL;
1126                 rxd->rx_dmamap = NULL;
1127                 error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0,
1128                     &rxd->rx_dmamap);
1129                 if (error != 0) {
1130                         device_printf(sc->age_dev,
1131                             "could not create Rx dmamap.\n");
1132                         goto fail;
1133                 }
1134         }
1135 fail:
1136         return (error);
1137 }
1138
1139 static void
1140 age_dma_free(struct age_softc *sc)
1141 {
1142         struct age_txdesc *txd;
1143         struct age_rxdesc *rxd;
1144         int i;
1145
1146         /* Tx buffers */
1147         if (sc->age_cdata.age_tx_tag != NULL) {
1148                 for (i = 0; i < AGE_TX_RING_CNT; i++) {
1149                         txd = &sc->age_cdata.age_txdesc[i];
1150                         if (txd->tx_dmamap != NULL) {
1151                                 bus_dmamap_destroy(sc->age_cdata.age_tx_tag,
1152                                     txd->tx_dmamap);
1153                                 txd->tx_dmamap = NULL;
1154                         }
1155                 }
1156                 bus_dma_tag_destroy(sc->age_cdata.age_tx_tag);
1157                 sc->age_cdata.age_tx_tag = NULL;
1158         }
1159         /* Rx buffers */
1160         if (sc->age_cdata.age_rx_tag != NULL) {
1161                 for (i = 0; i < AGE_RX_RING_CNT; i++) {
1162                         rxd = &sc->age_cdata.age_rxdesc[i];
1163                         if (rxd->rx_dmamap != NULL) {
1164                                 bus_dmamap_destroy(sc->age_cdata.age_rx_tag,
1165                                     rxd->rx_dmamap);
1166                                 rxd->rx_dmamap = NULL;
1167                         }
1168                 }
1169                 if (sc->age_cdata.age_rx_sparemap != NULL) {
1170                         bus_dmamap_destroy(sc->age_cdata.age_rx_tag,
1171                             sc->age_cdata.age_rx_sparemap);
1172                         sc->age_cdata.age_rx_sparemap = NULL;
1173                 }
1174                 bus_dma_tag_destroy(sc->age_cdata.age_rx_tag);
1175                 sc->age_cdata.age_rx_tag = NULL;
1176         }
1177         /* Tx ring. */
1178         if (sc->age_cdata.age_tx_ring_tag != NULL) {
1179                 if (sc->age_cdata.age_tx_ring_map != NULL)
1180                         bus_dmamap_unload(sc->age_cdata.age_tx_ring_tag,
1181                             sc->age_cdata.age_tx_ring_map);
1182                 if (sc->age_cdata.age_tx_ring_map != NULL &&
1183                     sc->age_rdata.age_tx_ring != NULL)
1184                         bus_dmamem_free(sc->age_cdata.age_tx_ring_tag,
1185                             sc->age_rdata.age_tx_ring,
1186                             sc->age_cdata.age_tx_ring_map);
1187                 sc->age_rdata.age_tx_ring = NULL;
1188                 sc->age_cdata.age_tx_ring_map = NULL;
1189                 bus_dma_tag_destroy(sc->age_cdata.age_tx_ring_tag);
1190                 sc->age_cdata.age_tx_ring_tag = NULL;
1191         }
1192         /* Rx ring. */
1193         if (sc->age_cdata.age_rx_ring_tag != NULL) {
1194                 if (sc->age_cdata.age_rx_ring_map != NULL)
1195                         bus_dmamap_unload(sc->age_cdata.age_rx_ring_tag,
1196                             sc->age_cdata.age_rx_ring_map);
1197                 if (sc->age_cdata.age_rx_ring_map != NULL &&
1198                     sc->age_rdata.age_rx_ring != NULL)
1199                         bus_dmamem_free(sc->age_cdata.age_rx_ring_tag,
1200                             sc->age_rdata.age_rx_ring,
1201                             sc->age_cdata.age_rx_ring_map);
1202                 sc->age_rdata.age_rx_ring = NULL;
1203                 sc->age_cdata.age_rx_ring_map = NULL;
1204                 bus_dma_tag_destroy(sc->age_cdata.age_rx_ring_tag);
1205                 sc->age_cdata.age_rx_ring_tag = NULL;
1206         }
1207         /* Rx return ring. */
1208         if (sc->age_cdata.age_rr_ring_tag != NULL) {
1209                 if (sc->age_cdata.age_rr_ring_map != NULL)
1210                         bus_dmamap_unload(sc->age_cdata.age_rr_ring_tag,
1211                             sc->age_cdata.age_rr_ring_map);
1212                 if (sc->age_cdata.age_rr_ring_map != NULL &&
1213                     sc->age_rdata.age_rr_ring != NULL)
1214                         bus_dmamem_free(sc->age_cdata.age_rr_ring_tag,
1215                             sc->age_rdata.age_rr_ring,
1216                             sc->age_cdata.age_rr_ring_map);
1217                 sc->age_rdata.age_rr_ring = NULL;
1218                 sc->age_cdata.age_rr_ring_map = NULL;
1219                 bus_dma_tag_destroy(sc->age_cdata.age_rr_ring_tag);
1220                 sc->age_cdata.age_rr_ring_tag = NULL;
1221         }
1222         /* CMB block */
1223         if (sc->age_cdata.age_cmb_block_tag != NULL) {
1224                 if (sc->age_cdata.age_cmb_block_map != NULL)
1225                         bus_dmamap_unload(sc->age_cdata.age_cmb_block_tag,
1226                             sc->age_cdata.age_cmb_block_map);
1227                 if (sc->age_cdata.age_cmb_block_map != NULL &&
1228                     sc->age_rdata.age_cmb_block != NULL)
1229                         bus_dmamem_free(sc->age_cdata.age_cmb_block_tag,
1230                             sc->age_rdata.age_cmb_block,
1231                             sc->age_cdata.age_cmb_block_map);
1232                 sc->age_rdata.age_cmb_block = NULL;
1233                 sc->age_cdata.age_cmb_block_map = NULL;
1234                 bus_dma_tag_destroy(sc->age_cdata.age_cmb_block_tag);
1235                 sc->age_cdata.age_cmb_block_tag = NULL;
1236         }
1237         /* SMB block */
1238         if (sc->age_cdata.age_smb_block_tag != NULL) {
1239                 if (sc->age_cdata.age_smb_block_map != NULL)
1240                         bus_dmamap_unload(sc->age_cdata.age_smb_block_tag,
1241                             sc->age_cdata.age_smb_block_map);
1242                 if (sc->age_cdata.age_smb_block_map != NULL &&
1243                     sc->age_rdata.age_smb_block != NULL)
1244                         bus_dmamem_free(sc->age_cdata.age_smb_block_tag,
1245                             sc->age_rdata.age_smb_block,
1246                             sc->age_cdata.age_smb_block_map);
1247                 sc->age_rdata.age_smb_block = NULL;
1248                 sc->age_cdata.age_smb_block_map = NULL;
1249                 bus_dma_tag_destroy(sc->age_cdata.age_smb_block_tag);
1250                 sc->age_cdata.age_smb_block_tag = NULL;
1251         }
1252
1253         if (sc->age_cdata.age_buffer_tag != NULL) {
1254                 bus_dma_tag_destroy(sc->age_cdata.age_buffer_tag);
1255                 sc->age_cdata.age_buffer_tag = NULL;
1256         }
1257         if (sc->age_cdata.age_parent_tag != NULL) {
1258                 bus_dma_tag_destroy(sc->age_cdata.age_parent_tag);
1259                 sc->age_cdata.age_parent_tag = NULL;
1260         }
1261 }
1262
1263 /*
1264  *      Make sure the interface is stopped at reboot time.
1265  */
1266 static int
1267 age_shutdown(device_t dev)
1268 {
1269         return age_suspend(dev);
1270 }
1271
1272 #ifdef wol_notyet
1273
1274 static void
1275 age_setwol(struct age_softc *sc)
1276 {
1277         struct ifnet *ifp;
1278         struct mii_data *mii;
1279         uint32_t reg, pmcs;
1280         uint16_t pmstat;
1281         int aneg, i, pmc;
1282
1283         AGE_LOCK_ASSERT(sc);
1284
1285         if (pci_find_extcap(sc->age_dev, PCIY_PMG, &pmc) == 0) {
1286                 CSR_WRITE_4(sc, AGE_WOL_CFG, 0);
1287                 /*
1288                  * No PME capability, PHY power down.
1289                  * XXX
1290                  * Due to an unknown reason powering down PHY resulted
1291                  * in unexpected results such as inaccessbility of
1292                  * hardware of freshly rebooted system. Disable
1293                  * powering down PHY until I got more information for
1294                  * Attansic/Atheros PHY hardwares.
1295                  */
1296 #ifdef notyet
1297                 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1298                     MII_BMCR, BMCR_PDOWN);
1299 #endif
1300                 return;
1301         }
1302
1303         ifp = sc->age_ifp;
1304         if ((ifp->if_capenable & IFCAP_WOL) != 0) {
1305                 /*
1306                  * Note, this driver resets the link speed to 10/100Mbps with
1307                  * auto-negotiation but we don't know whether that operation
1308                  * would succeed or not as it have no control after powering
1309                  * off. If the renegotiation fail WOL may not work. Running
1310                  * at 1Gbps will draw more power than 375mA at 3.3V which is
1311                  * specified in PCI specification and that would result in
1312                  * complete shutdowning power to ethernet controller.
1313                  *
1314                  * TODO
1315                  *  Save current negotiated media speed/duplex/flow-control
1316                  *  to softc and restore the same link again after resuming.
1317                  *  PHY handling such as power down/resetting to 100Mbps
1318                  *  may be better handled in suspend method in phy driver.
1319                  */
1320                 mii = device_get_softc(sc->age_miibus);
1321                 mii_pollstat(mii);
1322                 aneg = 0;
1323                 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1324                         switch IFM_SUBTYPE(mii->mii_media_active) {
1325                         case IFM_10_T:
1326                         case IFM_100_TX:
1327                                 goto got_link;
1328                         case IFM_1000_T:
1329                                 aneg++;
1330                         default:
1331                                 break;
1332                         }
1333                 }
1334                 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1335                     MII_100T2CR, 0);
1336                 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1337                     MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD |
1338                     ANAR_10 | ANAR_CSMA);
1339                 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1340                     MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
1341                 DELAY(1000);
1342                 if (aneg != 0) {
1343                         /* Poll link state until age(4) get a 10/100 link. */
1344                         for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1345                                 mii_pollstat(mii);
1346                                 if ((mii->mii_media_status & IFM_AVALID) != 0) {
1347                                         switch (IFM_SUBTYPE(
1348                                             mii->mii_media_active)) {
1349                                         case IFM_10_T:
1350                                         case IFM_100_TX:
1351                                                 age_mac_config(sc);
1352                                                 goto got_link;
1353                                         default:
1354                                                 break;
1355                                         }
1356                                 }
1357                                 AGE_UNLOCK(sc);
1358                                 pause("agelnk", hz);
1359                                 AGE_LOCK(sc);
1360                         }
1361                         if (i == MII_ANEGTICKS_GIGE)
1362                                 device_printf(sc->age_dev,
1363                                     "establishing link failed, "
1364                                     "WOL may not work!");
1365                 }
1366                 /*
1367                  * No link, force MAC to have 100Mbps, full-duplex link.
1368                  * This is the last resort and may/may not work.
1369                  */
1370                 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1371                 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1372                 age_mac_config(sc);
1373         }
1374
1375 got_link:
1376         pmcs = 0;
1377         if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
1378                 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB;
1379         CSR_WRITE_4(sc, AGE_WOL_CFG, pmcs);
1380         reg = CSR_READ_4(sc, AGE_MAC_CFG);
1381         reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC);
1382         reg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST);
1383         if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
1384                 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST;
1385         if ((ifp->if_capenable & IFCAP_WOL) != 0) {
1386                 reg |= MAC_CFG_RX_ENB;
1387                 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
1388         }
1389
1390         /* Request PME. */
1391         pmstat = pci_read_config(sc->age_dev, pmc + PCIR_POWER_STATUS, 2);
1392         pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1393         if ((ifp->if_capenable & IFCAP_WOL) != 0)
1394                 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1395         pci_write_config(sc->age_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1396 #ifdef notyet
1397         /* See above for powering down PHY issues. */
1398         if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1399                 /* No WOL, PHY power down. */
1400                 age_miibus_writereg(sc->age_dev, sc->age_phyaddr,
1401                     MII_BMCR, BMCR_PDOWN);
1402         }
1403 #endif
1404 }
1405
1406 #endif  /* wol_notyet */
1407
1408 static int
1409 age_suspend(device_t dev)
1410 {
1411         struct age_softc *sc = device_get_softc(dev);
1412         struct ifnet *ifp = &sc->arpcom.ac_if;
1413
1414         lwkt_serialize_enter(ifp->if_serializer);
1415         age_stop(sc);
1416 #ifdef wol_notyet
1417         age_setwol(sc);
1418 #endif
1419         lwkt_serialize_exit(ifp->if_serializer);
1420
1421         return (0);
1422 }
1423
1424 static int
1425 age_resume(device_t dev)
1426 {
1427         struct age_softc *sc = device_get_softc(dev);
1428         struct ifnet *ifp = &sc->arpcom.ac_if;
1429         uint16_t cmd;
1430
1431         lwkt_serialize_enter(ifp->if_serializer);
1432
1433         /*
1434          * Clear INTx emulation disable for hardwares that
1435          * is set in resume event. From Linux.
1436          */
1437         cmd = pci_read_config(sc->age_dev, PCIR_COMMAND, 2);
1438         if ((cmd & 0x0400) != 0) {
1439                 cmd &= ~0x0400;
1440                 pci_write_config(sc->age_dev, PCIR_COMMAND, cmd, 2);
1441         }
1442         if ((ifp->if_flags & IFF_UP) != 0)
1443                 age_init(sc);
1444
1445         lwkt_serialize_exit(ifp->if_serializer);
1446
1447         return (0);
1448 }
1449
1450 static int
1451 age_encap(struct age_softc *sc, struct mbuf **m_head)
1452 {
1453         struct age_txdesc *txd, *txd_last;
1454         struct tx_desc *desc;
1455         struct mbuf *m;
1456         struct age_dmamap_ctx ctx;
1457         bus_dma_segment_t txsegs[AGE_MAXTXSEGS];
1458         bus_dmamap_t map;
1459         uint32_t cflags, poff, vtag;
1460         int error, i, nsegs, prod;
1461
1462         M_ASSERTPKTHDR((*m_head));
1463
1464         m = *m_head;
1465         cflags = vtag = 0;
1466         poff = 0;
1467
1468         prod = sc->age_cdata.age_tx_prod;
1469         txd = &sc->age_cdata.age_txdesc[prod];
1470         txd_last = txd;
1471         map = txd->tx_dmamap;
1472
1473         ctx.nsegs = AGE_MAXTXSEGS;
1474         ctx.segs = txsegs;
1475         error = bus_dmamap_load_mbuf(sc->age_cdata.age_tx_tag, map,
1476                                      *m_head, age_dmamap_buf_cb, &ctx,
1477                                      BUS_DMA_NOWAIT);
1478         if (!error && ctx.nsegs == 0) {
1479                 bus_dmamap_unload(sc->age_cdata.age_tx_tag, map);
1480                 error = EFBIG;
1481         }
1482         if (error == EFBIG) {
1483                 m = m_defrag(*m_head, MB_DONTWAIT);
1484                 if (m == NULL) {
1485                         m_freem(*m_head);
1486                         *m_head = NULL;
1487                         return (ENOBUFS);
1488                 }
1489                 *m_head = m;
1490
1491                 ctx.nsegs = AGE_MAXTXSEGS;
1492                 ctx.segs = txsegs;
1493                 error = bus_dmamap_load_mbuf(sc->age_cdata.age_tx_tag, map,
1494                                              *m_head, age_dmamap_buf_cb, &ctx,
1495                                              BUS_DMA_NOWAIT);
1496                 if (error || ctx.nsegs == 0) {
1497                         if (!error) {
1498                                 bus_dmamap_unload(sc->age_cdata.age_tx_tag,
1499                                                   map);
1500                                 error = EFBIG;
1501                         }
1502                         m_freem(*m_head);
1503                         *m_head = NULL;
1504                         return (error);
1505                 }
1506         } else if (error != 0) {
1507                 return (error);
1508         }
1509         nsegs = ctx.nsegs;
1510
1511         if (nsegs == 0) {
1512                 m_freem(*m_head);
1513                 *m_head = NULL;
1514                 return (EIO);
1515         }
1516
1517         /* Check descriptor overrun. */
1518         if (sc->age_cdata.age_tx_cnt + nsegs >= AGE_TX_RING_CNT - 2) {
1519                 bus_dmamap_unload(sc->age_cdata.age_tx_tag, map);
1520                 return (ENOBUFS);
1521         }
1522
1523         m = *m_head;
1524         /* Configure Tx IP/TCP/UDP checksum offload. */
1525         if ((m->m_pkthdr.csum_flags & AGE_CSUM_FEATURES) != 0) {
1526                 cflags |= AGE_TD_CSUM;
1527                 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0)
1528                         cflags |= AGE_TD_TCPCSUM;
1529                 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0)
1530                         cflags |= AGE_TD_UDPCSUM;
1531                 /* Set checksum start offset. */
1532                 cflags |= (poff << AGE_TD_CSUM_PLOADOFFSET_SHIFT);
1533                 /* Set checksum insertion position of TCP/UDP. */
1534                 cflags |= ((poff + m->m_pkthdr.csum_data) <<
1535                     AGE_TD_CSUM_XSUMOFFSET_SHIFT);
1536         }
1537
1538         /* Configure VLAN hardware tag insertion. */
1539         if ((m->m_flags & M_VLANTAG) != 0) {
1540                 vtag = AGE_TX_VLAN_TAG(m->m_pkthdr.ether_vlantag);
1541                 vtag = ((vtag << AGE_TD_VLAN_SHIFT) & AGE_TD_VLAN_MASK);
1542                 cflags |= AGE_TD_INSERT_VLAN_TAG;
1543         }
1544
1545         desc = NULL;
1546         for (i = 0; i < nsegs; i++) {
1547                 desc = &sc->age_rdata.age_tx_ring[prod];
1548                 desc->addr = htole64(txsegs[i].ds_addr);
1549                 desc->len = htole32(AGE_TX_BYTES(txsegs[i].ds_len) | vtag);
1550                 desc->flags = htole32(cflags);
1551                 sc->age_cdata.age_tx_cnt++;
1552                 AGE_DESC_INC(prod, AGE_TX_RING_CNT);
1553         }
1554         /* Update producer index. */
1555         sc->age_cdata.age_tx_prod = prod;
1556
1557         /* Set EOP on the last descriptor. */
1558         prod = (prod + AGE_TX_RING_CNT - 1) % AGE_TX_RING_CNT;
1559         desc = &sc->age_rdata.age_tx_ring[prod];
1560         desc->flags |= htole32(AGE_TD_EOP);
1561
1562         /* Swap dmamap of the first and the last. */
1563         txd = &sc->age_cdata.age_txdesc[prod];
1564         map = txd_last->tx_dmamap;
1565         txd_last->tx_dmamap = txd->tx_dmamap;
1566         txd->tx_dmamap = map;
1567         txd->tx_m = m;
1568
1569         /* Sync descriptors. */
1570         bus_dmamap_sync(sc->age_cdata.age_tx_tag, map, BUS_DMASYNC_PREWRITE);
1571         bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag,
1572             sc->age_cdata.age_tx_ring_map, BUS_DMASYNC_PREWRITE);
1573
1574         return (0);
1575 }
1576
1577 static void
1578 age_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
1579 {
1580         struct age_softc *sc = ifp->if_softc;
1581         struct mbuf *m_head;
1582         int enq;
1583
1584         ASSERT_ALTQ_SQ_DEFAULT(ifp, ifsq);
1585         ASSERT_SERIALIZED(ifp->if_serializer);
1586
1587         if ((sc->age_flags & AGE_FLAG_LINK) == 0) {
1588                 ifq_purge(&ifp->if_snd);
1589                 return;
1590         }
1591
1592         if ((ifp->if_flags & IFF_RUNNING) == 0 || ifq_is_oactive(&ifp->if_snd))
1593                 return;
1594
1595         enq = 0;
1596         while (!ifq_is_empty(&ifp->if_snd)) {
1597                 m_head = ifq_dequeue(&ifp->if_snd);
1598                 if (m_head == NULL)
1599                         break;
1600
1601                 /*
1602                  * Pack the data into the transmit ring. If we
1603                  * don't have room, set the OACTIVE flag and wait
1604                  * for the NIC to drain the ring.
1605                  */
1606                 if (age_encap(sc, &m_head)) {
1607                         if (m_head == NULL)
1608                                 break;
1609                         ifq_prepend(&ifp->if_snd, m_head);
1610                         ifq_set_oactive(&ifp->if_snd);
1611                         break;
1612                 }
1613                 enq = 1;
1614
1615                 /*
1616                  * If there's a BPF listener, bounce a copy of this frame
1617                  * to him.
1618                  */
1619                 ETHER_BPF_MTAP(ifp, m_head);
1620         }
1621
1622         if (enq) {
1623                 /* Update mbox. */
1624                 AGE_COMMIT_MBOX(sc);
1625                 /* Set a timeout in case the chip goes out to lunch. */
1626                 ifp->if_timer = AGE_TX_TIMEOUT;
1627         }
1628 }
1629
1630 static void
1631 age_watchdog(struct ifnet *ifp)
1632 {
1633         struct age_softc *sc = ifp->if_softc;
1634
1635         ASSERT_SERIALIZED(ifp->if_serializer);
1636
1637         if ((sc->age_flags & AGE_FLAG_LINK) == 0) {
1638                 if_printf(ifp, "watchdog timeout (missed link)\n");
1639                 IFNET_STAT_INC(ifp, oerrors, 1);
1640                 age_init(sc);
1641                 return;
1642         }
1643
1644         if (sc->age_cdata.age_tx_cnt == 0) {
1645                 if_printf(ifp,
1646                     "watchdog timeout (missed Tx interrupts) -- recovering\n");
1647                 if (!ifq_is_empty(&ifp->if_snd))
1648                         if_devstart(ifp);
1649                 return;
1650         }
1651
1652         if_printf(ifp, "watchdog timeout\n");
1653         IFNET_STAT_INC(ifp, oerrors, 1);
1654         age_init(sc);
1655         if (!ifq_is_empty(&ifp->if_snd))
1656                 if_devstart(ifp);
1657 }
1658
1659 static int
1660 age_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data, struct ucred *cr)
1661 {
1662         struct age_softc *sc = ifp->if_softc;
1663         struct ifreq *ifr;
1664         struct mii_data *mii;
1665         uint32_t reg;
1666         int error, mask;
1667
1668         ASSERT_SERIALIZED(ifp->if_serializer);
1669
1670         ifr = (struct ifreq *)data;
1671         error = 0;
1672         switch (cmd) {
1673         case SIOCSIFMTU:
1674                 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > AGE_JUMBO_MTU) {
1675                         error = EINVAL;
1676                 } else if (ifp->if_mtu != ifr->ifr_mtu) {
1677                         ifp->if_mtu = ifr->ifr_mtu;
1678                         if ((ifp->if_flags & IFF_RUNNING) != 0)
1679                                 age_init(sc);
1680                 }
1681                 break;
1682
1683         case SIOCSIFFLAGS:
1684                 if ((ifp->if_flags & IFF_UP) != 0) {
1685                         if ((ifp->if_flags & IFF_RUNNING) != 0) {
1686                                 if (((ifp->if_flags ^ sc->age_if_flags)
1687                                     & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
1688                                         age_rxfilter(sc);
1689                         } else {
1690                                 if ((sc->age_flags & AGE_FLAG_DETACH) == 0)
1691                                         age_init(sc);
1692                         }
1693                 } else {
1694                         if ((ifp->if_flags & IFF_RUNNING) != 0)
1695                                 age_stop(sc);
1696                 }
1697                 sc->age_if_flags = ifp->if_flags;
1698                 break;
1699
1700         case SIOCADDMULTI:
1701         case SIOCDELMULTI:
1702                 if ((ifp->if_flags & IFF_RUNNING) != 0)
1703                         age_rxfilter(sc);
1704                 break;
1705
1706         case SIOCSIFMEDIA:
1707         case SIOCGIFMEDIA:
1708                 mii = device_get_softc(sc->age_miibus);
1709                 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
1710                 break;
1711
1712         case SIOCSIFCAP:
1713                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1714
1715                 if ((mask & IFCAP_TXCSUM) != 0 &&
1716                     (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
1717                         ifp->if_capenable ^= IFCAP_TXCSUM;
1718                         if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
1719                                 ifp->if_hwassist |= AGE_CSUM_FEATURES;
1720                         else
1721                                 ifp->if_hwassist &= ~AGE_CSUM_FEATURES;
1722                 }
1723
1724                 if ((mask & IFCAP_RXCSUM) != 0 &&
1725                     (ifp->if_capabilities & IFCAP_RXCSUM) != 0) {
1726                         ifp->if_capenable ^= IFCAP_RXCSUM;
1727                         reg = CSR_READ_4(sc, AGE_MAC_CFG);
1728                         reg &= ~MAC_CFG_RXCSUM_ENB;
1729                         if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
1730                                 reg |= MAC_CFG_RXCSUM_ENB;
1731                         CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
1732                 }
1733
1734                 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
1735                     (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
1736                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1737                         age_rxvlan(sc);
1738                 }
1739                 break;
1740
1741         default:
1742                 error = ether_ioctl(ifp, cmd, data);
1743                 break;
1744         }
1745         return (error);
1746 }
1747
1748 static void
1749 age_mac_config(struct age_softc *sc)
1750 {
1751         struct mii_data *mii = device_get_softc(sc->age_miibus);
1752         uint32_t reg;
1753
1754         reg = CSR_READ_4(sc, AGE_MAC_CFG);
1755         reg &= ~MAC_CFG_FULL_DUPLEX;
1756         reg &= ~(MAC_CFG_TX_FC | MAC_CFG_RX_FC);
1757         reg &= ~MAC_CFG_SPEED_MASK;
1758
1759         /* Reprogram MAC with resolved speed/duplex. */
1760         switch (IFM_SUBTYPE(mii->mii_media_active)) {
1761         case IFM_10_T:
1762         case IFM_100_TX:
1763                 reg |= MAC_CFG_SPEED_10_100;
1764                 break;
1765         case IFM_1000_T:
1766                 reg |= MAC_CFG_SPEED_1000;
1767                 break;
1768         }
1769         if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
1770                 reg |= MAC_CFG_FULL_DUPLEX;
1771 #ifdef notyet
1772                 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
1773                         reg |= MAC_CFG_TX_FC;
1774                 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
1775                         reg |= MAC_CFG_RX_FC;
1776 #endif
1777         }
1778         CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
1779 }
1780
1781 static void
1782 age_stats_update(struct age_softc *sc)
1783 {
1784         struct ifnet *ifp = &sc->arpcom.ac_if;
1785         struct age_stats *stat;
1786         struct smb *smb;
1787
1788         stat = &sc->age_stat;
1789
1790         bus_dmamap_sync(sc->age_cdata.age_smb_block_tag,
1791             sc->age_cdata.age_smb_block_map, BUS_DMASYNC_POSTREAD);
1792
1793         smb = sc->age_rdata.age_smb_block;
1794         if (smb->updated == 0)
1795                 return;
1796
1797         /* Rx stats. */
1798         stat->rx_frames += smb->rx_frames;
1799         stat->rx_bcast_frames += smb->rx_bcast_frames;
1800         stat->rx_mcast_frames += smb->rx_mcast_frames;
1801         stat->rx_pause_frames += smb->rx_pause_frames;
1802         stat->rx_control_frames += smb->rx_control_frames;
1803         stat->rx_crcerrs += smb->rx_crcerrs;
1804         stat->rx_lenerrs += smb->rx_lenerrs;
1805         stat->rx_bytes += smb->rx_bytes;
1806         stat->rx_runts += smb->rx_runts;
1807         stat->rx_fragments += smb->rx_fragments;
1808         stat->rx_pkts_64 += smb->rx_pkts_64;
1809         stat->rx_pkts_65_127 += smb->rx_pkts_65_127;
1810         stat->rx_pkts_128_255 += smb->rx_pkts_128_255;
1811         stat->rx_pkts_256_511 += smb->rx_pkts_256_511;
1812         stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023;
1813         stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518;
1814         stat->rx_pkts_1519_max += smb->rx_pkts_1519_max;
1815         stat->rx_pkts_truncated += smb->rx_pkts_truncated;
1816         stat->rx_fifo_oflows += smb->rx_fifo_oflows;
1817         stat->rx_desc_oflows += smb->rx_desc_oflows;
1818         stat->rx_alignerrs += smb->rx_alignerrs;
1819         stat->rx_bcast_bytes += smb->rx_bcast_bytes;
1820         stat->rx_mcast_bytes += smb->rx_mcast_bytes;
1821         stat->rx_pkts_filtered += smb->rx_pkts_filtered;
1822
1823         /* Tx stats. */
1824         stat->tx_frames += smb->tx_frames;
1825         stat->tx_bcast_frames += smb->tx_bcast_frames;
1826         stat->tx_mcast_frames += smb->tx_mcast_frames;
1827         stat->tx_pause_frames += smb->tx_pause_frames;
1828         stat->tx_excess_defer += smb->tx_excess_defer;
1829         stat->tx_control_frames += smb->tx_control_frames;
1830         stat->tx_deferred += smb->tx_deferred;
1831         stat->tx_bytes += smb->tx_bytes;
1832         stat->tx_pkts_64 += smb->tx_pkts_64;
1833         stat->tx_pkts_65_127 += smb->tx_pkts_65_127;
1834         stat->tx_pkts_128_255 += smb->tx_pkts_128_255;
1835         stat->tx_pkts_256_511 += smb->tx_pkts_256_511;
1836         stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023;
1837         stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518;
1838         stat->tx_pkts_1519_max += smb->tx_pkts_1519_max;
1839         stat->tx_single_colls += smb->tx_single_colls;
1840         stat->tx_multi_colls += smb->tx_multi_colls;
1841         stat->tx_late_colls += smb->tx_late_colls;
1842         stat->tx_excess_colls += smb->tx_excess_colls;
1843         stat->tx_underrun += smb->tx_underrun;
1844         stat->tx_desc_underrun += smb->tx_desc_underrun;
1845         stat->tx_lenerrs += smb->tx_lenerrs;
1846         stat->tx_pkts_truncated += smb->tx_pkts_truncated;
1847         stat->tx_bcast_bytes += smb->tx_bcast_bytes;
1848         stat->tx_mcast_bytes += smb->tx_mcast_bytes;
1849
1850         /* Update counters in ifnet. */
1851         IFNET_STAT_INC(ifp, opackets, smb->tx_frames);
1852
1853         IFNET_STAT_INC(ifp, collisions, smb->tx_single_colls +
1854             smb->tx_multi_colls + smb->tx_late_colls +
1855             smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT);
1856
1857         IFNET_STAT_INC(ifp, oerrors, smb->tx_excess_colls +
1858             smb->tx_late_colls + smb->tx_underrun +
1859             smb->tx_pkts_truncated);
1860
1861         IFNET_STAT_INC(ifp, ipackets, smb->rx_frames);
1862
1863         IFNET_STAT_INC(ifp, ierrors, smb->rx_crcerrs + smb->rx_lenerrs +
1864             smb->rx_runts + smb->rx_pkts_truncated +
1865             smb->rx_fifo_oflows + smb->rx_desc_oflows +
1866             smb->rx_alignerrs);
1867
1868         /* Update done, clear. */
1869         smb->updated = 0;
1870
1871         bus_dmamap_sync(sc->age_cdata.age_smb_block_tag,
1872             sc->age_cdata.age_smb_block_map, BUS_DMASYNC_PREWRITE);
1873 }
1874
1875 static void
1876 age_intr(void *xsc)
1877 {
1878         struct age_softc *sc = xsc;
1879         struct ifnet *ifp = &sc->arpcom.ac_if;
1880         struct cmb *cmb;
1881         uint32_t status;
1882
1883         ASSERT_SERIALIZED(ifp->if_serializer);
1884
1885         status = CSR_READ_4(sc, AGE_INTR_STATUS);
1886         if (status == 0 || (status & AGE_INTRS) == 0)
1887                 return;
1888
1889         /* Disable and acknowledge interrupts. */
1890         CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT);
1891
1892         cmb = sc->age_rdata.age_cmb_block;
1893
1894         bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag,
1895             sc->age_cdata.age_cmb_block_map, BUS_DMASYNC_POSTREAD);
1896         status = le32toh(cmb->intr_status);
1897         if ((status & AGE_INTRS) == 0)
1898                 goto done;
1899 again:
1900         sc->age_tpd_cons = (le32toh(cmb->tpd_cons) & TPD_CONS_MASK) >>
1901             TPD_CONS_SHIFT;
1902         sc->age_rr_prod = (le32toh(cmb->rprod_cons) & RRD_PROD_MASK) >>
1903             RRD_PROD_SHIFT;
1904
1905         /* Let hardware know CMB was served. */
1906         cmb->intr_status = 0;
1907         bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag,
1908             sc->age_cdata.age_cmb_block_map, BUS_DMASYNC_PREWRITE);
1909
1910 #if 0
1911         kprintf("INTR: 0x%08x\n", status);
1912         status &= ~INTR_DIS_DMA;
1913         CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT);
1914 #endif
1915
1916         if ((ifp->if_flags & IFF_RUNNING) != 0) {
1917                 if ((status & INTR_CMB_RX) != 0)
1918                         age_rxintr(sc, sc->age_rr_prod);
1919
1920                 if ((status & INTR_CMB_TX) != 0)
1921                         age_txintr(sc, sc->age_tpd_cons);
1922
1923                 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) {
1924                         if ((status & INTR_DMA_RD_TO_RST) != 0)
1925                                 device_printf(sc->age_dev,
1926                                     "DMA read error! -- resetting\n");
1927                         if ((status & INTR_DMA_WR_TO_RST) != 0)
1928                                 device_printf(sc->age_dev,
1929                                     "DMA write error! -- resetting\n");
1930                         age_init(sc);
1931                         /* XXX return? */
1932                 }
1933
1934                 if (!ifq_is_empty(&ifp->if_snd))
1935                         if_devstart(ifp);
1936
1937                 if ((status & INTR_SMB) != 0)
1938                         age_stats_update(sc);
1939         }
1940
1941         /* Check whether CMB was updated while serving Tx/Rx/SMB handler. */
1942         bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag,
1943             sc->age_cdata.age_cmb_block_map, BUS_DMASYNC_POSTREAD);
1944         status = le32toh(cmb->intr_status);
1945         if ((status & AGE_INTRS) != 0)
1946                 goto again;
1947 done:
1948         /* Re-enable interrupts. */
1949         CSR_WRITE_4(sc, AGE_INTR_STATUS, 0);
1950 }
1951
1952 static void
1953 age_txintr(struct age_softc *sc, int tpd_cons)
1954 {
1955         struct ifnet *ifp = &sc->arpcom.ac_if;
1956         struct age_txdesc *txd;
1957         int cons, prog;
1958
1959         bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag,
1960             sc->age_cdata.age_tx_ring_map, BUS_DMASYNC_POSTREAD);
1961
1962         /*
1963          * Go through our Tx list and free mbufs for those
1964          * frames which have been transmitted.
1965          */
1966         cons = sc->age_cdata.age_tx_cons;
1967         for (prog = 0; cons != tpd_cons; AGE_DESC_INC(cons, AGE_TX_RING_CNT)) {
1968                 if (sc->age_cdata.age_tx_cnt <= 0)
1969                         break;
1970                 prog++;
1971                 ifq_clr_oactive(&ifp->if_snd);
1972                 sc->age_cdata.age_tx_cnt--;
1973                 txd = &sc->age_cdata.age_txdesc[cons];
1974                 /*
1975                  * Clear Tx descriptors, it's not required but would
1976                  * help debugging in case of Tx issues.
1977                  */
1978                 txd->tx_desc->addr = 0;
1979                 txd->tx_desc->len = 0;
1980                 txd->tx_desc->flags = 0;
1981
1982                 if (txd->tx_m == NULL)
1983                         continue;
1984                 /* Reclaim transmitted mbufs. */
1985                 bus_dmamap_unload(sc->age_cdata.age_tx_tag, txd->tx_dmamap);
1986                 m_freem(txd->tx_m);
1987                 txd->tx_m = NULL;
1988         }
1989
1990         if (prog > 0) {
1991                 sc->age_cdata.age_tx_cons = cons;
1992
1993                 /*
1994                  * Unarm watchdog timer only when there are no pending
1995                  * Tx descriptors in queue.
1996                  */
1997                 if (sc->age_cdata.age_tx_cnt == 0)
1998                         ifp->if_timer = 0;
1999                 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag,
2000                     sc->age_cdata.age_tx_ring_map, BUS_DMASYNC_PREWRITE);
2001         }
2002 }
2003
2004 /* Receive a frame. */
2005 static void
2006 age_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd)
2007 {
2008         struct ifnet *ifp = &sc->arpcom.ac_if;
2009         struct age_rxdesc *rxd;
2010         struct rx_desc *desc;
2011         struct mbuf *mp, *m;
2012         uint32_t status, index, vtag;
2013         int count, nsegs, pktlen;
2014         int rx_cons;
2015
2016         status = le32toh(rxrd->flags);
2017         index = le32toh(rxrd->index);
2018         rx_cons = AGE_RX_CONS(index);
2019         nsegs = AGE_RX_NSEGS(index);
2020
2021         sc->age_cdata.age_rxlen = AGE_RX_BYTES(le32toh(rxrd->len));
2022         if ((status & AGE_RRD_ERROR) != 0 &&
2023             (status & (AGE_RRD_CRC | AGE_RRD_CODE | AGE_RRD_DRIBBLE |
2024             AGE_RRD_RUNT | AGE_RRD_OFLOW | AGE_RRD_TRUNC)) != 0) {
2025                 /*
2026                  * We want to pass the following frames to upper
2027                  * layer regardless of error status of Rx return
2028                  * ring.
2029                  *
2030                  *  o IP/TCP/UDP checksum is bad.
2031                  *  o frame length and protocol specific length
2032                  *     does not match.
2033                  */
2034                 sc->age_cdata.age_rx_cons += nsegs;
2035                 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT;
2036                 return;
2037         }
2038
2039         pktlen = 0;
2040         for (count = 0; count < nsegs; count++,
2041             AGE_DESC_INC(rx_cons, AGE_RX_RING_CNT)) {
2042                 rxd = &sc->age_cdata.age_rxdesc[rx_cons];
2043                 mp = rxd->rx_m;
2044                 desc = rxd->rx_desc;
2045                 /* Add a new receive buffer to the ring. */
2046                 if (age_newbuf(sc, rxd, 0) != 0) {
2047                         IFNET_STAT_INC(ifp, iqdrops, 1);
2048                         /* Reuse Rx buffers. */
2049                         if (sc->age_cdata.age_rxhead != NULL) {
2050                                 m_freem(sc->age_cdata.age_rxhead);
2051                                 AGE_RXCHAIN_RESET(sc);
2052                         }
2053                         break;
2054                 }
2055
2056                 /* The length of the first mbuf is computed last. */
2057                 if (count != 0) {
2058                         mp->m_len = AGE_RX_BYTES(le32toh(desc->len));
2059                         pktlen += mp->m_len;
2060                 }
2061
2062                 /* Chain received mbufs. */
2063                 if (sc->age_cdata.age_rxhead == NULL) {
2064                         sc->age_cdata.age_rxhead = mp;
2065                         sc->age_cdata.age_rxtail = mp;
2066                 } else {
2067                         mp->m_flags &= ~M_PKTHDR;
2068                         sc->age_cdata.age_rxprev_tail =
2069                             sc->age_cdata.age_rxtail;
2070                         sc->age_cdata.age_rxtail->m_next = mp;
2071                         sc->age_cdata.age_rxtail = mp;
2072                 }
2073
2074                 if (count == nsegs - 1) {
2075                         /*
2076                          * It seems that L1 controller has no way
2077                          * to tell hardware to strip CRC bytes.
2078                          */
2079                         sc->age_cdata.age_rxlen -= ETHER_CRC_LEN;
2080                         if (nsegs > 1) {
2081                                 /* Remove the CRC bytes in chained mbufs. */
2082                                 pktlen -= ETHER_CRC_LEN;
2083                                 if (mp->m_len <= ETHER_CRC_LEN) {
2084                                         sc->age_cdata.age_rxtail =
2085                                             sc->age_cdata.age_rxprev_tail;
2086                                         sc->age_cdata.age_rxtail->m_len -=
2087                                             (ETHER_CRC_LEN - mp->m_len);
2088                                         sc->age_cdata.age_rxtail->m_next = NULL;
2089                                         m_freem(mp);
2090                                 } else {
2091                                         mp->m_len -= ETHER_CRC_LEN;
2092                                 }
2093                         }
2094
2095                         m = sc->age_cdata.age_rxhead;
2096                         m->m_flags |= M_PKTHDR;
2097                         m->m_pkthdr.rcvif = ifp;
2098                         m->m_pkthdr.len = sc->age_cdata.age_rxlen;
2099                         /* Set the first mbuf length. */
2100                         m->m_len = sc->age_cdata.age_rxlen - pktlen;
2101
2102                         /*
2103                          * Set checksum information.
2104                          * It seems that L1 controller can compute partial
2105                          * checksum. The partial checksum value can be used
2106                          * to accelerate checksum computation for fragmented
2107                          * TCP/UDP packets. Upper network stack already
2108                          * takes advantage of the partial checksum value in
2109                          * IP reassembly stage. But I'm not sure the
2110                          * correctness of the partial hardware checksum
2111                          * assistance due to lack of data sheet. If it is
2112                          * proven to work on L1 I'll enable it.
2113                          */
2114                         if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 &&
2115                             (status & AGE_RRD_IPV4) != 0) {
2116                                 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2117                                 if ((status & AGE_RRD_IPCSUM_NOK) == 0)
2118                                         m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2119                                 if ((status & (AGE_RRD_TCP | AGE_RRD_UDP)) &&
2120                                     (status & AGE_RRD_TCP_UDPCSUM_NOK) == 0) {
2121                                         m->m_pkthdr.csum_flags |=
2122                                             CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2123                                         m->m_pkthdr.csum_data = 0xffff;
2124                                 }
2125                                 /*
2126                                  * Don't mark bad checksum for TCP/UDP frames
2127                                  * as fragmented frames may always have set
2128                                  * bad checksummed bit of descriptor status.
2129                                  */
2130                         }
2131
2132                         /* Check for VLAN tagged frames. */
2133                         if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 &&
2134                             (status & AGE_RRD_VLAN) != 0) {
2135                                 vtag = AGE_RX_VLAN(le32toh(rxrd->vtags));
2136                                 m->m_pkthdr.ether_vlantag =
2137                                     AGE_RX_VLAN_TAG(vtag);
2138                                 m->m_flags |= M_VLANTAG;
2139                         }
2140
2141                         /* Pass it on. */
2142                         ifp->if_input(ifp, m);
2143
2144                         /* Reset mbuf chains. */
2145                         AGE_RXCHAIN_RESET(sc);
2146                 }
2147         }
2148
2149         if (count != nsegs) {
2150                 sc->age_cdata.age_rx_cons += nsegs;
2151                 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT;
2152         } else {
2153                 sc->age_cdata.age_rx_cons = rx_cons;
2154         }
2155 }
2156
2157 static void
2158 age_rxintr(struct age_softc *sc, int rr_prod)
2159 {
2160         struct rx_rdesc *rxrd;
2161         int rr_cons, nsegs, pktlen, prog;
2162
2163         rr_cons = sc->age_cdata.age_rr_cons;
2164         if (rr_cons == rr_prod)
2165                 return;
2166
2167         bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag,
2168             sc->age_cdata.age_rr_ring_map, BUS_DMASYNC_POSTREAD);
2169
2170         for (prog = 0; rr_cons != rr_prod; prog++) {
2171                 rxrd = &sc->age_rdata.age_rr_ring[rr_cons];
2172                 nsegs = AGE_RX_NSEGS(le32toh(rxrd->index));
2173                 if (nsegs == 0)
2174                         break;
2175
2176                 /*
2177                  * Check number of segments against received bytes.
2178                  * Non-matching value would indicate that hardware
2179                  * is still trying to update Rx return descriptors.
2180                  * I'm not sure whether this check is really needed.
2181                  */
2182                 pktlen = AGE_RX_BYTES(le32toh(rxrd->len));
2183                 if (nsegs != ((pktlen + (MCLBYTES - ETHER_ALIGN - 1)) /
2184                     (MCLBYTES - ETHER_ALIGN)))
2185                         break;
2186
2187                 /* Received a frame. */
2188                 age_rxeof(sc, rxrd);
2189
2190                 /* Clear return ring. */
2191                 rxrd->index = 0;
2192                 AGE_DESC_INC(rr_cons, AGE_RR_RING_CNT);
2193         }
2194
2195         if (prog > 0) {
2196                 /* Update the consumer index. */
2197                 sc->age_cdata.age_rr_cons = rr_cons;
2198
2199                 /* Sync descriptors. */
2200                 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag,
2201                     sc->age_cdata.age_rr_ring_map, BUS_DMASYNC_PREWRITE);
2202
2203                 /* Notify hardware availability of new Rx buffers. */
2204                 AGE_COMMIT_MBOX(sc);
2205         }
2206 }
2207
2208 static void
2209 age_tick(void *xsc)
2210 {
2211         struct age_softc *sc = xsc;
2212         struct ifnet *ifp = &sc->arpcom.ac_if;
2213         struct mii_data *mii = device_get_softc(sc->age_miibus);
2214
2215         lwkt_serialize_enter(ifp->if_serializer);
2216
2217         mii_tick(mii);
2218         callout_reset(&sc->age_tick_ch, hz, age_tick, sc);
2219
2220         lwkt_serialize_exit(ifp->if_serializer);
2221 }
2222
2223 static void
2224 age_reset(struct age_softc *sc)
2225 {
2226         uint32_t reg;
2227         int i;
2228
2229         CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET);
2230         for (i = AGE_RESET_TIMEOUT; i > 0; i--) {
2231                 DELAY(1);
2232                 if ((CSR_READ_4(sc, AGE_MASTER_CFG) & MASTER_RESET) == 0)
2233                         break;
2234         }
2235         if (i == 0)
2236                 device_printf(sc->age_dev, "master reset timeout!\n");
2237
2238         for (i = AGE_RESET_TIMEOUT; i > 0; i--) {
2239                 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0)
2240                         break;
2241                 DELAY(10);
2242         }
2243         if (i == 0)
2244                 device_printf(sc->age_dev, "reset timeout(0x%08x)!\n", reg);
2245
2246         /* Initialize PCIe module. From Linux. */
2247         CSR_WRITE_4(sc, 0x12FC, 0x6500);
2248         CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);
2249 }
2250
2251 static void
2252 age_init(void *xsc)
2253 {
2254         struct age_softc *sc = xsc;
2255         struct ifnet *ifp = &sc->arpcom.ac_if;
2256         struct mii_data *mii;
2257         uint8_t eaddr[ETHER_ADDR_LEN];
2258         bus_addr_t paddr;
2259         uint32_t reg, fsize;
2260         uint32_t rxf_hi, rxf_lo, rrd_hi, rrd_lo;
2261         int error;
2262
2263         ASSERT_SERIALIZED(ifp->if_serializer);
2264
2265         mii = device_get_softc(sc->age_miibus);
2266
2267         /*
2268          * Cancel any pending I/O.
2269          */
2270         age_stop(sc);
2271
2272         /*
2273          * Reset the chip to a known state.
2274          */
2275         age_reset(sc);
2276
2277         /* Initialize descriptors. */
2278         error = age_init_rx_ring(sc);
2279         if (error != 0) {
2280                 device_printf(sc->age_dev, "no memory for Rx buffers.\n");
2281                 age_stop(sc);
2282                 return;
2283         }
2284         age_init_rr_ring(sc);
2285         age_init_tx_ring(sc);
2286         age_init_cmb_block(sc);
2287         age_init_smb_block(sc);
2288
2289         /* Reprogram the station address. */
2290         bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2291         CSR_WRITE_4(sc, AGE_PAR0,
2292             eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]);
2293         CSR_WRITE_4(sc, AGE_PAR1, eaddr[0] << 8 | eaddr[1]);
2294
2295         /* Set descriptor base addresses. */
2296         paddr = sc->age_rdata.age_tx_ring_paddr;
2297         CSR_WRITE_4(sc, AGE_DESC_ADDR_HI, AGE_ADDR_HI(paddr));
2298         paddr = sc->age_rdata.age_rx_ring_paddr;
2299         CSR_WRITE_4(sc, AGE_DESC_RD_ADDR_LO, AGE_ADDR_LO(paddr));
2300         paddr = sc->age_rdata.age_rr_ring_paddr;
2301         CSR_WRITE_4(sc, AGE_DESC_RRD_ADDR_LO, AGE_ADDR_LO(paddr));
2302         paddr = sc->age_rdata.age_tx_ring_paddr;
2303         CSR_WRITE_4(sc, AGE_DESC_TPD_ADDR_LO, AGE_ADDR_LO(paddr));
2304         paddr = sc->age_rdata.age_cmb_block_paddr;
2305         CSR_WRITE_4(sc, AGE_DESC_CMB_ADDR_LO, AGE_ADDR_LO(paddr));
2306         paddr = sc->age_rdata.age_smb_block_paddr;
2307         CSR_WRITE_4(sc, AGE_DESC_SMB_ADDR_LO, AGE_ADDR_LO(paddr));
2308
2309         /* Set Rx/Rx return descriptor counter. */
2310         CSR_WRITE_4(sc, AGE_DESC_RRD_RD_CNT,
2311             ((AGE_RR_RING_CNT << DESC_RRD_CNT_SHIFT) &
2312             DESC_RRD_CNT_MASK) |
2313             ((AGE_RX_RING_CNT << DESC_RD_CNT_SHIFT) & DESC_RD_CNT_MASK));
2314
2315         /* Set Tx descriptor counter. */
2316         CSR_WRITE_4(sc, AGE_DESC_TPD_CNT,
2317             (AGE_TX_RING_CNT << DESC_TPD_CNT_SHIFT) & DESC_TPD_CNT_MASK);
2318
2319         /* Tell hardware that we're ready to load descriptors. */
2320         CSR_WRITE_4(sc, AGE_DMA_BLOCK, DMA_BLOCK_LOAD);
2321
2322         /*
2323          * Initialize mailbox register.
2324          * Updated producer/consumer index information is exchanged
2325          * through this mailbox register. However Tx producer and
2326          * Rx return consumer/Rx producer are all shared such that
2327          * it's hard to separate code path between Tx and Rx without
2328          * locking. If L1 hardware have a separate mail box register
2329          * for Tx and Rx consumer/producer management we could have
2330          * indepent Tx/Rx handler which in turn Rx handler could have
2331          * been run without any locking.
2332          */
2333         AGE_COMMIT_MBOX(sc);
2334
2335         /* Configure IPG/IFG parameters. */
2336         CSR_WRITE_4(sc, AGE_IPG_IFG_CFG,
2337             ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK) |
2338             ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) |
2339             ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) |
2340             ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK));
2341
2342         /* Set parameters for half-duplex media. */
2343         CSR_WRITE_4(sc, AGE_HDPX_CFG,
2344             ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) &
2345             HDPX_CFG_LCOL_MASK) |
2346             ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) &
2347             HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN |
2348             ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) &
2349             HDPX_CFG_ABEBT_MASK) |
2350             ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) &
2351             HDPX_CFG_JAMIPG_MASK));
2352
2353         /* Configure interrupt moderation timer. */
2354         CSR_WRITE_2(sc, AGE_IM_TIMER, AGE_USECS(sc->age_int_mod));
2355         reg = CSR_READ_4(sc, AGE_MASTER_CFG);
2356         reg &= ~MASTER_MTIMER_ENB;
2357         if (AGE_USECS(sc->age_int_mod) == 0)
2358                 reg &= ~MASTER_ITIMER_ENB;
2359         else
2360                 reg |= MASTER_ITIMER_ENB;
2361         CSR_WRITE_4(sc, AGE_MASTER_CFG, reg);
2362         if (bootverbose)
2363                 device_printf(sc->age_dev, "interrupt moderation is %d us.\n",
2364                     sc->age_int_mod);
2365         CSR_WRITE_2(sc, AGE_INTR_CLR_TIMER, AGE_USECS(1000));
2366
2367         /* Set Maximum frame size but don't let MTU be lass than ETHER_MTU. */
2368         if (ifp->if_mtu < ETHERMTU)
2369                 sc->age_max_frame_size = ETHERMTU;
2370         else
2371                 sc->age_max_frame_size = ifp->if_mtu;
2372         sc->age_max_frame_size += ETHER_HDR_LEN +
2373             sizeof(struct ether_vlan_header) + ETHER_CRC_LEN;
2374         CSR_WRITE_4(sc, AGE_FRAME_SIZE, sc->age_max_frame_size);
2375
2376         /* Configure jumbo frame. */
2377         fsize = roundup(sc->age_max_frame_size, sizeof(uint64_t));
2378         CSR_WRITE_4(sc, AGE_RXQ_JUMBO_CFG,
2379             (((fsize / sizeof(uint64_t)) <<
2380             RXQ_JUMBO_CFG_SZ_THRESH_SHIFT) & RXQ_JUMBO_CFG_SZ_THRESH_MASK) |
2381             ((RXQ_JUMBO_CFG_LKAH_DEFAULT <<
2382             RXQ_JUMBO_CFG_LKAH_SHIFT) & RXQ_JUMBO_CFG_LKAH_MASK) |
2383             ((AGE_USECS(8) << RXQ_JUMBO_CFG_RRD_TIMER_SHIFT) &
2384             RXQ_JUMBO_CFG_RRD_TIMER_MASK));
2385
2386         /* Configure flow-control parameters. From Linux. */
2387         if ((sc->age_flags & AGE_FLAG_PCIE) != 0) {
2388                 /*
2389                  * Magic workaround for old-L1.
2390                  * Don't know which hw revision requires this magic.
2391                  */
2392                 CSR_WRITE_4(sc, 0x12FC, 0x6500);
2393                 /*
2394                  * Another magic workaround for flow-control mode
2395                  * change. From Linux.
2396                  */
2397                 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);
2398         }
2399         /*
2400          * TODO
2401          *  Should understand pause parameter relationships between FIFO
2402          *  size and number of Rx descriptors and Rx return descriptors.
2403          *
2404          *  Magic parameters came from Linux.
2405          */
2406         switch (sc->age_chip_rev) {
2407         case 0x8001:
2408         case 0x9001:
2409         case 0x9002:
2410         case 0x9003:
2411                 rxf_hi = AGE_RX_RING_CNT / 16;
2412                 rxf_lo = (AGE_RX_RING_CNT * 7) / 8;
2413                 rrd_hi = (AGE_RR_RING_CNT * 7) / 8;
2414                 rrd_lo = AGE_RR_RING_CNT / 16;
2415                 break;
2416         default:
2417                 reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN);
2418                 rxf_lo = reg / 16;
2419                 if (rxf_lo < 192)
2420                         rxf_lo = 192;
2421                 rxf_hi = (reg * 7) / 8;
2422                 if (rxf_hi < rxf_lo)
2423                         rxf_hi = rxf_lo + 16;
2424                 reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN);
2425                 rrd_lo = reg / 8;
2426                 rrd_hi = (reg * 7) / 8;
2427                 if (rrd_lo < 2)
2428                         rrd_lo = 2;
2429                 if (rrd_hi < rrd_lo)
2430                         rrd_hi = rrd_lo + 3;
2431                 break;
2432         }
2433         CSR_WRITE_4(sc, AGE_RXQ_FIFO_PAUSE_THRESH,
2434             ((rxf_lo << RXQ_FIFO_PAUSE_THRESH_LO_SHIFT) &
2435             RXQ_FIFO_PAUSE_THRESH_LO_MASK) |
2436             ((rxf_hi << RXQ_FIFO_PAUSE_THRESH_HI_SHIFT) &
2437             RXQ_FIFO_PAUSE_THRESH_HI_MASK));
2438         CSR_WRITE_4(sc, AGE_RXQ_RRD_PAUSE_THRESH,
2439             ((rrd_lo << RXQ_RRD_PAUSE_THRESH_LO_SHIFT) &
2440             RXQ_RRD_PAUSE_THRESH_LO_MASK) |
2441             ((rrd_hi << RXQ_RRD_PAUSE_THRESH_HI_SHIFT) &
2442             RXQ_RRD_PAUSE_THRESH_HI_MASK));
2443
2444         /* Configure RxQ. */
2445         CSR_WRITE_4(sc, AGE_RXQ_CFG,
2446             ((RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) &
2447             RXQ_CFG_RD_BURST_MASK) |
2448             ((RXQ_CFG_RRD_BURST_THRESH_DEFAULT <<
2449             RXQ_CFG_RRD_BURST_THRESH_SHIFT) & RXQ_CFG_RRD_BURST_THRESH_MASK) |
2450             ((RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT <<
2451             RXQ_CFG_RD_PREF_MIN_IPG_SHIFT) & RXQ_CFG_RD_PREF_MIN_IPG_MASK) |
2452             RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB);
2453
2454         /* Configure TxQ. */
2455         CSR_WRITE_4(sc, AGE_TXQ_CFG,
2456             ((TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) &
2457             TXQ_CFG_TPD_BURST_MASK) |
2458             ((TXQ_CFG_TX_FIFO_BURST_DEFAULT << TXQ_CFG_TX_FIFO_BURST_SHIFT) &
2459             TXQ_CFG_TX_FIFO_BURST_MASK) |
2460             ((TXQ_CFG_TPD_FETCH_DEFAULT <<
2461             TXQ_CFG_TPD_FETCH_THRESH_SHIFT) & TXQ_CFG_TPD_FETCH_THRESH_MASK) |
2462             TXQ_CFG_ENB);
2463
2464         CSR_WRITE_4(sc, AGE_TX_JUMBO_TPD_TH_IPG,
2465             (((fsize / sizeof(uint64_t) << TX_JUMBO_TPD_TH_SHIFT)) &
2466             TX_JUMBO_TPD_TH_MASK) |
2467             ((TX_JUMBO_TPD_IPG_DEFAULT << TX_JUMBO_TPD_IPG_SHIFT) &
2468             TX_JUMBO_TPD_IPG_MASK));
2469
2470         /* Configure DMA parameters. */
2471         CSR_WRITE_4(sc, AGE_DMA_CFG,
2472             DMA_CFG_ENH_ORDER | DMA_CFG_RCB_64 |
2473             sc->age_dma_rd_burst | DMA_CFG_RD_ENB |
2474             sc->age_dma_wr_burst | DMA_CFG_WR_ENB);
2475
2476         /* Configure CMB DMA write threshold. */
2477         CSR_WRITE_4(sc, AGE_CMB_WR_THRESH,
2478             ((CMB_WR_THRESH_RRD_DEFAULT << CMB_WR_THRESH_RRD_SHIFT) &
2479             CMB_WR_THRESH_RRD_MASK) |
2480             ((CMB_WR_THRESH_TPD_DEFAULT << CMB_WR_THRESH_TPD_SHIFT) &
2481             CMB_WR_THRESH_TPD_MASK));
2482
2483         /* Set CMB/SMB timer and enable them. */
2484         CSR_WRITE_4(sc, AGE_CMB_WR_TIMER,
2485             ((AGE_USECS(2) << CMB_WR_TIMER_TX_SHIFT) & CMB_WR_TIMER_TX_MASK) |
2486             ((AGE_USECS(2) << CMB_WR_TIMER_RX_SHIFT) & CMB_WR_TIMER_RX_MASK));
2487
2488         /* Request SMB updates for every seconds. */
2489         CSR_WRITE_4(sc, AGE_SMB_TIMER, AGE_USECS(1000 * 1000));
2490         CSR_WRITE_4(sc, AGE_CSMB_CTRL, CSMB_CTRL_SMB_ENB | CSMB_CTRL_CMB_ENB);
2491
2492         /*
2493          * Disable all WOL bits as WOL can interfere normal Rx
2494          * operation.
2495          */
2496         CSR_WRITE_4(sc, AGE_WOL_CFG, 0);
2497
2498         /*
2499          * Configure Tx/Rx MACs.
2500          *  - Auto-padding for short frames.
2501          *  - Enable CRC generation.
2502          *  Start with full-duplex/1000Mbps media. Actual reconfiguration
2503          *  of MAC is followed after link establishment.
2504          */
2505         CSR_WRITE_4(sc, AGE_MAC_CFG,
2506             MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD |
2507             MAC_CFG_FULL_DUPLEX | MAC_CFG_SPEED_1000 |
2508             ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) &
2509             MAC_CFG_PREAMBLE_MASK));
2510
2511         /* Set up the receive filter. */
2512         age_rxfilter(sc);
2513         age_rxvlan(sc);
2514
2515         reg = CSR_READ_4(sc, AGE_MAC_CFG);
2516         if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
2517                 reg |= MAC_CFG_RXCSUM_ENB;
2518
2519         /* Ack all pending interrupts and clear it. */
2520         CSR_WRITE_4(sc, AGE_INTR_STATUS, 0);
2521         CSR_WRITE_4(sc, AGE_INTR_MASK, AGE_INTRS);
2522
2523         /* Finally enable Tx/Rx MAC. */
2524         CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB);
2525
2526         sc->age_flags &= ~AGE_FLAG_LINK;
2527         /* Switch to the current media. */
2528         mii_mediachg(mii);
2529
2530         callout_reset(&sc->age_tick_ch, hz, age_tick, sc);
2531
2532         ifp->if_flags |= IFF_RUNNING;
2533         ifq_clr_oactive(&ifp->if_snd);
2534 }
2535
2536 static void
2537 age_stop(struct age_softc *sc)
2538 {
2539         struct ifnet *ifp = &sc->arpcom.ac_if;
2540         struct age_txdesc *txd;
2541         struct age_rxdesc *rxd;
2542         uint32_t reg;
2543         int i;
2544
2545         ASSERT_SERIALIZED(ifp->if_serializer);
2546
2547         /*
2548          * Mark the interface down and cancel the watchdog timer.
2549          */
2550         ifp->if_flags &= ~IFF_RUNNING;
2551         ifq_clr_oactive(&ifp->if_snd);
2552         ifp->if_timer = 0;
2553
2554         sc->age_flags &= ~AGE_FLAG_LINK;
2555         callout_stop(&sc->age_tick_ch);
2556
2557         /*
2558          * Disable interrupts.
2559          */
2560         CSR_WRITE_4(sc, AGE_INTR_MASK, 0);
2561         CSR_WRITE_4(sc, AGE_INTR_STATUS, 0xFFFFFFFF);
2562
2563         /* Stop CMB/SMB updates. */
2564         CSR_WRITE_4(sc, AGE_CSMB_CTRL, 0);
2565
2566         /* Stop Rx/Tx MAC. */
2567         age_stop_rxmac(sc);
2568         age_stop_txmac(sc);
2569
2570         /* Stop DMA. */
2571         CSR_WRITE_4(sc, AGE_DMA_CFG,
2572             CSR_READ_4(sc, AGE_DMA_CFG) & ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB));
2573
2574         /* Stop TxQ/RxQ. */
2575         CSR_WRITE_4(sc, AGE_TXQ_CFG,
2576             CSR_READ_4(sc, AGE_TXQ_CFG) & ~TXQ_CFG_ENB);
2577         CSR_WRITE_4(sc, AGE_RXQ_CFG,
2578             CSR_READ_4(sc, AGE_RXQ_CFG) & ~RXQ_CFG_ENB);
2579         for (i = AGE_RESET_TIMEOUT; i > 0; i--) {
2580                 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0)
2581                         break;
2582                 DELAY(10);
2583         }
2584         if (i == 0)
2585                 device_printf(sc->age_dev,
2586                     "stopping Rx/Tx MACs timed out(0x%08x)!\n", reg);
2587
2588         /* Reclaim Rx buffers that have been processed. */
2589         if (sc->age_cdata.age_rxhead != NULL)
2590                 m_freem(sc->age_cdata.age_rxhead);
2591         AGE_RXCHAIN_RESET(sc);
2592
2593         /*
2594          * Free RX and TX mbufs still in the queues.
2595          */
2596         for (i = 0; i < AGE_RX_RING_CNT; i++) {
2597                 rxd = &sc->age_cdata.age_rxdesc[i];
2598                 if (rxd->rx_m != NULL) {
2599                         bus_dmamap_unload(sc->age_cdata.age_rx_tag,
2600                             rxd->rx_dmamap);
2601                         m_freem(rxd->rx_m);
2602                         rxd->rx_m = NULL;
2603                 }
2604         }
2605         for (i = 0; i < AGE_TX_RING_CNT; i++) {
2606                 txd = &sc->age_cdata.age_txdesc[i];
2607                 if (txd->tx_m != NULL) {
2608                         bus_dmamap_unload(sc->age_cdata.age_tx_tag,
2609                             txd->tx_dmamap);
2610                         m_freem(txd->tx_m);
2611                         txd->tx_m = NULL;
2612                 }
2613         }
2614 }
2615
2616 static void
2617 age_stop_txmac(struct age_softc *sc)
2618 {
2619         uint32_t reg;
2620         int i;
2621
2622         reg = CSR_READ_4(sc, AGE_MAC_CFG);
2623         if ((reg & MAC_CFG_TX_ENB) != 0) {
2624                 reg &= ~MAC_CFG_TX_ENB;
2625                 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
2626         }
2627         /* Stop Tx DMA engine. */
2628         reg = CSR_READ_4(sc, AGE_DMA_CFG);
2629         if ((reg & DMA_CFG_RD_ENB) != 0) {
2630                 reg &= ~DMA_CFG_RD_ENB;
2631                 CSR_WRITE_4(sc, AGE_DMA_CFG, reg);
2632         }
2633         for (i = AGE_RESET_TIMEOUT; i > 0; i--) {
2634                 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) &
2635                     (IDLE_STATUS_TXMAC | IDLE_STATUS_DMARD)) == 0)
2636                         break;
2637                 DELAY(10);
2638         }
2639         if (i == 0)
2640                 device_printf(sc->age_dev, "stopping TxMAC timeout!\n");
2641 }
2642
2643 static void
2644 age_stop_rxmac(struct age_softc *sc)
2645 {
2646         uint32_t reg;
2647         int i;
2648
2649         reg = CSR_READ_4(sc, AGE_MAC_CFG);
2650         if ((reg & MAC_CFG_RX_ENB) != 0) {
2651                 reg &= ~MAC_CFG_RX_ENB;
2652                 CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
2653         }
2654         /* Stop Rx DMA engine. */
2655         reg = CSR_READ_4(sc, AGE_DMA_CFG);
2656         if ((reg & DMA_CFG_WR_ENB) != 0) {
2657                 reg &= ~DMA_CFG_WR_ENB;
2658                 CSR_WRITE_4(sc, AGE_DMA_CFG, reg);
2659         }
2660         for (i = AGE_RESET_TIMEOUT; i > 0; i--) {
2661                 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) &
2662                     (IDLE_STATUS_RXMAC | IDLE_STATUS_DMAWR)) == 0)
2663                         break;
2664                 DELAY(10);
2665         }
2666         if (i == 0)
2667                 device_printf(sc->age_dev, "stopping RxMAC timeout!\n");
2668 }
2669
2670 static void
2671 age_init_tx_ring(struct age_softc *sc)
2672 {
2673         struct age_ring_data *rd;
2674         struct age_txdesc *txd;
2675         int i;
2676
2677         sc->age_cdata.age_tx_prod = 0;
2678         sc->age_cdata.age_tx_cons = 0;
2679         sc->age_cdata.age_tx_cnt = 0;
2680
2681         rd = &sc->age_rdata;
2682         bzero(rd->age_tx_ring, AGE_TX_RING_SZ);
2683         for (i = 0; i < AGE_TX_RING_CNT; i++) {
2684                 txd = &sc->age_cdata.age_txdesc[i];
2685                 txd->tx_desc = &rd->age_tx_ring[i];
2686                 txd->tx_m = NULL;
2687         }
2688
2689         bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag,
2690             sc->age_cdata.age_tx_ring_map, BUS_DMASYNC_PREWRITE);
2691 }
2692
2693 static int
2694 age_init_rx_ring(struct age_softc *sc)
2695 {
2696         struct age_ring_data *rd;
2697         struct age_rxdesc *rxd;
2698         int i;
2699
2700         sc->age_cdata.age_rx_cons = AGE_RX_RING_CNT - 1;
2701         rd = &sc->age_rdata;
2702         bzero(rd->age_rx_ring, AGE_RX_RING_SZ);
2703         for (i = 0; i < AGE_RX_RING_CNT; i++) {
2704                 rxd = &sc->age_cdata.age_rxdesc[i];
2705                 rxd->rx_m = NULL;
2706                 rxd->rx_desc = &rd->age_rx_ring[i];
2707                 if (age_newbuf(sc, rxd, 1) != 0)
2708                         return (ENOBUFS);
2709         }
2710
2711         bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag,
2712             sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_PREWRITE);
2713
2714         return (0);
2715 }
2716
2717 static void
2718 age_init_rr_ring(struct age_softc *sc)
2719 {
2720         struct age_ring_data *rd;
2721
2722         sc->age_cdata.age_rr_cons = 0;
2723         AGE_RXCHAIN_RESET(sc);
2724
2725         rd = &sc->age_rdata;
2726         bzero(rd->age_rr_ring, AGE_RR_RING_SZ);
2727         bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag,
2728             sc->age_cdata.age_rr_ring_map, BUS_DMASYNC_PREWRITE);
2729 }
2730
2731 static void
2732 age_init_cmb_block(struct age_softc *sc)
2733 {
2734         struct age_ring_data *rd;
2735
2736         rd = &sc->age_rdata;
2737         bzero(rd->age_cmb_block, AGE_CMB_BLOCK_SZ);
2738         bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag,
2739             sc->age_cdata.age_cmb_block_map, BUS_DMASYNC_PREWRITE);
2740 }
2741
2742 static void
2743 age_init_smb_block(struct age_softc *sc)
2744 {
2745         struct age_ring_data *rd;
2746
2747         rd = &sc->age_rdata;
2748         bzero(rd->age_smb_block, AGE_SMB_BLOCK_SZ);
2749         bus_dmamap_sync(sc->age_cdata.age_smb_block_tag,
2750             sc->age_cdata.age_smb_block_map, BUS_DMASYNC_PREWRITE);
2751 }
2752
2753 static int
2754 age_newbuf(struct age_softc *sc, struct age_rxdesc *rxd, int init)
2755 {
2756         struct rx_desc *desc;
2757         struct mbuf *m;
2758         struct age_dmamap_ctx ctx;
2759         bus_dma_segment_t segs[1];
2760         bus_dmamap_t map;
2761         int error;
2762
2763         m = m_getcl(init ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2764         if (m == NULL)
2765                 return (ENOBUFS);
2766
2767         m->m_len = m->m_pkthdr.len = MCLBYTES;
2768         m_adj(m, ETHER_ALIGN);
2769
2770         ctx.nsegs = 1;
2771         ctx.segs = segs;
2772         error = bus_dmamap_load_mbuf(sc->age_cdata.age_rx_tag,
2773                                      sc->age_cdata.age_rx_sparemap,
2774                                      m, age_dmamap_buf_cb, &ctx,
2775                                      BUS_DMA_NOWAIT);
2776         if (error || ctx.nsegs == 0) {
2777                 if (!error) {
2778                         bus_dmamap_unload(sc->age_cdata.age_rx_tag,
2779                                           sc->age_cdata.age_rx_sparemap);
2780                         error = EFBIG;
2781                         if_printf(&sc->arpcom.ac_if, "too many segments?!\n");
2782                 }
2783                 m_freem(m);
2784
2785                 if (init)
2786                         if_printf(&sc->arpcom.ac_if, "can't load RX mbuf\n");
2787                 return (error);
2788         }
2789         KASSERT(ctx.nsegs == 1,
2790                 ("%s: %d segments returned!", __func__, ctx.nsegs));
2791
2792         if (rxd->rx_m != NULL) {
2793                 bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap,
2794                     BUS_DMASYNC_POSTREAD);
2795                 bus_dmamap_unload(sc->age_cdata.age_rx_tag, rxd->rx_dmamap);
2796         }
2797         map = rxd->rx_dmamap;
2798         rxd->rx_dmamap = sc->age_cdata.age_rx_sparemap;
2799         sc->age_cdata.age_rx_sparemap = map;
2800         rxd->rx_m = m;
2801
2802         desc = rxd->rx_desc;
2803         desc->addr = htole64(segs[0].ds_addr);
2804         desc->len = htole32((segs[0].ds_len & AGE_RD_LEN_MASK) <<
2805             AGE_RD_LEN_SHIFT);
2806         return (0);
2807 }
2808
2809 static void
2810 age_rxvlan(struct age_softc *sc)
2811 {
2812         struct ifnet *ifp = &sc->arpcom.ac_if;
2813         uint32_t reg;
2814
2815         reg = CSR_READ_4(sc, AGE_MAC_CFG);
2816         reg &= ~MAC_CFG_VLAN_TAG_STRIP;
2817         if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
2818                 reg |= MAC_CFG_VLAN_TAG_STRIP;
2819         CSR_WRITE_4(sc, AGE_MAC_CFG, reg);
2820 }
2821
2822 static void
2823 age_rxfilter(struct age_softc *sc)
2824 {
2825         struct ifnet *ifp = &sc->arpcom.ac_if;
2826         struct ifmultiaddr *ifma;
2827         uint32_t crc;
2828         uint32_t mchash[2];
2829         uint32_t rxcfg;
2830
2831         rxcfg = CSR_READ_4(sc, AGE_MAC_CFG);
2832         rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC);
2833         if ((ifp->if_flags & IFF_BROADCAST) != 0)
2834                 rxcfg |= MAC_CFG_BCAST;
2835         if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
2836                 if ((ifp->if_flags & IFF_PROMISC) != 0)
2837                         rxcfg |= MAC_CFG_PROMISC;
2838                 if ((ifp->if_flags & IFF_ALLMULTI) != 0)
2839                         rxcfg |= MAC_CFG_ALLMULTI;
2840                 CSR_WRITE_4(sc, AGE_MAR0, 0xFFFFFFFF);
2841                 CSR_WRITE_4(sc, AGE_MAR1, 0xFFFFFFFF);
2842                 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg);
2843                 return;
2844         }
2845
2846         /* Program new filter. */
2847         bzero(mchash, sizeof(mchash));
2848
2849         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2850                 if (ifma->ifma_addr->sa_family != AF_LINK)
2851                         continue;
2852                 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *)
2853                     ifma->ifma_addr), ETHER_ADDR_LEN);
2854                 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
2855         }
2856
2857         CSR_WRITE_4(sc, AGE_MAR0, mchash[0]);
2858         CSR_WRITE_4(sc, AGE_MAR1, mchash[1]);
2859         CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg);
2860 }
2861
2862 static int
2863 sysctl_age_stats(SYSCTL_HANDLER_ARGS)
2864 {
2865         struct age_softc *sc;
2866         struct age_stats *stats;
2867         int error, result;
2868
2869         result = -1;
2870         error = sysctl_handle_int(oidp, &result, 0, req);
2871
2872         if (error != 0 || req->newptr == NULL)
2873                 return (error);
2874
2875         if (result != 1)
2876                 return (error);
2877
2878         sc = (struct age_softc *)arg1;
2879         stats = &sc->age_stat;
2880         kprintf("%s statistics:\n", device_get_nameunit(sc->age_dev));
2881         kprintf("Transmit good frames : %ju\n",
2882             (uintmax_t)stats->tx_frames);
2883         kprintf("Transmit good broadcast frames : %ju\n",
2884             (uintmax_t)stats->tx_bcast_frames);
2885         kprintf("Transmit good multicast frames : %ju\n",
2886             (uintmax_t)stats->tx_mcast_frames);
2887         kprintf("Transmit pause control frames : %u\n",
2888             stats->tx_pause_frames);
2889         kprintf("Transmit control frames : %u\n",
2890             stats->tx_control_frames);
2891         kprintf("Transmit frames with excessive deferrals : %u\n",
2892             stats->tx_excess_defer);
2893         kprintf("Transmit deferrals : %u\n",
2894             stats->tx_deferred);
2895         kprintf("Transmit good octets : %ju\n",
2896             (uintmax_t)stats->tx_bytes);
2897         kprintf("Transmit good broadcast octets : %ju\n",
2898             (uintmax_t)stats->tx_bcast_bytes);
2899         kprintf("Transmit good multicast octets : %ju\n",
2900             (uintmax_t)stats->tx_mcast_bytes);
2901         kprintf("Transmit frames 64 bytes : %ju\n",
2902             (uintmax_t)stats->tx_pkts_64);
2903         kprintf("Transmit frames 65 to 127 bytes : %ju\n",
2904             (uintmax_t)stats->tx_pkts_65_127);
2905         kprintf("Transmit frames 128 to 255 bytes : %ju\n",
2906             (uintmax_t)stats->tx_pkts_128_255);
2907         kprintf("Transmit frames 256 to 511 bytes : %ju\n",
2908             (uintmax_t)stats->tx_pkts_256_511);
2909         kprintf("Transmit frames 512 to 1024 bytes : %ju\n",
2910             (uintmax_t)stats->tx_pkts_512_1023);
2911         kprintf("Transmit frames 1024 to 1518 bytes : %ju\n",
2912             (uintmax_t)stats->tx_pkts_1024_1518);
2913         kprintf("Transmit frames 1519 to MTU bytes : %ju\n",
2914             (uintmax_t)stats->tx_pkts_1519_max);
2915         kprintf("Transmit single collisions : %u\n",
2916             stats->tx_single_colls);
2917         kprintf("Transmit multiple collisions : %u\n",
2918             stats->tx_multi_colls);
2919         kprintf("Transmit late collisions : %u\n",
2920             stats->tx_late_colls);
2921         kprintf("Transmit abort due to excessive collisions : %u\n",
2922             stats->tx_excess_colls);
2923         kprintf("Transmit underruns due to FIFO underruns : %u\n",
2924             stats->tx_underrun);
2925         kprintf("Transmit descriptor write-back errors : %u\n",
2926             stats->tx_desc_underrun);
2927         kprintf("Transmit frames with length mismatched frame size : %u\n",
2928             stats->tx_lenerrs);
2929         kprintf("Transmit frames with truncated due to MTU size : %u\n",
2930             stats->tx_lenerrs);
2931
2932         kprintf("Receive good frames : %ju\n",
2933             (uintmax_t)stats->rx_frames);
2934         kprintf("Receive good broadcast frames : %ju\n",
2935             (uintmax_t)stats->rx_bcast_frames);
2936         kprintf("Receive good multicast frames : %ju\n",
2937             (uintmax_t)stats->rx_mcast_frames);
2938         kprintf("Receive pause control frames : %u\n",
2939             stats->rx_pause_frames);
2940         kprintf("Receive control frames : %u\n",
2941             stats->rx_control_frames);
2942         kprintf("Receive CRC errors : %u\n",
2943             stats->rx_crcerrs);
2944         kprintf("Receive frames with length errors : %u\n",
2945             stats->rx_lenerrs);
2946         kprintf("Receive good octets : %ju\n",
2947             (uintmax_t)stats->rx_bytes);
2948         kprintf("Receive good broadcast octets : %ju\n",
2949             (uintmax_t)stats->rx_bcast_bytes);
2950         kprintf("Receive good multicast octets : %ju\n",
2951             (uintmax_t)stats->rx_mcast_bytes);
2952         kprintf("Receive frames too short : %u\n",
2953             stats->rx_runts);
2954         kprintf("Receive fragmented frames : %ju\n",
2955             (uintmax_t)stats->rx_fragments);
2956         kprintf("Receive frames 64 bytes : %ju\n",
2957             (uintmax_t)stats->rx_pkts_64);
2958         kprintf("Receive frames 65 to 127 bytes : %ju\n",
2959             (uintmax_t)stats->rx_pkts_65_127);
2960         kprintf("Receive frames 128 to 255 bytes : %ju\n",
2961             (uintmax_t)stats->rx_pkts_128_255);
2962         kprintf("Receive frames 256 to 511 bytes : %ju\n",
2963             (uintmax_t)stats->rx_pkts_256_511);
2964         kprintf("Receive frames 512 to 1024 bytes : %ju\n",
2965             (uintmax_t)stats->rx_pkts_512_1023);
2966         kprintf("Receive frames 1024 to 1518 bytes : %ju\n",
2967             (uintmax_t)stats->rx_pkts_1024_1518);
2968         kprintf("Receive frames 1519 to MTU bytes : %ju\n",
2969             (uintmax_t)stats->rx_pkts_1519_max);
2970         kprintf("Receive frames too long : %ju\n",
2971             (uint64_t)stats->rx_pkts_truncated);
2972         kprintf("Receive frames with FIFO overflow : %u\n",
2973             stats->rx_fifo_oflows);
2974         kprintf("Receive frames with return descriptor overflow : %u\n",
2975             stats->rx_desc_oflows);
2976         kprintf("Receive frames with alignment errors : %u\n",
2977             stats->rx_alignerrs);
2978         kprintf("Receive frames dropped due to address filtering : %ju\n",
2979             (uint64_t)stats->rx_pkts_filtered);
2980
2981         return (error);
2982 }
2983
2984 static int
2985 sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS)
2986 {
2987
2988         return (sysctl_int_range(oidp, arg1, arg2, req, AGE_IM_TIMER_MIN,
2989             AGE_IM_TIMER_MAX));
2990 }
2991
2992 static void
2993 age_dmamap_buf_cb(void *xctx, bus_dma_segment_t *segs, int nsegs,
2994                   bus_size_t mapsz __unused, int error)
2995 {
2996         struct age_dmamap_ctx *ctx = xctx;
2997         int i;
2998
2999         if (error)
3000                 return;
3001
3002         if (nsegs > ctx->nsegs) {
3003                 ctx->nsegs = 0;
3004                 return;
3005         }
3006
3007         ctx->nsegs = nsegs;
3008         for (i = 0; i < nsegs; ++i)
3009                 ctx->segs[i] = segs[i];
3010 }