2 * Copyright (c) 2002 Myson Technology Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions, and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. The name of the author may not be used to endorse or promote products
12 * derived from this software without specific prior written permission.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
18 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * Written by: yen_cw@myson.com.tw available at: http://www.myson.com.tw/
28 * $FreeBSD: src/sys/dev/my/if_my.c,v 1.2.2.4 2002/04/17 02:05:27 julian Exp $
29 * $DragonFly: src/sys/dev/netif/my/if_my.c,v 1.26 2006/10/25 20:55:58 dillon Exp $
31 * Myson fast ethernet PCI NIC driver
33 * $Id: if_my.c,v 1.40 2001/11/30 03:55:00 <yen_cw@myson.com.tw> wpaul Exp $
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/sockio.h>
39 #include <sys/malloc.h>
40 #include <sys/kernel.h>
41 #include <sys/socket.h>
42 #include <sys/queue.h>
44 #include <sys/module.h>
45 #include <sys/serialize.h>
49 #include <sys/thread2.h>
52 #include <net/ifq_var.h>
53 #include <net/if_arp.h>
54 #include <net/ethernet.h>
55 #include <net/if_media.h>
56 #include <net/if_dl.h>
59 #include <vm/vm.h> /* for vtophys */
60 #include <vm/pmap.h> /* for vtophys */
61 #include <machine/clock.h> /* for DELAY */
63 #include <bus/pci/pcireg.h>
64 #include <bus/pci/pcivar.h>
66 #include "../mii_layer/mii.h"
67 #include "../mii_layer/miivar.h"
69 #include "miibus_if.h"
72 * #define MY_USEIOSPACE
75 static int MY_USEIOSPACE = 1;
78 #define MY_RES SYS_RES_IOPORT
79 #define MY_RID MY_PCI_LOIO
81 #define MY_RES SYS_RES_MEMORY
82 #define MY_RID MY_PCI_LOMEM
89 * Various supported device vendors/types and their names.
91 static struct my_type my_devs[] = {
92 {MYSONVENDORID, MTD800ID, "Myson MTD80X Based Fast Ethernet Card"},
93 {MYSONVENDORID, MTD803ID, "Myson MTD80X Based Fast Ethernet Card"},
94 {MYSONVENDORID, MTD891ID, "Myson MTD89X Based Giga Ethernet Card"},
99 * Various supported PHY vendors/types and their names. Note that this driver
100 * will work with pretty much any MII-compliant PHY, so failure to positively
101 * identify the chip is not a fatal error.
103 static struct my_type my_phys[] = {
104 {MysonPHYID0, MysonPHYID0, "<MYSON MTD981>"},
105 {SeeqPHYID0, SeeqPHYID0, "<SEEQ 80225>"},
106 {AhdocPHYID0, AhdocPHYID0, "<AHDOC 101>"},
107 {MarvellPHYID0, MarvellPHYID0, "<MARVELL 88E1000>"},
108 {LevelOnePHYID0, LevelOnePHYID0, "<LevelOne LXT1000>"},
109 {0, 0, "<MII-compliant physical interface>"}
112 static int my_probe(device_t);
113 static int my_attach(device_t);
114 static int my_detach(device_t);
115 static int my_newbuf(struct my_softc *, struct my_chain_onefrag *);
116 static int my_encap(struct my_softc *, struct my_chain *, struct mbuf *);
117 static void my_rxeof(struct my_softc *);
118 static void my_txeof(struct my_softc *);
119 static void my_txeoc(struct my_softc *);
120 static void my_intr(void *);
121 static void my_start(struct ifnet *);
122 static int my_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
123 static void my_init(void *);
124 static void my_stop(struct my_softc *);
125 static void my_watchdog(struct ifnet *);
126 static void my_shutdown(device_t);
127 static int my_ifmedia_upd(struct ifnet *);
128 static void my_ifmedia_sts(struct ifnet *, struct ifmediareq *);
129 static u_int16_t my_phy_readreg(struct my_softc *, int);
130 static void my_phy_writereg(struct my_softc *, int, int);
131 static void my_autoneg_xmit(struct my_softc *);
132 static void my_autoneg_mii(struct my_softc *, int, int);
133 static void my_setmode_mii(struct my_softc *, int);
134 static void my_getmode_mii(struct my_softc *);
135 static void my_setcfg(struct my_softc *, int);
136 static u_int8_t my_calchash(caddr_t);
137 static void my_setmulti(struct my_softc *);
138 static void my_reset(struct my_softc *);
139 static int my_list_rx_init(struct my_softc *);
140 static int my_list_tx_init(struct my_softc *);
141 static long my_send_cmd_to_phy(struct my_softc *, int, int);
143 #define MY_SETBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) | x)
144 #define MY_CLRBIT(sc, reg, x) CSR_WRITE_4(sc, reg, CSR_READ_4(sc, reg) & ~x)
146 static device_method_t my_methods[] = {
147 /* Device interface */
148 DEVMETHOD(device_probe, my_probe),
149 DEVMETHOD(device_attach, my_attach),
150 DEVMETHOD(device_detach, my_detach),
151 DEVMETHOD(device_shutdown, my_shutdown),
156 static driver_t my_driver = {
159 sizeof(struct my_softc)
162 static devclass_t my_devclass;
164 DECLARE_DUMMY_MODULE(if_my);
165 DRIVER_MODULE(if_my, pci, my_driver, my_devclass, 0, 0);
168 my_send_cmd_to_phy(struct my_softc * sc, int opcode, int regad)
174 /* enable MII output */
175 miir = CSR_READ_4(sc, MY_MANAGEMENT);
178 miir |= MY_MASK_MIIR_MII_WRITE + MY_MASK_MIIR_MII_MDO;
180 /* send 32 1's preamble */
181 for (i = 0; i < 32; i++) {
182 /* low MDC; MDO is already high (miir) */
183 miir &= ~MY_MASK_MIIR_MII_MDC;
184 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
187 miir |= MY_MASK_MIIR_MII_MDC;
188 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
191 /* calculate ST+OP+PHYAD+REGAD+TA */
192 data = opcode | (sc->my_phy_addr << 7) | (regad << 2);
197 /* low MDC, prepare MDO */
198 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO);
200 miir |= MY_MASK_MIIR_MII_MDO;
202 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
204 miir |= MY_MASK_MIIR_MII_MDC;
205 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
210 if (mask == 0x2 && opcode == MY_OP_READ)
211 miir &= ~MY_MASK_MIIR_MII_WRITE;
219 my_phy_readreg(struct my_softc * sc, int reg)
224 if (sc->my_info->my_did == MTD803ID)
225 data = CSR_READ_2(sc, MY_PHYBASE + reg * 2);
227 miir = my_send_cmd_to_phy(sc, MY_OP_READ, reg);
234 miir &= ~MY_MASK_MIIR_MII_MDC;
235 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
238 miir = CSR_READ_4(sc, MY_MANAGEMENT);
239 if (miir & MY_MASK_MIIR_MII_MDI)
242 /* high MDC, and wait */
243 miir |= MY_MASK_MIIR_MII_MDC;
244 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
252 miir &= ~MY_MASK_MIIR_MII_MDC;
253 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
256 return (u_int16_t) data;
261 my_phy_writereg(struct my_softc * sc, int reg, int data)
266 if (sc->my_info->my_did == MTD803ID)
267 CSR_WRITE_2(sc, MY_PHYBASE + reg * 2, data);
269 miir = my_send_cmd_to_phy(sc, MY_OP_WRITE, reg);
274 /* low MDC, prepare MDO */
275 miir &= ~(MY_MASK_MIIR_MII_MDC + MY_MASK_MIIR_MII_MDO);
277 miir |= MY_MASK_MIIR_MII_MDO;
278 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
282 miir |= MY_MASK_MIIR_MII_MDC;
283 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
291 miir &= ~MY_MASK_MIIR_MII_MDC;
292 CSR_WRITE_4(sc, MY_MANAGEMENT, miir);
297 my_calchash(caddr_t addr)
299 u_int32_t crc, carry;
303 /* Compute CRC for the address value. */
304 crc = 0xFFFFFFFF; /* initial value */
306 for (i = 0; i < 6; i++) {
308 for (j = 0; j < 8; j++) {
309 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01);
313 crc = (crc ^ 0x04c11db6) | carry;
318 * return the filter bit position Note: I arrived at the following
319 * nonsense through experimentation. It's not the usual way to
320 * generate the bit position but it's the only thing I could come up
323 return (~(crc >> 26) & 0x0000003F);
328 * Program the 64-bit multicast hash filter.
331 my_setmulti(struct my_softc * sc)
333 struct ifnet *ifp = &sc->arpcom.ac_if;
335 u_int32_t hashes[2] = {0, 0};
336 struct ifmultiaddr *ifma;
340 rxfilt = CSR_READ_4(sc, MY_TCRRCR);
342 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
344 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt);
345 CSR_WRITE_4(sc, MY_MAR0, 0xFFFFFFFF);
346 CSR_WRITE_4(sc, MY_MAR1, 0xFFFFFFFF);
350 /* first, zot all the existing hash bits */
351 CSR_WRITE_4(sc, MY_MAR0, 0);
352 CSR_WRITE_4(sc, MY_MAR1, 0);
354 /* now program new ones */
355 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
356 if (ifma->ifma_addr->sa_family != AF_LINK)
358 h = my_calchash(LLADDR((struct sockaddr_dl *) ifma->ifma_addr));
360 hashes[0] |= (1 << h);
362 hashes[1] |= (1 << (h - 32));
370 CSR_WRITE_4(sc, MY_MAR0, hashes[0]);
371 CSR_WRITE_4(sc, MY_MAR1, hashes[1]);
372 CSR_WRITE_4(sc, MY_TCRRCR, rxfilt);
376 * Initiate an autonegotiation session.
379 my_autoneg_xmit(struct my_softc * sc)
381 u_int16_t phy_sts = 0;
383 my_phy_writereg(sc, PHY_BMCR, PHY_BMCR_RESET);
385 while (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_RESET);
387 phy_sts = my_phy_readreg(sc, PHY_BMCR);
388 phy_sts |= PHY_BMCR_AUTONEGENBL | PHY_BMCR_AUTONEGRSTR;
389 my_phy_writereg(sc, PHY_BMCR, phy_sts);
394 * Invoke autonegotiation on a PHY.
397 my_autoneg_mii(struct my_softc * sc, int flag, int verbose)
399 u_int16_t phy_sts = 0, media, advert, ability;
400 u_int16_t ability2 = 0;
401 struct ifnet *ifp = &sc->arpcom.ac_if;
402 struct ifmedia *ifm = &sc->ifmedia;
404 ifm->ifm_media = IFM_ETHER | IFM_AUTO;
406 #ifndef FORCE_AUTONEG_TFOUR
408 * First, see if autoneg is supported. If not, there's no point in
411 phy_sts = my_phy_readreg(sc, PHY_BMSR);
412 if (!(phy_sts & PHY_BMSR_CANAUTONEG)) {
414 printf("my%d: autonegotiation not supported\n",
416 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
421 case MY_FLAG_FORCEDELAY:
423 * XXX Never use this option anywhere but in the probe
424 * routine: making the kernel stop dead in its tracks for
425 * three whole seconds after we've gone multi-user is really
431 case MY_FLAG_SCHEDDELAY:
433 * Wait for the transmitter to go idle before starting an
434 * autoneg session, otherwise my_start() may clobber our
435 * timeout, and we don't want to allow transmission during an
436 * autoneg session since that can screw it up.
438 if (sc->my_cdata.my_tx_head != NULL) {
439 sc->my_want_auto = 1;
445 sc->my_want_auto = 0;
447 case MY_FLAG_DELAYTIMEO:
452 printf("my%d: invalid autoneg flag: %d\n", sc->my_unit, flag);
456 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_AUTONEGCOMP) {
458 printf("my%d: autoneg complete, ", sc->my_unit);
459 phy_sts = my_phy_readreg(sc, PHY_BMSR);
462 printf("my%d: autoneg not complete, ", sc->my_unit);
465 media = my_phy_readreg(sc, PHY_BMCR);
467 /* Link is good. Report modes and set duplex mode. */
468 if (my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT) {
470 printf("my%d: link status good. ", sc->my_unit);
471 advert = my_phy_readreg(sc, PHY_ANAR);
472 ability = my_phy_readreg(sc, PHY_LPAR);
473 if ((sc->my_pinfo->my_vid == MarvellPHYID0) ||
474 (sc->my_pinfo->my_vid == LevelOnePHYID0)) {
475 ability2 = my_phy_readreg(sc, PHY_1000SR);
476 if (ability2 & PHY_1000SR_1000BTXFULL) {
480 * this version did not support 1000M,
482 * IFM_ETHER | IFM_1000_T | IFM_FDX;
485 IFM_ETHER | IFM_100_TX | IFM_FDX;
486 media &= ~PHY_BMCR_SPEEDSEL;
487 media |= PHY_BMCR_1000;
488 media |= PHY_BMCR_DUPLEX;
489 printf("(full-duplex, 1000Mbps)\n");
490 } else if (ability2 & PHY_1000SR_1000BTXHALF) {
494 * this version did not support 1000M,
495 * ifm->ifm_media = IFM_ETHER | IFM_1000_T;
497 ifm->ifm_media = IFM_ETHER | IFM_100_TX;
498 media &= ~PHY_BMCR_SPEEDSEL;
499 media &= ~PHY_BMCR_DUPLEX;
500 media |= PHY_BMCR_1000;
501 printf("(half-duplex, 1000Mbps)\n");
504 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4) {
505 ifm->ifm_media = IFM_ETHER | IFM_100_T4;
506 media |= PHY_BMCR_SPEEDSEL;
507 media &= ~PHY_BMCR_DUPLEX;
508 printf("(100baseT4)\n");
509 } else if (advert & PHY_ANAR_100BTXFULL &&
510 ability & PHY_ANAR_100BTXFULL) {
511 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX;
512 media |= PHY_BMCR_SPEEDSEL;
513 media |= PHY_BMCR_DUPLEX;
514 printf("(full-duplex, 100Mbps)\n");
515 } else if (advert & PHY_ANAR_100BTXHALF &&
516 ability & PHY_ANAR_100BTXHALF) {
517 ifm->ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX;
518 media |= PHY_BMCR_SPEEDSEL;
519 media &= ~PHY_BMCR_DUPLEX;
520 printf("(half-duplex, 100Mbps)\n");
521 } else if (advert & PHY_ANAR_10BTFULL &&
522 ability & PHY_ANAR_10BTFULL) {
523 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX;
524 media &= ~PHY_BMCR_SPEEDSEL;
525 media |= PHY_BMCR_DUPLEX;
526 printf("(full-duplex, 10Mbps)\n");
528 ifm->ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
529 media &= ~PHY_BMCR_SPEEDSEL;
530 media &= ~PHY_BMCR_DUPLEX;
531 printf("(half-duplex, 10Mbps)\n");
533 media &= ~PHY_BMCR_AUTONEGENBL;
535 /* Set ASIC's duplex mode to match the PHY. */
536 my_phy_writereg(sc, PHY_BMCR, media);
537 my_setcfg(sc, media);
540 printf("my%d: no carrier\n", sc->my_unit);
544 if (sc->my_tx_pend) {
552 * To get PHY ability.
555 my_getmode_mii(struct my_softc * sc)
557 struct ifnet *ifp = &sc->arpcom.ac_if;
560 bmsr = my_phy_readreg(sc, PHY_BMSR);
562 printf("my%d: PHY status word: %x\n", sc->my_unit, bmsr);
565 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_HDX;
567 if (bmsr & PHY_BMSR_10BTHALF) {
569 printf("my%d: 10Mbps half-duplex mode supported\n",
571 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_HDX,
573 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T, 0, NULL);
575 if (bmsr & PHY_BMSR_10BTFULL) {
577 printf("my%d: 10Mbps full-duplex mode supported\n",
580 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_10_T | IFM_FDX,
582 sc->ifmedia.ifm_media = IFM_ETHER | IFM_10_T | IFM_FDX;
584 if (bmsr & PHY_BMSR_100BTXHALF) {
586 printf("my%d: 100Mbps half-duplex mode supported\n",
588 ifp->if_baudrate = 100000000;
589 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX, 0, NULL);
590 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_HDX,
592 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_HDX;
594 if (bmsr & PHY_BMSR_100BTXFULL) {
596 printf("my%d: 100Mbps full-duplex mode supported\n",
598 ifp->if_baudrate = 100000000;
599 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_TX | IFM_FDX,
601 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_TX | IFM_FDX;
603 /* Some also support 100BaseT4. */
604 if (bmsr & PHY_BMSR_100BT4) {
606 printf("my%d: 100baseT4 mode supported\n", sc->my_unit);
607 ifp->if_baudrate = 100000000;
608 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_100_T4, 0, NULL);
609 sc->ifmedia.ifm_media = IFM_ETHER | IFM_100_T4;
610 #ifdef FORCE_AUTONEG_TFOUR
612 printf("my%d: forcing on autoneg support for BT4\n",
614 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0 NULL):
615 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO;
618 #if 0 /* this version did not support 1000M, */
619 if (sc->my_pinfo->my_vid == MarvellPHYID0) {
621 printf("my%d: 1000Mbps half-duplex mode supported\n",
624 ifp->if_baudrate = 1000000000;
625 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T, 0, NULL);
626 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_HDX,
629 printf("my%d: 1000Mbps full-duplex mode supported\n",
631 ifp->if_baudrate = 1000000000;
632 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_1000_T | IFM_FDX,
634 sc->ifmedia.ifm_media = IFM_ETHER | IFM_1000_T | IFM_FDX;
637 if (bmsr & PHY_BMSR_CANAUTONEG) {
639 printf("my%d: autoneg supported\n", sc->my_unit);
640 ifmedia_add(&sc->ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
641 sc->ifmedia.ifm_media = IFM_ETHER | IFM_AUTO;
646 * Set speed and duplex mode.
649 my_setmode_mii(struct my_softc * sc, int media)
651 struct ifnet *ifp = &sc->arpcom.ac_if;
655 * If an autoneg session is in progress, stop it.
657 if (sc->my_autoneg) {
658 printf("my%d: canceling autoneg session\n", sc->my_unit);
659 ifp->if_timer = sc->my_autoneg = sc->my_want_auto = 0;
660 bmcr = my_phy_readreg(sc, PHY_BMCR);
661 bmcr &= ~PHY_BMCR_AUTONEGENBL;
662 my_phy_writereg(sc, PHY_BMCR, bmcr);
664 printf("my%d: selecting MII, ", sc->my_unit);
665 bmcr = my_phy_readreg(sc, PHY_BMCR);
666 bmcr &= ~(PHY_BMCR_AUTONEGENBL | PHY_BMCR_SPEEDSEL | PHY_BMCR_1000 |
667 PHY_BMCR_DUPLEX | PHY_BMCR_LOOPBK);
669 #if 0 /* this version did not support 1000M, */
670 if (IFM_SUBTYPE(media) == IFM_1000_T) {
671 printf("1000Mbps/T4, half-duplex\n");
672 bmcr &= ~PHY_BMCR_SPEEDSEL;
673 bmcr &= ~PHY_BMCR_DUPLEX;
674 bmcr |= PHY_BMCR_1000;
677 if (IFM_SUBTYPE(media) == IFM_100_T4) {
678 printf("100Mbps/T4, half-duplex\n");
679 bmcr |= PHY_BMCR_SPEEDSEL;
680 bmcr &= ~PHY_BMCR_DUPLEX;
682 if (IFM_SUBTYPE(media) == IFM_100_TX) {
684 bmcr |= PHY_BMCR_SPEEDSEL;
686 if (IFM_SUBTYPE(media) == IFM_10_T) {
688 bmcr &= ~PHY_BMCR_SPEEDSEL;
690 if ((media & IFM_GMASK) == IFM_FDX) {
691 printf("full duplex\n");
692 bmcr |= PHY_BMCR_DUPLEX;
694 printf("half duplex\n");
695 bmcr &= ~PHY_BMCR_DUPLEX;
697 my_phy_writereg(sc, PHY_BMCR, bmcr);
702 * The Myson manual states that in order to fiddle with the 'full-duplex' and
703 * '100Mbps' bits in the netconfig register, we first have to put the
704 * transmit and/or receive logic in the idle state.
707 my_setcfg(struct my_softc * sc, int bmcr)
711 if (CSR_READ_4(sc, MY_TCRRCR) & (MY_TE | MY_RE)) {
713 MY_CLRBIT(sc, MY_TCRRCR, (MY_TE | MY_RE));
714 for (i = 0; i < MY_TIMEOUT; i++) {
716 if (!(CSR_READ_4(sc, MY_TCRRCR) &
717 (MY_TXRUN | MY_RXRUN)))
721 printf("my%d: failed to force tx and rx to idle \n",
724 MY_CLRBIT(sc, MY_TCRRCR, MY_PS1000);
725 MY_CLRBIT(sc, MY_TCRRCR, MY_PS10);
726 if (bmcr & PHY_BMCR_1000)
727 MY_SETBIT(sc, MY_TCRRCR, MY_PS1000);
728 else if (!(bmcr & PHY_BMCR_SPEEDSEL))
729 MY_SETBIT(sc, MY_TCRRCR, MY_PS10);
730 if (bmcr & PHY_BMCR_DUPLEX)
731 MY_SETBIT(sc, MY_TCRRCR, MY_FD);
733 MY_CLRBIT(sc, MY_TCRRCR, MY_FD);
735 MY_SETBIT(sc, MY_TCRRCR, MY_TE | MY_RE);
739 my_reset(struct my_softc * sc)
743 MY_SETBIT(sc, MY_BCR, MY_SWR);
744 for (i = 0; i < MY_TIMEOUT; i++) {
746 if (!(CSR_READ_4(sc, MY_BCR) & MY_SWR))
750 printf("m0x%d: reset never completed!\n", sc->my_unit);
752 /* Wait a little while for the chip to get its brains in order. */
757 * Probe for a Myson chip. Check the PCI vendor and device IDs against our
758 * list and return a device name if we find a match.
761 my_probe(device_t dev)
764 uint16_t vendor, product;
766 vendor = pci_get_vendor(dev);
767 product = pci_get_device(dev);
769 for (t = my_devs; t->my_name != NULL; t++) {
770 if (vendor == t->my_vid && product == t->my_did) {
771 device_set_desc(dev, t->my_name);
780 * Attach the interface. Allocate softc structures, do ifmedia setup and
781 * ethernet/BPF attach.
784 my_attach(device_t dev)
787 u_char eaddr[ETHER_ADDR_LEN];
788 u_int32_t command, iobase;
791 int media = IFM_ETHER | IFM_100_TX | IFM_FDX;
795 u_int16_t phy_vid, phy_did, phy_sts = 0;
796 int rid, unit, error = 0;
798 uint16_t vendor, product;
800 vendor = pci_get_vendor(dev);
801 product = pci_get_device(dev);
803 for (t = my_devs; t->my_name != NULL; t++) {
804 if (vendor == t->my_vid && product == t->my_did)
808 if (t->my_name == NULL)
811 sc = device_get_softc(dev);
812 unit = device_get_unit(dev);
815 * Map control/status registers.
817 command = pci_read_config(dev, PCIR_COMMAND, 4);
818 command |= (PCIM_CMD_PORTEN | PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN);
819 pci_write_config(dev, PCIR_COMMAND, command & 0x000000ff, 4);
820 command = pci_read_config(dev, PCIR_COMMAND, 4);
822 if (t->my_did == MTD800ID) {
823 iobase = pci_read_config(dev, MY_PCI_LOIO, 4);
828 if (!(command & PCIM_CMD_PORTEN)) {
829 printf("my%d: failed to enable I/O ports!\n", unit);
834 if (!(command & PCIM_CMD_MEMEN)) {
835 printf("my%d: failed to enable memory mapping!\n",
843 sc->my_res = bus_alloc_resource_any(dev, MY_RES, &rid, RF_ACTIVE);
845 if (sc->my_res == NULL) {
846 printf("my%d: couldn't map ports/memory\n", unit);
850 sc->my_btag = rman_get_bustag(sc->my_res);
851 sc->my_bhandle = rman_get_bushandle(sc->my_res);
854 sc->my_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
855 RF_SHAREABLE | RF_ACTIVE);
857 if (sc->my_irq == NULL) {
858 printf("my%d: couldn't map interrupt\n", unit);
865 /* Reset the adapter. */
869 * Get station address
871 for (i = 0; i < ETHER_ADDR_LEN; ++i)
872 eaddr[i] = CSR_READ_1(sc, MY_PAR0 + i);
876 sc->my_ldata_ptr = kmalloc(sizeof(struct my_list_data) + 8,
878 if (sc->my_ldata_ptr == NULL) {
879 printf("my%d: no memory for list buffers!\n", unit);
883 sc->my_ldata = (struct my_list_data *) sc->my_ldata_ptr;
884 round = (unsigned int)sc->my_ldata_ptr & 0xF;
885 roundptr = sc->my_ldata_ptr;
886 for (i = 0; i < 8; i++) {
893 sc->my_ldata = (struct my_list_data *) roundptr;
894 bzero(sc->my_ldata, sizeof(struct my_list_data));
896 ifp = &sc->arpcom.ac_if;
898 if_initname(ifp, "my", unit);
899 ifp->if_mtu = ETHERMTU;
900 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
901 ifp->if_ioctl = my_ioctl;
902 ifp->if_start = my_start;
903 ifp->if_watchdog = my_watchdog;
904 ifp->if_init = my_init;
905 ifp->if_baudrate = 10000000;
906 ifq_set_maxlen(&ifp->if_snd, IFQ_MAXLEN);
907 ifq_set_ready(&ifp->if_snd);
909 if (sc->my_info->my_did == MTD803ID)
910 sc->my_pinfo = my_phys;
913 printf("my%d: probing for a PHY\n", sc->my_unit);
914 for (i = MY_PHYADDR_MIN; i < MY_PHYADDR_MAX + 1; i++) {
916 printf("my%d: checking address: %d\n",
919 phy_sts = my_phy_readreg(sc, PHY_BMSR);
920 if ((phy_sts != 0) && (phy_sts != 0xffff))
926 phy_vid = my_phy_readreg(sc, PHY_VENID);
927 phy_did = my_phy_readreg(sc, PHY_DEVID);
929 printf("my%d: found PHY at address %d, ",
930 sc->my_unit, sc->my_phy_addr);
931 printf("vendor id: %x device id: %x\n",
936 if (phy_vid == p->my_vid) {
942 if (sc->my_pinfo == NULL)
943 sc->my_pinfo = &my_phys[PHY_UNKNOWN];
945 printf("my%d: PHY type: %s\n",
946 sc->my_unit, sc->my_pinfo->my_name);
948 printf("my%d: MII without any phy!\n", sc->my_unit);
954 /* Do ifmedia setup. */
955 ifmedia_init(&sc->ifmedia, 0, my_ifmedia_upd, my_ifmedia_sts);
957 my_autoneg_mii(sc, MY_FLAG_FORCEDELAY, 1);
958 media = sc->ifmedia.ifm_media;
960 ifmedia_set(&sc->ifmedia, media);
962 ether_ifattach(ifp, eaddr, NULL);
964 error = bus_setup_intr(dev, sc->my_irq, INTR_NETSAFE,
965 my_intr, sc, &sc->my_intrhand,
969 printf("my%d: couldn't set up irq\n", unit);
981 my_detach(device_t dev)
983 struct my_softc *sc = device_get_softc(dev);
984 struct ifnet *ifp = &sc->arpcom.ac_if;
986 if (device_is_attached(dev)) {
987 lwkt_serialize_enter(ifp->if_serializer);
989 bus_teardown_intr(dev, sc->my_irq, sc->my_intrhand);
990 lwkt_serialize_exit(ifp->if_serializer);
996 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->my_irq);
998 bus_release_resource(dev, MY_RES, MY_RID, sc->my_res);
1005 * Initialize the transmit descriptors.
1008 my_list_tx_init(struct my_softc * sc)
1010 struct my_chain_data *cd;
1011 struct my_list_data *ld;
1016 for (i = 0; i < MY_TX_LIST_CNT; i++) {
1017 cd->my_tx_chain[i].my_ptr = &ld->my_tx_list[i];
1018 if (i == (MY_TX_LIST_CNT - 1))
1019 cd->my_tx_chain[i].my_nextdesc = &cd->my_tx_chain[0];
1021 cd->my_tx_chain[i].my_nextdesc =
1022 &cd->my_tx_chain[i + 1];
1024 cd->my_tx_free = &cd->my_tx_chain[0];
1025 cd->my_tx_tail = cd->my_tx_head = NULL;
1030 * Initialize the RX descriptors and allocate mbufs for them. Note that we
1031 * arrange the descriptors in a closed ring, so that the last descriptor
1032 * points back to the first.
1035 my_list_rx_init(struct my_softc * sc)
1037 struct my_chain_data *cd;
1038 struct my_list_data *ld;
1043 for (i = 0; i < MY_RX_LIST_CNT; i++) {
1044 cd->my_rx_chain[i].my_ptr =
1045 (struct my_desc *) & ld->my_rx_list[i];
1046 if (my_newbuf(sc, &cd->my_rx_chain[i]) == ENOBUFS)
1048 if (i == (MY_RX_LIST_CNT - 1)) {
1049 cd->my_rx_chain[i].my_nextdesc = &cd->my_rx_chain[0];
1050 ld->my_rx_list[i].my_next = vtophys(&ld->my_rx_list[0]);
1052 cd->my_rx_chain[i].my_nextdesc =
1053 &cd->my_rx_chain[i + 1];
1054 ld->my_rx_list[i].my_next =
1055 vtophys(&ld->my_rx_list[i + 1]);
1058 cd->my_rx_head = &cd->my_rx_chain[0];
1063 * Initialize an RX descriptor and attach an MBUF cluster.
1066 my_newbuf(struct my_softc * sc, struct my_chain_onefrag * c)
1068 struct mbuf *m_new = NULL;
1070 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
1071 if (m_new == NULL) {
1072 printf("my%d: no memory for rx list -- packet dropped!\n",
1076 MCLGET(m_new, MB_DONTWAIT);
1077 if (!(m_new->m_flags & M_EXT)) {
1078 printf("my%d: no memory for rx list -- packet dropped!\n",
1084 c->my_ptr->my_data = vtophys(mtod(m_new, caddr_t));
1085 c->my_ptr->my_ctl = (MCLBYTES - 1) << MY_RBSShift;
1086 c->my_ptr->my_status = MY_OWNByNIC;
1091 * A frame has been uploaded: pass the resulting mbuf chain up to the higher
1095 my_rxeof(struct my_softc * sc)
1098 struct ifnet *ifp = &sc->arpcom.ac_if;
1099 struct my_chain_onefrag *cur_rx;
1103 while (!((rxstat = sc->my_cdata.my_rx_head->my_ptr->my_status)
1105 cur_rx = sc->my_cdata.my_rx_head;
1106 sc->my_cdata.my_rx_head = cur_rx->my_nextdesc;
1108 if (rxstat & MY_ES) { /* error summary: give up this rx pkt */
1110 cur_rx->my_ptr->my_status = MY_OWNByNIC;
1113 /* No errors; receive the packet. */
1114 total_len = (rxstat & MY_FLNGMASK) >> MY_FLNGShift;
1115 total_len -= ETHER_CRC_LEN;
1117 if (total_len < MINCLSIZE) {
1118 m = m_devget(mtod(cur_rx->my_mbuf, char *),
1119 total_len, 0, ifp, NULL);
1120 cur_rx->my_ptr->my_status = MY_OWNByNIC;
1126 m = cur_rx->my_mbuf;
1128 * Try to conjure up a new mbuf cluster. If that
1129 * fails, it means we have an out of memory condition
1130 * and should leave the buffer in place and continue.
1131 * This will result in a lost packet, but there's
1132 * little else we can do in this situation.
1134 if (my_newbuf(sc, cur_rx) == ENOBUFS) {
1136 cur_rx->my_ptr->my_status = MY_OWNByNIC;
1139 m->m_pkthdr.rcvif = ifp;
1140 m->m_pkthdr.len = m->m_len = total_len;
1143 ifp->if_input(ifp, m);
1149 * A frame was downloaded to the chip. It's safe for us to clean up the list
1153 my_txeof(struct my_softc * sc)
1155 struct ifnet *ifp = &sc->arpcom.ac_if;
1156 struct my_chain *cur_tx;
1158 /* Clear the timeout timer. */
1160 if (sc->my_cdata.my_tx_head == NULL)
1163 * Go through our tx list and free mbufs for those frames that have
1166 while (sc->my_cdata.my_tx_head->my_mbuf != NULL) {
1169 cur_tx = sc->my_cdata.my_tx_head;
1170 txstat = MY_TXSTATUS(cur_tx);
1171 if ((txstat & MY_OWNByNIC) || txstat == MY_UNSENT)
1173 if (!(CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced)) {
1174 if (txstat & MY_TXERR) {
1176 if (txstat & MY_EC) /* excessive collision */
1177 ifp->if_collisions++;
1178 if (txstat & MY_LC) /* late collision */
1179 ifp->if_collisions++;
1181 ifp->if_collisions += (txstat & MY_NCRMASK) >>
1185 m_freem(cur_tx->my_mbuf);
1186 cur_tx->my_mbuf = NULL;
1187 if (sc->my_cdata.my_tx_head == sc->my_cdata.my_tx_tail) {
1188 sc->my_cdata.my_tx_head = NULL;
1189 sc->my_cdata.my_tx_tail = NULL;
1192 sc->my_cdata.my_tx_head = cur_tx->my_nextdesc;
1194 if (CSR_READ_4(sc, MY_TCRRCR) & MY_Enhanced) {
1195 ifp->if_collisions += (CSR_READ_4(sc, MY_TSR) & MY_NCRMask);
1200 * TX 'end of channel' interrupt handler.
1203 my_txeoc(struct my_softc * sc)
1205 struct ifnet *ifp = &sc->arpcom.ac_if;
1208 if (sc->my_cdata.my_tx_head == NULL) {
1209 ifp->if_flags &= ~IFF_OACTIVE;
1210 sc->my_cdata.my_tx_tail = NULL;
1211 if (sc->my_want_auto)
1212 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1);
1214 if (MY_TXOWN(sc->my_cdata.my_tx_head) == MY_UNSENT) {
1215 MY_TXOWN(sc->my_cdata.my_tx_head) = MY_OWNByNIC;
1217 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF);
1225 struct my_softc *sc = arg;
1226 struct ifnet *ifp = &sc->arpcom.ac_if;
1229 if (!(ifp->if_flags & IFF_UP))
1232 /* Disable interrupts. */
1233 CSR_WRITE_4(sc, MY_IMR, 0x00000000);
1236 status = CSR_READ_4(sc, MY_ISR);
1239 CSR_WRITE_4(sc, MY_ISR, status);
1243 if (status & MY_RI) /* receive interrupt */
1246 if ((status & MY_RBU) || (status & MY_RxErr)) {
1247 /* rx buffer unavailable or rx error */
1255 if (status & MY_TI) /* tx interrupt */
1257 if (status & MY_ETI) /* tx early interrupt */
1259 if (status & MY_TBU) /* tx buffer unavailable */
1262 #if 0 /* 90/1/18 delete */
1263 if (status & MY_FBE) {
1271 /* Re-enable interrupts. */
1272 CSR_WRITE_4(sc, MY_IMR, MY_INTRS);
1273 if (!ifq_is_empty(&ifp->if_snd))
1278 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data
1279 * pointers to the fragment pointers.
1282 my_encap(struct my_softc * sc, struct my_chain * c, struct mbuf * m_head)
1284 struct my_desc *f = NULL;
1286 struct mbuf *m, *m_new = NULL;
1288 /* calculate the total tx pkt length */
1290 for (m = m_head; m != NULL; m = m->m_next)
1291 total_len += m->m_len;
1293 * Start packing the mbufs in this chain into the fragment pointers.
1294 * Stop when we run out of fragments or hit the end of the mbuf
1298 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
1299 if (m_new == NULL) {
1300 printf("my%d: no memory for tx list", sc->my_unit);
1303 if (m_head->m_pkthdr.len > MHLEN) {
1304 MCLGET(m_new, MB_DONTWAIT);
1305 if (!(m_new->m_flags & M_EXT)) {
1307 printf("my%d: no memory for tx list", sc->my_unit);
1311 m_copydata(m_head, 0, m_head->m_pkthdr.len, mtod(m_new, caddr_t));
1312 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len;
1315 f = &c->my_ptr->my_frag[0];
1317 f->my_data = vtophys(mtod(m_new, caddr_t));
1318 total_len = m_new->m_len;
1319 f->my_ctl = MY_TXFD | MY_TXLD | MY_CRCEnable | MY_PADEnable;
1320 f->my_ctl |= total_len << MY_PKTShift; /* pkt size */
1321 f->my_ctl |= total_len; /* buffer size */
1322 /* 89/12/29 add, for mtd891 *//* [ 89? ] */
1323 if (sc->my_info->my_did == MTD891ID)
1324 f->my_ctl |= MY_ETIControl | MY_RetryTxLC;
1325 c->my_mbuf = m_head;
1327 MY_TXNEXT(c) = vtophys(&c->my_nextdesc->my_ptr->my_frag[0]);
1332 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
1333 * to the mbuf data regions directly in the transmit lists. We also save a
1334 * copy of the pointers since the transmit list fragment pointers are
1335 * physical addresses.
1338 my_start(struct ifnet * ifp)
1340 struct my_softc *sc = ifp->if_softc;
1341 struct mbuf *m_head = NULL;
1342 struct my_chain *cur_tx = NULL, *start_tx;
1346 if (sc->my_autoneg) {
1352 * Check for an available queue slot. If there are none, punt.
1354 if (sc->my_cdata.my_tx_free->my_mbuf != NULL) {
1355 ifp->if_flags |= IFF_OACTIVE;
1360 start_tx = sc->my_cdata.my_tx_free;
1361 while (sc->my_cdata.my_tx_free->my_mbuf == NULL) {
1362 m_head = ifq_dequeue(&ifp->if_snd, NULL);
1366 /* Pick a descriptor off the free list. */
1367 cur_tx = sc->my_cdata.my_tx_free;
1368 sc->my_cdata.my_tx_free = cur_tx->my_nextdesc;
1370 /* Pack the data into the descriptor. */
1371 my_encap(sc, cur_tx, m_head);
1373 if (cur_tx != start_tx)
1374 MY_TXOWN(cur_tx) = MY_OWNByNIC;
1375 BPF_MTAP(ifp, cur_tx->my_mbuf);
1378 * If there are no packets queued, bail.
1380 if (cur_tx == NULL) {
1385 * Place the request for the upload interrupt in the last descriptor
1386 * in the chain. This way, if we're chaining several packets at once,
1387 * we'll only get an interupt once for the whole chain rather than
1388 * once for each packet.
1390 MY_TXCTL(cur_tx) |= MY_TXIC;
1391 cur_tx->my_ptr->my_frag[0].my_ctl |= MY_TXIC;
1392 sc->my_cdata.my_tx_tail = cur_tx;
1393 if (sc->my_cdata.my_tx_head == NULL)
1394 sc->my_cdata.my_tx_head = start_tx;
1395 MY_TXOWN(start_tx) = MY_OWNByNIC;
1396 CSR_WRITE_4(sc, MY_TXPDR, 0xFFFFFFFF); /* tx polling demand */
1399 * Set a timeout in case the chip goes out to lunch.
1409 struct my_softc *sc = xsc;
1410 struct ifnet *ifp = &sc->arpcom.ac_if;
1411 u_int16_t phy_bmcr = 0;
1414 if (sc->my_autoneg) {
1418 if (sc->my_pinfo != NULL)
1419 phy_bmcr = my_phy_readreg(sc, PHY_BMCR);
1421 * Cancel pending I/O and free all RX/TX buffers.
1427 * Set cache alignment and burst length.
1429 #if 0 /* 89/9/1 modify, */
1430 CSR_WRITE_4(sc, MY_BCR, MY_RPBLE512);
1431 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF);
1433 CSR_WRITE_4(sc, MY_BCR, MY_PBL8);
1434 CSR_WRITE_4(sc, MY_TCRRCR, MY_TFTSF | MY_RBLEN | MY_RPBLE512);
1436 * 89/12/29 add, for mtd891,
1438 if (sc->my_info->my_did == MTD891ID) {
1439 MY_SETBIT(sc, MY_BCR, MY_PROG);
1440 MY_SETBIT(sc, MY_TCRRCR, MY_Enhanced);
1442 my_setcfg(sc, phy_bmcr);
1443 /* Init circular RX list. */
1444 if (my_list_rx_init(sc) == ENOBUFS) {
1445 printf("my%d: init failed: no memory for rx buffers\n",
1451 /* Init TX descriptors. */
1452 my_list_tx_init(sc);
1454 /* If we want promiscuous mode, set the allframes bit. */
1455 if (ifp->if_flags & IFF_PROMISC)
1456 MY_SETBIT(sc, MY_TCRRCR, MY_PROM);
1458 MY_CLRBIT(sc, MY_TCRRCR, MY_PROM);
1461 * Set capture broadcast bit to capture broadcast frames.
1463 if (ifp->if_flags & IFF_BROADCAST)
1464 MY_SETBIT(sc, MY_TCRRCR, MY_AB);
1466 MY_CLRBIT(sc, MY_TCRRCR, MY_AB);
1469 * Program the multicast filter, if necessary.
1474 * Load the address of the RX list.
1476 MY_CLRBIT(sc, MY_TCRRCR, MY_RE);
1477 CSR_WRITE_4(sc, MY_RXLBA, vtophys(&sc->my_ldata->my_rx_list[0]));
1480 * Enable interrupts.
1482 CSR_WRITE_4(sc, MY_IMR, MY_INTRS);
1483 CSR_WRITE_4(sc, MY_ISR, 0xFFFFFFFF);
1485 /* Enable receiver and transmitter. */
1486 MY_SETBIT(sc, MY_TCRRCR, MY_RE);
1487 MY_CLRBIT(sc, MY_TCRRCR, MY_TE);
1488 CSR_WRITE_4(sc, MY_TXLBA, vtophys(&sc->my_ldata->my_tx_list[0]));
1489 MY_SETBIT(sc, MY_TCRRCR, MY_TE);
1491 /* Restore state of BMCR */
1492 if (sc->my_pinfo != NULL)
1493 my_phy_writereg(sc, PHY_BMCR, phy_bmcr);
1494 ifp->if_flags |= IFF_RUNNING;
1495 ifp->if_flags &= ~IFF_OACTIVE;
1500 * Set media options.
1504 my_ifmedia_upd(struct ifnet * ifp)
1506 struct my_softc *sc = ifp->if_softc;
1507 struct ifmedia *ifm = &sc->ifmedia;
1509 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1514 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO)
1515 my_autoneg_mii(sc, MY_FLAG_SCHEDDELAY, 1);
1517 my_setmode_mii(sc, ifm->ifm_media);
1525 * Report current media status.
1529 my_ifmedia_sts(struct ifnet * ifp, struct ifmediareq * ifmr)
1531 struct my_softc *sc = ifp->if_softc;
1532 u_int16_t advert = 0, ability = 0;
1536 ifmr->ifm_active = IFM_ETHER;
1537 if (!(my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_AUTONEGENBL)) {
1538 #if 0 /* this version did not support 1000M, */
1539 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_1000)
1540 ifmr->ifm_active = IFM_ETHER | IFM_1000TX;
1542 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_SPEEDSEL)
1543 ifmr->ifm_active = IFM_ETHER | IFM_100_TX;
1545 ifmr->ifm_active = IFM_ETHER | IFM_10_T;
1546 if (my_phy_readreg(sc, PHY_BMCR) & PHY_BMCR_DUPLEX)
1547 ifmr->ifm_active |= IFM_FDX;
1549 ifmr->ifm_active |= IFM_HDX;
1555 ability = my_phy_readreg(sc, PHY_LPAR);
1556 advert = my_phy_readreg(sc, PHY_ANAR);
1558 #if 0 /* this version did not support 1000M, */
1559 if (sc->my_pinfo->my_vid = MarvellPHYID0) {
1560 ability2 = my_phy_readreg(sc, PHY_1000SR);
1561 if (ability2 & PHY_1000SR_1000BTXFULL) {
1564 ifmr->ifm_active = IFM_ETHER | IFM_1000_T | IFM_FDX;
1565 } else if (ability & PHY_1000SR_1000BTXHALF) {
1568 ifmr->ifm_active = IFM_ETHER | IFM_1000_T | IFM_HDX;
1572 if (advert & PHY_ANAR_100BT4 && ability & PHY_ANAR_100BT4)
1573 ifmr->ifm_active = IFM_ETHER | IFM_100_T4;
1574 else if (advert & PHY_ANAR_100BTXFULL && ability & PHY_ANAR_100BTXFULL)
1575 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1576 else if (advert & PHY_ANAR_100BTXHALF && ability & PHY_ANAR_100BTXHALF)
1577 ifmr->ifm_active = IFM_ETHER | IFM_100_TX | IFM_HDX;
1578 else if (advert & PHY_ANAR_10BTFULL && ability & PHY_ANAR_10BTFULL)
1579 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_FDX;
1580 else if (advert & PHY_ANAR_10BTHALF && ability & PHY_ANAR_10BTHALF)
1581 ifmr->ifm_active = IFM_ETHER | IFM_10_T | IFM_HDX;
1587 my_ioctl(struct ifnet * ifp, u_long command, caddr_t data, struct ucred *cr)
1589 struct my_softc *sc = ifp->if_softc;
1590 struct ifreq *ifr = (struct ifreq *) data;
1596 if (ifp->if_flags & IFF_UP)
1598 else if (ifp->if_flags & IFF_RUNNING)
1609 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command);
1612 error = ether_ioctl(ifp, command, data);
1621 my_watchdog(struct ifnet * ifp)
1623 struct my_softc *sc = ifp->if_softc;
1627 if (sc->my_autoneg) {
1628 my_autoneg_mii(sc, MY_FLAG_DELAYTIMEO, 1);
1633 printf("my%d: watchdog timeout\n", sc->my_unit);
1634 if (!(my_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT))
1635 printf("my%d: no carrier - transceiver cable problem?\n",
1640 if (!ifq_is_empty(&ifp->if_snd))
1647 * Stop the adapter and free any mbufs allocated to the RX and TX lists.
1650 my_stop(struct my_softc * sc)
1652 struct ifnet *ifp = &sc->arpcom.ac_if;
1657 MY_CLRBIT(sc, MY_TCRRCR, (MY_RE | MY_TE));
1658 CSR_WRITE_4(sc, MY_IMR, 0x00000000);
1659 CSR_WRITE_4(sc, MY_TXLBA, 0x00000000);
1660 CSR_WRITE_4(sc, MY_RXLBA, 0x00000000);
1663 * Free data in the RX lists.
1665 for (i = 0; i < MY_RX_LIST_CNT; i++) {
1666 if (sc->my_cdata.my_rx_chain[i].my_mbuf != NULL) {
1667 m_freem(sc->my_cdata.my_rx_chain[i].my_mbuf);
1668 sc->my_cdata.my_rx_chain[i].my_mbuf = NULL;
1671 bzero((char *)&sc->my_ldata->my_rx_list,
1672 sizeof(sc->my_ldata->my_rx_list));
1674 * Free the TX list buffers.
1676 for (i = 0; i < MY_TX_LIST_CNT; i++) {
1677 if (sc->my_cdata.my_tx_chain[i].my_mbuf != NULL) {
1678 m_freem(sc->my_cdata.my_tx_chain[i].my_mbuf);
1679 sc->my_cdata.my_tx_chain[i].my_mbuf = NULL;
1682 bzero((char *)&sc->my_ldata->my_tx_list,
1683 sizeof(sc->my_ldata->my_tx_list));
1684 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1688 * Stop all chip I/O so that the kernel's probe routines don't get confused
1689 * by errant DMAs when rebooting.
1692 my_shutdown(device_t dev)
1694 struct my_softc *sc;
1696 sc = device_get_softc(dev);