sys/platform/pc64/isa/clock.c

   1 /*-
   2  * Copyright (c) 1990 The Regents of the University of California.
   3  * Copyright (c) 2008 The DragonFly Project.
   4  * All rights reserved.
   5  *
   6  * This code is derived from software contributed to Berkeley by
   7  * William Jolitz and Don Ahn.
   8  *
   9  * Redistribution and use in source and binary forms, with or without
  10  * modification, are permitted provided that the following conditions
  11  * are met:
  12  * 1. Redistributions of source code must retain the above copyright
  13  *    notice, this list of conditions and the following disclaimer.
  14  * 2. Redistributions in binary form must reproduce the above copyright
  15  *    notice, this list of conditions and the following disclaimer in the
  16  *    documentation and/or other materials provided with the distribution.
  17  * 3. All advertising materials mentioning features or use of this software
  18  *    must display the following acknowledgement:
  19  *      This product includes software developed by the University of
  20  *      California, Berkeley and its contributors.
  21  * 4. Neither the name of the University nor the names of its contributors
  22  *    may be used to endorse or promote products derived from this software
  23  *    without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
  26  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  27  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  28  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
  29  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  30  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  31  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  32  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  33  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  34  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  35  * SUCH DAMAGE.
  36  *
  37  *      from: @(#)clock.c       7.2 (Berkeley) 5/12/91
  38  * $FreeBSD: src/sys/i386/isa/clock.c,v 1.149.2.6 2002/11/02 04:41:50 iwasaki Exp $
  39  */
  40
  41 /*
  42  * Routines to handle clock hardware.
  43  */
  44
  45 /*
  46  * inittodr, settodr and support routines written
  47  * by Christoph Robitschko <chmr@edvz.tu-graz.ac.at>
  48  *
  49  * reintroduced and updated by Chris Stenton <chris@gnome.co.uk> 8/10/94
  50  */
  51
  52 #if 0
  53 #include "opt_clock.h"
  54 #endif
  55
  56 #include <sys/param.h>
  57 #include <sys/systm.h>
  58 #include <sys/eventhandler.h>
  59 #include <sys/time.h>
  60 #include <sys/kernel.h>
  61 #include <sys/bus.h>
  62 #include <sys/sysctl.h>
  63 #include <sys/cons.h>
  64 #include <sys/systimer.h>
  65 #include <sys/globaldata.h>
  66 #include <sys/thread2.h>
  67 #include <sys/machintr.h>
  68 #include <sys/interrupt.h>
  69
  70 #include <machine/clock.h>
  71 #include <machine/cputypes.h>
  72 #include <machine/frame.h>
  73 #include <machine/ipl.h>
  74 #include <machine/limits.h>
  75 #include <machine/md_var.h>
  76 #include <machine/psl.h>
  77 #include <machine/segments.h>
  78 #include <machine/smp.h>
  79 #include <machine/specialreg.h>
  80 #include <machine/intr_machdep.h>
  81
  82 #include <machine_base/apic/ioapic.h>
  83 #include <machine_base/apic/ioapic_abi.h>
  84 #include <machine_base/icu/icu.h>
  85 #include <bus/isa/isa.h>
  86 #include <bus/isa/rtc.h>
  87 #include <machine_base/isa/timerreg.h>
  88
  89 static void i8254_restore(void);
  90 static void resettodr_on_shutdown(void *arg __unused);
  91
  92 /*
  93  * 32-bit time_t's can't reach leap years before 1904 or after 2036, so we
  94  * can use a simple formula for leap years.
  95  */
  96 #define LEAPYEAR(y) ((u_int)(y) % 4 == 0)
  97 #define DAYSPERYEAR   (31+28+31+30+31+30+31+31+30+31+30+31)
  98
  99 #ifndef TIMER_FREQ
 100 #define TIMER_FREQ   1193182
 101 #endif
 102
 103 static uint8_t i8254_walltimer_sel;
 104 static uint16_t i8254_walltimer_cntr;
 105
 106 int     adjkerntz;              /* local offset from GMT in seconds */
 107 int     disable_rtc_set;        /* disable resettodr() if != 0 */
 108 int     tsc_present;
 109 int     tsc_invariant;
 110 int     tsc_mpsync;
 111 int64_t tsc_frequency;
 112 int     tsc_is_broken;
 113 int     wall_cmos_clock;        /* wall CMOS clock assumed if != 0 */
 114 int     timer0_running;
 115 enum tstate { RELEASED, ACQUIRED };
 116 enum tstate timer0_state;
 117 enum tstate timer1_state;
 118 enum tstate timer2_state;
 119
 120 static  int     beeping = 0;
 121 static  const u_char daysinmonth[] = {31,28,31,30,31,30,31,31,30,31,30,31};
 122 static  u_char  rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
 123 static  u_char  rtc_statusb = RTCSB_24HR | RTCSB_PINTR;
 124 static  int     rtc_loaded;
 125
 126 static int i8254_cputimer_div;
 127
 128 static int i8254_nointr;
 129 static int i8254_intr_disable = 1;
 130 TUNABLE_INT("hw.i8254.intr_disable", &i8254_intr_disable);
 131
 132 static struct callout sysbeepstop_ch;
 133
 134 static sysclock_t i8254_cputimer_count(void);
 135 static void i8254_cputimer_construct(struct cputimer *cputimer, sysclock_t last);
 136 static void i8254_cputimer_destruct(struct cputimer *cputimer);
 137
 138 static struct cputimer  i8254_cputimer = {
 139     SLIST_ENTRY_INITIALIZER,
 140     "i8254",
 141     CPUTIMER_PRI_8254,
 142     0,
 143     i8254_cputimer_count,
 144     cputimer_default_fromhz,
 145     cputimer_default_fromus,
 146     i8254_cputimer_construct,
 147     i8254_cputimer_destruct,
 148     TIMER_FREQ,
 149     0, 0, 0
 150 };
 151
 152 static sysclock_t tsc_cputimer_count_mfence(void);
 153 static sysclock_t tsc_cputimer_count_lfence(void);
 154 static void tsc_cputimer_construct(struct cputimer *, sysclock_t);
 155
 156 static struct cputimer  tsc_cputimer = {
 157     SLIST_ENTRY_INITIALIZER,
 158     "TSC",
 159     CPUTIMER_PRI_TSC,
 160     CPUTIMER_TSC,
 161     tsc_cputimer_count_mfence, /* safe bet */
 162     cputimer_default_fromhz,
 163     cputimer_default_fromus,
 164     tsc_cputimer_construct,
 165     cputimer_default_destruct,
 166     0,
 167     0, 0, 0
 168 };
 169
 170 static void i8254_intr_reload(struct cputimer_intr *, sysclock_t);
 171 static void i8254_intr_config(struct cputimer_intr *, const struct cputimer *);
 172 static void i8254_intr_initclock(struct cputimer_intr *, boolean_t);
 173
 174 static struct cputimer_intr i8254_cputimer_intr = {
 175     .freq = TIMER_FREQ,
 176     .reload = i8254_intr_reload,
 177     .enable = cputimer_intr_default_enable,
 178     .config = i8254_intr_config,
 179     .restart = cputimer_intr_default_restart,
 180     .pmfixup = cputimer_intr_default_pmfixup,
 181     .initclock = i8254_intr_initclock,
 182     .next = SLIST_ENTRY_INITIALIZER,
 183     .name = "i8254",
 184     .type = CPUTIMER_INTR_8254,
 185     .prio = CPUTIMER_INTR_PRIO_8254,
 186     .caps = CPUTIMER_INTR_CAP_PS
 187 };
 188
 189 /*
 190  * timer0 clock interrupt.  Timer0 is in one-shot mode and has stopped
 191  * counting as of this interrupt.  We use timer1 in free-running mode (not
 192  * generating any interrupts) as our main counter.  Each cpu has timeouts
 193  * pending.
 194  *
 195  * This code is INTR_MPSAFE and may be called without the BGL held.
 196  */
 197 static void
 198 clkintr(void *dummy, void *frame_arg)
 199 {
 200         static sysclock_t sysclock_count;       /* NOTE! Must be static */
 201         struct globaldata *gd = mycpu;
 202         struct globaldata *gscan;
 203         int n;
 204
 205         /*
 206          * SWSTROBE mode is a one-shot, the timer is no longer running
 207          */
 208         timer0_running = 0;
 209
 210         /*
 211          * XXX the dispatcher needs work.  right now we call systimer_intr()
 212          * directly or via IPI for any cpu with systimers queued, which is
 213          * usually *ALL* of them.  We need to use the LAPIC timer for this.
 214          */
 215         sysclock_count = sys_cputimer->count();
 216         for (n = 0; n < ncpus; ++n) {
 217             gscan = globaldata_find(n);
 218             if (TAILQ_FIRST(&gscan->gd_systimerq) == NULL)
 219                 continue;
 220             if (gscan != gd) {
 221                 lwkt_send_ipiq3(gscan, (ipifunc3_t)systimer_intr,
 222                                 &sysclock_count, 1);
 223             } else {
 224                 systimer_intr(&sysclock_count, 0, frame_arg);
 225             }
 226         }
 227 }
 228
 229
 230 /*
 231  * NOTE! not MP safe.
 232  */
 233 int
 234 acquire_timer2(int mode)
 235 {
 236         if (timer2_state != RELEASED)
 237                 return (-1);
 238         timer2_state = ACQUIRED;
 239
 240         /*
 241          * This access to the timer registers is as atomic as possible
 242          * because it is a single instruction.  We could do better if we
 243          * knew the rate.
 244          */
 245         outb(TIMER_MODE, TIMER_SEL2 | (mode & 0x3f));
 246         return (0);
 247 }
 248
 249 int
 250 release_timer2(void)
 251 {
 252         if (timer2_state != ACQUIRED)
 253                 return (-1);
 254         outb(TIMER_MODE, TIMER_SEL2 | TIMER_SQWAVE | TIMER_16BIT);
 255         timer2_state = RELEASED;
 256         return (0);
 257 }
 258
 259 #include "opt_ddb.h"
 260 #ifdef DDB
 261 #include <ddb/ddb.h>
 262
 263 DB_SHOW_COMMAND(rtc, rtc)
 264 {
 265         kprintf("%02x/%02x/%02x %02x:%02x:%02x, A = %02x, B = %02x, C = %02x\n",
 266                rtcin(RTC_YEAR), rtcin(RTC_MONTH), rtcin(RTC_DAY),
 267                rtcin(RTC_HRS), rtcin(RTC_MIN), rtcin(RTC_SEC),
 268                rtcin(RTC_STATUSA), rtcin(RTC_STATUSB), rtcin(RTC_INTR));
 269 }
 270 #endif /* DDB */
 271
 272 /*
 273  * Return the current cpu timer count as a 32 bit integer.
 274  */
 275 static
 276 sysclock_t
 277 i8254_cputimer_count(void)
 278 {
 279         static uint16_t cputimer_last;
 280         uint16_t count;
 281         sysclock_t ret;
 282
 283         clock_lock();
 284         outb(TIMER_MODE, i8254_walltimer_sel | TIMER_LATCH);
 285         count = (uint8_t)inb(i8254_walltimer_cntr);             /* get countdown */
 286         count |= ((uint8_t)inb(i8254_walltimer_cntr) << 8);
 287         count = -count;                                 /* -> countup */
 288         if (count < cputimer_last)                      /* rollover */
 289                 i8254_cputimer.base += 0x00010000;
 290         ret = i8254_cputimer.base | count;
 291         cputimer_last = count;
 292         clock_unlock();
 293         return(ret);
 294 }
 295
 296 /*
 297  * This function is called whenever the system timebase changes, allowing
 298  * us to calculate what is needed to convert a system timebase tick
 299  * into an 8254 tick for the interrupt timer.  If we can convert to a
 300  * simple shift, multiplication, or division, we do so.  Otherwise 64
 301  * bit arithmatic is required every time the interrupt timer is reloaded.
 302  */
 303 static void
 304 i8254_intr_config(struct cputimer_intr *cti, const struct cputimer *timer)
 305 {
 306     int freq;
 307     int div;
 308
 309     /*
 310      * Will a simple divide do the trick?
 311      */
 312     div = (timer->freq + (cti->freq / 2)) / cti->freq;
 313     freq = cti->freq * div;
 314
 315     if (freq >= timer->freq - 1 && freq <= timer->freq + 1)
 316         i8254_cputimer_div = div;
 317     else
 318         i8254_cputimer_div = 0;
 319 }
 320
 321 /*
 322  * Reload for the next timeout.  It is possible for the reload value
 323  * to be 0 or negative, indicating that an immediate timer interrupt
 324  * is desired.  For now make the minimum 2 ticks.
 325  *
 326  * We may have to convert from the system timebase to the 8254 timebase.
 327  */
 328 static void
 329 i8254_intr_reload(struct cputimer_intr *cti, sysclock_t reload)
 330 {
 331     uint16_t count;
 332
 333     if (i8254_cputimer_div)
 334         reload /= i8254_cputimer_div;
 335     else
 336         reload = (int64_t)reload * cti->freq / sys_cputimer->freq;
 337
 338     if ((int)reload < 2)
 339         reload = 2;
 340
 341     clock_lock();
 342     if (timer0_running) {
 343         outb(TIMER_MODE, TIMER_SEL0 | TIMER_LATCH);     /* count-down timer */
 344         count = (uint8_t)inb(TIMER_CNTR0);              /* lsb */
 345         count |= ((uint8_t)inb(TIMER_CNTR0) << 8);      /* msb */
 346         if (reload < count) {
 347             outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
 348             outb(TIMER_CNTR0, (uint8_t)reload);         /* lsb */
 349             outb(TIMER_CNTR0, (uint8_t)(reload >> 8));  /* msb */
 350         }
 351     } else {
 352         timer0_running = 1;
 353         if (reload > 0xFFFF)
 354             reload = 0;         /* full count */
 355         outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
 356         outb(TIMER_CNTR0, (uint8_t)reload);             /* lsb */
 357         outb(TIMER_CNTR0, (uint8_t)(reload >> 8));      /* msb */
 358     }
 359     clock_unlock();
 360 }
 361
 362 /*
 363  * DELAY(usec)       - Spin for the specified number of microseconds.
 364  * DRIVERSLEEP(usec) - Spin for the specified number of microseconds,
 365  *                     but do a thread switch in the loop
 366  *
 367  * Relies on timer 1 counting down from (cputimer_freq / hz)
 368  * Note: timer had better have been programmed before this is first used!
 369  */
 370 static void
 371 DODELAY(int n, int doswitch)
 372 {
 373         ssysclock_t delta, ticks_left;
 374         sysclock_t prev_tick, tick;
 375
 376 #ifdef DELAYDEBUG
 377         int getit_calls = 1;
 378         int n1;
 379         static int state = 0;
 380
 381         if (state == 0) {
 382                 state = 1;
 383                 for (n1 = 1; n1 <= 10000000; n1 *= 10)
 384                         DELAY(n1);
 385                 state = 2;
 386         }
 387         if (state == 1)
 388                 kprintf("DELAY(%d)...", n);
 389 #endif
 390         /*
 391          * Guard against the timer being uninitialized if we are called
 392          * early for console i/o.
 393          */
 394         if (timer0_state == RELEASED)
 395                 i8254_restore();
 396
 397         /*
 398          * Read the counter first, so that the rest of the setup overhead is
 399          * counted.  Then calculate the number of hardware timer ticks
 400          * required, rounding up to be sure we delay at least the requested
 401          * number of microseconds.
 402          */
 403         prev_tick = sys_cputimer->count();
 404         ticks_left = ((u_int)n * (int64_t)sys_cputimer->freq + 999999) /
 405                      1000000;
 406
 407         /*
 408          * Loop until done.
 409          */
 410         while (ticks_left > 0) {
 411                 tick = sys_cputimer->count();
 412 #ifdef DELAYDEBUG
 413                 ++getit_calls;
 414 #endif
 415                 delta = tick - prev_tick;
 416                 prev_tick = tick;
 417                 if (delta < 0)
 418                         delta = 0;
 419                 ticks_left -= delta;
 420                 if (doswitch && ticks_left > 0)
 421                         lwkt_switch();
 422                 cpu_pause();
 423         }
 424 #ifdef DELAYDEBUG
 425         if (state == 1)
 426                 kprintf(" %d calls to getit() at %d usec each\n",
 427                        getit_calls, (n + 5) / getit_calls);
 428 #endif
 429 }
 430
 431 /*
 432  * DELAY() never switches.
 433  */
 434 void
 435 DELAY(int n)
 436 {
 437         DODELAY(n, 0);
 438 }
 439
 440 /*
 441  * Returns non-zero if the specified time period has elapsed.  Call
 442  * first with last_clock set to 0.
 443  */
 444 int
 445 CHECKTIMEOUT(TOTALDELAY *tdd)
 446 {
 447         sysclock_t delta;
 448         int us;
 449
 450         if (tdd->started == 0) {
 451                 if (timer0_state == RELEASED)
 452                         i8254_restore();
 453                 tdd->last_clock = sys_cputimer->count();
 454                 tdd->started = 1;
 455                 return(0);
 456         }
 457         delta = sys_cputimer->count() - tdd->last_clock;
 458         us = (u_int64_t)delta * (u_int64_t)1000000 /
 459              (u_int64_t)sys_cputimer->freq;
 460         tdd->last_clock += (u_int64_t)us * (u_int64_t)sys_cputimer->freq /
 461                            1000000;
 462         tdd->us -= us;
 463         return (tdd->us < 0);
 464 }
 465
 466
 467 /*
 468  * DRIVERSLEEP() does not switch if called with a spinlock held or
 469  * from a hard interrupt.
 470  */
 471 void
 472 DRIVERSLEEP(int usec)
 473 {
 474         globaldata_t gd = mycpu;
 475
 476         if (gd->gd_intr_nesting_level || gd->gd_spinlocks) {
 477                 DODELAY(usec, 0);
 478         } else {
 479                 DODELAY(usec, 1);
 480         }
 481 }
 482
 483 static void
 484 sysbeepstop(void *chan)
 485 {
 486         outb(IO_PPI, inb(IO_PPI)&0xFC); /* disable counter2 output to speaker */
 487         beeping = 0;
 488         release_timer2();
 489 }
 490
 491 int
 492 sysbeep(int pitch, int period)
 493 {
 494         if (acquire_timer2(TIMER_SQWAVE|TIMER_16BIT))
 495                 return(-1);
 496         if (sysbeep_enable == 0)
 497                 return(-1);
 498         /*
 499          * Nobody else is using timer2, we do not need the clock lock
 500          */
 501         outb(TIMER_CNTR2, pitch);
 502         outb(TIMER_CNTR2, (pitch>>8));
 503         if (!beeping) {
 504                 /* enable counter2 output to speaker */
 505                 outb(IO_PPI, inb(IO_PPI) | 3);
 506                 beeping = period;
 507                 callout_reset(&sysbeepstop_ch, period, sysbeepstop, NULL);
 508         }
 509         return (0);
 510 }
 511
 512 /*
 513  * RTC support routines
 514  */
 515
 516 int
 517 rtcin(int reg)
 518 {
 519         u_char val;
 520
 521         crit_enter();
 522         outb(IO_RTC, reg);
 523         inb(0x84);
 524         val = inb(IO_RTC + 1);
 525         inb(0x84);
 526         crit_exit();
 527         return (val);
 528 }
 529
 530 static __inline void
 531 writertc(u_char reg, u_char val)
 532 {
 533         crit_enter();
 534         inb(0x84);
 535         outb(IO_RTC, reg);
 536         inb(0x84);
 537         outb(IO_RTC + 1, val);
 538         inb(0x84);              /* XXX work around wrong order in rtcin() */
 539         crit_exit();
 540 }
 541
 542 static __inline int
 543 readrtc(int port)
 544 {
 545         return(bcd2bin(rtcin(port)));
 546 }
 547
 548 static u_int
 549 calibrate_clocks(void)
 550 {
 551         u_int64_t old_tsc;
 552         u_int tot_count;
 553         sysclock_t count, prev_count;
 554         int sec, start_sec, timeout;
 555
 556         if (bootverbose)
 557                 kprintf("Calibrating clock(s) ...\n");
 558         if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
 559                 goto fail;
 560         timeout = 100000000;
 561
 562         /* Read the mc146818A seconds counter. */
 563         for (;;) {
 564                 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
 565                         sec = rtcin(RTC_SEC);
 566                         break;
 567                 }
 568                 if (--timeout == 0)
 569                         goto fail;
 570         }
 571
 572         /* Wait for the mC146818A seconds counter to change. */
 573         start_sec = sec;
 574         for (;;) {
 575                 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP)) {
 576                         sec = rtcin(RTC_SEC);
 577                         if (sec != start_sec)
 578                                 break;
 579                 }
 580                 if (--timeout == 0)
 581                         goto fail;
 582         }
 583
 584         /* Start keeping track of the i8254 counter. */
 585         prev_count = sys_cputimer->count();
 586         tot_count = 0;
 587
 588         if (tsc_present)
 589                 old_tsc = rdtsc();
 590         else
 591                 old_tsc = 0;            /* shut up gcc */
 592
 593         /*
 594          * Wait for the mc146818A seconds counter to change.  Read the i8254
 595          * counter for each iteration since this is convenient and only
 596          * costs a few usec of inaccuracy. The timing of the final reads
 597          * of the counters almost matches the timing of the initial reads,
 598          * so the main cause of inaccuracy is the varying latency from
 599          * inside getit() or rtcin(RTC_STATUSA) to the beginning of the
 600          * rtcin(RTC_SEC) that returns a changed seconds count.  The
 601          * maximum inaccuracy from this cause is < 10 usec on 486's.
 602          */
 603         start_sec = sec;
 604         for (;;) {
 605                 if (!(rtcin(RTC_STATUSA) & RTCSA_TUP))
 606                         sec = rtcin(RTC_SEC);
 607                 count = sys_cputimer->count();
 608                 tot_count += (int)(count - prev_count);
 609                 prev_count = count;
 610                 if (sec != start_sec)
 611                         break;
 612                 if (--timeout == 0)
 613                         goto fail;
 614         }
 615
 616         /*
 617          * Read the cpu cycle counter.  The timing considerations are
 618          * similar to those for the i8254 clock.
 619          */
 620         if (tsc_present) {
 621                 tsc_frequency = rdtsc() - old_tsc;
 622         }
 623
 624         if (tsc_present) {
 625                 kprintf("TSC%s clock: %llu Hz, ",
 626                     tsc_invariant ? " invariant" : "",
 627                     (long long)tsc_frequency);
 628         }
 629         kprintf("i8254 clock: %u Hz\n", tot_count);
 630         return (tot_count);
 631
 632 fail:
 633         kprintf("failed, using default i8254 clock of %u Hz\n",
 634                 i8254_cputimer.freq);
 635         return (i8254_cputimer.freq);
 636 }
 637
 638 static void
 639 i8254_restore(void)
 640 {
 641         timer0_state = ACQUIRED;
 642
 643         clock_lock();
 644
 645         /*
 646          * Timer0 is our fine-grained variable clock interrupt
 647          */
 648         outb(TIMER_MODE, TIMER_SEL0 | TIMER_SWSTROBE | TIMER_16BIT);
 649         outb(TIMER_CNTR0, 2);   /* lsb */
 650         outb(TIMER_CNTR0, 0);   /* msb */
 651         clock_unlock();
 652
 653         if (!i8254_nointr) {
 654                 cputimer_intr_register(&i8254_cputimer_intr);
 655                 cputimer_intr_select(&i8254_cputimer_intr, 0);
 656         }
 657
 658         /*
 659          * Timer1 or timer2 is our free-running clock, but only if another
 660          * has not been selected.
 661          */
 662         cputimer_register(&i8254_cputimer);
 663         cputimer_select(&i8254_cputimer, 0);
 664 }
 665
 666 static void
 667 i8254_cputimer_construct(struct cputimer *timer, sysclock_t oldclock)
 668 {
 669         int which;
 670
 671         /*
 672          * Should we use timer 1 or timer 2 ?
 673          */
 674         which = 0;
 675         TUNABLE_INT_FETCH("hw.i8254.walltimer", &which);
 676         if (which != 1 && which != 2)
 677                 which = 2;
 678
 679         switch(which) {
 680         case 1:
 681                 timer->name = "i8254_timer1";
 682                 timer->type = CPUTIMER_8254_SEL1;
 683                 i8254_walltimer_sel = TIMER_SEL1;
 684                 i8254_walltimer_cntr = TIMER_CNTR1;
 685                 timer1_state = ACQUIRED;
 686                 break;
 687         case 2:
 688                 timer->name = "i8254_timer2";
 689                 timer->type = CPUTIMER_8254_SEL2;
 690                 i8254_walltimer_sel = TIMER_SEL2;
 691                 i8254_walltimer_cntr = TIMER_CNTR2;
 692                 timer2_state = ACQUIRED;
 693                 break;
 694         }
 695
 696         timer->base = (oldclock + 0xFFFF) & ~0xFFFF;
 697
 698         clock_lock();
 699         outb(TIMER_MODE, i8254_walltimer_sel | TIMER_RATEGEN | TIMER_16BIT);
 700         outb(i8254_walltimer_cntr, 0);  /* lsb */
 701         outb(i8254_walltimer_cntr, 0);  /* msb */
 702         outb(IO_PPI, inb(IO_PPI) | 1);  /* bit 0: enable gate, bit 1: spkr */
 703         clock_unlock();
 704 }
 705
 706 static void
 707 i8254_cputimer_destruct(struct cputimer *timer)
 708 {
 709         switch(timer->type) {
 710         case CPUTIMER_8254_SEL1:
 711             timer1_state = RELEASED;
 712             break;
 713         case CPUTIMER_8254_SEL2:
 714             timer2_state = RELEASED;
 715             break;
 716         default:
 717             break;
 718         }
 719         timer->type = 0;
 720 }
 721
 722 static void
 723 rtc_restore(void)
 724 {
 725         /* Restore all of the RTC's "status" (actually, control) registers. */
 726         writertc(RTC_STATUSB, RTCSB_24HR);
 727         writertc(RTC_STATUSA, rtc_statusa);
 728         writertc(RTC_STATUSB, rtc_statusb);
 729 }
 730
 731 /*
 732  * Restore all the timers.
 733  *
 734  * This function is called to resynchronize our core timekeeping after a
 735  * long halt, e.g. from apm_default_resume() and friends.  It is also
 736  * called if after a BIOS call we have detected munging of the 8254.
 737  * It is necessary because cputimer_count() counter's delta may have grown
 738  * too large for nanouptime() and friends to handle, or (in the case of 8254
 739  * munging) might cause the SYSTIMER code to prematurely trigger.
 740  */
 741 void
 742 timer_restore(void)
 743 {
 744         crit_enter();
 745         i8254_restore();                /* restore timer_freq and hz */
 746         rtc_restore();                  /* reenable RTC interrupts */
 747         crit_exit();
 748 }
 749
 750 /*
 751  * Initialize 8254 timer 0 early so that it can be used in DELAY().
 752  */
 753 void
 754 startrtclock(void)
 755 {
 756         u_int delta, freq;
 757
 758         /*
 759          * Can we use the TSC?
 760          *
 761          * NOTE: If running under qemu, probably a good idea to force the
 762          *       TSC because we are not likely to detect it as being
 763          *       invariant or mpsyncd if you don't.  This will greatly
 764          *       reduce SMP contention.
 765          */
 766         if (cpu_feature & CPUID_TSC) {
 767                 tsc_present = 1;
 768                 TUNABLE_INT_FETCH("hw.tsc_cputimer_force", &tsc_invariant);
 769
 770                 if ((cpu_vendor_id == CPU_VENDOR_INTEL ||
 771                      cpu_vendor_id == CPU_VENDOR_AMD) &&
 772                     cpu_exthigh >= 0x80000007) {
 773                         u_int regs[4];
 774
 775                         do_cpuid(0x80000007, regs);
 776                         if (regs[3] & 0x100)
 777                                 tsc_invariant = 1;
 778                 }
 779         } else {
 780                 tsc_present = 0;
 781         }
 782
 783         /*
 784          * Initial RTC state, don't do anything unexpected
 785          */
 786         writertc(RTC_STATUSA, rtc_statusa);
 787         writertc(RTC_STATUSB, RTCSB_24HR);
 788
 789         /*
 790          * Set the 8254 timer0 in TIMER_SWSTROBE mode and cause it to
 791          * generate an interrupt, which we will ignore for now.
 792          *
 793          * Set the 8254 timer1 in TIMER_RATEGEN mode and load 0x0000
 794          * (so it counts a full 2^16 and repeats).  We will use this timer
 795          * for our counting.
 796          */
 797         i8254_restore();
 798         freq = calibrate_clocks();
 799 #ifdef CLK_CALIBRATION_LOOP
 800         if (bootverbose) {
 801                 kprintf(
 802                 "Press a key on the console to abort clock calibration\n");
 803                 while (cncheckc() == -1)
 804                         calibrate_clocks();
 805         }
 806 #endif
 807
 808         /*
 809          * Use the calibrated i8254 frequency if it seems reasonable.
 810          * Otherwise use the default, and don't use the calibrated i586
 811          * frequency.
 812          */
 813         delta = freq > i8254_cputimer.freq ?
 814                         freq - i8254_cputimer.freq : i8254_cputimer.freq - freq;
 815         if (delta < i8254_cputimer.freq / 100) {
 816 #ifndef CLK_USE_I8254_CALIBRATION
 817                 if (bootverbose)
 818                         kprintf(
 819 "CLK_USE_I8254_CALIBRATION not specified - using default frequency\n");
 820                 freq = i8254_cputimer.freq;
 821 #endif
 822                 /*
 823                  * NOTE:
 824                  * Interrupt timer's freq must be adjusted
 825                  * before we change the cuptimer's frequency.
 826                  */
 827                 i8254_cputimer_intr.freq = freq;
 828                 cputimer_set_frequency(&i8254_cputimer, freq);
 829         } else {
 830                 if (bootverbose)
 831                         kprintf(
 832                     "%d Hz differs from default of %d Hz by more than 1%%\n",
 833                                freq, i8254_cputimer.freq);
 834                 tsc_frequency = 0;
 835         }
 836
 837 #ifndef CLK_USE_TSC_CALIBRATION
 838         if (tsc_frequency != 0) {
 839                 if (bootverbose)
 840                         kprintf(
 841 "CLK_USE_TSC_CALIBRATION not specified - using old calibration method\n");
 842                 tsc_frequency = 0;
 843         }
 844 #endif
 845         if (tsc_present && tsc_frequency == 0) {
 846                 /*
 847                  * Calibration of the i586 clock relative to the mc146818A
 848                  * clock failed.  Do a less accurate calibration relative
 849                  * to the i8254 clock.
 850                  */
 851                 u_int64_t old_tsc = rdtsc();
 852
 853                 DELAY(1000000);
 854                 tsc_frequency = rdtsc() - old_tsc;
 855 #ifdef CLK_USE_TSC_CALIBRATION
 856                 if (bootverbose) {
 857                         kprintf("TSC clock: %llu Hz (Method B)\n",
 858                                 tsc_frequency);
 859                 }
 860 #endif
 861         }
 862
 863         EVENTHANDLER_REGISTER(shutdown_post_sync, resettodr_on_shutdown, NULL, SHUTDOWN_PRI_LAST);
 864 }
 865
 866 /*
 867  * Sync the time of day back to the RTC on shutdown, but only if
 868  * we have already loaded it and have not crashed.
 869  */
 870 static void
 871 resettodr_on_shutdown(void *arg __unused)
 872 {
 873         if (rtc_loaded && panicstr == NULL) {
 874                 resettodr();
 875         }
 876 }
 877
 878 /*
 879  * Initialize the time of day register, based on the time base which is, e.g.
 880  * from a filesystem.
 881  */
 882 void
 883 inittodr(time_t base)
 884 {
 885         unsigned long   sec, days;
 886         int             year, month;
 887         int             y, m;
 888         struct timespec ts;
 889
 890         if (base) {
 891                 ts.tv_sec = base;
 892                 ts.tv_nsec = 0;
 893                 set_timeofday(&ts);
 894         }
 895
 896         /* Look if we have a RTC present and the time is valid */
 897         if (!(rtcin(RTC_STATUSD) & RTCSD_PWR))
 898                 goto wrong_time;
 899
 900         /* wait for time update to complete */
 901         /* If RTCSA_TUP is zero, we have at least 244us before next update */
 902         crit_enter();
 903         while (rtcin(RTC_STATUSA) & RTCSA_TUP) {
 904                 crit_exit();
 905                 crit_enter();
 906         }
 907
 908         days = 0;
 909 #ifdef USE_RTC_CENTURY
 910         year = readrtc(RTC_YEAR) + readrtc(RTC_CENTURY) * 100;
 911 #else
 912         year = readrtc(RTC_YEAR) + 1900;
 913         if (year < 1970)
 914                 year += 100;
 915 #endif
 916         if (year < 1970) {
 917                 crit_exit();
 918                 goto wrong_time;
 919         }
 920         month = readrtc(RTC_MONTH);
 921         for (m = 1; m < month; m++)
 922                 days += daysinmonth[m-1];
 923         if ((month > 2) && LEAPYEAR(year))
 924                 days ++;
 925         days += readrtc(RTC_DAY) - 1;
 926         for (y = 1970; y < year; y++)
 927                 days += DAYSPERYEAR + LEAPYEAR(y);
 928         sec = ((( days * 24 +
 929                   readrtc(RTC_HRS)) * 60 +
 930                   readrtc(RTC_MIN)) * 60 +
 931                   readrtc(RTC_SEC));
 932         /* sec now contains the number of seconds, since Jan 1 1970,
 933            in the local time zone */
 934
 935         sec += tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
 936
 937         y = (int)(time_second - sec);
 938         if (y <= -2 || y >= 2) {
 939                 /* badly off, adjust it */
 940                 ts.tv_sec = sec;
 941                 ts.tv_nsec = 0;
 942                 set_timeofday(&ts);
 943         }
 944         rtc_loaded = 1;
 945         crit_exit();
 946         return;
 947
 948 wrong_time:
 949         kprintf("Invalid time in real time clock.\n");
 950         kprintf("Check and reset the date immediately!\n");
 951 }
 952
 953 /*
 954  * Write system time back to RTC
 955  */
 956 void
 957 resettodr(void)
 958 {
 959         struct timeval tv;
 960         unsigned long tm;
 961         int m;
 962         int y;
 963
 964         if (disable_rtc_set)
 965                 return;
 966
 967         microtime(&tv);
 968         tm = tv.tv_sec;
 969
 970         crit_enter();
 971         /* Disable RTC updates and interrupts. */
 972         writertc(RTC_STATUSB, RTCSB_HALT | RTCSB_24HR);
 973
 974         /* Calculate local time to put in RTC */
 975
 976         tm -= tz.tz_minuteswest * 60 + (wall_cmos_clock ? adjkerntz : 0);
 977
 978         writertc(RTC_SEC, bin2bcd(tm%60)); tm /= 60;    /* Write back Seconds */
 979         writertc(RTC_MIN, bin2bcd(tm%60)); tm /= 60;    /* Write back Minutes */
 980         writertc(RTC_HRS, bin2bcd(tm%24)); tm /= 24;    /* Write back Hours   */
 981
 982         /* We have now the days since 01-01-1970 in tm */
 983         writertc(RTC_WDAY, (tm+4)%7);                   /* Write back Weekday */
 984         for (y = 1970, m = DAYSPERYEAR + LEAPYEAR(y);
 985              tm >= m;
 986              y++,      m = DAYSPERYEAR + LEAPYEAR(y))
 987              tm -= m;
 988
 989         /* Now we have the years in y and the day-of-the-year in tm */
 990         writertc(RTC_YEAR, bin2bcd(y%100));             /* Write back Year    */
 991 #ifdef USE_RTC_CENTURY
 992         writertc(RTC_CENTURY, bin2bcd(y/100));          /* ... and Century    */
 993 #endif
 994         for (m = 0; ; m++) {
 995                 int ml;
 996
 997                 ml = daysinmonth[m];
 998                 if (m == 1 && LEAPYEAR(y))
 999                         ml++;
1000                 if (tm < ml)
1001                         break;
1002                 tm -= ml;
1003         }
1004
1005         writertc(RTC_MONTH, bin2bcd(m + 1));            /* Write back Month   */
1006         writertc(RTC_DAY, bin2bcd(tm + 1));             /* Write back Month Day */
1007
1008         /* Reenable RTC updates and interrupts. */
1009         writertc(RTC_STATUSB, rtc_statusb);
1010         crit_exit();
1011 }
1012
1013 static int
1014 i8254_ioapic_trial(int irq, struct cputimer_intr *cti)
1015 {
1016         sysclock_t base;
1017         long lastcnt;
1018
1019         /*
1020          * Following code assumes the 8254 is the cpu timer,
1021          * so make sure it is.
1022          */
1023         KKASSERT(sys_cputimer == &i8254_cputimer);
1024         KKASSERT(cti == &i8254_cputimer_intr);
1025
1026         lastcnt = get_interrupt_counter(irq, mycpuid);
1027
1028         /*
1029          * Force an 8254 Timer0 interrupt and wait 1/100s for
1030          * it to happen, then see if we got it.
1031          */
1032         kprintf("IOAPIC: testing 8254 interrupt delivery\n");
1033
1034         i8254_intr_reload(cti, 2);
1035         base = sys_cputimer->count();
1036         while (sys_cputimer->count() - base < sys_cputimer->freq / 100)
1037                 ; /* nothing */
1038
1039         if (get_interrupt_counter(irq, mycpuid) - lastcnt == 0)
1040                 return ENOENT;
1041         return 0;
1042 }
1043
1044 /*
1045  * Start both clocks running.  DragonFly note: the stat clock is no longer
1046  * used.  Instead, 8254 based systimers are used for all major clock
1047  * interrupts.
1048  */
1049 static void
1050 i8254_intr_initclock(struct cputimer_intr *cti, boolean_t selected)
1051 {
1052         void *clkdesc = NULL;
1053         int irq = 0, mixed_mode = 0, error;
1054
1055         KKASSERT(mycpuid == 0);
1056         callout_init_mp(&sysbeepstop_ch);
1057
1058         if (!selected && i8254_intr_disable)
1059                 goto nointr;
1060
1061         /*
1062          * The stat interrupt mask is different without the
1063          * statistics clock.  Also, don't set the interrupt
1064          * flag which would normally cause the RTC to generate
1065          * interrupts.
1066          */
1067         rtc_statusb = RTCSB_24HR;
1068
1069         /* Finish initializing 8254 timer 0. */
1070         if (ioapic_enable) {
1071                 irq = machintr_legacy_intr_find(0, INTR_TRIGGER_EDGE,
1072                         INTR_POLARITY_HIGH);
1073                 if (irq < 0) {
1074 mixed_mode_setup:
1075                         error = ioapic_conf_legacy_extint(0);
1076                         if (!error) {
1077                                 irq = machintr_legacy_intr_find(0,
1078                                     INTR_TRIGGER_EDGE, INTR_POLARITY_HIGH);
1079                                 if (irq < 0)
1080                                         error = ENOENT;
1081                         }
1082
1083                         if (error) {
1084                                 if (!selected) {
1085                                         kprintf("IOAPIC: setup mixed mode for "
1086                                                 "irq 0 failed: %d\n", error);
1087                                         goto nointr;
1088                                 } else {
1089                                         panic("IOAPIC: setup mixed mode for "
1090                                               "irq 0 failed: %d\n", error);
1091                                 }
1092                         }
1093                         mixed_mode = 1;
1094                 }
1095                 clkdesc = register_int(irq, clkintr, NULL, "clk",
1096                                        NULL,
1097                                        INTR_EXCL | INTR_CLOCK |
1098                                        INTR_NOPOLL | INTR_MPSAFE |
1099                                        INTR_NOENTROPY, 0);
1100         } else {
1101                 register_int(0, clkintr, NULL, "clk", NULL,
1102                              INTR_EXCL | INTR_CLOCK |
1103                              INTR_NOPOLL | INTR_MPSAFE |
1104                              INTR_NOENTROPY, 0);
1105         }
1106
1107         /* Initialize RTC. */
1108         writertc(RTC_STATUSA, rtc_statusa);
1109         writertc(RTC_STATUSB, RTCSB_24HR);
1110
1111         if (ioapic_enable) {
1112                 error = i8254_ioapic_trial(irq, cti);
1113                 if (error) {
1114                         if (mixed_mode) {
1115                                 if (!selected) {
1116                                         kprintf("IOAPIC: mixed mode for irq %d "
1117                                                 "trial failed: %d\n",
1118                                                 irq, error);
1119                                         goto nointr;
1120                                 } else {
1121                                         panic("IOAPIC: mixed mode for irq %d "
1122                                               "trial failed: %d\n", irq, error);
1123                                 }
1124                         } else {
1125                                 kprintf("IOAPIC: warning 8254 is not connected "
1126                                         "to the correct pin, try mixed mode\n");
1127                                 unregister_int(clkdesc, 0);
1128                                 goto mixed_mode_setup;
1129                         }
1130                 }
1131         }
1132         return;
1133
1134 nointr:
1135         i8254_nointr = 1; /* don't try to register again */
1136         cputimer_intr_deregister(cti);
1137 }
1138
1139 void
1140 setstatclockrate(int newhz)
1141 {
1142         if (newhz == RTC_PROFRATE)
1143                 rtc_statusa = RTCSA_DIVIDER | RTCSA_PROF;
1144         else
1145                 rtc_statusa = RTCSA_DIVIDER | RTCSA_NOPROF;
1146         writertc(RTC_STATUSA, rtc_statusa);
1147 }
1148
1149 #if 0
1150 static unsigned
1151 tsc_get_timecount(struct timecounter *tc)
1152 {
1153         return (rdtsc());
1154 }
1155 #endif
1156
1157 #ifdef KERN_TIMESTAMP
1158 #define KERN_TIMESTAMP_SIZE 16384
1159 static u_long tsc[KERN_TIMESTAMP_SIZE] ;
1160 SYSCTL_OPAQUE(_debug, OID_AUTO, timestamp, CTLFLAG_RD, tsc,
1161         sizeof(tsc), "LU", "Kernel timestamps");
1162 void
1163 _TSTMP(u_int32_t x)
1164 {
1165         static int i;
1166
1167         tsc[i] = (u_int32_t)rdtsc();
1168         tsc[i+1] = x;
1169         i = i + 2;
1170         if (i >= KERN_TIMESTAMP_SIZE)
1171                 i = 0;
1172         tsc[i] = 0; /* mark last entry */
1173 }
1174 #endif /* KERN_TIMESTAMP */
1175
1176 /*
1177  *
1178  */
1179
1180 static int
1181 hw_i8254_timestamp(SYSCTL_HANDLER_ARGS)
1182 {
1183     sysclock_t count;
1184     uint64_t tscval;
1185     char buf[32];
1186
1187     crit_enter();
1188     if (sys_cputimer == &i8254_cputimer)
1189         count = sys_cputimer->count();
1190     else
1191         count = 0;
1192     if (tsc_present)
1193         tscval = rdtsc();
1194     else
1195         tscval = 0;
1196     crit_exit();
1197     ksnprintf(buf, sizeof(buf), "%08x %016llx", count, (long long)tscval);
1198     return(SYSCTL_OUT(req, buf, strlen(buf) + 1));
1199 }
1200
1201 struct tsc_mpsync_arg {
1202         volatile uint64_t       tsc_target;
1203         volatile int            tsc_mpsync;
1204 };
1205
1206 struct tsc_mpsync_thr {
1207         volatile int            tsc_done_cnt;
1208         volatile int            tsc_mpsync_cnt;
1209 };
1210
1211 static void
1212 tsc_mpsync_test_remote(void *xarg)
1213 {
1214         struct tsc_mpsync_arg *arg = xarg;
1215         uint64_t tsc;
1216
1217         tsc = rdtsc_ordered();
1218         if (tsc < arg->tsc_target)
1219                 arg->tsc_mpsync = 0;
1220 }
1221
1222 static void
1223 tsc_mpsync_test_loop(struct tsc_mpsync_arg *arg)
1224 {
1225         struct globaldata *gd = mycpu;
1226         uint64_t test_end, test_begin;
1227         u_int i;
1228
1229         if (bootverbose) {
1230                 kprintf("cpu%d: TSC testing MP synchronization ...\n",
1231                     gd->gd_cpuid);
1232         }
1233
1234         test_begin = rdtsc_ordered();
1235         /* Run test for 100ms */
1236         test_end = test_begin + (tsc_frequency / 10);
1237
1238         arg->tsc_mpsync = 1;
1239         arg->tsc_target = test_begin;
1240
1241 #define TSC_TEST_TRYMAX         1000000 /* Make sure we could stop */
1242 #define TSC_TEST_TRYMIN         50000
1243
1244         for (i = 0; i < TSC_TEST_TRYMAX; ++i) {
1245                 struct lwkt_cpusync cs;
1246
1247                 crit_enter();
1248                 lwkt_cpusync_init(&cs, gd->gd_other_cpus,
1249                     tsc_mpsync_test_remote, arg);
1250                 lwkt_cpusync_interlock(&cs);
1251                 arg->tsc_target = rdtsc_ordered();
1252                 cpu_mfence();
1253                 lwkt_cpusync_deinterlock(&cs);
1254                 crit_exit();
1255
1256                 if (!arg->tsc_mpsync) {
1257                         kprintf("cpu%d: TSC is not MP synchronized @%u\n",
1258                             gd->gd_cpuid, i);
1259                         break;
1260                 }
1261                 if (arg->tsc_target > test_end && i >= TSC_TEST_TRYMIN)
1262                         break;
1263         }
1264
1265 #undef TSC_TEST_TRYMIN
1266 #undef TSC_TEST_TRYMAX
1267
1268         if (arg->tsc_target == test_begin) {
1269                 kprintf("cpu%d: TSC does not tick?!\n", gd->gd_cpuid);
1270                 /* XXX disable TSC? */
1271                 tsc_invariant = 0;
1272                 arg->tsc_mpsync = 0;
1273                 return;
1274         }
1275
1276         if (arg->tsc_mpsync && bootverbose) {
1277                 kprintf("cpu%d: TSC is MP synchronized after %u tries\n",
1278                     gd->gd_cpuid, i);
1279         }
1280 }
1281
1282 static void
1283 tsc_mpsync_ap_thread(void *xthr)
1284 {
1285         struct tsc_mpsync_thr *thr = xthr;
1286         struct tsc_mpsync_arg arg;
1287
1288         tsc_mpsync_test_loop(&arg);
1289         if (arg.tsc_mpsync) {
1290                 atomic_add_int(&thr->tsc_mpsync_cnt, 1);
1291                 cpu_sfence();
1292         }
1293         atomic_add_int(&thr->tsc_done_cnt, 1);
1294
1295         lwkt_exit();
1296 }
1297
1298 static void
1299 tsc_mpsync_test(void)
1300 {
1301         struct tsc_mpsync_arg arg;
1302
1303         if (!tsc_invariant) {
1304                 /* Not even invariant TSC */
1305                 return;
1306         }
1307
1308         if (ncpus == 1) {
1309                 /* Only one CPU */
1310                 tsc_mpsync = 1;
1311                 return;
1312         }
1313
1314         /*
1315          * Forcing can be used w/qemu to reduce contention
1316          */
1317         TUNABLE_INT_FETCH("hw.tsc_cputimer_force", &tsc_mpsync);
1318         if (tsc_mpsync) {
1319                 kprintf("TSC as cputimer forced\n");
1320                 return;
1321         }
1322
1323         if (cpu_vendor_id != CPU_VENDOR_INTEL) {
1324                 /* XXX only Intel works */
1325                 return;
1326         }
1327
1328         kprintf("TSC testing MP synchronization ...\n");
1329
1330         tsc_mpsync_test_loop(&arg);
1331         if (arg.tsc_mpsync) {
1332                 struct tsc_mpsync_thr thr;
1333                 int cpu;
1334
1335                 /*
1336                  * Test TSC MP synchronization on APs.
1337                  */
1338
1339                 thr.tsc_done_cnt = 1;
1340                 thr.tsc_mpsync_cnt = 1;
1341
1342                 for (cpu = 0; cpu < ncpus; ++cpu) {
1343                         if (cpu == mycpuid)
1344                                 continue;
1345
1346                         lwkt_create(tsc_mpsync_ap_thread, &thr, NULL,
1347                             NULL, 0, cpu, "tsc mpsync %d", cpu);
1348                 }
1349
1350                 while (thr.tsc_done_cnt != ncpus) {
1351                         cpu_pause();
1352                         cpu_lfence();
1353                 }
1354                 if (thr.tsc_mpsync_cnt == ncpus)
1355                         tsc_mpsync = 1;
1356         }
1357
1358         if (tsc_mpsync)
1359                 kprintf("TSC is MP synchronized\n");
1360         else
1361                 kprintf("TSC is not MP synchronized\n");
1362 }
1363 SYSINIT(tsc_mpsync, SI_BOOT2_FINISH_SMP, SI_ORDER_ANY, tsc_mpsync_test, NULL);
1364
1365 #define TSC_CPUTIMER_FREQMAX    128000000       /* 128Mhz */
1366
1367 static int tsc_cputimer_shift;
1368
1369 static void
1370 tsc_cputimer_construct(struct cputimer *timer, sysclock_t oldclock)
1371 {
1372         timer->base = 0;
1373         timer->base = oldclock - timer->count();
1374 }
1375
1376 static __inline sysclock_t
1377 tsc_cputimer_count(void)
1378 {
1379         uint64_t tsc;
1380
1381         tsc = rdtsc();
1382         tsc >>= tsc_cputimer_shift;
1383
1384         return (tsc + tsc_cputimer.base);
1385 }
1386
1387 static sysclock_t
1388 tsc_cputimer_count_lfence(void)
1389 {
1390         cpu_lfence();
1391         return tsc_cputimer_count();
1392 }
1393
1394 static sysclock_t
1395 tsc_cputimer_count_mfence(void)
1396 {
1397         cpu_mfence();
1398         return tsc_cputimer_count();
1399 }
1400
1401 static void
1402 tsc_cputimer_register(void)
1403 {
1404         uint64_t freq;
1405         int enable = 1;
1406
1407         if (!tsc_mpsync)
1408                 return;
1409
1410         TUNABLE_INT_FETCH("hw.tsc_cputimer_enable", &enable);
1411         if (!enable)
1412                 return;
1413
1414         freq = tsc_frequency;
1415         while (freq > TSC_CPUTIMER_FREQMAX) {
1416                 freq >>= 1;
1417                 ++tsc_cputimer_shift;
1418         }
1419         kprintf("TSC: cputimer freq %ju, shift %d\n",
1420             (uintmax_t)freq, tsc_cputimer_shift);
1421
1422         tsc_cputimer.freq = freq;
1423
1424         if (cpu_vendor_id == CPU_VENDOR_INTEL)
1425                 tsc_cputimer.count = tsc_cputimer_count_lfence;
1426         else
1427                 tsc_cputimer.count = tsc_cputimer_count_mfence; /* safe bet */
1428
1429         cputimer_register(&tsc_cputimer);
1430         cputimer_select(&tsc_cputimer, 0);
1431 }
1432 SYSINIT(tsc_cputimer_reg, SI_BOOT2_POST_SMP, SI_ORDER_FIRST,
1433         tsc_cputimer_register, NULL);
1434
1435 SYSCTL_NODE(_hw, OID_AUTO, i8254, CTLFLAG_RW, 0, "I8254");
1436 SYSCTL_UINT(_hw_i8254, OID_AUTO, freq, CTLFLAG_RD, &i8254_cputimer.freq, 0,
1437             "frequency");
1438 SYSCTL_PROC(_hw_i8254, OID_AUTO, timestamp, CTLTYPE_STRING|CTLFLAG_RD,
1439             0, 0, hw_i8254_timestamp, "A", "");
1440
1441 SYSCTL_INT(_hw, OID_AUTO, tsc_present, CTLFLAG_RD,
1442             &tsc_present, 0, "TSC Available");
1443 SYSCTL_INT(_hw, OID_AUTO, tsc_invariant, CTLFLAG_RD,
1444             &tsc_invariant, 0, "Invariant TSC");
1445 SYSCTL_INT(_hw, OID_AUTO, tsc_mpsync, CTLFLAG_RD,
1446             &tsc_mpsync, 0, "TSC is synchronized across CPUs");
1447 SYSCTL_QUAD(_hw, OID_AUTO, tsc_frequency, CTLFLAG_RD,
1448             &tsc_frequency, 0, "TSC Frequency");