2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mpapic.c,v 1.37.2.7 2003/01/25 02:31:47 peter Exp $
26 * $DragonFly: src/sys/platform/pc32/apic/mpapic.c,v 1.22 2008/04/20 13:44:26 swildner Exp $
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <sys/kernel.h>
32 #include <machine/globaldata.h>
33 #include <machine/smp.h>
34 #include <machine/md_var.h>
35 #include <machine_base/apic/mpapic.h>
36 #include <machine/segments.h>
37 #include <sys/thread2.h>
39 #include <machine_base/isa/intr_machdep.h> /* Xspuriousint() */
41 /* EISA Edge/Level trigger control registers */
42 #define ELCR0 0x4d0 /* eisa irq 0-7 */
43 #define ELCR1 0x4d1 /* eisa irq 8-15 */
45 static void lapic_timer_calibrate(void);
46 static void lapic_timer_set_divisor(int);
47 static void lapic_timer_intr_reload(sysclock_t);
48 static void lapic_timer_fixup_handler(void *);
49 static void lapic_timer_restart_handler(void *);
51 void lapic_timer_fixup(void);
52 void lapic_timer_process(void);
53 void lapic_timer_process_frame(struct intrframe *);
54 void lapic_timer_intr_test(void);
55 void lapic_timer_oneshot_intr_enable(void);
56 void lapic_timer_restart(void);
58 int lapic_timer_enable;
60 TUNABLE_INT("hw.lapic_timer_enable", &lapic_timer_enable);
63 * pointers to pmapped apic hardware.
66 volatile ioapic_t **ioapic;
68 static sysclock_t lapic_timer_freq;
69 static int lapic_timer_divisor_idx = -1;
70 static const uint32_t lapic_timer_divisors[] = {
71 APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
72 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128, APIC_TDCR_1
74 #define APIC_TIMER_NDIVISORS \
75 (int)(sizeof(lapic_timer_divisors) / sizeof(lapic_timer_divisors[0]))
79 * Enable APIC, configure interrupts.
82 apic_initialize(boolean_t bsp)
88 * setup LVT1 as ExtINT on the BSP. This is theoretically an
89 * aggregate interrupt input from the 8259. The INTA cycle
90 * will be routed to the external controller (the 8259) which
91 * is expected to supply the vector.
93 * Must be setup edge triggered, active high.
95 * Disable LVT1 on the APs. It doesn't matter what delivery
96 * mode we use because we leave it masked.
98 temp = lapic.lvt_lint0;
99 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
100 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
101 if (mycpu->gd_cpuid == 0)
102 temp |= APIC_LVT_DM_EXTINT;
104 temp |= APIC_LVT_DM_FIXED | APIC_LVT_MASKED;
105 lapic.lvt_lint0 = temp;
108 * setup LVT2 as NMI, masked till later. Edge trigger, active high.
110 temp = lapic.lvt_lint1;
111 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
112 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
113 temp |= APIC_LVT_MASKED | APIC_LVT_DM_NMI;
114 lapic.lvt_lint1 = temp;
117 * Mask the apic error interrupt, apic performance counter
120 lapic.lvt_error = lapic.lvt_error | APIC_LVT_MASKED;
121 lapic.lvt_pcint = lapic.lvt_pcint | APIC_LVT_MASKED;
123 /* Set apic timer vector and mask the apic timer interrupt. */
124 timer = lapic.lvt_timer;
125 timer &= ~APIC_LVTT_VECTOR;
126 timer |= XTIMER_OFFSET;
127 timer |= APIC_LVTT_MASKED;
128 lapic.lvt_timer = timer;
131 * Set the Task Priority Register as needed. At the moment allow
132 * interrupts on all cpus (the APs will remain CLId until they are
133 * ready to deal). We could disable all but IPIs by setting
134 * temp |= TPR_IPI_ONLY for cpu != 0.
137 temp &= ~APIC_TPR_PRIO; /* clear priority field */
140 * If we are NOT running the IO APICs, the LAPIC will only be used
141 * for IPIs. Set the TPR to prevent any unintentional interrupts.
143 temp |= TPR_IPI_ONLY;
149 * enable the local APIC
152 temp |= APIC_SVR_ENABLE; /* enable the APIC */
153 temp &= ~APIC_SVR_FOCUS_DISABLE; /* enable lopri focus processor */
156 * Set the spurious interrupt vector. The low 4 bits of the vector
159 if ((XSPURIOUSINT_OFFSET & 0x0F) != 0x0F)
160 panic("bad XSPURIOUSINT_OFFSET: 0x%08x", XSPURIOUSINT_OFFSET);
161 temp &= ~APIC_SVR_VECTOR;
162 temp |= XSPURIOUSINT_OFFSET;
167 * Pump out a few EOIs to clean out interrupts that got through
168 * before we were able to set the TPR.
175 lapic_timer_calibrate();
176 if (lapic_timer_enable)
177 cputimer_intr_reload = lapic_timer_intr_reload;
179 lapic_timer_set_divisor(lapic_timer_divisor_idx);
183 apic_dump("apic_initialize()");
188 lapic_timer_set_divisor(int divisor_idx)
190 KKASSERT(divisor_idx >= 0 && divisor_idx < APIC_TIMER_NDIVISORS);
191 lapic.dcr_timer = lapic_timer_divisors[divisor_idx];
195 lapic_timer_oneshot(u_int count)
199 value = lapic.lvt_timer;
200 value &= ~APIC_LVTT_PERIODIC;
201 lapic.lvt_timer = value;
202 lapic.icr_timer = count;
206 lapic_timer_oneshot_quick(u_int count)
208 lapic.icr_timer = count;
212 lapic_timer_calibrate(void)
216 /* Try to calibrate the local APIC timer. */
217 for (lapic_timer_divisor_idx = 0;
218 lapic_timer_divisor_idx < APIC_TIMER_NDIVISORS;
219 lapic_timer_divisor_idx++) {
220 lapic_timer_set_divisor(lapic_timer_divisor_idx);
221 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT);
223 value = APIC_TIMER_MAX_COUNT - lapic.ccr_timer;
224 if (value != APIC_TIMER_MAX_COUNT)
227 if (lapic_timer_divisor_idx >= APIC_TIMER_NDIVISORS)
228 panic("lapic: no proper timer divisor?!\n");
229 lapic_timer_freq = value / 2;
231 kprintf("lapic: divisor index %d, frequency %u Hz\n",
232 lapic_timer_divisor_idx, lapic_timer_freq);
236 lapic_timer_process_oncpu(struct globaldata *gd, struct intrframe *frame)
240 gd->gd_timer_running = 0;
242 count = sys_cputimer->count();
243 if (TAILQ_FIRST(&gd->gd_systimerq) != NULL)
244 systimer_intr(&count, 0, frame);
248 lapic_timer_process(void)
250 lapic_timer_process_oncpu(mycpu, NULL);
254 lapic_timer_process_frame(struct intrframe *frame)
256 lapic_timer_process_oncpu(mycpu, frame);
260 lapic_timer_intr_test(void)
262 struct globaldata *gd = mycpu;
264 if (!gd->gd_timer_running) {
265 gd->gd_timer_running = 1;
266 KKASSERT(lapic_timer_freq != 0);
267 lapic_timer_oneshot_quick(lapic_timer_freq);
272 lapic_timer_intr_reload(sysclock_t reload)
274 struct globaldata *gd = mycpu;
276 reload = (int64_t)reload * lapic_timer_freq / sys_cputimer->freq;
280 if (gd->gd_timer_running) {
281 if (reload < lapic.ccr_timer)
282 lapic_timer_oneshot_quick(reload);
284 gd->gd_timer_running = 1;
285 lapic_timer_oneshot_quick(reload);
290 lapic_timer_oneshot_intr_enable(void)
294 timer = lapic.lvt_timer;
295 timer &= ~(APIC_LVTT_MASKED | APIC_LVTT_PERIODIC);
296 lapic.lvt_timer = timer;
298 lapic_timer_fixup_handler(NULL);
302 lapic_timer_fixup_handler(void *arg)
309 if (strcmp(cpu_vendor, "AuthenticAMD") == 0) {
311 * Detect the presence of C1E capability mostly on latest
312 * dual-cores (or future) k8 family. This feature renders
313 * the local APIC timer dead, so we disable it by reading
314 * the Interrupt Pending Message register and clearing both
315 * C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
318 * "BIOS and Kernel Developer's Guide for AMD NPT
319 * Family 0Fh Processors"
320 * #32559 revision 3.00
322 if ((cpu_id & 0x00000f00) == 0x00000f00 &&
323 (cpu_id & 0x0fff0000) >= 0x00040000) {
326 msr = rdmsr(0xc0010055);
327 if (msr & 0x18000000) {
328 struct globaldata *gd = mycpu;
330 kprintf("cpu%d: AMD C1E detected\n",
332 wrmsr(0xc0010055, msr & ~0x18000000ULL);
335 * We are kinda stalled;
338 gd->gd_timer_running = 1;
339 lapic_timer_oneshot_quick(2);
349 lapic_timer_restart_handler(void *dummy __unused)
353 lapic_timer_fixup_handler(&started);
355 struct globaldata *gd = mycpu;
357 gd->gd_timer_running = 1;
358 lapic_timer_oneshot_quick(2);
363 * This function is called only by ACPI-CA code currently:
364 * - AMD C1E fixup. AMD C1E only seems to happen after ACPI
365 * module controls PM. So once ACPI-CA is attached, we try
366 * to apply the fixup to prevent LAPIC timer from hanging.
369 lapic_timer_fixup(void)
371 if (lapic_timer_enable) {
372 lwkt_send_ipiq_mask(smp_active_mask,
373 lapic_timer_fixup_handler, NULL);
378 lapic_timer_restart(void)
380 KKASSERT(lapic_timer_enable);
381 cputimer_intr_reload = lapic_timer_intr_reload;
382 lwkt_send_ipiq_mask(smp_active_mask, lapic_timer_restart_handler, NULL);
387 * dump contents of local APIC registers
392 kprintf("SMP: CPU%d %s:\n", mycpu->gd_cpuid, str);
393 kprintf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
394 lapic.lvt_lint0, lapic.lvt_lint1, lapic.tpr, lapic.svr);
404 #define IOAPIC_ISA_INTS 16
405 #define REDIRCNT_IOAPIC(A) \
406 ((int)((io_apic_versions[(A)] & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1)
408 static int trigger (int apic, int pin, u_int32_t * flags);
409 static void polarity (int apic, int pin, u_int32_t * flags, int level);
411 #define DEFAULT_FLAGS \
417 #define DEFAULT_ISA_FLAGS \
426 io_apic_set_id(int apic, int id)
430 ux = io_apic_read(apic, IOAPIC_ID); /* get current contents */
431 if (((ux & APIC_ID_MASK) >> 24) != id) {
432 kprintf("Changing APIC ID for IO APIC #%d"
433 " from %d to %d on chip\n",
434 apic, ((ux & APIC_ID_MASK) >> 24), id);
435 ux &= ~APIC_ID_MASK; /* clear the ID field */
437 io_apic_write(apic, IOAPIC_ID, ux); /* write new value */
438 ux = io_apic_read(apic, IOAPIC_ID); /* re-read && test */
439 if (((ux & APIC_ID_MASK) >> 24) != id)
440 panic("can't control IO APIC #%d ID, reg: 0x%08x",
447 io_apic_get_id(int apic)
449 return (io_apic_read(apic, IOAPIC_ID) & APIC_ID_MASK) >> 24;
458 extern int apic_pin_trigger; /* 'opaque' */
461 io_apic_setup_intpin(int apic, int pin)
463 int bus, bustype, irq;
464 u_char select; /* the select register is 8 bits */
465 u_int32_t flags; /* the window register is 32 bits */
466 u_int32_t target; /* the window register is 32 bits */
467 u_int32_t vector; /* the window register is 32 bits */
470 select = pin * 2 + IOAPIC_REDTBL0; /* register */
473 * Always clear an IO APIC pin before [re]programming it. This is
474 * particularly important if the pin is set up for a level interrupt
475 * as the IOART_REM_IRR bit might be set. When we reprogram the
476 * vector any EOI from pending ints on this pin could be lost and
477 * IRR might never get reset.
479 * To fix this problem, clear the vector and make sure it is
480 * programmed as an edge interrupt. This should theoretically
481 * clear IRR so we can later, safely program it as a level
486 flags = io_apic_read(apic, select) & IOART_RESV;
487 flags |= IOART_INTMSET | IOART_TRGREDG | IOART_INTAHI;
488 flags |= IOART_DESTPHY | IOART_DELFIXED;
490 target = io_apic_read(apic, select + 1) & IOART_HI_DEST_RESV;
491 target |= 0; /* fixed mode cpu mask of 0 - don't deliver anywhere */
495 io_apic_write(apic, select, flags | vector);
496 io_apic_write(apic, select + 1, target);
501 * We only deal with vectored interrupts here. ? documentation is
502 * lacking, I'm guessing an interrupt type of 0 is the 'INT' type,
505 * This test also catches unconfigured pins.
507 if (apic_int_type(apic, pin) != 0)
511 * Leave the pin unprogrammed if it does not correspond to
514 irq = apic_irq(apic, pin);
518 /* determine the bus type for this pin */
519 bus = apic_src_bus_id(apic, pin);
522 bustype = apic_bus_type(bus);
524 if ((bustype == ISA) &&
525 (pin < IOAPIC_ISA_INTS) &&
527 (apic_polarity(apic, pin) == 0x1) &&
528 (apic_trigger(apic, pin) == 0x3)) {
530 * A broken BIOS might describe some ISA
531 * interrupts as active-high level-triggered.
532 * Use default ISA flags for those interrupts.
534 flags = DEFAULT_ISA_FLAGS;
537 * Program polarity and trigger mode according to
540 flags = DEFAULT_FLAGS;
541 level = trigger(apic, pin, &flags);
543 apic_pin_trigger |= (1 << irq);
544 polarity(apic, pin, &flags, level);
548 kprintf("IOAPIC #%d intpin %d -> irq %d\n",
553 * Program the appropriate registers. This routing may be
554 * overridden when an interrupt handler for a device is
555 * actually added (see register_int(), which calls through
556 * the MACHINTR ABI to set up an interrupt handler/vector).
558 * The order in which we must program the two registers for
559 * safety is unclear! XXX
563 vector = IDT_OFFSET + irq; /* IDT vec */
564 target = io_apic_read(apic, select + 1) & IOART_HI_DEST_RESV;
565 target |= IOART_HI_DEST_BROADCAST;
566 flags |= io_apic_read(apic, select) & IOART_RESV;
567 io_apic_write(apic, select, flags | vector);
568 io_apic_write(apic, select + 1, target);
574 io_apic_setup(int apic)
580 apic_pin_trigger = 0; /* default to edge-triggered */
582 maxpin = REDIRCNT_IOAPIC(apic); /* pins in APIC */
583 kprintf("Programming %d pins in IOAPIC #%d\n", maxpin, apic);
585 for (pin = 0; pin < maxpin; ++pin) {
586 io_apic_setup_intpin(apic, pin);
589 if (apic_int_type(apic, pin) >= 0) {
590 kprintf("Warning: IOAPIC #%d pin %d does not exist,"
591 " cannot program!\n", apic, pin);
596 /* return GOOD status */
599 #undef DEFAULT_ISA_FLAGS
603 #define DEFAULT_EXTINT_FLAGS \
612 * Setup the source of External INTerrupts.
615 ext_int_setup(int apic, int intr)
617 u_char select; /* the select register is 8 bits */
618 u_int32_t flags; /* the window register is 32 bits */
619 u_int32_t target; /* the window register is 32 bits */
620 u_int32_t vector; /* the window register is 32 bits */
622 if (apic_int_type(apic, intr) != 3)
625 target = IOART_HI_DEST_BROADCAST;
626 select = IOAPIC_REDTBL0 + (2 * intr);
627 vector = IDT_OFFSET + intr;
628 flags = DEFAULT_EXTINT_FLAGS;
630 io_apic_write(apic, select, flags | vector);
631 io_apic_write(apic, select + 1, target);
635 #undef DEFAULT_EXTINT_FLAGS
639 * Set the trigger level for an IO APIC pin.
642 trigger(int apic, int pin, u_int32_t * flags)
647 static int intcontrol = -1;
649 switch (apic_trigger(apic, pin)) {
655 *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG */
659 *flags |= IOART_TRGRLVL;
667 if ((id = apic_src_bus_id(apic, pin)) == -1)
670 switch (apic_bus_type(id)) {
672 *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG; */
676 eirq = apic_src_bus_irq(apic, pin);
678 if (eirq < 0 || eirq > 15) {
679 kprintf("EISA IRQ %d?!?!\n", eirq);
683 if (intcontrol == -1) {
684 intcontrol = inb(ELCR1) << 8;
685 intcontrol |= inb(ELCR0);
686 kprintf("EISA INTCONTROL = %08x\n", intcontrol);
689 /* Use ELCR settings to determine level or edge mode */
690 level = (intcontrol >> eirq) & 1;
693 * Note that on older Neptune chipset based systems, any
694 * pci interrupts often show up here and in the ELCR as well
695 * as level sensitive interrupts attributed to the EISA bus.
699 *flags |= IOART_TRGRLVL;
701 *flags &= ~IOART_TRGRLVL;
706 *flags |= IOART_TRGRLVL;
715 panic("bad APIC IO INT flags");
720 * Set the polarity value for an IO APIC pin.
723 polarity(int apic, int pin, u_int32_t * flags, int level)
727 switch (apic_polarity(apic, pin)) {
733 *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
737 *flags |= IOART_INTALO;
745 if ((id = apic_src_bus_id(apic, pin)) == -1)
748 switch (apic_bus_type(id)) {
750 *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
754 /* polarity converter always gives active high */
755 *flags &= ~IOART_INTALO;
759 *flags |= IOART_INTALO;
768 panic("bad APIC IO INT flags");
773 * Print contents of apic_imen.
775 extern u_int apic_imen; /* keep apic_imen 'opaque' */
781 kprintf("SMP: enabled INTs: ");
782 for (x = 0; x < 24; ++x)
783 if ((apic_imen & (1 << x)) == 0)
785 kprintf("apic_imen: 0x%08x\n", apic_imen);
790 * Inter Processor Interrupt functions.
796 * Send APIC IPI 'vector' to 'destType' via 'deliveryMode'.
798 * destType is 1 of: APIC_DEST_SELF, APIC_DEST_ALLISELF, APIC_DEST_ALLESELF
799 * vector is any valid SYSTEM INT vector
800 * delivery_mode is 1 of: APIC_DELMODE_FIXED, APIC_DELMODE_LOWPRIO
802 * A backlog of requests can create a deadlock between cpus. To avoid this
803 * we have to be able to accept IPIs at the same time we are trying to send
804 * them. The critical section prevents us from attempting to send additional
805 * IPIs reentrantly, but also prevents IPIQ processing so we have to call
806 * lwkt_process_ipiq() manually. It's rather messy and expensive for this
807 * to occur but fortunately it does not happen too often.
810 apic_ipi(int dest_type, int vector, int delivery_mode)
815 if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
816 unsigned int eflags = read_eflags();
818 while ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
821 write_eflags(eflags);
824 icr_lo = (lapic.icr_lo & APIC_ICRLO_RESV_MASK) | dest_type |
825 delivery_mode | vector;
826 lapic.icr_lo = icr_lo;
832 single_apic_ipi(int cpu, int vector, int delivery_mode)
838 if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
839 unsigned int eflags = read_eflags();
841 while ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
844 write_eflags(eflags);
846 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
847 icr_hi |= (CPU_TO_ID(cpu) << 24);
848 lapic.icr_hi = icr_hi;
851 icr_lo = (lapic.icr_lo & APIC_ICRLO_RESV_MASK)
852 | APIC_DEST_DESTFLD | delivery_mode | vector;
855 lapic.icr_lo = icr_lo;
862 * Returns 0 if the apic is busy, 1 if we were able to queue the request.
864 * NOT WORKING YET! The code as-is may end up not queueing an IPI at all
865 * to the target, and the scheduler does not 'poll' for IPI messages.
868 single_apic_ipi_passive(int cpu, int vector, int delivery_mode)
874 if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
878 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
879 icr_hi |= (CPU_TO_ID(cpu) << 24);
880 lapic.icr_hi = icr_hi;
883 icr_lo = (lapic.icr_lo & APIC_RESV2_MASK)
884 | APIC_DEST_DESTFLD | delivery_mode | vector;
887 lapic.icr_lo = icr_lo;
895 * Send APIC IPI 'vector' to 'target's via 'delivery_mode'.
897 * target is a bitmask of destination cpus. Vector is any
898 * valid system INT vector. Delivery mode may be either
899 * APIC_DELMODE_FIXED or APIC_DELMODE_LOWPRIO.
902 selected_apic_ipi(u_int target, int vector, int delivery_mode)
906 int n = bsfl(target);
908 single_apic_ipi(n, vector, delivery_mode);
914 * Timer code, in development...
915 * - suggested by rgrimes@gndrsh.aac.dev.com
919 * Load a 'downcount time' in uSeconds.
922 set_apic_timer(int us)
927 * When we reach here, lapic timer's frequency
928 * must have been calculated as well as the
929 * divisor (lapic.dcr_timer is setup during the
930 * divisor calculation).
932 KKASSERT(lapic_timer_freq != 0 &&
933 lapic_timer_divisor_idx >= 0);
935 count = ((us * (int64_t)lapic_timer_freq) + 999999) / 1000000;
936 lapic_timer_oneshot(count);
941 * Read remaining time in timer.
944 read_apic_timer(void)
947 /** XXX FIXME: we need to return the actual remaining time,
948 * for now we just return the remaining count.
951 return lapic.ccr_timer;
957 * Spin-style delay, set delay time in uS, spin till it drains.
962 set_apic_timer(count);
963 while (read_apic_timer())