2 * Copyright (c) 2001 Wind River Systems
3 * Copyright (c) 1997, 1998, 1999, 2001
4 * Bill Paul <wpaul@windriver.com>. All rights reserved.
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
14 * 3. All advertising materials mentioning features or use of this software
15 * must display the following acknowledgement:
16 * This product includes software developed by Bill Paul.
17 * 4. Neither the name of the author nor the names of any co-contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
31 * THE POSSIBILITY OF SUCH DAMAGE.
33 * $FreeBSD: src/sys/dev/bge/if_bge.c,v 1.3.2.29 2003/12/01 21:06:59 ambrisko Exp $
34 * $DragonFly: src/sys/dev/netif/bge/if_bge.c,v 1.51 2005/11/29 19:56:50 dillon Exp $
39 * Broadcom BCM570x family gigabit ethernet driver for FreeBSD.
41 * Written by Bill Paul <wpaul@windriver.com>
42 * Senior Engineer, Wind River Systems
46 * The Broadcom BCM5700 is based on technology originally developed by
47 * Alteon Networks as part of the Tigon I and Tigon II gigabit ethernet
48 * MAC chips. The BCM5700, sometimes refered to as the Tigon III, has
49 * two on-board MIPS R4000 CPUs and can have as much as 16MB of external
50 * SSRAM. The BCM5700 supports TCP, UDP and IP checksum offload, jumbo
51 * frames, highly configurable RX filtering, and 16 RX and TX queues
52 * (which, along with RX filter rules, can be used for QOS applications).
53 * Other features, such as TCP segmentation, may be available as part
54 * of value-added firmware updates. Unlike the Tigon I and Tigon II,
55 * firmware images can be stored in hardware and need not be compiled
58 * The BCM5700 supports the PCI v2.2 and PCI-X v1.0 standards, and will
59 * function in a 32-bit/64-bit 33/66Mhz bus, or a 64-bit/133Mhz bus.
61 * The BCM5701 is a single-chip solution incorporating both the BCM5700
62 * MAC and a BCM5401 10/100/1000 PHY. Unlike the BCM5700, the BCM5701
63 * does not support external SSRAM.
65 * Broadcom also produces a variation of the BCM5700 under the "Altima"
66 * brand name, which is functionally similar but lacks PCI-X support.
68 * Without external SSRAM, you can only have at most 4 TX rings,
69 * and the use of the mini RX ring is disabled. This seems to imply
70 * that these features are simply not available on the BCM5701. As a
71 * result, this driver does not implement any support for the mini RX
77 #include <sys/param.h>
78 #include <sys/systm.h>
79 #include <sys/sockio.h>
81 #include <sys/malloc.h>
82 #include <sys/kernel.h>
83 #include <sys/socket.h>
84 #include <sys/queue.h>
85 #include <sys/serialize.h>
86 #include <sys/thread2.h>
89 #include <net/ifq_var.h>
90 #include <net/if_arp.h>
91 #include <net/ethernet.h>
92 #include <net/if_dl.h>
93 #include <net/if_media.h>
97 #include <net/if_types.h>
98 #include <net/vlan/if_vlan_var.h>
100 #include <netinet/in_systm.h>
101 #include <netinet/in.h>
102 #include <netinet/ip.h>
104 #include <vm/vm.h> /* for vtophys */
105 #include <vm/pmap.h> /* for vtophys */
106 #include <machine/resource.h>
108 #include <sys/rman.h>
110 #include <dev/netif/mii_layer/mii.h>
111 #include <dev/netif/mii_layer/miivar.h>
112 #include <dev/netif/mii_layer/miidevs.h>
113 #include <dev/netif/mii_layer/brgphyreg.h>
115 #include <bus/pci/pcidevs.h>
116 #include <bus/pci/pcireg.h>
117 #include <bus/pci/pcivar.h>
119 #include "if_bgereg.h"
121 #define BGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP)
123 /* "controller miibus0" required. See GENERIC if you get errors here. */
124 #include "miibus_if.h"
127 * Various supported device vendors/types and their names. Note: the
128 * spec seems to indicate that the hardware still has Alteon's vendor
129 * ID burned into it, though it will always be overriden by the vendor
130 * ID in the EEPROM. Just to be safe, we cover all possibilities.
132 #define BGE_DEVDESC_MAX 64 /* Maximum device description length */
134 static struct bge_type bge_devs[] = {
135 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5700,
136 "Alteon BCM5700 Gigabit Ethernet" },
137 { PCI_VENDOR_ALTEON, PCI_PRODUCT_ALTEON_BCM5701,
138 "Alteon BCM5701 Gigabit Ethernet" },
139 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5700,
140 "Broadcom BCM5700 Gigabit Ethernet" },
141 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5701,
142 "Broadcom BCM5701 Gigabit Ethernet" },
143 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702X,
144 "Broadcom BCM5702X Gigabit Ethernet" },
145 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5702_ALT,
146 "Broadcom BCM5702 Gigabit Ethernet" },
147 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703X,
148 "Broadcom BCM5703X Gigabit Ethernet" },
149 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5703A3,
150 "Broadcom BCM5703 Gigabit Ethernet" },
151 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704C,
152 "Broadcom BCM5704C Dual Gigabit Ethernet" },
153 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5704S,
154 "Broadcom BCM5704S Dual Gigabit Ethernet" },
155 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705,
156 "Broadcom BCM5705 Gigabit Ethernet" },
157 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705K,
158 "Broadcom BCM5705K Gigabit Ethernet" },
159 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M,
160 "Broadcom BCM5705M Gigabit Ethernet" },
161 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5705M_ALT,
162 "Broadcom BCM5705M Gigabit Ethernet" },
163 { PCI_VENDOR_BROADCOM, BCOM_DEVICEID_BCM5714C,
164 "Broadcom BCM5714C Gigabit Ethernet" },
165 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5721,
166 "Broadcom BCM5721 Gigabit Ethernet" },
167 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750,
168 "Broadcom BCM5750 Gigabit Ethernet" },
169 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5750M,
170 "Broadcom BCM5750M Gigabit Ethernet" },
171 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751,
172 "Broadcom BCM5751 Gigabit Ethernet" },
173 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5751M,
174 "Broadcom BCM5751M Gigabit Ethernet" },
175 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5782,
176 "Broadcom BCM5782 Gigabit Ethernet" },
177 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5788,
178 "Broadcom BCM5788 Gigabit Ethernet" },
179 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5789,
180 "Broadcom BCM5789 Gigabit Ethernet" },
181 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901,
182 "Broadcom BCM5901 Fast Ethernet" },
183 { PCI_VENDOR_BROADCOM, PCI_PRODUCT_BROADCOM_BCM5901A2,
184 "Broadcom BCM5901A2 Fast Ethernet" },
185 { PCI_VENDOR_SCHNEIDERKOCH, PCI_PRODUCT_SCHNEIDERKOCH_SK_9DX1,
186 "SysKonnect Gigabit Ethernet" },
187 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1000,
188 "Altima AC1000 Gigabit Ethernet" },
189 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC1001,
190 "Altima AC1002 Gigabit Ethernet" },
191 { PCI_VENDOR_ALTIMA, PCI_PRODUCT_ALTIMA_AC9100,
192 "Altima AC9100 Gigabit Ethernet" },
196 static int bge_probe(device_t);
197 static int bge_attach(device_t);
198 static int bge_detach(device_t);
199 static void bge_release_resources(struct bge_softc *);
200 static void bge_txeof(struct bge_softc *);
201 static void bge_rxeof(struct bge_softc *);
203 static void bge_tick(void *);
204 static void bge_tick_serialized(void *);
205 static void bge_stats_update(struct bge_softc *);
206 static void bge_stats_update_regs(struct bge_softc *);
207 static int bge_encap(struct bge_softc *, struct mbuf *, uint32_t *);
209 static void bge_intr(void *);
210 static void bge_start(struct ifnet *);
211 static int bge_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
212 static void bge_init(void *);
213 static void bge_stop(struct bge_softc *);
214 static void bge_watchdog(struct ifnet *);
215 static void bge_shutdown(device_t);
216 static int bge_ifmedia_upd(struct ifnet *);
217 static void bge_ifmedia_sts(struct ifnet *, struct ifmediareq *);
219 static uint8_t bge_eeprom_getbyte(struct bge_softc *, uint32_t, uint8_t *);
220 static int bge_read_eeprom(struct bge_softc *, caddr_t, uint32_t, size_t);
222 static void bge_setmulti(struct bge_softc *);
224 static void bge_handle_events(struct bge_softc *);
225 static int bge_alloc_jumbo_mem(struct bge_softc *);
226 static void bge_free_jumbo_mem(struct bge_softc *);
227 static struct bge_jslot
228 *bge_jalloc(struct bge_softc *);
229 static void bge_jfree(void *);
230 static void bge_jref(void *);
231 static int bge_newbuf_std(struct bge_softc *, int, struct mbuf *);
232 static int bge_newbuf_jumbo(struct bge_softc *, int, struct mbuf *);
233 static int bge_init_rx_ring_std(struct bge_softc *);
234 static void bge_free_rx_ring_std(struct bge_softc *);
235 static int bge_init_rx_ring_jumbo(struct bge_softc *);
236 static void bge_free_rx_ring_jumbo(struct bge_softc *);
237 static void bge_free_tx_ring(struct bge_softc *);
238 static int bge_init_tx_ring(struct bge_softc *);
240 static int bge_chipinit(struct bge_softc *);
241 static int bge_blockinit(struct bge_softc *);
244 static uint8_t bge_vpd_readbyte(struct bge_softc *, uint32_t);
245 static void bge_vpd_read_res(struct bge_softc *, struct vpd_res *, uint32_t);
246 static void bge_vpd_read(struct bge_softc *);
249 static uint32_t bge_readmem_ind(struct bge_softc *, uint32_t);
250 static void bge_writemem_ind(struct bge_softc *, uint32_t, uint32_t);
252 static uint32_t bge_readreg_ind(struct bge_softc *, uint32_t);
254 static void bge_writereg_ind(struct bge_softc *, uint32_t, uint32_t);
256 static int bge_miibus_readreg(device_t, int, int);
257 static int bge_miibus_writereg(device_t, int, int, int);
258 static void bge_miibus_statchg(device_t);
260 static void bge_reset(struct bge_softc *);
262 static device_method_t bge_methods[] = {
263 /* Device interface */
264 DEVMETHOD(device_probe, bge_probe),
265 DEVMETHOD(device_attach, bge_attach),
266 DEVMETHOD(device_detach, bge_detach),
267 DEVMETHOD(device_shutdown, bge_shutdown),
270 DEVMETHOD(bus_print_child, bus_generic_print_child),
271 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
274 DEVMETHOD(miibus_readreg, bge_miibus_readreg),
275 DEVMETHOD(miibus_writereg, bge_miibus_writereg),
276 DEVMETHOD(miibus_statchg, bge_miibus_statchg),
281 static DEFINE_CLASS_0(bge, bge_driver, bge_methods, sizeof(struct bge_softc));
282 static devclass_t bge_devclass;
284 DECLARE_DUMMY_MODULE(if_bge);
285 DRIVER_MODULE(if_bge, pci, bge_driver, bge_devclass, 0, 0);
286 DRIVER_MODULE(miibus, bge, miibus_driver, miibus_devclass, 0, 0);
289 bge_readmem_ind(struct bge_softc *sc, uint32_t off)
291 device_t dev = sc->bge_dev;
293 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
294 return(pci_read_config(dev, BGE_PCI_MEMWIN_DATA, 4));
298 bge_writemem_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
300 device_t dev = sc->bge_dev;
302 pci_write_config(dev, BGE_PCI_MEMWIN_BASEADDR, off, 4);
303 pci_write_config(dev, BGE_PCI_MEMWIN_DATA, val, 4);
308 bge_readreg_ind(struct bge_softc *sc, uin32_t off)
310 device_t dev = sc->bge_dev;
312 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
313 return(pci_read_config(dev, BGE_PCI_REG_DATA, 4));
318 bge_writereg_ind(struct bge_softc *sc, uint32_t off, uint32_t val)
320 device_t dev = sc->bge_dev;
322 pci_write_config(dev, BGE_PCI_REG_BASEADDR, off, 4);
323 pci_write_config(dev, BGE_PCI_REG_DATA, val, 4);
328 bge_vpd_readbyte(struct bge_softc *sc, uint32_t addr)
330 device_t dev = sc->bge_dev;
334 pci_write_config(dev, BGE_PCI_VPD_ADDR, addr, 2);
335 for (i = 0; i < BGE_TIMEOUT * 10; i++) {
337 if (pci_read_config(dev, BGE_PCI_VPD_ADDR, 2) & BGE_VPD_FLAG)
341 if (i == BGE_TIMEOUT) {
342 device_printf(sc->bge_dev, "VPD read timed out\n");
346 val = pci_read_config(dev, BGE_PCI_VPD_DATA, 4);
348 return((val >> ((addr % 4) * 8)) & 0xFF);
352 bge_vpd_read_res(struct bge_softc *sc, struct vpd_res *res, uint32_t addr)
357 ptr = (uint8_t *)res;
358 for (i = 0; i < sizeof(struct vpd_res); i++)
359 ptr[i] = bge_vpd_readbyte(sc, i + addr);
365 bge_vpd_read(struct bge_softc *sc)
370 if (sc->bge_vpd_prodname != NULL)
371 free(sc->bge_vpd_prodname, M_DEVBUF);
372 if (sc->bge_vpd_readonly != NULL)
373 free(sc->bge_vpd_readonly, M_DEVBUF);
374 sc->bge_vpd_prodname = NULL;
375 sc->bge_vpd_readonly = NULL;
377 bge_vpd_read_res(sc, &res, pos);
379 if (res.vr_id != VPD_RES_ID) {
380 device_printf(sc->bge_dev,
381 "bad VPD resource id: expected %x got %x\n",
382 VPD_RES_ID, res.vr_id);
387 sc->bge_vpd_prodname = malloc(res.vr_len + 1, M_DEVBUF, M_INTWAIT);
388 for (i = 0; i < res.vr_len; i++)
389 sc->bge_vpd_prodname[i] = bge_vpd_readbyte(sc, i + pos);
390 sc->bge_vpd_prodname[i] = '\0';
393 bge_vpd_read_res(sc, &res, pos);
395 if (res.vr_id != VPD_RES_READ) {
396 device_printf(sc->bge_dev,
397 "bad VPD resource id: expected %x got %x\n",
398 VPD_RES_READ, res.vr_id);
403 sc->bge_vpd_readonly = malloc(res.vr_len, M_DEVBUF, M_INTWAIT);
404 for (i = 0; i < res.vr_len + 1; i++)
405 sc->bge_vpd_readonly[i] = bge_vpd_readbyte(sc, i + pos);
410 * Read a byte of data stored in the EEPROM at address 'addr.' The
411 * BCM570x supports both the traditional bitbang interface and an
412 * auto access interface for reading the EEPROM. We use the auto
416 bge_eeprom_getbyte(struct bge_softc *sc, uint32_t addr, uint8_t *dest)
422 * Enable use of auto EEPROM access so we can avoid
423 * having to use the bitbang method.
425 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_AUTO_EEPROM);
427 /* Reset the EEPROM, load the clock period. */
428 CSR_WRITE_4(sc, BGE_EE_ADDR,
429 BGE_EEADDR_RESET|BGE_EEHALFCLK(BGE_HALFCLK_384SCL));
432 /* Issue the read EEPROM command. */
433 CSR_WRITE_4(sc, BGE_EE_ADDR, BGE_EE_READCMD | addr);
435 /* Wait for completion */
436 for(i = 0; i < BGE_TIMEOUT * 10; i++) {
438 if (CSR_READ_4(sc, BGE_EE_ADDR) & BGE_EEADDR_DONE)
442 if (i == BGE_TIMEOUT) {
443 if_printf(&sc->arpcom.ac_if, "eeprom read timed out\n");
448 byte = CSR_READ_4(sc, BGE_EE_DATA);
450 *dest = (byte >> ((addr % 4) * 8)) & 0xFF;
456 * Read a sequence of bytes from the EEPROM.
459 bge_read_eeprom(struct bge_softc *sc, caddr_t dest, uint32_t off, size_t len)
465 for (byte = 0, err = 0, i = 0; i < len; i++) {
466 err = bge_eeprom_getbyte(sc, off + i, &byte);
476 bge_miibus_readreg(device_t dev, int phy, int reg)
478 struct bge_softc *sc;
480 uint32_t val, autopoll;
483 sc = device_get_softc(dev);
484 ifp = &sc->arpcom.ac_if;
487 * Broadcom's own driver always assumes the internal
488 * PHY is at GMII address 1. On some chips, the PHY responds
489 * to accesses at all addresses, which could cause us to
490 * bogusly attach the PHY 32 times at probe type. Always
491 * restricting the lookup to address 1 is simpler than
492 * trying to figure out which chips revisions should be
498 /* Reading with autopolling on may trigger PCI errors */
499 autopoll = CSR_READ_4(sc, BGE_MI_MODE);
500 if (autopoll & BGE_MIMODE_AUTOPOLL) {
501 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
505 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_READ|BGE_MICOMM_BUSY|
506 BGE_MIPHY(phy)|BGE_MIREG(reg));
508 for (i = 0; i < BGE_TIMEOUT; i++) {
509 val = CSR_READ_4(sc, BGE_MI_COMM);
510 if (!(val & BGE_MICOMM_BUSY))
514 if (i == BGE_TIMEOUT) {
515 if_printf(ifp, "PHY read timed out\n");
520 val = CSR_READ_4(sc, BGE_MI_COMM);
523 if (autopoll & BGE_MIMODE_AUTOPOLL) {
524 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
528 if (val & BGE_MICOMM_READFAIL)
531 return(val & 0xFFFF);
535 bge_miibus_writereg(device_t dev, int phy, int reg, int val)
537 struct bge_softc *sc;
541 sc = device_get_softc(dev);
543 /* Reading with autopolling on may trigger PCI errors */
544 autopoll = CSR_READ_4(sc, BGE_MI_MODE);
545 if (autopoll & BGE_MIMODE_AUTOPOLL) {
546 BGE_CLRBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
550 CSR_WRITE_4(sc, BGE_MI_COMM, BGE_MICMD_WRITE|BGE_MICOMM_BUSY|
551 BGE_MIPHY(phy)|BGE_MIREG(reg)|val);
553 for (i = 0; i < BGE_TIMEOUT; i++) {
554 if (!(CSR_READ_4(sc, BGE_MI_COMM) & BGE_MICOMM_BUSY))
558 if (autopoll & BGE_MIMODE_AUTOPOLL) {
559 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL);
563 if (i == BGE_TIMEOUT) {
564 if_printf(&sc->arpcom.ac_if, "PHY read timed out\n");
572 bge_miibus_statchg(device_t dev)
574 struct bge_softc *sc;
575 struct mii_data *mii;
577 sc = device_get_softc(dev);
578 mii = device_get_softc(sc->bge_miibus);
580 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_PORTMODE);
581 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) {
582 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_GMII);
584 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_PORTMODE_MII);
587 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) {
588 BGE_CLRBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
590 BGE_SETBIT(sc, BGE_MAC_MODE, BGE_MACMODE_HALF_DUPLEX);
595 * Handle events that have triggered interrupts.
598 bge_handle_events(struct bge_softc *sc)
603 * Memory management for jumbo frames.
606 bge_alloc_jumbo_mem(struct bge_softc *sc)
608 struct bge_jslot *entry;
612 /* Grab a big chunk o' storage. */
613 sc->bge_cdata.bge_jumbo_buf = contigmalloc(BGE_JMEM, M_DEVBUF,
614 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
616 if (sc->bge_cdata.bge_jumbo_buf == NULL) {
617 if_printf(&sc->arpcom.ac_if, "no memory for jumbo buffers!\n");
621 SLIST_INIT(&sc->bge_jfree_listhead);
624 * Now divide it up into 9K pieces and save the addresses
625 * in an array. Note that we play an evil trick here by using
626 * the first few bytes in the buffer to hold the the address
627 * of the softc structure for this interface. This is because
628 * bge_jfree() needs it, but it is called by the mbuf management
629 * code which will not pass it to us explicitly.
631 ptr = sc->bge_cdata.bge_jumbo_buf;
632 for (i = 0; i < BGE_JSLOTS; i++) {
633 entry = &sc->bge_cdata.bge_jslots[i];
635 entry->bge_buf = ptr;
636 entry->bge_inuse = 0;
638 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead, entry, jslot_link);
646 bge_free_jumbo_mem(struct bge_softc *sc)
648 if (sc->bge_cdata.bge_jumbo_buf)
649 contigfree(sc->bge_cdata.bge_jumbo_buf, BGE_JMEM, M_DEVBUF);
653 * Allocate a jumbo buffer.
655 static struct bge_jslot *
656 bge_jalloc(struct bge_softc *sc)
658 struct bge_jslot *entry;
660 lwkt_serialize_enter(&sc->bge_jslot_serializer);
661 entry = SLIST_FIRST(&sc->bge_jfree_listhead);
663 SLIST_REMOVE_HEAD(&sc->bge_jfree_listhead, jslot_link);
664 entry->bge_inuse = 1;
666 if_printf(&sc->arpcom.ac_if, "no free jumbo buffers\n");
668 lwkt_serialize_exit(&sc->bge_jslot_serializer);
673 * Adjust usage count on a jumbo buffer.
678 struct bge_jslot *entry = (struct bge_jslot *)arg;
679 struct bge_softc *sc = entry->bge_sc;
682 panic("bge_jref: can't find softc pointer!");
684 if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
685 panic("bge_jref: asked to reference buffer "
686 "that we don't manage!");
687 } else if (entry->bge_inuse == 0) {
688 panic("bge_jref: buffer already free!");
690 atomic_add_int(&entry->bge_inuse, 1);
695 * Release a jumbo buffer.
700 struct bge_jslot *entry = (struct bge_jslot *)arg;
701 struct bge_softc *sc = entry->bge_sc;
704 panic("bge_jfree: can't find softc pointer!");
706 if (&sc->bge_cdata.bge_jslots[entry->bge_slot] != entry) {
707 panic("bge_jfree: asked to free buffer that we don't manage!");
708 } else if (entry->bge_inuse == 0) {
709 panic("bge_jfree: buffer already free!");
712 * Possible MP race to 0, use the serializer. The atomic insn
713 * is still needed for races against bge_jref().
715 lwkt_serialize_enter(&sc->bge_jslot_serializer);
716 atomic_subtract_int(&entry->bge_inuse, 1);
717 if (entry->bge_inuse == 0) {
718 SLIST_INSERT_HEAD(&sc->bge_jfree_listhead,
721 lwkt_serialize_exit(&sc->bge_jslot_serializer);
727 * Intialize a standard receive ring descriptor.
730 bge_newbuf_std(struct bge_softc *sc, int i, struct mbuf *m)
732 struct mbuf *m_new = NULL;
736 m_new = m_getcl(MB_DONTWAIT, MT_DATA, M_PKTHDR);
739 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
742 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES;
743 m_new->m_data = m_new->m_ext.ext_buf;
746 if (!sc->bge_rx_alignment_bug)
747 m_adj(m_new, ETHER_ALIGN);
748 sc->bge_cdata.bge_rx_std_chain[i] = m_new;
749 r = &sc->bge_rdata->bge_rx_std_ring[i];
750 BGE_HOSTADDR(r->bge_addr, vtophys(mtod(m_new, caddr_t)));
751 r->bge_flags = BGE_RXBDFLAG_END;
752 r->bge_len = m_new->m_len;
759 * Initialize a jumbo receive ring descriptor. This allocates
760 * a jumbo buffer from the pool managed internally by the driver.
763 bge_newbuf_jumbo(struct bge_softc *sc, int i, struct mbuf *m)
765 struct mbuf *m_new = NULL;
769 struct bge_jslot *buf;
771 /* Allocate the mbuf. */
772 MGETHDR(m_new, MB_DONTWAIT, MT_DATA);
776 /* Allocate the jumbo buffer */
777 buf = bge_jalloc(sc);
780 if_printf(&sc->arpcom.ac_if, "jumbo allocation failed "
781 "-- packet dropped!\n");
785 /* Attach the buffer to the mbuf. */
786 m_new->m_ext.ext_arg = buf;
787 m_new->m_ext.ext_buf = buf->bge_buf;
788 m_new->m_ext.ext_free = bge_jfree;
789 m_new->m_ext.ext_ref = bge_jref;
790 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
792 m_new->m_data = m_new->m_ext.ext_buf;
793 m_new->m_flags |= M_EXT;
794 m_new->m_len = m_new->m_pkthdr.len = m_new->m_ext.ext_size;
797 m_new->m_data = m_new->m_ext.ext_buf;
798 m_new->m_ext.ext_size = BGE_JUMBO_FRAMELEN;
801 if (!sc->bge_rx_alignment_bug)
802 m_adj(m_new, ETHER_ALIGN);
803 /* Set up the descriptor. */
804 r = &sc->bge_rdata->bge_rx_jumbo_ring[i];
805 sc->bge_cdata.bge_rx_jumbo_chain[i] = m_new;
806 BGE_HOSTADDR(r->bge_addr, vtophys(mtod(m_new, caddr_t)));
807 r->bge_flags = BGE_RXBDFLAG_END|BGE_RXBDFLAG_JUMBO_RING;
808 r->bge_len = m_new->m_len;
815 * The standard receive ring has 512 entries in it. At 2K per mbuf cluster,
816 * that's 1MB or memory, which is a lot. For now, we fill only the first
817 * 256 ring entries and hope that our CPU is fast enough to keep up with
821 bge_init_rx_ring_std(struct bge_softc *sc)
825 for (i = 0; i < BGE_SSLOTS; i++) {
826 if (bge_newbuf_std(sc, i, NULL) == ENOBUFS)
831 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
837 bge_free_rx_ring_std(struct bge_softc *sc)
841 for (i = 0; i < BGE_STD_RX_RING_CNT; i++) {
842 if (sc->bge_cdata.bge_rx_std_chain[i] != NULL) {
843 m_freem(sc->bge_cdata.bge_rx_std_chain[i]);
844 sc->bge_cdata.bge_rx_std_chain[i] = NULL;
846 bzero(&sc->bge_rdata->bge_rx_std_ring[i],
847 sizeof(struct bge_rx_bd));
852 bge_init_rx_ring_jumbo(struct bge_softc *sc)
857 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
858 if (bge_newbuf_jumbo(sc, i, NULL) == ENOBUFS)
862 sc->bge_jumbo = i - 1;
864 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb;
865 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(0, 0);
866 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
868 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
874 bge_free_rx_ring_jumbo(struct bge_softc *sc)
878 for (i = 0; i < BGE_JUMBO_RX_RING_CNT; i++) {
879 if (sc->bge_cdata.bge_rx_jumbo_chain[i] != NULL) {
880 m_freem(sc->bge_cdata.bge_rx_jumbo_chain[i]);
881 sc->bge_cdata.bge_rx_jumbo_chain[i] = NULL;
883 bzero(&sc->bge_rdata->bge_rx_jumbo_ring[i],
884 sizeof(struct bge_rx_bd));
889 bge_free_tx_ring(struct bge_softc *sc)
893 if (sc->bge_rdata->bge_tx_ring == NULL)
896 for (i = 0; i < BGE_TX_RING_CNT; i++) {
897 if (sc->bge_cdata.bge_tx_chain[i] != NULL) {
898 m_freem(sc->bge_cdata.bge_tx_chain[i]);
899 sc->bge_cdata.bge_tx_chain[i] = NULL;
901 bzero(&sc->bge_rdata->bge_tx_ring[i],
902 sizeof(struct bge_tx_bd));
907 bge_init_tx_ring(struct bge_softc *sc)
910 sc->bge_tx_saved_considx = 0;
912 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0);
914 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
915 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, 0);
917 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
919 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
920 CSR_WRITE_4(sc, BGE_MBX_TX_NIC_PROD0_LO, 0);
926 bge_setmulti(struct bge_softc *sc)
929 struct ifmultiaddr *ifma;
930 uint32_t hashes[4] = { 0, 0, 0, 0 };
933 ifp = &sc->arpcom.ac_if;
935 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) {
936 for (i = 0; i < 4; i++)
937 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0xFFFFFFFF);
941 /* First, zot all the existing filters. */
942 for (i = 0; i < 4; i++)
943 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), 0);
945 /* Now program new ones. */
946 LIST_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
947 if (ifma->ifma_addr->sa_family != AF_LINK)
950 LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
951 ETHER_ADDR_LEN) & 0x7f;
952 hashes[(h & 0x60) >> 5] |= 1 << (h & 0x1F);
955 for (i = 0; i < 4; i++)
956 CSR_WRITE_4(sc, BGE_MAR0 + (i * 4), hashes[i]);
960 * Do endian, PCI and DMA initialization. Also check the on-board ROM
964 bge_chipinit(struct bge_softc *sc)
969 /* Set endianness before we access any non-PCI registers. */
970 #if BYTE_ORDER == BIG_ENDIAN
971 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL,
972 BGE_BIGENDIAN_INIT, 4);
974 pci_write_config(sc->bge_dev, BGE_PCI_MISC_CTL,
975 BGE_LITTLEENDIAN_INIT, 4);
979 * Check the 'ROM failed' bit on the RX CPU to see if
982 if (CSR_READ_4(sc, BGE_RXCPU_MODE) & BGE_RXCPUMODE_ROMFAIL) {
983 if_printf(&sc->arpcom.ac_if,
984 "RX CPU self-diagnostics failed!\n");
988 /* Clear the MAC control register */
989 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
992 * Clear the MAC statistics block in the NIC's
995 for (i = BGE_STATS_BLOCK;
996 i < BGE_STATS_BLOCK_END + 1; i += sizeof(uint32_t))
997 BGE_MEMWIN_WRITE(sc, i, 0);
999 for (i = BGE_STATUS_BLOCK;
1000 i < BGE_STATUS_BLOCK_END + 1; i += sizeof(uint32_t))
1001 BGE_MEMWIN_WRITE(sc, i, 0);
1003 /* Set up the PCI DMA control register. */
1006 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1007 (0xf << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1008 (0x2 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1009 } else if (pci_read_config(sc->bge_dev, BGE_PCI_PCISTATE, 4) &
1010 BGE_PCISTATE_PCI_BUSMODE) {
1011 /* Conventional PCI bus */
1012 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1013 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1014 (0x7 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1019 * The 5704 uses a different encoding of read/write
1022 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1023 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1024 (0x7 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1025 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT);
1027 dma_rw_ctl = BGE_PCI_READ_CMD|BGE_PCI_WRITE_CMD |
1028 (0x3 << BGE_PCIDMARWCTL_RD_WAT_SHIFT) |
1029 (0x3 << BGE_PCIDMARWCTL_WR_WAT_SHIFT) |
1033 * 5703 and 5704 need ONEDMA_AT_ONCE as a workaround
1034 * for hardware bugs.
1036 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1037 sc->bge_asicrev == BGE_ASICREV_BCM5704) {
1040 tmp = CSR_READ_4(sc, BGE_PCI_CLKCTL) & 0x1f;
1041 if (tmp == 0x6 || tmp == 0x7)
1042 dma_rw_ctl |= BGE_PCIDMARWCTL_ONEDMA_ATONCE;
1046 if (sc->bge_asicrev == BGE_ASICREV_BCM5703 ||
1047 sc->bge_asicrev == BGE_ASICREV_BCM5704 ||
1048 sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
1049 sc->bge_asicrev == BGE_ASICREV_BCM5750)
1050 dma_rw_ctl &= ~BGE_PCIDMARWCTL_MINDMA;
1051 pci_write_config(sc->bge_dev, BGE_PCI_DMA_RW_CTL, dma_rw_ctl, 4);
1054 * Set up general mode register.
1056 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_WORDSWAP_NONFRAME|
1057 BGE_MODECTL_BYTESWAP_DATA|BGE_MODECTL_WORDSWAP_DATA|
1058 BGE_MODECTL_MAC_ATTN_INTR|BGE_MODECTL_HOST_SEND_BDS|
1059 BGE_MODECTL_TX_NO_PHDR_CSUM|BGE_MODECTL_RX_NO_PHDR_CSUM);
1062 * Disable memory write invalidate. Apparently it is not supported
1063 * properly by these devices.
1065 PCI_CLRBIT(sc->bge_dev, BGE_PCI_CMD, PCIM_CMD_MWIEN, 4);
1067 /* Set the timer prescaler (always 66Mhz) */
1068 CSR_WRITE_4(sc, BGE_MISC_CFG, 65 << 1/*BGE_32BITTIME_66MHZ*/);
1074 bge_blockinit(struct bge_softc *sc)
1076 struct bge_rcb *rcb;
1077 volatile struct bge_rcb *vrcb;
1081 * Initialize the memory window pointer register so that
1082 * we can access the first 32K of internal NIC RAM. This will
1083 * allow us to set up the TX send ring RCBs and the RX return
1084 * ring RCBs, plus other things which live in NIC memory.
1086 CSR_WRITE_4(sc, BGE_PCI_MEMWIN_BASEADDR, 0);
1088 /* Note: the BCM5704 has a smaller mbuf space than other chips. */
1090 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1091 sc->bge_asicrev != BGE_ASICREV_BCM5750) {
1092 /* Configure mbuf memory pool */
1093 if (sc->bge_extram) {
1094 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR,
1096 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1097 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1099 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1101 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_BASEADDR,
1103 if (sc->bge_asicrev == BGE_ASICREV_BCM5704)
1104 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x10000);
1106 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_LEN, 0x18000);
1109 /* Configure DMA resource pool */
1110 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_BASEADDR,
1111 BGE_DMA_DESCRIPTORS);
1112 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LEN, 0x2000);
1115 /* Configure mbuf pool watermarks */
1116 if (sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
1117 sc->bge_asicrev == BGE_ASICREV_BCM5750) {
1118 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x0);
1119 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x10);
1121 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_READDMA_LOWAT, 0x50);
1122 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_MACRX_LOWAT, 0x20);
1124 CSR_WRITE_4(sc, BGE_BMAN_MBUFPOOL_HIWAT, 0x60);
1126 /* Configure DMA resource watermarks */
1127 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_LOWAT, 5);
1128 CSR_WRITE_4(sc, BGE_BMAN_DMA_DESCPOOL_HIWAT, 10);
1130 /* Enable buffer manager */
1131 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1132 sc->bge_asicrev != BGE_ASICREV_BCM5750) {
1133 CSR_WRITE_4(sc, BGE_BMAN_MODE,
1134 BGE_BMANMODE_ENABLE|BGE_BMANMODE_LOMBUF_ATTN);
1136 /* Poll for buffer manager start indication */
1137 for (i = 0; i < BGE_TIMEOUT; i++) {
1138 if (CSR_READ_4(sc, BGE_BMAN_MODE) & BGE_BMANMODE_ENABLE)
1143 if (i == BGE_TIMEOUT) {
1144 if_printf(&sc->arpcom.ac_if,
1145 "buffer manager failed to start\n");
1150 /* Enable flow-through queues */
1151 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
1152 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
1154 /* Wait until queue initialization is complete */
1155 for (i = 0; i < BGE_TIMEOUT; i++) {
1156 if (CSR_READ_4(sc, BGE_FTQ_RESET) == 0)
1161 if (i == BGE_TIMEOUT) {
1162 if_printf(&sc->arpcom.ac_if,
1163 "flow-through queue init failed\n");
1167 /* Initialize the standard RX ring control block */
1168 rcb = &sc->bge_rdata->bge_info.bge_std_rx_rcb;
1169 BGE_HOSTADDR(rcb->bge_hostaddr,
1170 vtophys(&sc->bge_rdata->bge_rx_std_ring));
1171 if (sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
1172 sc->bge_asicrev == BGE_ASICREV_BCM5750)
1173 rcb->bge_maxlen_flags = BGE_RCB_MAXLEN_FLAGS(512, 0);
1175 rcb->bge_maxlen_flags =
1176 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN, 0);
1178 rcb->bge_nicaddr = BGE_EXT_STD_RX_RINGS;
1180 rcb->bge_nicaddr = BGE_STD_RX_RINGS;
1181 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_HI, rcb->bge_hostaddr.bge_addr_hi);
1182 CSR_WRITE_4(sc, BGE_RX_STD_RCB_HADDR_LO, rcb->bge_hostaddr.bge_addr_lo);
1183 CSR_WRITE_4(sc, BGE_RX_STD_RCB_MAXLEN_FLAGS, rcb->bge_maxlen_flags);
1184 CSR_WRITE_4(sc, BGE_RX_STD_RCB_NICADDR, rcb->bge_nicaddr);
1187 * Initialize the jumbo RX ring control block
1188 * We set the 'ring disabled' bit in the flags
1189 * field until we're actually ready to start
1190 * using this ring (i.e. once we set the MTU
1191 * high enough to require it).
1193 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1194 sc->bge_asicrev != BGE_ASICREV_BCM5750) {
1195 rcb = &sc->bge_rdata->bge_info.bge_jumbo_rx_rcb;
1196 BGE_HOSTADDR(rcb->bge_hostaddr,
1197 vtophys(&sc->bge_rdata->bge_rx_jumbo_ring));
1198 rcb->bge_maxlen_flags =
1199 BGE_RCB_MAXLEN_FLAGS(BGE_MAX_FRAMELEN,
1200 BGE_RCB_FLAG_RING_DISABLED);
1202 rcb->bge_nicaddr = BGE_EXT_JUMBO_RX_RINGS;
1204 rcb->bge_nicaddr = BGE_JUMBO_RX_RINGS;
1205 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_HI,
1206 rcb->bge_hostaddr.bge_addr_hi);
1207 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_HADDR_LO,
1208 rcb->bge_hostaddr.bge_addr_lo);
1209 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_MAXLEN_FLAGS,
1210 rcb->bge_maxlen_flags);
1211 CSR_WRITE_4(sc, BGE_RX_JUMBO_RCB_NICADDR, rcb->bge_nicaddr);
1213 /* Set up dummy disabled mini ring RCB */
1214 rcb = &sc->bge_rdata->bge_info.bge_mini_rx_rcb;
1215 rcb->bge_maxlen_flags =
1216 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1217 CSR_WRITE_4(sc, BGE_RX_MINI_RCB_MAXLEN_FLAGS,
1218 rcb->bge_maxlen_flags);
1222 * Set the BD ring replentish thresholds. The recommended
1223 * values are 1/8th the number of descriptors allocated to
1226 CSR_WRITE_4(sc, BGE_RBDI_STD_REPL_THRESH, BGE_STD_RX_RING_CNT/8);
1227 CSR_WRITE_4(sc, BGE_RBDI_JUMBO_REPL_THRESH, BGE_JUMBO_RX_RING_CNT/8);
1230 * Disable all unused send rings by setting the 'ring disabled'
1231 * bit in the flags field of all the TX send ring control blocks.
1232 * These are located in NIC memory.
1234 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1236 for (i = 0; i < BGE_TX_RINGS_EXTSSRAM_MAX; i++) {
1237 vrcb->bge_maxlen_flags =
1238 BGE_RCB_MAXLEN_FLAGS(0, BGE_RCB_FLAG_RING_DISABLED);
1239 vrcb->bge_nicaddr = 0;
1243 /* Configure TX RCB 0 (we use only the first ring) */
1244 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1246 vrcb->bge_hostaddr.bge_addr_hi = 0;
1247 BGE_HOSTADDR(vrcb->bge_hostaddr, vtophys(&sc->bge_rdata->bge_tx_ring));
1248 vrcb->bge_nicaddr = BGE_NIC_TXRING_ADDR(0, BGE_TX_RING_CNT);
1249 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1250 sc->bge_asicrev != BGE_ASICREV_BCM5750)
1251 vrcb->bge_maxlen_flags =
1252 BGE_RCB_MAXLEN_FLAGS(BGE_TX_RING_CNT, 0);
1254 /* Disable all unused RX return rings */
1255 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1256 BGE_RX_RETURN_RING_RCB);
1257 for (i = 0; i < BGE_RX_RINGS_MAX; i++) {
1258 vrcb->bge_hostaddr.bge_addr_hi = 0;
1259 vrcb->bge_hostaddr.bge_addr_lo = 0;
1260 vrcb->bge_maxlen_flags =
1261 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt,
1262 BGE_RCB_FLAG_RING_DISABLED);
1263 vrcb->bge_nicaddr = 0;
1264 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO +
1265 (i * (sizeof(uint64_t))), 0);
1269 /* Initialize RX ring indexes */
1270 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, 0);
1271 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, 0);
1272 CSR_WRITE_4(sc, BGE_MBX_RX_MINI_PROD_LO, 0);
1275 * Set up RX return ring 0
1276 * Note that the NIC address for RX return rings is 0x00000000.
1277 * The return rings live entirely within the host, so the
1278 * nicaddr field in the RCB isn't used.
1280 vrcb = (volatile struct bge_rcb *)(sc->bge_vhandle + BGE_MEMWIN_START +
1281 BGE_RX_RETURN_RING_RCB);
1282 vrcb->bge_hostaddr.bge_addr_hi = 0;
1283 BGE_HOSTADDR(vrcb->bge_hostaddr,
1284 vtophys(&sc->bge_rdata->bge_rx_return_ring));
1285 vrcb->bge_nicaddr = 0x00000000;
1286 vrcb->bge_maxlen_flags =
1287 BGE_RCB_MAXLEN_FLAGS(sc->bge_return_ring_cnt, 0);
1289 /* Set random backoff seed for TX */
1290 CSR_WRITE_4(sc, BGE_TX_RANDOM_BACKOFF,
1291 sc->arpcom.ac_enaddr[0] + sc->arpcom.ac_enaddr[1] +
1292 sc->arpcom.ac_enaddr[2] + sc->arpcom.ac_enaddr[3] +
1293 sc->arpcom.ac_enaddr[4] + sc->arpcom.ac_enaddr[5] +
1294 BGE_TX_BACKOFF_SEED_MASK);
1296 /* Set inter-packet gap */
1297 CSR_WRITE_4(sc, BGE_TX_LENGTHS, 0x2620);
1300 * Specify which ring to use for packets that don't match
1303 CSR_WRITE_4(sc, BGE_RX_RULES_CFG, 0x08);
1306 * Configure number of RX lists. One interrupt distribution
1307 * list, sixteen active lists, one bad frames class.
1309 CSR_WRITE_4(sc, BGE_RXLP_CFG, 0x181);
1311 /* Inialize RX list placement stats mask. */
1312 CSR_WRITE_4(sc, BGE_RXLP_STATS_ENABLE_MASK, 0x007FFFFF);
1313 CSR_WRITE_4(sc, BGE_RXLP_STATS_CTL, 0x1);
1315 /* Disable host coalescing until we get it set up */
1316 CSR_WRITE_4(sc, BGE_HCC_MODE, 0x00000000);
1318 /* Poll to make sure it's shut down. */
1319 for (i = 0; i < BGE_TIMEOUT; i++) {
1320 if (!(CSR_READ_4(sc, BGE_HCC_MODE) & BGE_HCCMODE_ENABLE))
1325 if (i == BGE_TIMEOUT) {
1326 if_printf(&sc->arpcom.ac_if,
1327 "host coalescing engine failed to idle\n");
1331 /* Set up host coalescing defaults */
1332 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS, sc->bge_rx_coal_ticks);
1333 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS, sc->bge_tx_coal_ticks);
1334 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS, sc->bge_rx_max_coal_bds);
1335 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS, sc->bge_tx_max_coal_bds);
1336 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1337 sc->bge_asicrev != BGE_ASICREV_BCM5750) {
1338 CSR_WRITE_4(sc, BGE_HCC_RX_COAL_TICKS_INT, 0);
1339 CSR_WRITE_4(sc, BGE_HCC_TX_COAL_TICKS_INT, 0);
1341 CSR_WRITE_4(sc, BGE_HCC_RX_MAX_COAL_BDS_INT, 0);
1342 CSR_WRITE_4(sc, BGE_HCC_TX_MAX_COAL_BDS_INT, 0);
1344 /* Set up address of statistics block */
1345 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1346 sc->bge_asicrev != BGE_ASICREV_BCM5750) {
1347 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_HI, 0);
1348 CSR_WRITE_4(sc, BGE_HCC_STATS_ADDR_LO,
1349 vtophys(&sc->bge_rdata->bge_info.bge_stats));
1351 CSR_WRITE_4(sc, BGE_HCC_STATS_BASEADDR, BGE_STATS_BLOCK);
1352 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_BASEADDR, BGE_STATUS_BLOCK);
1353 CSR_WRITE_4(sc, BGE_HCC_STATS_TICKS, sc->bge_stat_ticks);
1356 /* Set up address of status block */
1357 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_HI, 0);
1358 CSR_WRITE_4(sc, BGE_HCC_STATUSBLK_ADDR_LO,
1359 vtophys(&sc->bge_rdata->bge_status_block));
1361 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx = 0;
1362 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx = 0;
1364 /* Turn on host coalescing state machine */
1365 CSR_WRITE_4(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
1367 /* Turn on RX BD completion state machine and enable attentions */
1368 CSR_WRITE_4(sc, BGE_RBDC_MODE,
1369 BGE_RBDCMODE_ENABLE|BGE_RBDCMODE_ATTN);
1371 /* Turn on RX list placement state machine */
1372 CSR_WRITE_4(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
1374 /* Turn on RX list selector state machine. */
1375 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1376 sc->bge_asicrev != BGE_ASICREV_BCM5750)
1377 CSR_WRITE_4(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
1379 /* Turn on DMA, clear stats */
1380 CSR_WRITE_4(sc, BGE_MAC_MODE, BGE_MACMODE_TXDMA_ENB|
1381 BGE_MACMODE_RXDMA_ENB|BGE_MACMODE_RX_STATS_CLEAR|
1382 BGE_MACMODE_TX_STATS_CLEAR|BGE_MACMODE_RX_STATS_ENB|
1383 BGE_MACMODE_TX_STATS_ENB|BGE_MACMODE_FRMHDR_DMA_ENB|
1384 (sc->bge_tbi ? BGE_PORTMODE_TBI : BGE_PORTMODE_MII));
1386 /* Set misc. local control, enable interrupts on attentions */
1387 CSR_WRITE_4(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_INTR_ONATTN);
1390 /* Assert GPIO pins for PHY reset */
1391 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUT0|
1392 BGE_MLC_MISCIO_OUT1|BGE_MLC_MISCIO_OUT2);
1393 BGE_SETBIT(sc, BGE_MISC_LOCAL_CTL, BGE_MLC_MISCIO_OUTEN0|
1394 BGE_MLC_MISCIO_OUTEN1|BGE_MLC_MISCIO_OUTEN2);
1397 /* Turn on DMA completion state machine */
1398 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1399 sc->bge_asicrev != BGE_ASICREV_BCM5750)
1400 CSR_WRITE_4(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
1402 /* Turn on write DMA state machine */
1403 CSR_WRITE_4(sc, BGE_WDMA_MODE,
1404 BGE_WDMAMODE_ENABLE|BGE_WDMAMODE_ALL_ATTNS);
1406 /* Turn on read DMA state machine */
1407 CSR_WRITE_4(sc, BGE_RDMA_MODE,
1408 BGE_RDMAMODE_ENABLE|BGE_RDMAMODE_ALL_ATTNS);
1410 /* Turn on RX data completion state machine */
1411 CSR_WRITE_4(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
1413 /* Turn on RX BD initiator state machine */
1414 CSR_WRITE_4(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
1416 /* Turn on RX data and RX BD initiator state machine */
1417 CSR_WRITE_4(sc, BGE_RDBDI_MODE, BGE_RDBDIMODE_ENABLE);
1419 /* Turn on Mbuf cluster free state machine */
1420 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1421 sc->bge_asicrev != BGE_ASICREV_BCM5750)
1422 CSR_WRITE_4(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
1424 /* Turn on send BD completion state machine */
1425 CSR_WRITE_4(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
1427 /* Turn on send data completion state machine */
1428 CSR_WRITE_4(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
1430 /* Turn on send data initiator state machine */
1431 CSR_WRITE_4(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
1433 /* Turn on send BD initiator state machine */
1434 CSR_WRITE_4(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
1436 /* Turn on send BD selector state machine */
1437 CSR_WRITE_4(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
1439 CSR_WRITE_4(sc, BGE_SDI_STATS_ENABLE_MASK, 0x007FFFFF);
1440 CSR_WRITE_4(sc, BGE_SDI_STATS_CTL,
1441 BGE_SDISTATSCTL_ENABLE|BGE_SDISTATSCTL_FASTER);
1443 /* ack/clear link change events */
1444 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
1445 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
1446 BGE_MACSTAT_LINK_CHANGED);
1448 /* Enable PHY auto polling (for MII/GMII only) */
1450 CSR_WRITE_4(sc, BGE_MI_STS, BGE_MISTS_LINK);
1452 BGE_SETBIT(sc, BGE_MI_MODE, BGE_MIMODE_AUTOPOLL|10<<16);
1453 if (sc->bge_asicrev == BGE_ASICREV_BCM5700)
1454 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
1455 BGE_EVTENB_MI_INTERRUPT);
1458 /* Enable link state change attentions. */
1459 BGE_SETBIT(sc, BGE_MAC_EVT_ENB, BGE_EVTENB_LINK_CHANGED);
1465 * Probe for a Broadcom chip. Check the PCI vendor and device IDs
1466 * against our list and return its name if we find a match. Note
1467 * that since the Broadcom controller contains VPD support, we
1468 * can get the device name string from the controller itself instead
1469 * of the compiled-in string. This is a little slow, but it guarantees
1470 * we'll always announce the right product name.
1473 bge_probe(device_t dev)
1475 struct bge_softc *sc;
1478 uint16_t product, vendor;
1480 product = pci_get_device(dev);
1481 vendor = pci_get_vendor(dev);
1483 for (t = bge_devs; t->bge_name != NULL; t++) {
1484 if (vendor == t->bge_vid && product == t->bge_did)
1488 if (t->bge_name == NULL)
1491 sc = device_get_softc(dev);
1496 device_set_desc(dev, sc->bge_vpd_prodname);
1498 descbuf = malloc(BGE_DEVDESC_MAX, M_TEMP, M_WAITOK);
1499 snprintf(descbuf, BGE_DEVDESC_MAX, "%s, ASIC rev. %#04x", t->bge_name,
1500 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) >> 16);
1501 device_set_desc_copy(dev, descbuf);
1502 if (pci_get_subvendor(dev) == PCI_VENDOR_DELL)
1503 sc->bge_no_3_led = 1;
1504 free(descbuf, M_TEMP);
1509 bge_attach(device_t dev)
1512 struct bge_softc *sc;
1514 uint32_t mac_addr = 0;
1516 uint8_t ether_addr[ETHER_ADDR_LEN];
1518 sc = device_get_softc(dev);
1520 callout_init(&sc->bge_stat_timer);
1521 lwkt_serialize_init(&sc->bge_jslot_serializer);
1524 * Map control/status registers.
1526 pci_enable_busmaster(dev);
1529 sc->bge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
1532 if (sc->bge_res == NULL) {
1533 device_printf(dev, "couldn't map memory\n");
1538 sc->bge_btag = rman_get_bustag(sc->bge_res);
1539 sc->bge_bhandle = rman_get_bushandle(sc->bge_res);
1540 sc->bge_vhandle = (vm_offset_t)rman_get_virtual(sc->bge_res);
1542 /* Allocate interrupt */
1545 sc->bge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
1546 RF_SHAREABLE | RF_ACTIVE);
1548 if (sc->bge_irq == NULL) {
1549 device_printf(dev, "couldn't map interrupt\n");
1554 /* Save ASIC rev. */
1556 pci_read_config(dev, BGE_PCI_MISC_CTL, 4) &
1557 BGE_PCIMISCCTL_ASICREV;
1558 sc->bge_asicrev = BGE_ASICREV(sc->bge_chipid);
1559 sc->bge_chiprev = BGE_CHIPREV(sc->bge_chipid);
1562 * Treat the 5714 like the 5750 until we have more info
1565 if (sc->bge_asicrev == BGE_ASICREV_BCM5714)
1566 sc->bge_asicrev = BGE_ASICREV_BCM5750;
1569 * XXX: Broadcom Linux driver. Not in specs or eratta.
1572 if (sc->bge_asicrev == BGE_ASICREV_BCM5750) {
1575 v = pci_read_config(dev, BGE_PCI_MSI_CAPID, 4);
1576 if (((v >> 8) & 0xff) == BGE_PCIE_MSI_CAPID) {
1577 v = pci_read_config(dev, BGE_PCIE_MSI_CAPID, 4);
1578 if ((v & 0xff) == BGE_PCIE_MSI_CAPID_VAL)
1583 ifp = &sc->arpcom.ac_if;
1584 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1586 /* Try to reset the chip. */
1589 if (bge_chipinit(sc)) {
1590 device_printf(dev, "chip initialization failed\n");
1596 * Get station address from the EEPROM.
1598 mac_addr = bge_readmem_ind(sc, 0x0c14);
1599 if ((mac_addr >> 16) == 0x484b) {
1600 ether_addr[0] = (uint8_t)(mac_addr >> 8);
1601 ether_addr[1] = (uint8_t)mac_addr;
1602 mac_addr = bge_readmem_ind(sc, 0x0c18);
1603 ether_addr[2] = (uint8_t)(mac_addr >> 24);
1604 ether_addr[3] = (uint8_t)(mac_addr >> 16);
1605 ether_addr[4] = (uint8_t)(mac_addr >> 8);
1606 ether_addr[5] = (uint8_t)mac_addr;
1607 } else if (bge_read_eeprom(sc, ether_addr,
1608 BGE_EE_MAC_OFFSET + 2, ETHER_ADDR_LEN)) {
1609 device_printf(dev, "failed to read station address\n");
1614 /* Allocate the general information block and ring buffers. */
1615 sc->bge_rdata = contigmalloc(sizeof(struct bge_ring_data), M_DEVBUF,
1616 M_WAITOK, 0, 0xffffffff, PAGE_SIZE, 0);
1618 if (sc->bge_rdata == NULL) {
1620 device_printf(dev, "no memory for list buffers!\n");
1624 bzero(sc->bge_rdata, sizeof(struct bge_ring_data));
1627 * Try to allocate memory for jumbo buffers.
1628 * The 5705/5750 does not appear to support jumbo frames.
1630 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1631 sc->bge_asicrev != BGE_ASICREV_BCM5750) {
1632 if (bge_alloc_jumbo_mem(sc)) {
1633 device_printf(dev, "jumbo buffer allocation failed\n");
1639 /* Set default tuneable values. */
1640 sc->bge_stat_ticks = BGE_TICKS_PER_SEC;
1641 sc->bge_rx_coal_ticks = 150;
1642 sc->bge_tx_coal_ticks = 150;
1643 sc->bge_rx_max_coal_bds = 64;
1644 sc->bge_tx_max_coal_bds = 128;
1646 /* 5705/5750 limits RX return ring to 512 entries. */
1647 if (sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
1648 sc->bge_asicrev == BGE_ASICREV_BCM5750)
1649 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT_5705;
1651 sc->bge_return_ring_cnt = BGE_RETURN_RING_CNT;
1653 /* Set up ifnet structure */
1655 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1656 ifp->if_ioctl = bge_ioctl;
1657 ifp->if_start = bge_start;
1658 ifp->if_watchdog = bge_watchdog;
1659 ifp->if_init = bge_init;
1660 ifp->if_mtu = ETHERMTU;
1661 ifq_set_maxlen(&ifp->if_snd, BGE_TX_RING_CNT - 1);
1662 ifq_set_ready(&ifp->if_snd);
1663 ifp->if_hwassist = BGE_CSUM_FEATURES;
1664 ifp->if_capabilities = IFCAP_HWCSUM;
1665 ifp->if_capenable = ifp->if_capabilities;
1668 * Figure out what sort of media we have by checking the
1669 * hardware config word in the first 32k of NIC internal memory,
1670 * or fall back to examining the EEPROM if necessary.
1671 * Note: on some BCM5700 cards, this value appears to be unset.
1672 * If that's the case, we have to rely on identifying the NIC
1673 * by its PCI subsystem ID, as we do below for the SysKonnect
1676 if (bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_SIG) == BGE_MAGIC_NUMBER)
1677 hwcfg = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM_NICCFG);
1679 bge_read_eeprom(sc, (caddr_t)&hwcfg,
1680 BGE_EE_HWCFG_OFFSET, sizeof(hwcfg));
1681 hwcfg = ntohl(hwcfg);
1684 if ((hwcfg & BGE_HWCFG_MEDIA) == BGE_MEDIA_FIBER)
1687 /* The SysKonnect SK-9D41 is a 1000baseSX card. */
1688 if (pci_get_subvendor(dev) == PCI_PRODUCT_SCHNEIDERKOCH_SK_9D41)
1692 ifmedia_init(&sc->bge_ifmedia, IFM_IMASK,
1693 bge_ifmedia_upd, bge_ifmedia_sts);
1694 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_1000_SX, 0, NULL);
1695 ifmedia_add(&sc->bge_ifmedia,
1696 IFM_ETHER|IFM_1000_SX|IFM_FDX, 0, NULL);
1697 ifmedia_add(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO, 0, NULL);
1698 ifmedia_set(&sc->bge_ifmedia, IFM_ETHER|IFM_AUTO);
1699 sc->bge_ifmedia.ifm_media = sc->bge_ifmedia.ifm_cur->ifm_media;
1702 * Do transceiver setup.
1704 if (mii_phy_probe(dev, &sc->bge_miibus,
1705 bge_ifmedia_upd, bge_ifmedia_sts)) {
1706 device_printf(dev, "MII without any PHY!\n");
1713 * When using the BCM5701 in PCI-X mode, data corruption has
1714 * been observed in the first few bytes of some received packets.
1715 * Aligning the packet buffer in memory eliminates the corruption.
1716 * Unfortunately, this misaligns the packet payloads. On platforms
1717 * which do not support unaligned accesses, we will realign the
1718 * payloads by copying the received packets.
1720 switch (sc->bge_chipid) {
1721 case BGE_CHIPID_BCM5701_A0:
1722 case BGE_CHIPID_BCM5701_B0:
1723 case BGE_CHIPID_BCM5701_B2:
1724 case BGE_CHIPID_BCM5701_B5:
1725 /* If in PCI-X mode, work around the alignment bug. */
1726 if ((pci_read_config(dev, BGE_PCI_PCISTATE, 4) &
1727 (BGE_PCISTATE_PCI_BUSMODE | BGE_PCISTATE_PCI_BUSSPEED)) ==
1728 BGE_PCISTATE_PCI_BUSSPEED)
1729 sc->bge_rx_alignment_bug = 1;
1734 * Call MI attach routine.
1736 ether_ifattach(ifp, ether_addr, NULL);
1738 error = bus_setup_intr(dev, sc->bge_irq, INTR_NETSAFE,
1739 bge_intr, sc, &sc->bge_intrhand,
1740 ifp->if_serializer);
1742 ether_ifdetach(ifp);
1743 device_printf(dev, "couldn't set up irq\n");
1756 bge_detach(device_t dev)
1758 struct bge_softc *sc = device_get_softc(dev);
1759 struct ifnet *ifp = &sc->arpcom.ac_if;
1761 lwkt_serialize_enter(ifp->if_serializer);
1763 if (device_is_attached(dev)) {
1764 ether_ifdetach(ifp);
1770 ifmedia_removeall(&sc->bge_ifmedia);
1771 if (sc->bge_miibus);
1772 device_delete_child(dev, sc->bge_miibus);
1773 bus_generic_detach(dev);
1775 bge_release_resources(sc);
1777 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
1778 sc->bge_asicrev != BGE_ASICREV_BCM5750)
1779 bge_free_jumbo_mem(sc);
1781 lwkt_serialize_exit(ifp->if_serializer);
1787 bge_release_resources(struct bge_softc *sc)
1793 if (sc->bge_vpd_prodname != NULL)
1794 free(sc->bge_vpd_prodname, M_DEVBUF);
1796 if (sc->bge_vpd_readonly != NULL)
1797 free(sc->bge_vpd_readonly, M_DEVBUF);
1799 if (sc->bge_intrhand != NULL)
1800 bus_teardown_intr(dev, sc->bge_irq, sc->bge_intrhand);
1802 if (sc->bge_irq != NULL)
1803 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->bge_irq);
1805 if (sc->bge_res != NULL)
1806 bus_release_resource(dev, SYS_RES_MEMORY,
1807 BGE_PCI_BAR0, sc->bge_res);
1809 if (sc->bge_rdata != NULL)
1810 contigfree(sc->bge_rdata, sizeof(struct bge_ring_data),
1817 bge_reset(struct bge_softc *sc)
1820 uint32_t cachesize, command, pcistate, reset;
1825 /* Save some important PCI state. */
1826 cachesize = pci_read_config(dev, BGE_PCI_CACHESZ, 4);
1827 command = pci_read_config(dev, BGE_PCI_CMD, 4);
1828 pcistate = pci_read_config(dev, BGE_PCI_PCISTATE, 4);
1830 pci_write_config(dev, BGE_PCI_MISC_CTL,
1831 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
1832 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4);
1834 reset = BGE_MISCCFG_RESET_CORE_CLOCKS|(65<<1);
1836 /* XXX: Broadcom Linux driver. */
1838 if (CSR_READ_4(sc, 0x7e2c) == 0x60) /* PCIE 1.0 */
1839 CSR_WRITE_4(sc, 0x7e2c, 0x20);
1840 if (sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
1841 /* Prevent PCIE link training during global reset */
1842 CSR_WRITE_4(sc, BGE_MISC_CFG, (1<<29));
1847 /* Issue global reset */
1848 bge_writereg_ind(sc, BGE_MISC_CFG, reset);
1852 /* XXX: Broadcom Linux driver. */
1854 if (sc->bge_chipid == BGE_CHIPID_BCM5750_A0) {
1857 DELAY(500000); /* wait for link training to complete */
1858 v = pci_read_config(dev, 0xc4, 4);
1859 pci_write_config(dev, 0xc4, v | (1<<15), 4);
1861 /* Set PCIE max payload size and clear error status. */
1862 pci_write_config(dev, 0xd8, 0xf5000, 4);
1865 /* Reset some of the PCI state that got zapped by reset */
1866 pci_write_config(dev, BGE_PCI_MISC_CTL,
1867 BGE_PCIMISCCTL_INDIRECT_ACCESS|BGE_PCIMISCCTL_MASK_PCI_INTR|
1868 BGE_PCIMISCCTL_ENDIAN_WORDSWAP|BGE_PCIMISCCTL_PCISTATE_RW, 4);
1869 pci_write_config(dev, BGE_PCI_CACHESZ, cachesize, 4);
1870 pci_write_config(dev, BGE_PCI_CMD, command, 4);
1871 bge_writereg_ind(sc, BGE_MISC_CFG, (65 << 1));
1873 /* Enable memory arbiter. */
1874 if (sc->bge_asicrev != BGE_ASICREV_BCM5705)
1875 CSR_WRITE_4(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
1878 * Prevent PXE restart: write a magic number to the
1879 * general communications memory at 0xB50.
1881 bge_writemem_ind(sc, BGE_SOFTWARE_GENCOMM, BGE_MAGIC_NUMBER);
1883 * Poll the value location we just wrote until
1884 * we see the 1's complement of the magic number.
1885 * This indicates that the firmware initialization
1888 for (i = 0; i < BGE_TIMEOUT; i++) {
1889 val = bge_readmem_ind(sc, BGE_SOFTWARE_GENCOMM);
1890 if (val == ~BGE_MAGIC_NUMBER)
1895 if (i == BGE_TIMEOUT) {
1896 if_printf(&sc->arpcom.ac_if, "firmware handshake timed out\n");
1901 * XXX Wait for the value of the PCISTATE register to
1902 * return to its original pre-reset state. This is a
1903 * fairly good indicator of reset completion. If we don't
1904 * wait for the reset to fully complete, trying to read
1905 * from the device's non-PCI registers may yield garbage
1908 for (i = 0; i < BGE_TIMEOUT; i++) {
1909 if (pci_read_config(dev, BGE_PCI_PCISTATE, 4) == pcistate)
1914 /* Fix up byte swapping */
1915 CSR_WRITE_4(sc, BGE_MODE_CTL, BGE_MODECTL_BYTESWAP_NONFRAME|
1916 BGE_MODECTL_BYTESWAP_DATA);
1918 CSR_WRITE_4(sc, BGE_MAC_MODE, 0);
1921 * The 5704 in TBI mode apparently needs some special
1922 * adjustment to insure the SERDES drive level is set
1925 if (sc->bge_asicrev == BGE_ASICREV_BCM5704 && sc->bge_tbi) {
1928 serdescfg = CSR_READ_4(sc, BGE_SERDES_CFG);
1929 serdescfg = (serdescfg & ~0xFFF) | 0x880;
1930 CSR_WRITE_4(sc, BGE_SERDES_CFG, serdescfg);
1933 /* XXX: Broadcom Linux driver. */
1934 if (sc->bge_pcie && sc->bge_chipid != BGE_CHIPID_BCM5750_A0) {
1937 v = CSR_READ_4(sc, 0x7c00);
1938 CSR_WRITE_4(sc, 0x7c00, v | (1<<25));
1945 * Frame reception handling. This is called if there's a frame
1946 * on the receive return list.
1948 * Note: we have to be able to handle two possibilities here:
1949 * 1) the frame is from the jumbo recieve ring
1950 * 2) the frame is from the standard receive ring
1954 bge_rxeof(struct bge_softc *sc)
1957 int stdcnt = 0, jumbocnt = 0;
1959 ifp = &sc->arpcom.ac_if;
1961 while(sc->bge_rx_saved_considx !=
1962 sc->bge_rdata->bge_status_block.bge_idx[0].bge_rx_prod_idx) {
1963 struct bge_rx_bd *cur_rx;
1965 struct mbuf *m = NULL;
1966 uint16_t vlan_tag = 0;
1970 &sc->bge_rdata->bge_rx_return_ring[sc->bge_rx_saved_considx];
1972 rxidx = cur_rx->bge_idx;
1973 BGE_INC(sc->bge_rx_saved_considx, sc->bge_return_ring_cnt);
1975 if (cur_rx->bge_flags & BGE_RXBDFLAG_VLAN_TAG) {
1977 vlan_tag = cur_rx->bge_vlan_tag;
1980 if (cur_rx->bge_flags & BGE_RXBDFLAG_JUMBO_RING) {
1981 BGE_INC(sc->bge_jumbo, BGE_JUMBO_RX_RING_CNT);
1982 m = sc->bge_cdata.bge_rx_jumbo_chain[rxidx];
1983 sc->bge_cdata.bge_rx_jumbo_chain[rxidx] = NULL;
1985 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
1987 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
1990 if (bge_newbuf_jumbo(sc,
1991 sc->bge_jumbo, NULL) == ENOBUFS) {
1993 bge_newbuf_jumbo(sc, sc->bge_jumbo, m);
1997 BGE_INC(sc->bge_std, BGE_STD_RX_RING_CNT);
1998 m = sc->bge_cdata.bge_rx_std_chain[rxidx];
1999 sc->bge_cdata.bge_rx_std_chain[rxidx] = NULL;
2001 if (cur_rx->bge_flags & BGE_RXBDFLAG_ERROR) {
2003 bge_newbuf_std(sc, sc->bge_std, m);
2006 if (bge_newbuf_std(sc, sc->bge_std,
2009 bge_newbuf_std(sc, sc->bge_std, m);
2017 * The i386 allows unaligned accesses, but for other
2018 * platforms we must make sure the payload is aligned.
2020 if (sc->bge_rx_alignment_bug) {
2021 bcopy(m->m_data, m->m_data + ETHER_ALIGN,
2023 m->m_data += ETHER_ALIGN;
2026 m->m_pkthdr.len = m->m_len = cur_rx->bge_len - ETHER_CRC_LEN;
2027 m->m_pkthdr.rcvif = ifp;
2029 #if 0 /* currently broken for some packets, possibly related to TCP options */
2030 if (ifp->if_hwassist) {
2031 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2032 if ((cur_rx->bge_ip_csum ^ 0xffff) == 0)
2033 m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2034 if (cur_rx->bge_flags & BGE_RXBDFLAG_TCP_UDP_CSUM) {
2035 m->m_pkthdr.csum_data =
2036 cur_rx->bge_tcp_udp_csum;
2037 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID;
2043 * If we received a packet with a vlan tag, pass it
2044 * to vlan_input() instead of ether_input().
2047 VLAN_INPUT_TAG(m, vlan_tag);
2048 have_tag = vlan_tag = 0;
2050 ifp->if_input(ifp, m);
2054 CSR_WRITE_4(sc, BGE_MBX_RX_CONS0_LO, sc->bge_rx_saved_considx);
2056 CSR_WRITE_4(sc, BGE_MBX_RX_STD_PROD_LO, sc->bge_std);
2058 CSR_WRITE_4(sc, BGE_MBX_RX_JUMBO_PROD_LO, sc->bge_jumbo);
2062 bge_txeof(struct bge_softc *sc)
2064 struct bge_tx_bd *cur_tx = NULL;
2067 ifp = &sc->arpcom.ac_if;
2070 * Go through our tx ring and free mbufs for those
2071 * frames that have been sent.
2073 while (sc->bge_tx_saved_considx !=
2074 sc->bge_rdata->bge_status_block.bge_idx[0].bge_tx_cons_idx) {
2077 idx = sc->bge_tx_saved_considx;
2078 cur_tx = &sc->bge_rdata->bge_tx_ring[idx];
2079 if (cur_tx->bge_flags & BGE_TXBDFLAG_END)
2081 if (sc->bge_cdata.bge_tx_chain[idx] != NULL) {
2082 m_freem(sc->bge_cdata.bge_tx_chain[idx]);
2083 sc->bge_cdata.bge_tx_chain[idx] = NULL;
2086 BGE_INC(sc->bge_tx_saved_considx, BGE_TX_RING_CNT);
2091 ifp->if_flags &= ~IFF_OACTIVE;
2097 struct bge_softc *sc = xsc;
2098 struct ifnet *ifp = &sc->arpcom.ac_if;
2099 uint32_t status, statusword, mimode;
2102 statusword = loadandclear(&sc->bge_rdata->bge_status_block.bge_status);
2105 /* Avoid this for now -- checking this register is expensive. */
2106 /* Make sure this is really our interrupt. */
2107 if (!(CSR_READ_4(sc, BGE_MISC_LOCAL_CTL) & BGE_MLC_INTR_STATE))
2110 /* Ack interrupt and stop others from occuring. */
2111 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
2114 * Process link state changes.
2115 * Grrr. The link status word in the status block does
2116 * not work correctly on the BCM5700 rev AX and BX chips,
2117 * according to all available information. Hence, we have
2118 * to enable MII interrupts in order to properly obtain
2119 * async link changes. Unfortunately, this also means that
2120 * we have to read the MAC status register to detect link
2121 * changes, thereby adding an additional register access to
2122 * the interrupt handler.
2125 if (sc->bge_asicrev == BGE_ASICREV_BCM5700) {
2126 status = CSR_READ_4(sc, BGE_MAC_STS);
2127 if (status & BGE_MACSTAT_MI_INTERRUPT) {
2129 callout_stop(&sc->bge_stat_timer);
2130 bge_tick_serialized(sc);
2131 /* Clear the interrupt */
2132 CSR_WRITE_4(sc, BGE_MAC_EVT_ENB,
2133 BGE_EVTENB_MI_INTERRUPT);
2134 bge_miibus_readreg(sc->bge_dev, 1, BRGPHY_MII_ISR);
2135 bge_miibus_writereg(sc->bge_dev, 1, BRGPHY_MII_IMR,
2139 if (statusword & BGE_STATFLAG_LINKSTATE_CHANGED) {
2141 * Sometimes PCS encoding errors are detected in
2142 * TBI mode (on fiber NICs), and for some reason
2143 * the chip will signal them as link changes.
2144 * If we get a link change event, but the 'PCS
2145 * encoding error' bit in the MAC status register
2146 * is set, don't bother doing a link check.
2147 * This avoids spurious "gigabit link up" messages
2148 * that sometimes appear on fiber NICs during
2149 * periods of heavy traffic. (There should be no
2150 * effect on copper NICs.)
2152 * If we do have a copper NIC (bge_tbi == 0) then
2153 * check that the AUTOPOLL bit is set before
2154 * processing the event as a real link change.
2155 * Turning AUTOPOLL on and off in the MII read/write
2156 * functions will often trigger a link status
2157 * interrupt for no reason.
2159 status = CSR_READ_4(sc, BGE_MAC_STS);
2160 mimode = CSR_READ_4(sc, BGE_MI_MODE);
2161 if (!(status & (BGE_MACSTAT_PORT_DECODE_ERROR |
2162 BGE_MACSTAT_MI_COMPLETE)) &&
2163 (!sc->bge_tbi && (mimode & BGE_MIMODE_AUTOPOLL))) {
2165 callout_stop(&sc->bge_stat_timer);
2166 bge_tick_serialized(sc);
2169 callout_stop(&sc->bge_stat_timer);
2170 bge_tick_serialized(sc);
2171 /* Clear the interrupt */
2172 CSR_WRITE_4(sc, BGE_MAC_STS, BGE_MACSTAT_SYNC_CHANGED|
2173 BGE_MACSTAT_CFG_CHANGED|BGE_MACSTAT_MI_COMPLETE|
2174 BGE_MACSTAT_LINK_CHANGED);
2176 /* Force flush the status block cached by PCI bridge */
2177 CSR_READ_4(sc, BGE_MBX_IRQ0_LO);
2181 if (ifp->if_flags & IFF_RUNNING) {
2182 /* Check RX return ring producer/consumer */
2185 /* Check TX ring producer/consumer */
2189 bge_handle_events(sc);
2191 /* Re-enable interrupts. */
2192 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
2194 if ((ifp->if_flags & IFF_RUNNING) && !ifq_is_empty(&ifp->if_snd))
2195 (*ifp->if_start)(ifp);
2201 struct bge_softc *sc = xsc;
2202 struct ifnet *ifp = &sc->arpcom.ac_if;
2204 lwkt_serialize_enter(ifp->if_serializer);
2205 bge_tick_serialized(xsc);
2206 lwkt_serialize_exit(ifp->if_serializer);
2210 bge_tick_serialized(void *xsc)
2212 struct bge_softc *sc = xsc;
2213 struct ifnet *ifp = &sc->arpcom.ac_if;
2214 struct mii_data *mii = NULL;
2215 struct ifmedia *ifm = NULL;
2217 if (sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
2218 sc->bge_asicrev == BGE_ASICREV_BCM5750)
2219 bge_stats_update_regs(sc);
2221 bge_stats_update(sc);
2223 callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2230 ifm = &sc->bge_ifmedia;
2231 if (CSR_READ_4(sc, BGE_MAC_STS) &
2232 BGE_MACSTAT_TBI_PCS_SYNCHED) {
2234 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
2235 BGE_CLRBIT(sc, BGE_MAC_MODE,
2236 BGE_MACMODE_TBI_SEND_CFGS);
2238 CSR_WRITE_4(sc, BGE_MAC_STS, 0xFFFFFFFF);
2239 if_printf(ifp, "gigabit link up\n");
2240 if (!ifq_is_empty(&ifp->if_snd))
2241 (*ifp->if_start)(ifp);
2246 mii = device_get_softc(sc->bge_miibus);
2249 if (!sc->bge_link) {
2251 if (mii->mii_media_status & IFM_ACTIVE &&
2252 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) {
2254 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
2255 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX)
2256 if_printf(ifp, "gigabit link up\n");
2257 if (!ifq_is_empty(&ifp->if_snd))
2258 (*ifp->if_start)(ifp);
2264 bge_stats_update_regs(struct bge_softc *sc)
2266 struct ifnet *ifp = &sc->arpcom.ac_if;
2267 struct bge_mac_stats_regs stats;
2271 s = (uint32_t *)&stats;
2272 for (i = 0; i < sizeof(struct bge_mac_stats_regs); i += 4) {
2273 *s = CSR_READ_4(sc, BGE_RX_STATS + i);
2277 ifp->if_collisions +=
2278 (stats.dot3StatsSingleCollisionFrames +
2279 stats.dot3StatsMultipleCollisionFrames +
2280 stats.dot3StatsExcessiveCollisions +
2281 stats.dot3StatsLateCollisions) -
2286 bge_stats_update(struct bge_softc *sc)
2288 struct ifnet *ifp = &sc->arpcom.ac_if;
2289 struct bge_stats *stats;
2291 stats = (struct bge_stats *)(sc->bge_vhandle +
2292 BGE_MEMWIN_START + BGE_STATS_BLOCK);
2294 ifp->if_collisions +=
2295 (stats->txstats.dot3StatsSingleCollisionFrames.bge_addr_lo +
2296 stats->txstats.dot3StatsMultipleCollisionFrames.bge_addr_lo +
2297 stats->txstats.dot3StatsExcessiveCollisions.bge_addr_lo +
2298 stats->txstats.dot3StatsLateCollisions.bge_addr_lo) -
2302 ifp->if_collisions +=
2303 (sc->bge_rdata->bge_info.bge_stats.dot3StatsSingleCollisionFrames +
2304 sc->bge_rdata->bge_info.bge_stats.dot3StatsMultipleCollisionFrames +
2305 sc->bge_rdata->bge_info.bge_stats.dot3StatsExcessiveCollisions +
2306 sc->bge_rdata->bge_info.bge_stats.dot3StatsLateCollisions) -
2312 * Encapsulate an mbuf chain in the tx ring by coupling the mbuf data
2313 * pointers to descriptors.
2316 bge_encap(struct bge_softc *sc, struct mbuf *m_head, uint32_t *txidx)
2318 struct bge_tx_bd *f = NULL;
2320 uint32_t frag, cur, cnt = 0;
2321 uint16_t csum_flags = 0;
2322 struct ifvlan *ifv = NULL;
2324 if ((m_head->m_flags & (M_PROTO1|M_PKTHDR)) == (M_PROTO1|M_PKTHDR) &&
2325 m_head->m_pkthdr.rcvif != NULL &&
2326 m_head->m_pkthdr.rcvif->if_type == IFT_L2VLAN)
2327 ifv = m_head->m_pkthdr.rcvif->if_softc;
2330 cur = frag = *txidx;
2332 if (m_head->m_pkthdr.csum_flags) {
2333 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
2334 csum_flags |= BGE_TXBDFLAG_IP_CSUM;
2335 if (m_head->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
2336 csum_flags |= BGE_TXBDFLAG_TCP_UDP_CSUM;
2337 if (m_head->m_flags & M_LASTFRAG)
2338 csum_flags |= BGE_TXBDFLAG_IP_FRAG_END;
2339 else if (m_head->m_flags & M_FRAG)
2340 csum_flags |= BGE_TXBDFLAG_IP_FRAG;
2343 * Start packing the mbufs in this chain into
2344 * the fragment pointers. Stop when we run out
2345 * of fragments or hit the end of the mbuf chain.
2347 for (m = m_head; m != NULL; m = m->m_next) {
2348 if (m->m_len != 0) {
2349 f = &sc->bge_rdata->bge_tx_ring[frag];
2350 if (sc->bge_cdata.bge_tx_chain[frag] != NULL)
2352 BGE_HOSTADDR(f->bge_addr,
2353 vtophys(mtod(m, vm_offset_t)));
2354 f->bge_len = m->m_len;
2355 f->bge_flags = csum_flags;
2357 f->bge_flags |= BGE_TXBDFLAG_VLAN_TAG;
2358 f->bge_vlan_tag = ifv->ifv_tag;
2360 f->bge_vlan_tag = 0;
2363 * Sanity check: avoid coming within 16 descriptors
2364 * of the end of the ring.
2366 if ((BGE_TX_RING_CNT - (sc->bge_txcnt + cnt)) < 16)
2369 BGE_INC(frag, BGE_TX_RING_CNT);
2377 if (frag == sc->bge_tx_saved_considx)
2380 sc->bge_rdata->bge_tx_ring[cur].bge_flags |= BGE_TXBDFLAG_END;
2381 sc->bge_cdata.bge_tx_chain[cur] = m_head;
2382 sc->bge_txcnt += cnt;
2390 * Main transmit routine. To avoid having to do mbuf copies, we put pointers
2391 * to the mbuf data regions directly in the transmit descriptors.
2394 bge_start(struct ifnet *ifp)
2396 struct bge_softc *sc;
2397 struct mbuf *m_head = NULL;
2398 uint32_t prodidx = 0;
2406 prodidx = CSR_READ_4(sc, BGE_MBX_TX_HOST_PROD0_LO);
2409 while(sc->bge_cdata.bge_tx_chain[prodidx] == NULL) {
2410 m_head = ifq_poll(&ifp->if_snd);
2416 * safety overkill. If this is a fragmented packet chain
2417 * with delayed TCP/UDP checksums, then only encapsulate
2418 * it if we have enough descriptors to handle the entire
2420 * (paranoia -- may not actually be needed)
2422 if (m_head->m_flags & M_FIRSTFRAG &&
2423 m_head->m_pkthdr.csum_flags & (CSUM_DELAY_DATA)) {
2424 if ((BGE_TX_RING_CNT - sc->bge_txcnt) <
2425 m_head->m_pkthdr.csum_data + 16) {
2426 ifp->if_flags |= IFF_OACTIVE;
2432 * Pack the data into the transmit ring. If we
2433 * don't have room, set the OACTIVE flag and wait
2434 * for the NIC to drain the ring.
2436 if (bge_encap(sc, m_head, &prodidx)) {
2437 ifp->if_flags |= IFF_OACTIVE;
2440 ifq_dequeue(&ifp->if_snd, m_head);
2443 BPF_MTAP(ifp, m_head);
2450 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2451 /* 5700 b2 errata */
2452 if (sc->bge_chiprev == BGE_CHIPREV_5700_BX)
2453 CSR_WRITE_4(sc, BGE_MBX_TX_HOST_PROD0_LO, prodidx);
2456 * Set a timeout in case the chip goes out to lunch.
2464 struct bge_softc *sc = xsc;
2465 struct ifnet *ifp = &sc->arpcom.ac_if;
2468 if (ifp->if_flags & IFF_RUNNING) {
2472 /* Cancel pending I/O and flush buffers. */
2478 * Init the various state machines, ring
2479 * control blocks and firmware.
2481 if (bge_blockinit(sc)) {
2482 if_printf(ifp, "initialization failure\n");
2487 CSR_WRITE_4(sc, BGE_RX_MTU, ifp->if_mtu +
2488 ETHER_HDR_LEN + ETHER_CRC_LEN);
2490 /* Load our MAC address. */
2491 m = (uint16_t *)&sc->arpcom.ac_enaddr[0];
2492 CSR_WRITE_4(sc, BGE_MAC_ADDR1_LO, htons(m[0]));
2493 CSR_WRITE_4(sc, BGE_MAC_ADDR1_HI, (htons(m[1]) << 16) | htons(m[2]));
2495 /* Enable or disable promiscuous mode as needed. */
2496 if (ifp->if_flags & IFF_PROMISC) {
2497 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
2499 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_RX_PROMISC);
2502 /* Program multicast filter. */
2506 bge_init_rx_ring_std(sc);
2509 * Workaround for a bug in 5705 ASIC rev A0. Poll the NIC's
2510 * memory to insure that the chip has in fact read the first
2511 * entry of the ring.
2513 if (sc->bge_chipid == BGE_CHIPID_BCM5705_A0) {
2515 for (i = 0; i < 10; i++) {
2517 v = bge_readmem_ind(sc, BGE_STD_RX_RINGS + 8);
2518 if (v == (MCLBYTES - ETHER_ALIGN))
2522 if_printf(ifp, "5705 A0 chip failed to load RX ring\n");
2525 /* Init jumbo RX ring. */
2526 if (ifp->if_mtu > (ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN))
2527 bge_init_rx_ring_jumbo(sc);
2529 /* Init our RX return ring index */
2530 sc->bge_rx_saved_considx = 0;
2533 bge_init_tx_ring(sc);
2535 /* Turn on transmitter */
2536 BGE_SETBIT(sc, BGE_TX_MODE, BGE_TXMODE_ENABLE);
2538 /* Turn on receiver */
2539 BGE_SETBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
2541 /* Tell firmware we're alive. */
2542 BGE_SETBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2544 /* Enable host interrupts. */
2545 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_CLEAR_INTA);
2546 BGE_CLRBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
2547 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 0);
2549 bge_ifmedia_upd(ifp);
2551 ifp->if_flags |= IFF_RUNNING;
2552 ifp->if_flags &= ~IFF_OACTIVE;
2554 callout_reset(&sc->bge_stat_timer, hz, bge_tick, sc);
2558 * Set media options.
2561 bge_ifmedia_upd(struct ifnet *ifp)
2563 struct bge_softc *sc = ifp->if_softc;
2564 struct ifmedia *ifm = &sc->bge_ifmedia;
2565 struct mii_data *mii;
2567 /* If this is a 1000baseX NIC, enable the TBI port. */
2569 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
2571 switch(IFM_SUBTYPE(ifm->ifm_media)) {
2573 #ifndef BGE_FAKE_AUTONEG
2575 * The BCM5704 ASIC appears to have a special
2576 * mechanism for programming the autoneg
2577 * advertisement registers in TBI mode.
2579 if (sc->bge_asicrev == BGE_ASICREV_BCM5704) {
2582 CSR_WRITE_4(sc, BGE_TX_TBI_AUTONEG, 0);
2583 sgdig = CSR_READ_4(sc, BGE_SGDIG_CFG);
2584 sgdig |= BGE_SGDIGCFG_AUTO |
2585 BGE_SGDIGCFG_PAUSE_CAP |
2586 BGE_SGDIGCFG_ASYM_PAUSE;
2587 CSR_WRITE_4(sc, BGE_SGDIG_CFG,
2588 sgdig | BGE_SGDIGCFG_SEND);
2590 CSR_WRITE_4(sc, BGE_SGDIG_CFG, sgdig);
2592 #endif /* !BEG_FAKE_AUTONEG */
2595 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX) {
2596 BGE_CLRBIT(sc, BGE_MAC_MODE,
2597 BGE_MACMODE_HALF_DUPLEX);
2599 BGE_SETBIT(sc, BGE_MAC_MODE,
2600 BGE_MACMODE_HALF_DUPLEX);
2609 mii = device_get_softc(sc->bge_miibus);
2611 if (mii->mii_instance) {
2612 struct mii_softc *miisc;
2613 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
2614 miisc = LIST_NEXT(miisc, mii_list))
2615 mii_phy_reset(miisc);
2623 * Report current media status.
2626 bge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
2628 struct bge_softc *sc = ifp->if_softc;
2629 struct mii_data *mii;
2632 ifmr->ifm_status = IFM_AVALID;
2633 ifmr->ifm_active = IFM_ETHER;
2634 if (CSR_READ_4(sc, BGE_MAC_STS) &
2635 BGE_MACSTAT_TBI_PCS_SYNCHED)
2636 ifmr->ifm_status |= IFM_ACTIVE;
2637 ifmr->ifm_active |= IFM_1000_SX;
2638 if (CSR_READ_4(sc, BGE_MAC_MODE) & BGE_MACMODE_HALF_DUPLEX)
2639 ifmr->ifm_active |= IFM_HDX;
2641 ifmr->ifm_active |= IFM_FDX;
2645 mii = device_get_softc(sc->bge_miibus);
2647 ifmr->ifm_active = mii->mii_media_active;
2648 ifmr->ifm_status = mii->mii_media_status;
2652 bge_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
2654 struct bge_softc *sc = ifp->if_softc;
2655 struct ifreq *ifr = (struct ifreq *) data;
2656 int mask, error = 0;
2657 struct mii_data *mii;
2661 /* Disallow jumbo frames on 5705/5750. */
2662 if (((sc->bge_asicrev == BGE_ASICREV_BCM5705 ||
2663 sc->bge_asicrev == BGE_ASICREV_BCM5750) &&
2664 ifr->ifr_mtu > ETHERMTU) || ifr->ifr_mtu > BGE_JUMBO_MTU)
2667 ifp->if_mtu = ifr->ifr_mtu;
2668 ifp->if_flags &= ~IFF_RUNNING;
2673 if (ifp->if_flags & IFF_UP) {
2675 * If only the state of the PROMISC flag changed,
2676 * then just use the 'set promisc mode' command
2677 * instead of reinitializing the entire NIC. Doing
2678 * a full re-init means reloading the firmware and
2679 * waiting for it to start up, which may take a
2682 if (ifp->if_flags & IFF_RUNNING &&
2683 ifp->if_flags & IFF_PROMISC &&
2684 !(sc->bge_if_flags & IFF_PROMISC)) {
2685 BGE_SETBIT(sc, BGE_RX_MODE,
2686 BGE_RXMODE_RX_PROMISC);
2687 } else if (ifp->if_flags & IFF_RUNNING &&
2688 !(ifp->if_flags & IFF_PROMISC) &&
2689 sc->bge_if_flags & IFF_PROMISC) {
2690 BGE_CLRBIT(sc, BGE_RX_MODE,
2691 BGE_RXMODE_RX_PROMISC);
2695 if (ifp->if_flags & IFF_RUNNING) {
2699 sc->bge_if_flags = ifp->if_flags;
2704 if (ifp->if_flags & IFF_RUNNING) {
2712 error = ifmedia_ioctl(ifp, ifr,
2713 &sc->bge_ifmedia, command);
2715 mii = device_get_softc(sc->bge_miibus);
2716 error = ifmedia_ioctl(ifp, ifr,
2717 &mii->mii_media, command);
2721 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2722 if (mask & IFCAP_HWCSUM) {
2723 if (IFCAP_HWCSUM & ifp->if_capenable)
2724 ifp->if_capenable &= ~IFCAP_HWCSUM;
2726 ifp->if_capenable |= IFCAP_HWCSUM;
2731 error = ether_ioctl(ifp, command, data);
2738 bge_watchdog(struct ifnet *ifp)
2740 struct bge_softc *sc = ifp->if_softc;
2742 if_printf(ifp, "watchdog timeout -- resetting\n");
2744 ifp->if_flags &= ~IFF_RUNNING;
2749 if (!ifq_is_empty(&ifp->if_snd))
2754 * Stop the adapter and free any mbufs allocated to the
2758 bge_stop(struct bge_softc *sc)
2760 struct ifnet *ifp = &sc->arpcom.ac_if;
2761 struct ifmedia_entry *ifm;
2762 struct mii_data *mii = NULL;
2766 mii = device_get_softc(sc->bge_miibus);
2768 callout_stop(&sc->bge_stat_timer);
2771 * Disable all of the receiver blocks
2773 BGE_CLRBIT(sc, BGE_RX_MODE, BGE_RXMODE_ENABLE);
2774 BGE_CLRBIT(sc, BGE_RBDI_MODE, BGE_RBDIMODE_ENABLE);
2775 BGE_CLRBIT(sc, BGE_RXLP_MODE, BGE_RXLPMODE_ENABLE);
2776 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
2777 sc->bge_asicrev != BGE_ASICREV_BCM5750)
2778 BGE_CLRBIT(sc, BGE_RXLS_MODE, BGE_RXLSMODE_ENABLE);
2779 BGE_CLRBIT(sc, BGE_RDBDI_MODE, BGE_RBDIMODE_ENABLE);
2780 BGE_CLRBIT(sc, BGE_RDC_MODE, BGE_RDCMODE_ENABLE);
2781 BGE_CLRBIT(sc, BGE_RBDC_MODE, BGE_RBDCMODE_ENABLE);
2784 * Disable all of the transmit blocks
2786 BGE_CLRBIT(sc, BGE_SRS_MODE, BGE_SRSMODE_ENABLE);
2787 BGE_CLRBIT(sc, BGE_SBDI_MODE, BGE_SBDIMODE_ENABLE);
2788 BGE_CLRBIT(sc, BGE_SDI_MODE, BGE_SDIMODE_ENABLE);
2789 BGE_CLRBIT(sc, BGE_RDMA_MODE, BGE_RDMAMODE_ENABLE);
2790 BGE_CLRBIT(sc, BGE_SDC_MODE, BGE_SDCMODE_ENABLE);
2791 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
2792 sc->bge_asicrev != BGE_ASICREV_BCM5750)
2793 BGE_CLRBIT(sc, BGE_DMAC_MODE, BGE_DMACMODE_ENABLE);
2794 BGE_CLRBIT(sc, BGE_SBDC_MODE, BGE_SBDCMODE_ENABLE);
2797 * Shut down all of the memory managers and related
2800 BGE_CLRBIT(sc, BGE_HCC_MODE, BGE_HCCMODE_ENABLE);
2801 BGE_CLRBIT(sc, BGE_WDMA_MODE, BGE_WDMAMODE_ENABLE);
2802 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
2803 sc->bge_asicrev != BGE_ASICREV_BCM5750)
2804 BGE_CLRBIT(sc, BGE_MBCF_MODE, BGE_MBCFMODE_ENABLE);
2805 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0xFFFFFFFF);
2806 CSR_WRITE_4(sc, BGE_FTQ_RESET, 0);
2807 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
2808 sc->bge_asicrev != BGE_ASICREV_BCM5750) {
2809 BGE_CLRBIT(sc, BGE_BMAN_MODE, BGE_BMANMODE_ENABLE);
2810 BGE_CLRBIT(sc, BGE_MARB_MODE, BGE_MARBMODE_ENABLE);
2813 /* Disable host interrupts. */
2814 BGE_SETBIT(sc, BGE_PCI_MISC_CTL, BGE_PCIMISCCTL_MASK_PCI_INTR);
2815 CSR_WRITE_4(sc, BGE_MBX_IRQ0_LO, 1);
2818 * Tell firmware we're shutting down.
2820 BGE_CLRBIT(sc, BGE_MODE_CTL, BGE_MODECTL_STACKUP);
2822 /* Free the RX lists. */
2823 bge_free_rx_ring_std(sc);
2825 /* Free jumbo RX list. */
2826 if (sc->bge_asicrev != BGE_ASICREV_BCM5705 &&
2827 sc->bge_asicrev != BGE_ASICREV_BCM5750)
2828 bge_free_rx_ring_jumbo(sc);
2830 /* Free TX buffers. */
2831 bge_free_tx_ring(sc);
2834 * Isolate/power down the PHY, but leave the media selection
2835 * unchanged so that things will be put back to normal when
2836 * we bring the interface back up.
2839 itmp = ifp->if_flags;
2840 ifp->if_flags |= IFF_UP;
2841 ifm = mii->mii_media.ifm_cur;
2842 mtmp = ifm->ifm_media;
2843 ifm->ifm_media = IFM_ETHER|IFM_NONE;
2845 ifm->ifm_media = mtmp;
2846 ifp->if_flags = itmp;
2851 sc->bge_tx_saved_considx = BGE_TXCONS_UNSET;
2853 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
2857 * Stop all chip I/O so that the kernel's probe routines don't
2858 * get confused by errant DMAs when rebooting.
2861 bge_shutdown(device_t dev)
2863 struct bge_softc *sc = device_get_softc(dev);