2 * Copyright (c) 2000, 2001 Sergio Prallon. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
16 * 4. Altered versions must be plainly marked as such, and must not be
17 * misrepresented as being the original software and/or documentation.
19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 *---------------------------------------------------------------------------
33 * i4b_itjc_pci.c: NetJet-S hardware driver
34 * ----------------------------------------
36 * $FreeBSD: src/sys/i4b/layer1/itjc/i4b_itjc_pci.c,v 1.1.2.1 2001/08/10 14:08:39 obrien Exp $
37 * $DragonFly: src/sys/net/i4b/layer1/itjc/i4b_itjc_pci.c,v 1.14 2005/10/12 17:35:55 dillon Exp $
39 * last edit-date: [Thu Jan 11 11:29:38 2001]
41 *---------------------------------------------------------------------------*/
49 #include <sys/param.h>
50 #include <sys/kernel.h>
51 #include <sys/systm.h>
54 #include <machine/clock.h>
55 #include <machine/bus_pio.h>
56 #include <machine/bus.h>
57 #include <machine/resource.h>
61 #include <bus/pci/pcireg.h>
62 #include <bus/pci/pcivar.h>
64 #include <sys/socket.h>
65 #include <sys/thread2.h>
68 #include <net/i4b/include/machine/i4b_debug.h>
69 #include <net/i4b/include/machine/i4b_ioctl.h>
70 #include <net/i4b/include/machine/i4b_trace.h>
72 #include "../../include/i4b_global.h"
73 #include "../../include/i4b_mbuf.h"
75 #include "../i4b_l1.h"
77 #include "i4b_hdlc.h" /* XXXXXXXXXXXXXXXXXXXXXXXX */
79 #include "../isic/i4b_isic.h"
80 #include "../isic/i4b_isac.h"
82 #include "i4b_itjc_ext.h"
84 #define PCI_TJNET_VID (0xe159)
85 #define PCI_TJ300_DID (0x0001)
92 static int itjc_probe(device_t dev);
93 static int itjc_attach(device_t dev);
94 static void itjc_shutdown(device_t dev);
95 static void itjc_intr(void *xsc);
96 static int itjc_dma_start(struct l1_softc *sc);
97 static void itjc_dma_stop(struct l1_softc *sc);
98 static void itjc_isac_intr(struct l1_softc *sc);
99 static void itjc_init_linktab(struct l1_softc *sc);
100 static void itjc_bchannel_setup(int unit, int h_chan, int bprot,
102 static void itjc_bchannel_stat(int unit, int h_chan, bchan_statistics_t *bsp);
106 * Shorter names to bus resource manager routines.
109 #define itjc_bus_setup(sc) \
110 bus_space_handle_t h = \
111 rman_get_bushandle((sc)->sc_resources.io_base[0]); \
112 bus_space_tag_t t = \
113 rman_get_bustag((sc)->sc_resources.io_base[0]);
115 #define itjc_read_1(port) (bus_space_read_1(t, h, (port)))
116 #define itjc_read_4(port) (bus_space_read_4(t, h, (port)))
117 #define itjc_write_1(port, data) (bus_space_write_1(t, h, (port), (data)))
118 #define itjc_write_4(port, data) (bus_space_write_4(t, h, (port), (data)))
119 #define itjc_read_multi_1(port, buf, size) \
120 (bus_space_read_multi_1(t, h, (port), (buf), (size)))
121 #define itjc_write_multi_1(port, buf, size) \
122 (bus_space_write_multi_1(t, h, (port), (buf), (size)))
125 /*---------------------------------------------------------------------------*
126 * Glue data to register ourselves as a PCI device driver.
127 *---------------------------------------------------------------------------*/
129 static device_method_t itjc_pci_methods[] =
131 /* Device interface */
132 DEVMETHOD(device_probe, itjc_probe),
133 DEVMETHOD(device_attach, itjc_attach),
134 DEVMETHOD(device_shutdown, itjc_shutdown),
137 DEVMETHOD(bus_print_child, bus_generic_print_child),
138 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
143 static driver_t itjc_pci_driver =
147 sizeof(struct l1_softc)
150 static devclass_t itjc_pci_devclass;
152 DRIVER_MODULE(netjet, pci, itjc_pci_driver, itjc_pci_devclass, 0, 0);
155 * Jump table for multiplex routines.
158 struct i4b_l1mux_func itjc_l1mux_func =
162 itjc_mph_command_req,
164 itjc_ph_activate_req,
167 struct l1_softc *itjc_scp[ITJC_MAXUNIT];
170 /*---------------------------------------------------------------------------*
171 * Tiger300/320 PCI ASIC registers.
172 *---------------------------------------------------------------------------*/
175 * Register offsets from i/o base.
179 TIGER_RESET_PIB_CL_TIME = 0x00,
180 TIGER_DMA_OPER = 0x01,
181 TIGER_AUX_PORT_CNTL = 0x02,
182 TIGER_AUX_PORT_DATA = 0x03,
183 TIGER_INT0_MASK = 0x04,
184 TIGER_INT1_MASK = 0x05,
185 TIGER_INT0_STATUS = 0x06,
186 TIGER_INT1_STATUS = 0x07,
187 TIGER_DMA_WR_START_ADDR = 0x08,
188 TIGER_DMA_WR_INT_ADDR = 0x0C,
189 TIGER_DMA_WR_END_ADDR = 0x10,
190 TIGER_DMA_WR_CURR_ADDR = 0x14,
191 TIGER_DMA_RD_START_ADDR = 0x18,
192 TIGER_DMA_RD_INT_ADDR = 0x1C,
193 TIGER_DMA_RD_END_ADDR = 0x20,
194 TIGER_DMA_RD_CURR_ADDR = 0x24,
195 TIGER_PULSE_COUNTER = 0x28,
199 * Bits on the above registers.
204 /* Reset and PIB Cycle Timing */
206 TIGER_DMA_OP_MODE_MASK = 0x80,
207 TIGER_SELF_ADDR_DMA = 0x00, /* Wrap around ending addr */
208 TIGER_NORMAL_DMA = 0x80, /* Stop at ending addr */
210 TIGER_DMA_INT_MODE_MASK = 0x40,
211 TIGER_DONT_LATCH_DMA_INT= 0x00, /* Bits on int0 status will be
212 set only while curr addr
213 equals int or end addr */
214 TIGER_LATCH_DMA_INT = 0x40, /* Bits on int0 status remain
215 set until cleared by CPU */
217 TIGER_PIB_CYCLE_TIMING_MASK = 0x30,
218 TIGER_PIB_3_CYCLES = 0x00,
219 TIGER_PIB_5_CYCLES = 0x01,
220 TIGER_PIB_12_CYCLES = 0x10,
222 TIGER_RESET_MASK = 0x0F,
223 TIGER_RESET_PULSE_COUNT = 0x08,
224 TIGER_RESET_SERIAL_PORT = 0x04,
225 TIGER_RESET_DMA_LOGIC = 0x02,
226 TIGER_RESET_EXTERNAL = 0x01,
227 TIGER_RESET_ALL = 0x0F,
230 TIGER_DMA_RESTART_MASK = 0x02,
231 TIGER_HOLD_DMA = 0x00,
232 TIGER_RESTART_DMA = 0x00,
234 TIGER_DMA_ENABLE_MASK = 0x01,
235 TIGER_ENABLE_DMA = 0x01,
236 TIGER_DISABLE_DMA = 0x00,
238 /* AUX Port Control & Data plus Interrupt 1 Mask & Status */
239 TIGER_AUX_7_MASK = 0x80,
240 TIGER_AUX_6_MASK = 0x40,
241 TIGER_AUX_5_MASK = 0x20,
242 TIGER_AUX_4_MASK = 0x10,
243 TIGER_ISAC_INT_MASK = 0x10,
244 TIGER_AUX_3_MASK = 0x08,
245 TIGER_AUX_2_MASK = 0x04,
246 TIGER_AUX_1_MASK = 0x02,
247 TIGER_AUX_0_MASK = 0x01,
249 /* AUX Port Control */
250 TIGER_AUX_7_IS_INPUT = 0x00,
251 TIGER_AUX_7_IS_OUTPUT = 0x80,
252 TIGER_AUX_6_IS_INPUT = 0x00,
253 TIGER_AUX_6_IS_OUTPUT = 0x40,
254 TIGER_AUX_5_IS_INPUT = 0x00,
255 TIGER_AUX_5_IS_OUTPUT = 0x20,
256 TIGER_AUX_4_IS_INPUT = 0x00,
257 TIGER_AUX_4_IS_OUTPUT = 0x10,
258 TIGER_AUX_3_IS_INPUT = 0x00,
259 TIGER_AUX_3_IS_OUTPUT = 0x80,
260 TIGER_AUX_2_IS_INPUT = 0x00,
261 TIGER_AUX_2_IS_OUTPUT = 0x40,
262 TIGER_AUX_1_IS_INPUT = 0x00,
263 TIGER_AUX_1_IS_OUTPUT = 0x20,
264 TIGER_AUX_0_IS_INPUT = 0x00,
265 TIGER_AUX_0_IS_OUTPUT = 0x10,
266 TIGER_AUX_NJ_DEFAULT = 0xEF, /* All but ISAC int is output */
268 /* Interrupt 0 Mask & Status */
269 TIGER_PCI_TARGET_ABORT_INT_MASK = 0x20,
270 TIGER_NO_TGT_ABORT_INT = 0x00,
271 TIGER_TARGET_ABORT_INT = 0x20,
272 TIGER_PCI_MASTER_ABORT_INT_MASK = 0x10,
273 TIGER_NO_MST_ABORT_INT = 0x00,
274 TIGER_MASTER_ABORT_INT = 0x10,
275 TIGER_DMA_RD_END_INT_MASK = 0x08,
276 TIGER_NO_RD_END_INT = 0x00,
277 TIGER_RD_END_INT = 0x08,
278 TIGER_DMA_RD_INT_INT_MASK = 0x04,
279 TIGER_NO_RD_INT_INT = 0x00,
280 TIGER_RD_INT_INT = 0x04,
281 TIGER_DMA_WR_END_INT_MASK = 0x02,
282 TIGER_NO_WR_END_INT = 0x00,
283 TIGER_WR_END_INT = 0x02,
284 TIGER_DMA_WR_INT_INT_MASK = 0x01,
285 TIGER_NO_WR_INT_INT = 0x00,
286 TIGER_WR_INT_INT = 0x01,
288 /* Interrupt 1 Mask & Status */
289 TIGER_NO_AUX_7_INT = 0x00,
290 TIGER_AUX_7_INT = 0x80,
291 TIGER_NO_AUX_6_INT = 0x00,
292 TIGER_AUX_6_INT = 0x40,
293 TIGER_NO_AUX_5_INT = 0x00,
294 TIGER_AUX_5_INT = 0x20,
295 TIGER_NO_AUX_4_INT = 0x00,
296 TIGER_AUX_4_INT = 0x10,
297 TIGER_NO_ISAC_INT = 0x00,
298 TIGER_ISAC_INT = 0x10,
299 TIGER_NO_AUX_3_INT = 0x00,
300 TIGER_AUX_3_INT = 0x08,
301 TIGER_NO_AUX_2_INT = 0x00,
302 TIGER_AUX_2_INT = 0x04,
303 TIGER_NO_AUX_1_INT = 0x00,
304 TIGER_AUX_1_INT = 0x02,
305 TIGER_NO_AUX_0_INT = 0x00,
306 TIGER_AUX_0_INT = 0x01
310 * Peripheral Interface Bus definitions. This is an ISA like bus
311 * created by the Tiger ASIC to keep ISA chips like the ISAC happy
312 * on a PCI environment.
314 * Since the PIB only supplies 4 addressing lines, the 2 higher bits
315 * (A4 & A5) of the ISAC register addresses are wired on the 2 lower
316 * AUX lines. Another restriction is that all I/O to the PIB (8bit
317 * wide) is mapped on the PCI side as 32bit data. So the PCI address
318 * of a given ISAC register has to be multiplied by 4 before being
319 * added to the PIB base offset.
321 enum tiger_pib_regs_defs
323 /* Offset from the I/O base to the ISAC registers. */
325 PIB_LO_ADDR_MASK = 0x0F,
326 PIB_HI_ADDR_MASK = 0x30,
327 PIB_LO_ADDR_SHIFT = 2, /* Align on dword boundary */
328 PIB_HI_ADDR_SHIFT = 4 /* Right shift to AUX_1 & AUX_0 */
332 #define itjc_set_pib_addr_msb(a) \
334 itjc_write_1(TIGER_AUX_PORT_DATA, \
335 ((a) & PIB_HI_ADDR_MASK) >> PIB_HI_ADDR_SHIFT) \
338 #define itjc_pib_2_pci(a) \
340 (((a) & PIB_LO_ADDR_MASK) << PIB_LO_ADDR_SHIFT) + PIB_OFFSET \
343 #define itjc_get_dma_offset(ctx,reg) \
345 (u_int16_t)((bus_addr_t)itjc_read_4((reg)) - (ctx)->bus_addr) \
350 * IOM-2 serial channel 0 DMA data ring buffers.
352 * The Tiger300/320 ASIC do not nothing more than transfer via DMA the
353 * first 32 bits of every IOM-2 frame on the serial interface to the
354 * ISAC. So we have no framing/deframing facilities like we would have
355 * with an HSCX, having to do the job with CPU cycles. On the plus side
356 * we are able to specify large rings which can limit the occurrence of
362 ITJC_RING_SLOT_WORDS = 64,
363 ITJC_RING_WORDS = 3 * ITJC_RING_SLOT_WORDS,
364 ITJC_RING_SLOT_BYTES = 4 * ITJC_RING_SLOT_WORDS,
365 ITJC_RING_BYTES = 4 * ITJC_RING_WORDS,
366 ITJC_DMA_POOL_WORDS = 2 * ITJC_RING_WORDS,
367 ITJC_DMA_POOL_BYTES = 4 * ITJC_DMA_POOL_WORDS
370 #define itjc_ring_add(x, d) (((x) + 4 * (d)) % ITJC_RING_BYTES)
371 #define itjc_ring_sub(x, d) (((x) + ITJC_RING_BYTES - 4 * (d)) \
380 HSCX_CH_A = 0, /* For compatibility reasons. */
386 ITJC_TEL_SILENCE_BYTE = 0x00,
387 ITJC_HDLC_FLAG_BYTE = 0x7E,
388 ITJC_HDLC_ABORT_BYTE = 0xFF
392 * Hardware DMA control block (one per card).
396 ITJC_DS_LOAD_FAILED = -1,
416 dma_context [ ITJC_MAXUNIT ];
419 * B-channel DMA control blocks (4 per card -- 1 RX & 1 TX per channel).
445 u_int8_t hdlc_blevel;
447 dma_rx_state_t state;
455 u_int16_t next_write;
457 u_int16_t hdlc_blevel;
460 u_int16_t next_frame;
463 dma_tx_state_t state;
468 dma_rx_context [ ITJC_MAXUNIT ] [ 2 ];
471 dma_tx_context [ ITJC_MAXUNIT ] [ 2 ];
474 * Used by the mbuf handling functions.
485 /*---------------------------------------------------------------------------*
486 * itjc_map_callback - get DMA bus address from resource mgr.
487 *---------------------------------------------------------------------------*/
489 itjc_map_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error)
491 dma_context_t *ctx = (dma_context_t *)arg;
496 ctx->state = ITJC_DS_LOAD_FAILED;
500 ctx->bus_addr = segs->ds_addr;
501 ctx->state = ITJC_DS_STOPPED;
505 /*---------------------------------------------------------------------------*
506 * itjc_dma_start - Complete DMA setup & start the Tiger DMA engine.
507 *---------------------------------------------------------------------------*/
509 itjc_dma_start(struct l1_softc *sc)
511 int unit = sc->sc_unit;
512 dma_context_t *ctx = &dma_context[unit];
513 dma_rx_context_t *rxc = &dma_rx_context[unit][0];
514 dma_tx_context_t *txc = &dma_tx_context[unit][0];
520 bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[0]);
521 bus_space_tag_t t = rman_get_bustag(sc->sc_resources.io_base[0]);
523 /* See if it is already running. */
525 if (ctx->state == ITJC_DS_RUNNING)
528 if (ctx->state == ITJC_DS_LOAD_FAILED)
530 NDBGL1(L1_ERROR, "itjc%d: dma_start: DMA map loading "
531 "failed (error=%d).\n", unit, ctx->error);
535 if (ctx->state != ITJC_DS_STOPPED)
537 NDBGL1(L1_ERROR, "itjc%d: dma_start: Unexpected DMA "
538 "state (%d).\n", unit, ctx->state);
543 * Initialize the DMA control structures (hardware & B-channel).
547 txc->ring = ctx->pool + TIGER_CH_A;
548 rxc->ring = ctx->pool + TIGER_CH_A + ITJC_RING_BYTES;
551 rxc->bus_addr = ba + ITJC_RING_BYTES;
555 txc->ring = ctx->pool + TIGER_CH_B;
556 rxc->ring = ctx->pool + TIGER_CH_B + ITJC_RING_BYTES;
559 rxc->bus_addr = ba + ITJC_RING_BYTES;
562 * Fill the DMA ring buffers with IOM-2 channel 0 frames made of
563 * idle/abort sequences for the B & D channels and NOP for IOM-2
564 * cmd/ind, monitor handshake & data.
566 pool_end = (u_int32_t *)ctx->pool + ITJC_DMA_POOL_WORDS;
567 for (ip = (u_int32_t *)ctx->pool; ip < pool_end; ++ip)
571 * Program the Tiger DMA gears.
574 itjc_write_4(TIGER_DMA_WR_START_ADDR, ba);
575 itjc_write_4(TIGER_DMA_WR_INT_ADDR, ba + ITJC_RING_SLOT_BYTES - 4);
576 itjc_write_4(TIGER_DMA_WR_END_ADDR, ba + ITJC_RING_BYTES - 4);
578 ba += ITJC_RING_BYTES;
580 itjc_write_4(TIGER_DMA_RD_START_ADDR, ba);
581 itjc_write_4(TIGER_DMA_RD_INT_ADDR, ba + ITJC_RING_SLOT_BYTES * 2 - 4);
582 itjc_write_4(TIGER_DMA_RD_END_ADDR, ba + ITJC_RING_BYTES - 4);
584 itjc_write_1(TIGER_INT0_MASK,
585 TIGER_WR_END_INT | TIGER_WR_INT_INT | TIGER_RD_INT_INT);
587 itjc_write_1(TIGER_DMA_OPER, TIGER_ENABLE_DMA);
590 * See if it really started.
592 ba = itjc_read_4(TIGER_DMA_RD_CURR_ADDR);
593 for (i = 0; i < 10; ++i)
595 DELAY(SEC_DELAY/1000);
596 if (ba != itjc_read_4(TIGER_DMA_RD_CURR_ADDR))
598 ctx->state = ITJC_DS_RUNNING;
603 NDBGL1(L1_ERROR, "itjc%d: dma_start: DMA start failed.\n ", unit);
608 /*---------------------------------------------------------------------------*
609 * itjc_dma_stop - Stop the Tiger DMA engine.
610 *---------------------------------------------------------------------------*/
612 itjc_dma_stop(struct l1_softc *sc)
614 dma_context_t *ctx = &dma_context[sc->sc_unit];
616 bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[0]);
617 bus_space_tag_t t = rman_get_bustag(sc->sc_resources.io_base[0]);
619 /* Only stop the DMA if it is running. */
621 if (ctx->state != ITJC_DS_RUNNING)
624 itjc_write_1(TIGER_DMA_OPER, TIGER_DISABLE_DMA);
625 DELAY(SEC_DELAY/1000);
627 ctx->state = ITJC_DS_STOPPED;
631 /*---------------------------------------------------------------------------*
632 * itjc_bchannel_dma_setup - The DMA side of itjc_bchannel_setup.
633 *---------------------------------------------------------------------------*/
635 itjc_bchannel_dma_setup(struct l1_softc *sc, int h_chan, int activate)
637 dma_rx_context_t *rxc = &dma_rx_context[sc->sc_unit][h_chan];
638 dma_tx_context_t *txc = &dma_tx_context[sc->sc_unit][h_chan];
640 l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
645 bus_space_handle_t h;
649 h = rman_get_bushandle(sc->sc_resources.io_base[0]);
650 t = rman_get_bustag(sc->sc_resources.io_base[0]);
655 * Get the DMA engine going if it's not running already.
659 rxc->hdlc_len = rxc->hdlc_tmp = rxc->hdlc_crc = 0;
660 rxc->hdlc_ib = rxc->hdlc_blevel = rxc->hdlc_flag = 0;
662 txc->hdlc_tmp = txc->hdlc_blevel = txc->hdlc_crc = 0;
667 if (chan->bprot == BPROT_NONE)
668 fill_byte = ITJC_TEL_SILENCE_BYTE;
670 fill_byte = ITJC_HDLC_ABORT_BYTE;
672 ring_end = rxc->ring + ITJC_RING_BYTES;
673 for (cp = rxc->ring; cp < ring_end; cp += 4)
676 ring_end = txc->ring + ITJC_RING_BYTES;
677 for (cp = txc->ring; cp < ring_end; cp += 4)
681 itjc_get_dma_offset(rxc, TIGER_DMA_RD_CURR_ADDR);
683 txc->next_frame = txc->next_write =
684 itjc_get_dma_offset(txc, TIGER_DMA_WR_CURR_ADDR);
686 rxc->state = ITJC_RS_ACTIVE;
687 txc->state = ITJC_TS_AFTER_XDU;
691 dma_rx_context_t *rxc2;
693 txc->state = ITJC_TS_IDLE;
694 rxc->state = ITJC_RS_IDLE;
696 rxc2 = &dma_rx_context[sc->sc_unit][0];
698 if (rxc2->state == ITJC_RS_IDLE
699 && rxc2[1].state == ITJC_RS_IDLE)
707 /*---------------------------------------------------------------------------*
708 * Mbuf & if_queues management routines.
709 *---------------------------------------------------------------------------*/
712 itjc_get_rx_mbuf(l1_bchan_state_t *chan, u_int8_t **dst_end_p,
715 struct mbuf *mbuf = chan->in_mbuf;
717 if (mbuf == NULL && which == ITJC_MB_NEW)
719 if ((mbuf = i4b_Bgetmbuf(BCH_MAX_DATALEN)) == NULL)
720 panic("itjc_get_rx_mbuf: cannot allocate mbuf!");
722 chan->in_mbuf = mbuf;
723 chan->in_cbptr = (u_int8_t *)mbuf->m_data;
727 if (dst_end_p != NULL)
730 *dst_end_p = (u_int8_t *)(mbuf->m_data)
736 return chan->in_cbptr;
741 itjc_save_rx_mbuf(l1_bchan_state_t *chan, u_int8_t * dst)
743 struct mbuf *mbuf = chan->in_mbuf;
745 if (dst != NULL && mbuf != NULL)
747 chan->in_cbptr = dst;
748 chan->in_len = dst - (u_int8_t *)mbuf->m_data;
750 else if (dst == NULL && mbuf == NULL)
752 chan->in_cbptr = NULL;
756 panic("itjc_save_rx_mbuf: stale pointer dst=%p mbuf=%p "
757 "in_cbptr=%p in_len=%d", dst, mbuf,
758 chan->in_cbptr, chan->in_len);
763 itjc_free_rx_mbuf(l1_bchan_state_t *chan)
765 struct mbuf *mbuf = chan->in_mbuf;
770 chan->in_mbuf = NULL;
771 chan->in_cbptr = NULL;
777 itjc_put_rx_mbuf(struct l1_softc *sc, l1_bchan_state_t *chan, u_int16_t len)
780 struct mbuf *mbuf = chan->in_mbuf;
781 u_int8_t *data = mbuf->m_data;
784 mbuf->m_pkthdr.len = mbuf->m_len = len;
786 if (sc->sc_trace & TRACE_B_RX)
788 hdr.unit = L0ITJCUNIT(sc->sc_unit);
789 hdr.type = (chan->channel == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
791 hdr.count = ++sc->sc_trace_bcount;
793 i4b_l1_trace_ind(&hdr, len, data);
796 if (chan->bprot == BPROT_NONE)
798 activity = ! i4b_l1_bchan_tel_silence(data, len);
800 /* move rx'd data to rx queue */
802 if (!IF_QFULL(&chan->rx_queue))
804 IF_ENQUEUE(&chan->rx_queue, mbuf);
815 chan->rxcount += len;
817 (*chan->isic_drvr_linktab->bch_rx_data_ready)
818 (chan->isic_drvr_linktab->unit);
822 (*chan->isic_drvr_linktab->bch_activity)
823 (chan->isic_drvr_linktab->unit, ACT_RX);
825 chan->in_mbuf = NULL;
826 chan->in_cbptr = NULL;
831 #define itjc_free_tx_mbufs(chan) \
833 i4b_Bfreembuf((chan)->out_mbuf_head); \
834 (chan)->out_mbuf_cur = (chan)->out_mbuf_head = NULL; \
835 (chan)->out_mbuf_cur_ptr = NULL; \
836 (chan)->out_mbuf_cur_len = 0; \
841 itjc_get_tx_mbuf(struct l1_softc *sc, l1_bchan_state_t *chan,
842 u_int8_t **src_p, which_mb_t which)
845 struct mbuf *mbuf = chan->out_mbuf_cur;
846 u_int8_t activity = 1;
855 *src_p = chan->out_mbuf_cur_ptr;
856 return chan->out_mbuf_cur_len;
864 chan->txcount += mbuf->m_len;
872 chan->out_mbuf_cur_ptr = *src_p = NULL;
873 chan->out_mbuf_cur_len = 0;
875 if (chan->out_mbuf_head != NULL)
877 i4b_Bfreembuf(chan->out_mbuf_head);
878 chan->out_mbuf_head = NULL;
885 chan->txcount += mbuf->m_len;
888 if (chan->out_mbuf_head != NULL)
889 i4b_Bfreembuf(chan->out_mbuf_head);
891 IF_DEQUEUE(&chan->tx_queue, mbuf);
895 chan->out_mbuf_cur = chan->out_mbuf_head = NULL;
896 chan->out_mbuf_cur_ptr = *src_p = NULL;
897 chan->out_mbuf_cur_len = 0;
899 chan->state &= ~(HSCX_TX_ACTIVE);
901 (*chan->isic_drvr_linktab->bch_tx_queue_empty)
902 (chan->isic_drvr_linktab->unit);
907 chan->out_mbuf_head = mbuf;
910 chan->out_mbuf_cur = mbuf;
911 chan->out_mbuf_cur_ptr = data = mbuf->m_data;
912 chan->out_mbuf_cur_len = len = mbuf->m_len;
914 chan->state |= HSCX_TX_ACTIVE;
916 if (sc->sc_trace & TRACE_B_TX)
918 hdr.unit = L0ITJCUNIT(sc->sc_unit);
919 hdr.type = (chan->channel == HSCX_CH_A ? TRC_CH_B1 : TRC_CH_B2);
921 hdr.count = ++sc->sc_trace_bcount;
923 i4b_l1_trace_ind(&hdr, len, data);
926 if (chan->bprot == BPROT_NONE)
927 activity = ! i4b_l1_bchan_tel_silence(data, len);
930 (*chan->isic_drvr_linktab->bch_activity)
931 (chan->isic_drvr_linktab->unit, ACT_TX);
938 #define itjc_save_tx_mbuf(chan, src, dst) \
940 (chan)->out_mbuf_cur != NULL ? \
942 (chan)->out_mbuf_cur_ptr = (src), \
943 (chan)->out_mbuf_cur_len = (len) \
950 /*---------------------------------------------------------------------------*
951 * B-channel interrupt service routines.
952 *---------------------------------------------------------------------------*/
955 * Since the Tiger ASIC doesn't produce a XMIT underflow indication,
956 * we need to deduce it ourselves. This is somewhat tricky because we
957 * are dealing with modulo m arithmetic. The idea here is to have a
958 * "XDU zone" ahead of the writing pointer sized 1/3 of total ring
959 * length (a ring slot). If the hardware DMA pointer is found there we
960 * consider that a XDU has occurred. To complete the scheme, we never
961 * let the ring have more than 2 slots of (unsent) data and adjust the
962 * interrupt registers to cause an interrupt at every slot.
965 itjc_xdu(struct l1_softc *sc, l1_bchan_state_t *chan, dma_tx_context_t *ctx,
966 u_int16_t *dst_p, u_int16_t *dst_end_p, u_int8_t tx_restart)
978 bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[0]);
979 bus_space_tag_t t = rman_get_bustag(sc->sc_resources.io_base[0]);
982 * Since the hardware is running, be conservative and assume
983 * the pointer location has a `fuzy' error factor.
985 dma = itjc_get_dma_offset(ctx, TIGER_DMA_WR_CURR_ADDR);
987 dma_h = itjc_ring_add(dma, 1);
989 dst_end = itjc_ring_sub(dma_l, ITJC_RING_SLOT_WORDS);
991 if (ctx->state != ITJC_TS_ACTIVE)
993 xdu = (ctx->state == ITJC_TS_AFTER_XDU);
994 dst = itjc_ring_add(dma_h, 4);
999 * Check for xmit underruns.
1001 xdu_l = dst = ctx->next_write;
1002 xdu_h = itjc_ring_add(dst, ITJC_RING_SLOT_WORDS);
1005 xdu = (xdu_l <= dma_l && dma_l < xdu_h)
1006 || (xdu_l <= dma_h && dma_h < xdu_h);
1008 xdu = (xdu_l <= dma_l || dma_l < xdu_h)
1009 || (xdu_l <= dma_h || dma_h < xdu_h);
1013 ctx->state = ITJC_TS_AFTER_XDU;
1015 dst = itjc_ring_add(dma_h, 4);
1017 else if (tx_restart)
1020 * See if we still can restart from immediately
1021 * after the last frame sent. It's a XDU test but
1022 * using the real data end on the comparsions. We
1023 * don't consider XDU an error here because we were
1024 * just trying to avoid send a filling gap between
1025 * frames. If it's already sent no harm is done.
1027 xdu_l = dst = ctx->next_frame;
1028 xdu_h = itjc_ring_add(dst, ITJC_RING_SLOT_WORDS);
1031 xdu = (xdu_l <= dma_l && dma_l < xdu_h)
1032 || (xdu_l <= dma_h && dma_h < xdu_h);
1034 xdu = (xdu_l <= dma_l || dma_l < xdu_h)
1035 || (xdu_l <= dma_h || dma_h < xdu_h);
1038 dst = itjc_ring_add(dma_h, 4);
1047 if (dst_end_p != NULL)
1048 *dst_end_p = dst_end;
1050 ctx->next_write = dst_end;
1056 #define itjc_rotate_hdlc_flag(blevel) \
1057 ((u_int8_t)(0x7E7E >> (8 - (u_int8_t)((blevel) >> 8))))
1061 itjc_dma_rx_intr(struct l1_softc *sc, l1_bchan_state_t *chan,
1062 dma_rx_context_t *ctx)
1078 bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[0]);
1079 bus_space_tag_t t = rman_get_bustag(sc->sc_resources.io_base[0]);
1082 if (ctx->state == ITJC_RS_IDLE)
1086 dma = itjc_get_dma_offset(ctx, TIGER_DMA_RD_CURR_ADDR);
1087 dma = itjc_ring_sub(dma, 1);
1088 src = ctx->next_read;
1090 if (chan->bprot == BPROT_NONE)
1092 dst = itjc_get_rx_mbuf(chan, &dst_end, ITJC_MB_CURR);
1097 dst = itjc_get_rx_mbuf(chan, &dst_end,
1101 src = itjc_ring_add(src, 1);
1105 itjc_put_rx_mbuf(sc, chan, BCH_MAX_DATALEN);
1106 dst = dst_end = NULL;
1109 ctx->next_read = src;
1110 itjc_save_rx_mbuf(chan, dst);
1114 blevel = ctx->hdlc_blevel;
1115 flag = ctx->hdlc_flag;
1116 len = ctx->hdlc_len;
1117 tmp = ctx->hdlc_tmp;
1118 crc = ctx->hdlc_crc;
1121 dst = itjc_get_rx_mbuf(chan, NULL, ITJC_MB_CURR);
1125 HDLC_DECODE(*dst++, len, tmp, tmp2, blevel, ib, crc, flag,
1128 src = itjc_ring_add(src, 1);
1132 panic("itjc_dma_rx_intr: nfrcmd with "
1133 "valid current frame");
1135 dst = itjc_get_rx_mbuf(chan, &dst_end, ITJC_MB_NEW);
1136 len = dst_end - dst;
1139 len = BCH_MAX_DATALEN - len;
1141 if ((!len) || (len > BCH_MAX_DATALEN))
1144 * NOTE: frames without any data, only crc
1145 * field, should be silently discared.
1147 NDBGL1(L1_S_MSG, "itjc_dma_rx_intr: "
1148 "bad frame (len=%d, unit=%d)",
1151 itjc_free_rx_mbuf(chan);
1159 "CRC (crc=0x%04x, len=%d, unit=%d)",
1160 crc, len, sc->sc_unit);
1162 itjc_free_rx_mbuf(chan);
1167 itjc_put_rx_mbuf(sc, chan, len);
1174 NDBGL1(L1_S_ERR, "Read Abort (unit=%d)", sc->sc_unit);
1176 itjc_free_rx_mbuf(chan);
1181 NDBGL1(L1_S_ERR, "RDO (unit=%d) dma=%d src=%d",
1182 sc->sc_unit, dma, src);
1184 itjc_free_rx_mbuf(chan);
1192 itjc_save_rx_mbuf(chan, dst);
1194 ctx->next_read = src;
1195 ctx->hdlc_blevel= blevel;
1196 ctx->hdlc_flag = flag;
1197 ctx->hdlc_len = len;
1198 ctx->hdlc_tmp = tmp;
1199 ctx->hdlc_crc = crc;
1205 * The HDLC side of itjc_dma_tx_intr. We made a separate function
1206 * to improve readability and (perhaps) help the compiler with
1207 * register allocation.
1210 itjc_hdlc_encode(struct l1_softc *sc, l1_bchan_state_t *chan,
1211 dma_tx_context_t * ctx)
1220 u_int16_t saved_len,
1234 saved_len = len = itjc_get_tx_mbuf(sc, chan, &src, ITJC_MB_CURR);
1236 filled = ctx->filled;
1237 flag = ctx->hdlc_flag;
1239 if (src == NULL && flag == 2 && filled >= ITJC_RING_WORDS)
1242 tx_restart = (flag == 2 && src != NULL);
1243 xdu = itjc_xdu(sc, chan, ctx, &dst, &dst_end, tx_restart);
1248 crc = ctx->hdlc_crc;
1249 tmp = ctx->hdlc_tmp;
1250 blevel = ctx->hdlc_blevel;
1256 NDBGL1(L1_H_XFRERR, "XDU");
1260 * Abort the current frame and
1261 * prepare for a full restart.
1263 itjc_free_tx_mbufs(chan);
1264 saved_len = len = filled = 0;
1265 flag = (u_int8_t)-2;
1267 else if (filled < ITJC_RING_SLOT_WORDS)
1270 * A little garbage may have been retransmitted.
1271 * Send an abort before any new data.
1274 flag = (u_int8_t)-2;
1281 while (dst != dst_end)
1284 *src++, len, tmp, tmp2, blevel, ib, crc, flag,
1286 if ((len = saved_len) == 0)
1287 len = itjc_get_tx_mbuf(sc, chan, &src,
1292 ctx->next_frame = dst;
1294 flag_byte = itjc_rotate_hdlc_flag(blevel);
1296 for (dst_end1 = itjc_ring_sub(dst_end, 1);
1298 dst = itjc_ring_add(dst, 1))
1300 ring[dst] = flag_byte;
1307 ctx->state = ITJC_TS_ACTIVE;
1311 len = itjc_get_tx_mbuf(sc, chan, &src, ITJC_MB_NEXT);
1314 ring[dst] = (u_int8_t)tmp;
1315 dst = itjc_ring_add(dst, 1);
1320 ctx->hdlc_blevel = blevel;
1321 ctx->hdlc_flag = flag;
1322 ctx->hdlc_tmp = tmp;
1323 ctx->hdlc_crc = crc;
1326 ctx->filled = filled;
1327 ctx->next_write = dst;
1329 itjc_save_tx_mbuf(chan, src, len);
1334 itjc_dma_tx_intr(struct l1_softc *sc, l1_bchan_state_t *chan,
1335 dma_tx_context_t * ctx)
1348 if (ctx->state == ITJC_TS_IDLE)
1351 if (chan->bprot != BPROT_NONE)
1353 itjc_hdlc_encode(sc, chan, ctx);
1358 filled = ctx->filled;
1360 len = itjc_get_tx_mbuf(sc, chan, &src, ITJC_MB_CURR);
1362 if (len == 0 && filled >= ITJC_RING_WORDS)
1365 xdu = itjc_xdu(sc, chan, ctx, &dst, &dst_end, len != 0);
1367 if (xdu && filled < ITJC_RING_WORDS)
1369 NDBGL1(L1_H_XFRERR, "XDU");
1377 ctx->state = ITJC_TS_ACTIVE;
1379 data_end = src + len;
1380 while (dst != dst_end)
1382 ring[dst] = *src++; --len;
1384 dst = itjc_ring_add(dst, 1);
1386 if (src >= data_end)
1388 len = itjc_get_tx_mbuf(sc, chan, &src, ITJC_MB_NEXT);
1390 len = itjc_get_tx_mbuf(sc, chan,
1398 data_end = src + len;
1402 itjc_save_tx_mbuf(chan, src, len);
1407 ctx->next_frame = dst;
1409 for (; dst != dst_end; dst = itjc_ring_add(dst, 1))
1411 ring[dst] = ITJC_TEL_SILENCE_BYTE;
1415 ctx->next_write = dst;
1416 ctx->filled = filled;
1423 /*---------------------------------------------------------------------------*
1424 * NetJet fifo read/write routines.
1425 *---------------------------------------------------------------------------*/
1428 itjc_read_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
1430 bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[0]);
1431 bus_space_tag_t t = rman_get_bustag(sc->sc_resources.io_base[0]);
1433 if (what != ISIC_WHAT_ISAC)
1434 panic("itjc_write_fifo: Trying to read from HSCX fifo.\n");
1436 itjc_set_pib_addr_msb(0);
1437 itjc_read_multi_1(PIB_OFFSET, buf, size);
1442 itjc_write_fifo(struct l1_softc *sc, int what, void *buf, size_t size)
1444 bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[0]);
1445 bus_space_tag_t t = rman_get_bustag(sc->sc_resources.io_base[0]);
1447 if (what != ISIC_WHAT_ISAC)
1448 panic("itjc_write_fifo: Trying to write to HSCX fifo.\n");
1450 itjc_set_pib_addr_msb(0);
1451 itjc_write_multi_1(PIB_OFFSET, buf, size);
1455 /*---------------------------------------------------------------------------*
1456 * Read an ISAC register.
1457 *---------------------------------------------------------------------------*/
1459 itjc_read_reg(struct l1_softc *sc, int what, bus_size_t offs)
1461 bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[0]);
1462 bus_space_tag_t t = rman_get_bustag(sc->sc_resources.io_base[0]);
1464 if (what != ISIC_WHAT_ISAC)
1466 panic("itjc_read_reg: what(%d) != ISIC_WHAT_ISAC\n",
1471 itjc_set_pib_addr_msb(offs);
1472 return itjc_read_1(itjc_pib_2_pci(offs));
1476 /*---------------------------------------------------------------------------*
1477 * Write an ISAC register.
1478 *---------------------------------------------------------------------------*/
1480 itjc_write_reg(struct l1_softc *sc, int what, bus_size_t offs, u_int8_t data)
1482 bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[0]);
1483 bus_space_tag_t t = rman_get_bustag(sc->sc_resources.io_base[0]);
1485 if (what != ISIC_WHAT_ISAC)
1487 panic("itjc_write_reg: what(%d) != ISIC_WHAT_ISAC\n",
1492 itjc_set_pib_addr_msb(offs);
1493 itjc_write_1(itjc_pib_2_pci(offs), data);
1497 /*---------------------------------------------------------------------------*
1498 * itjc_probe - probe for a card.
1499 *---------------------------------------------------------------------------*/
1500 static int itjc_probe(device_t dev)
1502 u_int16_t vid = pci_get_vendor(dev),
1503 did = pci_get_device(dev);
1505 if ((vid == PCI_TJNET_VID) && (did == PCI_TJ300_DID))
1507 device_set_desc(dev, "NetJet-S");
1515 /*---------------------------------------------------------------------------*
1516 * itjc_attach - attach a (previously probed) card.
1517 *---------------------------------------------------------------------------*/
1519 itjc_attach(device_t dev)
1521 bus_space_handle_t h;
1524 struct l1_softc *sc = device_get_softc(dev);
1526 u_int16_t vid = pci_get_vendor(dev),
1527 did = pci_get_device(dev);
1529 int unit = device_get_unit(dev),
1535 dma_context_t *ctx = &dma_context[unit];
1538 bzero(sc, sizeof(struct l1_softc));
1540 /* Probably not really required. */
1541 if (unit > ITJC_MAXUNIT)
1543 printf("itjc%d: Error, unit > ITJC_MAXUNIT!\n", unit);
1548 if (!(vid == PCI_TJNET_VID && did == PCI_TJ300_DID))
1550 printf("itjc%d: unknown device (%04X,%04X)!\n", unit, vid, did);
1554 itjc_scp[unit] = sc;
1556 sc->sc_resources.io_rid[0] = PCIR_MAPS+0;
1557 sc->sc_resources.io_base[0] = bus_alloc_resource(dev, SYS_RES_IOPORT,
1558 &sc->sc_resources.io_rid[0], 0, ~0, 1, RF_ACTIVE);
1560 if (sc->sc_resources.io_base[0] == NULL)
1562 printf("itjc%d: couldn't map IO port\n", unit);
1567 h = rman_get_bushandle(sc->sc_resources.io_base[0]);
1568 t = rman_get_bustag(sc->sc_resources.io_base[0]);
1572 /* Allocate interrupt. */
1573 sc->sc_resources.irq_rid = 0;
1574 sc->sc_resources.irq = bus_alloc_resource(dev, SYS_RES_IRQ,
1575 &sc->sc_resources.irq_rid, 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE);
1577 if (sc->sc_resources.irq == NULL)
1579 printf("itjc%d: couldn't map interrupt\n", unit);
1586 error = bus_setup_intr(dev, sc->sc_resources.irq, 0,
1587 itjc_intr, sc, &ih, NULL);
1591 printf("itjc%d: couldn't set up irq handler\n", unit);
1597 * Reset the ASIC & the ISAC.
1599 itjc_write_1(TIGER_RESET_PIB_CL_TIME, TIGER_RESET_ALL);
1601 DELAY(SEC_DELAY/100); /* Give it 10 ms to reset ...*/
1603 itjc_write_1(TIGER_RESET_PIB_CL_TIME,
1604 TIGER_SELF_ADDR_DMA | TIGER_PIB_3_CYCLES);
1606 DELAY(SEC_DELAY/100); /* ... and more 10 to recover. */
1609 * First part of DMA initialization. Create & map the memory
1610 * pool that will be used to bear the rx & tx ring buffers.
1612 ctx->state = ITJC_DS_LOADING;
1614 error = bus_dma_tag_create(
1618 BUS_SPACE_MAXADDR_32BIT, /* lowaddr*/
1619 BUS_SPACE_MAXADDR, /* highaddr*/
1621 NULL, /* filterarg*/
1622 ITJC_DMA_POOL_BYTES, /* maxsize*/
1624 ITJC_DMA_POOL_BYTES, /* maxsegsz*/
1625 BUS_DMA_ALLOCNOW | BUS_DMA_COHERENT, /* flags*/
1630 printf("itjc%d: couldn't create bus DMA tag.\n", unit);
1636 error = bus_dmamem_alloc(
1637 ctx->tag, /* DMA tag */
1638 (void **)&ctx->pool, /* KV addr of the allocated memory */
1639 BUS_DMA_NOWAIT | BUS_DMA_COHERENT, /* flags */
1640 &ctx->map); /* KV <-> PCI map */
1646 * Load the KV <-> PCI map so the device sees the same
1647 * memory segment as pointed by pool. Note: since the
1648 * load may happen assyncronously (completion indicated by
1649 * the execution of the callback function) we have to
1650 * delay the initialization of the DMA engine to a moment we
1651 * actually have the proper bus addresses to feed the Tiger
1652 * and our DMA control blocks. This will be done in
1653 * itjc_bchannel_setup via a call to itjc_dma_start.
1656 ctx->tag, /* DMA tag */
1657 ctx->map, /* DMA map */
1658 ctx->pool, /* KV addr of buffer */
1659 ITJC_DMA_POOL_BYTES, /* buffer size */
1660 itjc_map_callback, /* this receive the bus addr/error */
1661 ctx, /* callback aux arg */
1667 * Setup the AUX port so we can talk to the ISAC.
1669 itjc_write_1(TIGER_AUX_PORT_CNTL, TIGER_AUX_NJ_DEFAULT);
1670 itjc_write_1(TIGER_INT1_MASK, TIGER_ISAC_INT);
1673 * From now on, almost like a `normal' ISIC driver.
1678 ISAC_BASE = (caddr_t)ISIC_WHAT_ISAC;
1680 HSCX_A_BASE = (caddr_t)ISIC_WHAT_HSCXA;
1681 HSCX_B_BASE = (caddr_t)ISIC_WHAT_HSCXB;
1683 /* setup access routines */
1685 sc->clearirq = NULL;
1686 sc->readreg = itjc_read_reg;
1687 sc->writereg = itjc_write_reg;
1689 sc->readfifo = itjc_read_fifo;
1690 sc->writefifo = itjc_write_fifo;
1692 /* setup card type */
1694 sc->sc_cardtyp = CARD_TYPEP_NETJET_S;
1696 /* setup IOM bus type */
1698 sc->sc_bustyp = BUS_TYPE_IOM2;
1700 /* set up some other miscellaneous things */
1702 sc->sc_bfifolen = 2 * ITJC_RING_SLOT_WORDS;
1704 printf("itjc%d: ISAC 2186 Version 1.1 (IOM-2)\n", unit);
1709 /* init the "HSCX" */
1710 itjc_bchannel_setup(sc->sc_unit, HSCX_CH_A, BPROT_NONE, 0);
1712 itjc_bchannel_setup(sc->sc_unit, HSCX_CH_B, BPROT_NONE, 0);
1714 /* can't use the normal B-Channel stuff */
1715 itjc_init_linktab(sc);
1717 /* set trace level */
1719 sc->sc_trace = TRACE_OFF;
1721 sc->sc_state = ISAC_IDLE;
1730 sc->sc_freeflag = 0;
1732 sc->sc_obuf2 = NULL;
1733 sc->sc_freeflag2 = 0;
1735 callout_init(&sc->sc_T3_timeout);
1736 callout_init(&sc->sc_T4_timeout);
1738 /* init higher protocol layers */
1740 i4b_l1_mph_status_ind(L0ITJCUNIT(sc->sc_unit), STI_ATTACH,
1741 sc->sc_cardtyp, &itjc_l1mux_func);
1747 switch (res_init_level)
1750 bus_dmamap_unload(ctx->tag, ctx->map);
1754 bus_dmamem_free(ctx->tag, ctx->pool, ctx->map);
1755 bus_dmamap_destroy(ctx->tag, ctx->map);
1759 bus_dma_tag_destroy(ctx->tag);
1763 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_resources.irq);
1767 bus_release_resource(dev, SYS_RES_IOPORT, PCIR_MAPS+0,
1768 sc->sc_resources.io_base[0]);
1775 itjc_scp[unit] = NULL;
1782 /*---------------------------------------------------------------------------*
1783 * itjc_intr - main interrupt service routine.
1784 *---------------------------------------------------------------------------*/
1786 itjc_intr(void *xsc)
1788 struct l1_softc *sc = xsc;
1789 l1_bchan_state_t *chan = &sc->sc_chan[0];
1790 dma_context_t *dma = &dma_context[sc->sc_unit];
1791 dma_rx_context_t *rxc = &dma_rx_context[sc->sc_unit][0];
1792 dma_tx_context_t *txc = &dma_tx_context[sc->sc_unit][0];
1794 bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[0]);
1795 bus_space_tag_t t = rman_get_bustag(sc->sc_resources.io_base[0]);
1797 /* Honor interrupts from successfully configured cards only. */
1798 if (dma->state < ITJC_DS_STOPPED)
1801 /* First, we check the ISAC... */
1802 if (! (itjc_read_1(TIGER_AUX_PORT_DATA) & TIGER_ISAC_INT_MASK))
1804 itjc_write_1(TIGER_INT1_STATUS, TIGER_ISAC_INT);
1805 NDBGL1(L1_H_IRQ, "ISAC");
1809 /* ... after what we always have a look at the DMA rings. */
1811 NDBGL1(L1_H_IRQ, "Tiger");
1813 itjc_read_1(TIGER_INT0_STATUS);
1814 itjc_write_1(TIGER_INT0_STATUS, TIGER_TARGET_ABORT_INT
1815 | TIGER_MASTER_ABORT_INT | TIGER_RD_END_INT
1816 | TIGER_RD_INT_INT | TIGER_WR_END_INT | TIGER_WR_INT_INT);
1818 itjc_dma_rx_intr(sc, chan, rxc);
1819 itjc_dma_tx_intr(sc, chan, txc);
1821 ++chan; ++rxc; ++txc;
1823 itjc_dma_rx_intr(sc, chan, rxc);
1824 itjc_dma_tx_intr(sc, chan, txc);
1828 /*---------------------------------------------------------------------------*
1829 * itjc_bchannel_setup - (Re)initialize and start/stop a Bchannel.
1830 *---------------------------------------------------------------------------*/
1832 itjc_bchannel_setup(int unit, int h_chan, int bprot, int activate)
1834 struct l1_softc *sc = itjc_scp[unit];
1835 l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1839 NDBGL1(L1_BCHAN, "unit=%d, channel=%d, %s",
1840 unit, h_chan, activate ? "activate" : "deactivate");
1843 * If we are deactivating the channel, we have to stop
1844 * the DMA before we reset the channel control structures.
1847 itjc_bchannel_dma_setup(sc, h_chan, activate);
1851 chan->state = HSCX_IDLE;
1853 chan->unit = sc->sc_unit; /* unit number */
1854 chan->channel = h_chan; /* B channel */
1855 chan->bprot = bprot; /* B channel protocol */
1859 i4b_Bcleanifq(&chan->rx_queue); /* clean rx queue */
1861 chan->rx_queue.ifq_maxlen = IFQ_MAXLEN;
1863 chan->rxcount = 0; /* reset rx counter */
1865 i4b_Bfreembuf(chan->in_mbuf); /* clean rx mbuf */
1867 chan->in_mbuf = NULL; /* reset mbuf ptr */
1868 chan->in_cbptr = NULL; /* reset mbuf curr ptr */
1869 chan->in_len = 0; /* reset mbuf data len */
1871 /* transmitter part */
1873 i4b_Bcleanifq(&chan->tx_queue); /* clean tx queue */
1875 chan->tx_queue.ifq_maxlen = IFQ_MAXLEN;
1877 chan->txcount = 0; /* reset tx counter */
1879 i4b_Bfreembuf(chan->out_mbuf_head); /* clean tx mbuf */
1881 chan->out_mbuf_head = NULL; /* reset head mbuf ptr */
1882 chan->out_mbuf_cur = NULL; /* reset current mbuf ptr */
1883 chan->out_mbuf_cur_ptr = NULL; /* reset current mbuf data ptr */
1884 chan->out_mbuf_cur_len = 0; /* reset current mbuf data cnt */
1887 * Only setup & start the DMA after all other channel
1888 * control structures are in place.
1891 itjc_bchannel_dma_setup(sc, h_chan, activate);
1897 /*---------------------------------------------------------------------------*
1898 * itjc_bchannel_start - Signal us we have more data to send.
1899 *---------------------------------------------------------------------------*/
1901 itjc_bchannel_start(int unit, int h_chan)
1905 * I disabled this routine because it was causing crashes when
1906 * this driver was used with the ISP (kernel SPPP) protocol driver.
1907 * The scenario is reproductible:
1908 * Use the -link1 (dial on demand) ifconfig option.
1909 * Start an interactive TCP connection to somewhere.
1910 * Wait until the PPP connection times out and is dropped.
1911 * Try to send something on the TCP connection.
1912 * The machine will print some garbage and halt or reboot
1913 * (no panic messages).
1915 * I've nailed down the problem to the fact that this routine
1916 * was being called before the B channel had been setup again.
1918 * For now, I don't have a good solution other than this one.
1919 * But, don't despair. The impact of it is unnoticeable.
1922 struct l1_softc *sc = itjc_scp[unit];
1923 l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
1924 dma_tx_context_t *txc = &dma_tx_context[unit][h_chan];
1928 if (chan->state & HSCX_TX_ACTIVE)
1934 itjc_dma_tx_intr(sc, chan, txc);
1941 /*---------------------------------------------------------------------------*
1942 * itjc_shutdown - Stop the driver and reset the card.
1943 *---------------------------------------------------------------------------*/
1945 itjc_shutdown(device_t dev)
1947 struct l1_softc *sc = device_get_softc(dev);
1948 bus_space_handle_t h = rman_get_bushandle(sc->sc_resources.io_base[0]);
1949 bus_space_tag_t t = rman_get_bustag(sc->sc_resources.io_base[0]);
1952 * Stop the DMA the nice and easy way.
1954 itjc_bchannel_setup(sc->sc_unit, 0, BPROT_NONE, 0);
1955 itjc_bchannel_setup(sc->sc_unit, 1, BPROT_NONE, 0);
1960 itjc_write_1(TIGER_RESET_PIB_CL_TIME, TIGER_RESET_ALL);
1962 DELAY(SEC_DELAY/100); /* Give it 10 ms to reset ...*/
1964 itjc_write_1(TIGER_RESET_PIB_CL_TIME,
1965 TIGER_SELF_ADDR_DMA | TIGER_LATCH_DMA_INT | TIGER_PIB_3_CYCLES);
1967 DELAY(SEC_DELAY/100); /* ... and more 10 to recover */
1971 /*---------------------------------------------------------------------------*
1972 * itjc_ret_linktab - Return the address of itjc drivers linktab.
1973 *---------------------------------------------------------------------------*/
1975 itjc_ret_linktab(int unit, int channel)
1977 struct l1_softc *sc = itjc_scp[unit];
1978 l1_bchan_state_t *chan = &sc->sc_chan[channel];
1980 return(&chan->isic_isdn_linktab);
1983 /*---------------------------------------------------------------------------*
1984 * itjc_set_linktab - Set the driver linktab in the b channel softc.
1985 *---------------------------------------------------------------------------*/
1987 itjc_set_linktab(int unit, int channel, drvr_link_t *dlt)
1989 struct l1_softc *sc = itjc_scp[unit];
1990 l1_bchan_state_t *chan = &sc->sc_chan[channel];
1992 chan->isic_drvr_linktab = dlt;
1996 /*---------------------------------------------------------------------------*
1997 * itjc_init_linktab - Initialize our local linktab.
1998 *---------------------------------------------------------------------------*/
2000 itjc_init_linktab(struct l1_softc *sc)
2002 l1_bchan_state_t *chan = &sc->sc_chan[HSCX_CH_A];
2003 isdn_link_t *lt = &chan->isic_isdn_linktab;
2005 /* make sure the hardware driver is known to layer 4 */
2006 /* avoid overwriting if already set */
2007 if (ctrl_types[CTRL_PASSIVE].set_linktab == NULL)
2009 ctrl_types[CTRL_PASSIVE].set_linktab = itjc_set_linktab;
2010 ctrl_types[CTRL_PASSIVE].get_linktab = itjc_ret_linktab;
2014 lt->unit = sc->sc_unit;
2015 lt->channel = HSCX_CH_A;
2016 lt->bch_config = itjc_bchannel_setup;
2017 lt->bch_tx_start = itjc_bchannel_start;
2018 lt->bch_stat = itjc_bchannel_stat;
2019 lt->tx_queue = &chan->tx_queue;
2021 /* used by non-HDLC data transfers, i.e. telephony drivers */
2022 lt->rx_queue = &chan->rx_queue;
2024 /* used by HDLC data transfers, i.e. ipr and isp drivers */
2025 lt->rx_mbuf = &chan->in_mbuf;
2027 chan = &sc->sc_chan[HSCX_CH_B];
2028 lt = &chan->isic_isdn_linktab;
2030 lt->unit = sc->sc_unit;
2031 lt->channel = HSCX_CH_B;
2032 lt->bch_config = itjc_bchannel_setup;
2033 lt->bch_tx_start = itjc_bchannel_start;
2034 lt->bch_stat = itjc_bchannel_stat;
2035 lt->tx_queue = &chan->tx_queue;
2037 /* used by non-HDLC data transfers, i.e. telephony drivers */
2038 lt->rx_queue = &chan->rx_queue;
2040 /* used by HDLC data transfers, i.e. ipr and isp drivers */
2041 lt->rx_mbuf = &chan->in_mbuf;
2045 /*---------------------------------------------------------------------------*
2046 * itjc_bchannel_stat - Collect link statistics for a given B channel.
2047 *---------------------------------------------------------------------------*/
2049 itjc_bchannel_stat(int unit, int h_chan, bchan_statistics_t *bsp)
2051 struct l1_softc *sc = itjc_scp[unit];
2052 l1_bchan_state_t *chan = &sc->sc_chan[h_chan];
2056 bsp->outbytes = chan->txcount;
2057 bsp->inbytes = chan->rxcount;
2066 /*---------------------------------------------------------------------------*
2067 * Netjet - ISAC interrupt routine.
2068 *---------------------------------------------------------------------------*/
2070 itjc_isac_intr(struct l1_softc *sc)
2076 /* get isac irq status */
2077 irq_stat = ISAC_READ(I_ISTA);
2080 itjc_isac_irq(sc, irq_stat); /* isac handler */
2084 ISAC_WRITE(I_MASK, 0xff);
2088 ISAC_WRITE(I_MASK, ISAC_IMASK);
2092 /*---------------------------------------------------------------------------*
2093 * itjc_recover - Try to recover from ISAC irq lockup.
2094 *---------------------------------------------------------------------------*/
2096 itjc_recover(struct l1_softc *sc)
2100 /* get isac irq status */
2102 byte = ISAC_READ(I_ISTA);
2104 NDBGL1(L1_ERROR, " ISAC: ISTA = 0x%x", byte);
2106 if(byte & ISAC_ISTA_EXI)
2107 NDBGL1(L1_ERROR, " ISAC: EXIR = 0x%x", (u_char)ISAC_READ(I_EXIR));
2109 if(byte & ISAC_ISTA_CISQ)
2111 byte = ISAC_READ(I_CIRR);
2113 NDBGL1(L1_ERROR, " ISAC: CISQ = 0x%x", byte);
2115 if(byte & ISAC_CIRR_SQC)
2116 NDBGL1(L1_ERROR, " ISAC: SQRR = 0x%x", (u_char)ISAC_READ(I_SQRR));
2119 NDBGL1(L1_ERROR, " ISAC: IMASK = 0x%x", ISAC_IMASK);
2121 ISAC_WRITE(I_MASK, 0xff);
2123 ISAC_WRITE(I_MASK, ISAC_IMASK);
2126 #endif /* NITJC > 0 */