2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mp_machdep.c,v 1.115.2.15 2003/03/14 21:22:35 jhb Exp $
26 * $DragonFly: src/sys/platform/pc32/i386/mp_machdep.c,v 1.60 2008/06/07 12:03:52 mneumann Exp $
31 #include <sys/param.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
34 #include <sys/sysctl.h>
35 #include <sys/malloc.h>
36 #include <sys/memrange.h>
37 #include <sys/cons.h> /* cngetc() */
38 #include <sys/machintr.h>
41 #include <vm/vm_param.h>
43 #include <vm/vm_kern.h>
44 #include <vm/vm_extern.h>
46 #include <vm/vm_map.h>
52 #include <machine/smp.h>
53 #include <machine_base/apic/apicreg.h>
54 #include <machine/atomic.h>
55 #include <machine/cpufunc.h>
56 #include <machine_base/apic/mpapic.h>
57 #include <machine/psl.h>
58 #include <machine/segments.h>
59 #include <machine/tss.h>
60 #include <machine/specialreg.h>
61 #include <machine/globaldata.h>
63 #include <machine/md_var.h> /* setidt() */
64 #include <machine_base/icu/icu.h> /* IPIs */
65 #include <machine_base/isa/intr_machdep.h> /* IPIs */
67 #define FIXUP_EXTRA_APIC_INTS 8 /* additional entries we may create */
69 #define WARMBOOT_TARGET 0
70 #define WARMBOOT_OFF (KERNBASE + 0x0467)
71 #define WARMBOOT_SEG (KERNBASE + 0x0469)
73 #define BIOS_BASE (0xf0000)
74 #define BIOS_SIZE (0x10000)
75 #define BIOS_COUNT (BIOS_SIZE/4)
77 #define CMOS_REG (0x70)
78 #define CMOS_DATA (0x71)
79 #define BIOS_RESET (0x0f)
80 #define BIOS_WARM (0x0a)
82 #define PROCENTRY_FLAG_EN 0x01
83 #define PROCENTRY_FLAG_BP 0x02
84 #define IOAPICENTRY_FLAG_EN 0x01
87 /* MP Floating Pointer Structure */
88 typedef struct MPFPS {
101 /* MP Configuration Table Header */
102 typedef struct MPCTH {
104 u_short base_table_length;
108 u_char product_id[12];
109 void *oem_table_pointer;
110 u_short oem_table_size;
113 u_short extended_table_length;
114 u_char extended_table_checksum;
119 typedef struct PROCENTRY {
124 u_long cpu_signature;
125 u_long feature_flags;
130 typedef struct BUSENTRY {
136 typedef struct IOAPICENTRY {
142 } *io_apic_entry_ptr;
144 typedef struct INTENTRY {
154 /* descriptions of MP basetable entries */
155 typedef struct BASETABLE_ENTRY {
162 * this code MUST be enabled here and in mpboot.s.
163 * it follows the very early stages of AP boot by placing values in CMOS ram.
164 * it NORMALLY will never be needed and thus the primitive method for enabling.
167 #if defined(CHECK_POINTS)
168 #define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA))
169 #define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D)))
171 #define CHECK_INIT(D); \
172 CHECK_WRITE(0x34, (D)); \
173 CHECK_WRITE(0x35, (D)); \
174 CHECK_WRITE(0x36, (D)); \
175 CHECK_WRITE(0x37, (D)); \
176 CHECK_WRITE(0x38, (D)); \
177 CHECK_WRITE(0x39, (D));
179 #define CHECK_PRINT(S); \
180 kprintf("%s: %d, %d, %d, %d, %d, %d\n", \
189 #else /* CHECK_POINTS */
191 #define CHECK_INIT(D)
192 #define CHECK_PRINT(S)
194 #endif /* CHECK_POINTS */
197 * Values to send to the POST hardware.
199 #define MP_BOOTADDRESS_POST 0x10
200 #define MP_PROBE_POST 0x11
201 #define MPTABLE_PASS1_POST 0x12
203 #define MP_START_POST 0x13
204 #define MP_ENABLE_POST 0x14
205 #define MPTABLE_PASS2_POST 0x15
207 #define START_ALL_APS_POST 0x16
208 #define INSTALL_AP_TRAMP_POST 0x17
209 #define START_AP_POST 0x18
211 #define MP_ANNOUNCE_POST 0x19
213 static int need_hyperthreading_fixup;
214 static u_int logical_cpus;
215 u_int logical_cpus_mask;
217 /** XXX FIXME: where does this really belong, isa.h/isa.c perhaps? */
218 int current_postcode;
220 /** XXX FIXME: what system files declare these??? */
221 extern struct region_descriptor r_gdt, r_idt;
223 int bsp_apic_ready = 0; /* flags useability of BSP apic */
224 int mp_naps; /* # of Applications processors */
225 int mp_nbusses; /* # of busses */
227 int mp_napics; /* # of IO APICs */
229 int boot_cpu_id; /* designated BSP */
230 vm_offset_t cpu_apic_address;
232 vm_offset_t io_apic_address[NAPICID]; /* NAPICID is more than enough */
233 u_int32_t *io_apic_versions;
237 u_int32_t cpu_apic_versions[MAXCPU];
239 extern int64_t tsc_offsets[];
241 extern u_long ebda_addr;
244 struct apic_intmapinfo int_to_apicintpin[APIC_INTMAPSIZE];
248 * APIC ID logical/physical mapping structures.
249 * We oversize these to simplify boot-time config.
251 int cpu_num_to_apic_id[NAPICID];
253 int io_num_to_apic_id[NAPICID];
255 int apic_id_to_logical[NAPICID];
257 /* AP uses this during bootstrap. Do not staticize. */
261 /* Hotwire a 0->4MB V==P mapping */
262 extern pt_entry_t *KPTphys;
265 * SMP page table page. Setup by locore to point to a page table
266 * page from which we allocate per-cpu privatespace areas io_apics,
270 #define IO_MAPPING_START_INDEX \
271 (SMP_MAXCPU * sizeof(struct privatespace) / PAGE_SIZE)
273 extern pt_entry_t *SMPpt;
274 static int SMPpt_alloc_index = IO_MAPPING_START_INDEX;
276 struct pcb stoppcbs[MAXCPU];
279 * Local data and functions.
282 static u_int boot_address;
283 static u_int base_memory;
284 static int mp_finish;
286 static mpfps_t mpfps;
287 static int search_for_sig(u_int32_t target, int count);
288 static void mp_enable(u_int boot_addr);
290 static void mptable_hyperthread_fixup(u_int id_mask);
291 static void mptable_pass1(void);
292 static int mptable_pass2(void);
293 static void default_mp_table(int type);
294 static void fix_mp_table(void);
296 static void setup_apic_irq_mapping(void);
297 static int apic_int_is_bus_type(int intr, int bus_type);
299 static int start_all_aps(u_int boot_addr);
300 static void install_ap_tramp(u_int boot_addr);
301 static int start_ap(struct mdglobaldata *gd, u_int boot_addr);
303 static cpumask_t smp_startup_mask = 1; /* which cpus have been started */
304 cpumask_t smp_active_mask = 1; /* which cpus are ready for IPIs etc? */
305 SYSCTL_INT(_machdep, OID_AUTO, smp_active, CTLFLAG_RD, &smp_active_mask, 0, "");
308 * Calculate usable address in base memory for AP trampoline code.
311 mp_bootaddress(u_int basemem)
313 POSTCODE(MP_BOOTADDRESS_POST);
315 base_memory = basemem;
317 boot_address = base_memory & ~0xfff; /* round down to 4k boundary */
318 if ((base_memory - boot_address) < bootMP_size)
319 boot_address -= 4096; /* not enough, lower by 4k */
326 * Look for an Intel MP spec table (ie, SMP capable hardware).
335 * Make sure our SMPpt[] page table is big enough to hold all the
338 KKASSERT(IO_MAPPING_START_INDEX < NPTEPG - 2);
340 POSTCODE(MP_PROBE_POST);
342 /* see if EBDA exists */
343 if (ebda_addr != 0) {
344 /* search first 1K of EBDA */
345 target = (u_int32_t)ebda_addr;
346 if ((x = search_for_sig(target, 1024 / 4)) > 0)
349 /* last 1K of base memory, effective 'top of base' passed in */
350 target = (u_int32_t)(base_memory - 0x400);
351 if ((x = search_for_sig(target, 1024 / 4)) > 0)
355 /* search the BIOS */
356 target = (u_int32_t)BIOS_BASE;
357 if ((x = search_for_sig(target, BIOS_COUNT)) > 0)
366 * Startup the SMP processors.
371 POSTCODE(MP_START_POST);
372 mp_enable(boot_address);
377 * Print various information about the SMP system hardware and setup.
384 POSTCODE(MP_ANNOUNCE_POST);
386 kprintf("DragonFly/MP: Multiprocessor motherboard\n");
387 kprintf(" cpu0 (BSP): apic id: %2d", CPU_TO_ID(0));
388 kprintf(", version: 0x%08x", cpu_apic_versions[0]);
389 kprintf(", at 0x%08x\n", cpu_apic_address);
390 for (x = 1; x <= mp_naps; ++x) {
391 kprintf(" cpu%d (AP): apic id: %2d", x, CPU_TO_ID(x));
392 kprintf(", version: 0x%08x", cpu_apic_versions[x]);
393 kprintf(", at 0x%08x\n", cpu_apic_address);
397 for (x = 0; x < mp_napics; ++x) {
398 kprintf(" io%d (APIC): apic id: %2d", x, IO_TO_ID(x));
399 kprintf(", version: 0x%08x", io_apic_versions[x]);
400 kprintf(", at 0x%08x\n", io_apic_address[x]);
403 kprintf(" Warning: APIC I/O disabled\n");
408 * AP cpu's call this to sync up protected mode.
410 * WARNING! We must ensure that the cpu is sufficiently initialized to
411 * be able to use to the FP for our optimized bzero/bcopy code before
412 * we enter more mainstream C code.
414 * WARNING! %fs is not set up on entry. This routine sets up %fs.
420 int x, myid = bootAP;
422 struct mdglobaldata *md;
423 struct privatespace *ps;
425 ps = &CPU_prvspace[myid];
427 gdt_segs[GPRIV_SEL].ssd_base = (int)ps;
428 gdt_segs[GPROC0_SEL].ssd_base =
429 (int) &ps->mdglobaldata.gd_common_tss;
430 ps->mdglobaldata.mi.gd_prvspace = ps;
432 for (x = 0; x < NGDT; x++) {
433 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd);
436 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1;
437 r_gdt.rd_base = (int) &gdt[myid * NGDT];
438 lgdt(&r_gdt); /* does magic intra-segment return */
443 mdcpu->gd_currentldt = _default_ldt;
445 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL);
446 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS;
448 md = mdcpu; /* loaded through %fs:0 (mdglobaldata.mi.gd_prvspace)*/
450 md->gd_common_tss.tss_esp0 = 0; /* not used until after switch */
451 md->gd_common_tss.tss_ss0 = GSEL(GDATA_SEL, SEL_KPL);
452 md->gd_common_tss.tss_ioopt = (sizeof md->gd_common_tss) << 16;
453 md->gd_tss_gdt = &gdt[myid * NGDT + GPROC0_SEL].sd;
454 md->gd_common_tssd = *md->gd_tss_gdt;
458 * Set to a known state:
459 * Set by mpboot.s: CR0_PG, CR0_PE
460 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM
463 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM);
465 pmap_set_opt(); /* PSE/4MB pages, etc */
467 /* set up CPU registers and state */
470 /* set up FPU state on the AP */
471 npxinit(__INITIAL_NPXCW__);
473 /* set up SSE registers */
477 /*******************************************************************
478 * local functions and data
482 * start the SMP system
485 mp_enable(u_int boot_addr)
493 POSTCODE(MP_ENABLE_POST);
495 mpfps = (mpfps_t)mp_probe();
497 panic("mp_enable: mp_probe failed\n");
499 /* turn on 4MB of V == P addressing so we can get to MP table */
500 *(int *)PTD = PG_V | PG_RW | ((uintptr_t)(void *)KPTphys & PG_FRAME);
504 * We can safely map physical memory into SMPpt after
505 * mptable_pass1() completes.
509 if (cpu_apic_address == 0)
510 panic("mp_enable: no local apic!\n");
512 /* examine the MP table for needed info, uses physical addresses */
518 /* local apic is mapped on last page */
519 SMPpt[NPTEPG - 1] = (pt_entry_t)(PG_V | PG_RW | PG_N |
520 pmap_get_pgeflag() | (cpu_apic_address & PG_FRAME));
522 /* can't process default configs till the CPU APIC is pmapped */
526 /* post scan cleanup */
531 setup_apic_irq_mapping();
533 /* fill the LOGICAL io_apic_versions table */
534 for (apic = 0; apic < mp_napics; ++apic) {
535 ux = io_apic_read(apic, IOAPIC_VER);
536 io_apic_versions[apic] = ux;
537 io_apic_set_id(apic, IO_TO_ID(apic));
540 /* program each IO APIC in the system */
541 for (apic = 0; apic < mp_napics; ++apic)
542 if (io_apic_setup(apic) < 0)
543 panic("IO APIC setup failure");
548 * These are required for SMP operation
551 /* install a 'Spurious INTerrupt' vector */
552 setidt(XSPURIOUSINT_OFFSET, Xspuriousint,
553 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
555 /* install an inter-CPU IPI for TLB invalidation */
556 setidt(XINVLTLB_OFFSET, Xinvltlb,
557 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
559 /* install an inter-CPU IPI for IPIQ messaging */
560 setidt(XIPIQ_OFFSET, Xipiq,
561 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
563 /* install a timer vector */
564 setidt(XTIMER_OFFSET, Xtimer,
565 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
567 /* install an inter-CPU IPI for CPU stop/restart */
568 setidt(XCPUSTOP_OFFSET, Xcpustop,
569 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
571 /* start each Application Processor */
572 start_all_aps(boot_addr);
577 * look for the MP spec signature
580 /* string defined by the Intel MP Spec as identifying the MP table */
581 #define MP_SIG 0x5f504d5f /* _MP_ */
582 #define NEXT(X) ((X) += 4)
584 search_for_sig(u_int32_t target, int count)
590 KKASSERT(target != 0);
592 map_size = count * sizeof(u_int32_t);
593 addr = pmap_mapdev((vm_paddr_t)target, map_size);
596 for (x = 0; x < count; NEXT(x)) {
597 if (addr[x] == MP_SIG) {
598 /* make array index a byte index */
599 ret = target + (x * sizeof(u_int32_t));
604 pmap_unmapdev((vm_offset_t)addr, map_size);
609 static basetable_entry basetable_entry_types[] =
611 {0, 20, "Processor"},
618 typedef struct BUSDATA {
620 enum busTypes bus_type;
623 typedef struct INTDATA {
633 typedef struct BUSTYPENAME {
638 static bus_type_name bus_type_table[] =
644 {UNKNOWN_BUSTYPE, "---"},
647 {UNKNOWN_BUSTYPE, "---"},
648 {UNKNOWN_BUSTYPE, "---"},
649 {UNKNOWN_BUSTYPE, "---"},
650 {UNKNOWN_BUSTYPE, "---"},
651 {UNKNOWN_BUSTYPE, "---"},
653 {UNKNOWN_BUSTYPE, "---"},
654 {UNKNOWN_BUSTYPE, "---"},
655 {UNKNOWN_BUSTYPE, "---"},
656 {UNKNOWN_BUSTYPE, "---"},
658 {UNKNOWN_BUSTYPE, "---"}
660 /* from MP spec v1.4, table 5-1 */
661 static int default_data[7][5] =
663 /* nbus, id0, type0, id1, type1 */
664 {1, 0, ISA, 255, 255},
665 {1, 0, EISA, 255, 255},
666 {1, 0, EISA, 255, 255},
667 {1, 0, MCA, 255, 255},
669 {2, 0, EISA, 1, PCI},
675 static bus_datum *bus_data;
678 /* the IO INT data, one entry per possible APIC INTerrupt */
679 static io_int *io_apic_ints;
683 static int processor_entry (proc_entry_ptr entry, int cpu);
684 static int bus_entry (bus_entry_ptr entry, int bus);
686 static int io_apic_entry (io_apic_entry_ptr entry, int apic);
687 static int int_entry (int_entry_ptr entry, int intr);
689 static int lookup_bus_type (char *name);
693 * 1st pass on motherboard's Intel MP specification table.
699 * cpu_apic_address (common to all CPUs)
719 POSTCODE(MPTABLE_PASS1_POST);
722 panic("mptable_pass1: MP float pointer is not found\n");
725 /* clear various tables */
726 for (x = 0; x < NAPICID; ++x) {
727 io_apic_address[x] = ~0; /* IO APIC address table */
731 /* init everything to empty */
740 /* check for use of 'default' configuration */
741 if (mpfps->mpfb1 != 0) {
742 /* use default addresses */
743 cpu_apic_address = DEFAULT_APIC_BASE;
745 io_apic_address[0] = DEFAULT_IO_APIC_BASE;
748 /* fill in with defaults */
749 mp_naps = 2; /* includes BSP */
750 mp_nbusses = default_data[mpfps->mpfb1 - 1][0];
757 if ((cth = mpfps->pap) == 0)
758 panic("MP Configuration Table Header MISSING!");
760 cpu_apic_address = (vm_offset_t) cth->apic_address;
762 /* walk the table, recording info of interest */
763 totalSize = cth->base_table_length - sizeof(struct MPCTH);
764 position = (u_char *) cth + sizeof(struct MPCTH);
765 count = cth->entry_count;
768 switch (type = *(u_char *) position) {
769 case 0: /* processor_entry */
770 if (((proc_entry_ptr)position)->cpu_flags
771 & PROCENTRY_FLAG_EN) {
774 ((proc_entry_ptr)position)->apic_id;
777 case 1: /* bus_entry */
780 case 2: /* io_apic_entry */
782 if (((io_apic_entry_ptr)position)->apic_flags
783 & IOAPICENTRY_FLAG_EN)
784 io_apic_address[mp_napics++] =
785 (vm_offset_t)((io_apic_entry_ptr)
786 position)->apic_address;
789 case 3: /* int_entry */
794 case 4: /* int_entry */
797 panic("mpfps Base Table HOSED!");
801 totalSize -= basetable_entry_types[type].length;
802 position = (uint8_t *)position +
803 basetable_entry_types[type].length;
807 /* qualify the numbers */
808 if (mp_naps > MAXCPU) {
809 kprintf("Warning: only using %d of %d available CPUs!\n",
814 /* See if we need to fixup HT logical CPUs. */
815 mptable_hyperthread_fixup(id_mask);
817 --mp_naps; /* subtract the BSP */
822 * 2nd pass on motherboard's Intel MP specification table.
826 * ID_TO_IO(N), phy APIC ID to log CPU/IO table
827 * CPU_TO_ID(N), logical CPU to APIC ID table
828 * IO_TO_ID(N), logical IO to APIC ID table
835 struct PROCENTRY proc;
842 int apic, bus, cpu, intr;
845 POSTCODE(MPTABLE_PASS2_POST);
847 /* Initialize fake proc entry for use with HT fixup. */
848 bzero(&proc, sizeof(proc));
850 proc.cpu_flags = PROCENTRY_FLAG_EN;
853 MALLOC(io_apic_versions, u_int32_t *, sizeof(u_int32_t) * mp_napics,
855 MALLOC(ioapic, volatile ioapic_t **, sizeof(ioapic_t *) * mp_napics,
856 M_DEVBUF, M_WAITOK | M_ZERO);
857 MALLOC(io_apic_ints, io_int *, sizeof(io_int) * (nintrs + FIXUP_EXTRA_APIC_INTS),
860 MALLOC(bus_data, bus_datum *, sizeof(bus_datum) * mp_nbusses,
864 for (i = 0; i < mp_napics; i++) {
865 ioapic[i] = permanent_io_mapping(io_apic_address[i]);
869 /* clear various tables */
870 for (x = 0; x < NAPICID; ++x) {
871 CPU_TO_ID(x) = -1; /* logical CPU to APIC ID table */
873 ID_TO_IO(x) = -1; /* phy APIC ID to log CPU/IO table */
874 IO_TO_ID(x) = -1; /* logical IO to APIC ID table */
878 /* clear bus data table */
879 for (x = 0; x < mp_nbusses; ++x)
880 bus_data[x].bus_id = 0xff;
883 /* clear IO APIC INT table */
884 for (x = 0; x < (nintrs + 1); ++x) {
885 io_apic_ints[x].int_type = 0xff;
886 io_apic_ints[x].int_vector = 0xff;
890 /* setup the cpu/apic mapping arrays */
893 /* record whether PIC or virtual-wire mode */
894 machintr_setvar_simple(MACHINTR_VAR_IMCR_PRESENT, mpfps->mpfb2 & 0x80);
896 /* check for use of 'default' configuration */
897 if (mpfps->mpfb1 != 0)
898 return mpfps->mpfb1; /* return default configuration type */
900 if ((cth = mpfps->pap) == 0)
901 panic("MP Configuration Table Header MISSING!");
903 /* walk the table, recording info of interest */
904 totalSize = cth->base_table_length - sizeof(struct MPCTH);
905 position = (u_char *) cth + sizeof(struct MPCTH);
906 count = cth->entry_count;
907 apic = bus = intr = 0;
908 cpu = 1; /* pre-count the BSP */
911 switch (type = *(u_char *) position) {
913 if (processor_entry(position, cpu))
916 if (need_hyperthreading_fixup) {
918 * Create fake mptable processor entries
919 * and feed them to processor_entry() to
920 * enumerate the logical CPUs.
922 proc.apic_id = ((proc_entry_ptr)position)->apic_id;
923 for (i = 1; i < logical_cpus; i++) {
925 processor_entry(&proc, cpu);
926 logical_cpus_mask |= (1 << cpu);
932 if (bus_entry(position, bus))
937 if (io_apic_entry(position, apic))
943 if (int_entry(position, intr))
948 /* int_entry(position); */
951 panic("mpfps Base Table HOSED!");
955 totalSize -= basetable_entry_types[type].length;
956 position = (uint8_t *)position + basetable_entry_types[type].length;
959 if (boot_cpu_id == -1)
960 panic("NO BSP found!");
962 /* report fact that its NOT a default configuration */
967 * Check if we should perform a hyperthreading "fix-up" to
968 * enumerate any logical CPU's that aren't already listed
971 * XXX: We assume that all of the physical CPUs in the
972 * system have the same number of logical CPUs.
974 * XXX: We assume that APIC ID's are allocated such that
975 * the APIC ID's for a physical processor are aligned
976 * with the number of logical CPU's in the processor.
979 mptable_hyperthread_fixup(u_int id_mask)
983 /* Nothing to do if there is no HTT support. */
984 if ((cpu_feature & CPUID_HTT) == 0)
986 logical_cpus = (cpu_procinfo & CPUID_HTT_CORES) >> 16;
987 if (logical_cpus <= 1)
991 * For each APIC ID of a CPU that is set in the mask,
992 * scan the other candidate APIC ID's for this
993 * physical processor. If any of those ID's are
994 * already in the table, then kill the fixup.
996 for (id = 0; id <= MAXCPU; id++) {
997 if ((id_mask & 1 << id) == 0)
999 /* First, make sure we are on a logical_cpus boundary. */
1000 if (id % logical_cpus != 0)
1002 for (i = id + 1; i < id + logical_cpus; i++)
1003 if ((id_mask & 1 << i) != 0)
1008 * Ok, the ID's checked out, so enable the fixup. We have to fixup
1009 * mp_naps right now.
1011 need_hyperthreading_fixup = 1;
1012 mp_naps *= logical_cpus;
1018 assign_apic_irq(int apic, int intpin, int irq)
1022 if (int_to_apicintpin[irq].ioapic != -1)
1023 panic("assign_apic_irq: inconsistent table");
1025 int_to_apicintpin[irq].ioapic = apic;
1026 int_to_apicintpin[irq].int_pin = intpin;
1027 int_to_apicintpin[irq].apic_address = ioapic[apic];
1028 int_to_apicintpin[irq].redirindex = IOAPIC_REDTBL + 2 * intpin;
1030 for (x = 0; x < nintrs; x++) {
1031 if ((io_apic_ints[x].int_type == 0 ||
1032 io_apic_ints[x].int_type == 3) &&
1033 io_apic_ints[x].int_vector == 0xff &&
1034 io_apic_ints[x].dst_apic_id == IO_TO_ID(apic) &&
1035 io_apic_ints[x].dst_apic_int == intpin)
1036 io_apic_ints[x].int_vector = irq;
1041 revoke_apic_irq(int irq)
1047 if (int_to_apicintpin[irq].ioapic == -1)
1048 panic("revoke_apic_irq: inconsistent table");
1050 oldapic = int_to_apicintpin[irq].ioapic;
1051 oldintpin = int_to_apicintpin[irq].int_pin;
1053 int_to_apicintpin[irq].ioapic = -1;
1054 int_to_apicintpin[irq].int_pin = 0;
1055 int_to_apicintpin[irq].apic_address = NULL;
1056 int_to_apicintpin[irq].redirindex = 0;
1058 for (x = 0; x < nintrs; x++) {
1059 if ((io_apic_ints[x].int_type == 0 ||
1060 io_apic_ints[x].int_type == 3) &&
1061 io_apic_ints[x].int_vector != 0xff &&
1062 io_apic_ints[x].dst_apic_id == IO_TO_ID(oldapic) &&
1063 io_apic_ints[x].dst_apic_int == oldintpin)
1064 io_apic_ints[x].int_vector = 0xff;
1072 allocate_apic_irq(int intr)
1078 if (io_apic_ints[intr].int_vector != 0xff)
1079 return; /* Interrupt handler already assigned */
1081 if (io_apic_ints[intr].int_type != 0 &&
1082 (io_apic_ints[intr].int_type != 3 ||
1083 (io_apic_ints[intr].dst_apic_id == IO_TO_ID(0) &&
1084 io_apic_ints[intr].dst_apic_int == 0)))
1085 return; /* Not INT or ExtInt on != (0, 0) */
1088 while (irq < APIC_INTMAPSIZE &&
1089 int_to_apicintpin[irq].ioapic != -1)
1092 if (irq >= APIC_INTMAPSIZE)
1093 return; /* No free interrupt handlers */
1095 apic = ID_TO_IO(io_apic_ints[intr].dst_apic_id);
1096 intpin = io_apic_ints[intr].dst_apic_int;
1098 assign_apic_irq(apic, intpin, irq);
1099 io_apic_setup_intpin(apic, intpin);
1104 swap_apic_id(int apic, int oldid, int newid)
1111 return; /* Nothing to do */
1113 kprintf("Changing APIC ID for IO APIC #%d from %d to %d in MP table\n",
1114 apic, oldid, newid);
1116 /* Swap physical APIC IDs in interrupt entries */
1117 for (x = 0; x < nintrs; x++) {
1118 if (io_apic_ints[x].dst_apic_id == oldid)
1119 io_apic_ints[x].dst_apic_id = newid;
1120 else if (io_apic_ints[x].dst_apic_id == newid)
1121 io_apic_ints[x].dst_apic_id = oldid;
1124 /* Swap physical APIC IDs in IO_TO_ID mappings */
1125 for (oapic = 0; oapic < mp_napics; oapic++)
1126 if (IO_TO_ID(oapic) == newid)
1129 if (oapic < mp_napics) {
1130 kprintf("Changing APIC ID for IO APIC #%d from "
1131 "%d to %d in MP table\n",
1132 oapic, newid, oldid);
1133 IO_TO_ID(oapic) = oldid;
1135 IO_TO_ID(apic) = newid;
1140 fix_id_to_io_mapping(void)
1144 for (x = 0; x < NAPICID; x++)
1147 for (x = 0; x <= mp_naps; x++)
1148 if (CPU_TO_ID(x) < NAPICID)
1149 ID_TO_IO(CPU_TO_ID(x)) = x;
1151 for (x = 0; x < mp_napics; x++)
1152 if (IO_TO_ID(x) < NAPICID)
1153 ID_TO_IO(IO_TO_ID(x)) = x;
1158 first_free_apic_id(void)
1162 for (freeid = 0; freeid < NAPICID; freeid++) {
1163 for (x = 0; x <= mp_naps; x++)
1164 if (CPU_TO_ID(x) == freeid)
1168 for (x = 0; x < mp_napics; x++)
1169 if (IO_TO_ID(x) == freeid)
1180 io_apic_id_acceptable(int apic, int id)
1182 int cpu; /* Logical CPU number */
1183 int oapic; /* Logical IO APIC number for other IO APIC */
1186 return 0; /* Out of range */
1188 for (cpu = 0; cpu <= mp_naps; cpu++)
1189 if (CPU_TO_ID(cpu) == id)
1190 return 0; /* Conflict with CPU */
1192 for (oapic = 0; oapic < mp_napics && oapic < apic; oapic++)
1193 if (IO_TO_ID(oapic) == id)
1194 return 0; /* Conflict with other APIC */
1196 return 1; /* ID is acceptable for IO APIC */
1201 io_apic_find_int_entry(int apic, int pin)
1205 /* search each of the possible INTerrupt sources */
1206 for (x = 0; x < nintrs; ++x) {
1207 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1208 (pin == io_apic_ints[x].dst_apic_int))
1209 return (&io_apic_ints[x]);
1217 * parse an Intel MP specification table
1225 int apic; /* IO APIC unit number */
1226 int freeid; /* Free physical APIC ID */
1227 int physid; /* Current physical IO APIC ID */
1230 int bus_0 = 0; /* Stop GCC warning */
1231 int bus_pci = 0; /* Stop GCC warning */
1235 * Fix mis-numbering of the PCI bus and its INT entries if the BIOS
1236 * did it wrong. The MP spec says that when more than 1 PCI bus
1237 * exists the BIOS must begin with bus entries for the PCI bus and use
1238 * actual PCI bus numbering. This implies that when only 1 PCI bus
1239 * exists the BIOS can choose to ignore this ordering, and indeed many
1240 * MP motherboards do ignore it. This causes a problem when the PCI
1241 * sub-system makes requests of the MP sub-system based on PCI bus
1242 * numbers. So here we look for the situation and renumber the
1243 * busses and associated INTs in an effort to "make it right".
1246 /* find bus 0, PCI bus, count the number of PCI busses */
1247 for (num_pci_bus = 0, x = 0; x < mp_nbusses; ++x) {
1248 if (bus_data[x].bus_id == 0) {
1251 if (bus_data[x].bus_type == PCI) {
1257 * bus_0 == slot of bus with ID of 0
1258 * bus_pci == slot of last PCI bus encountered
1261 /* check the 1 PCI bus case for sanity */
1262 /* if it is number 0 all is well */
1263 if (num_pci_bus == 1 &&
1264 bus_data[bus_pci].bus_id != 0) {
1266 /* mis-numbered, swap with whichever bus uses slot 0 */
1268 /* swap the bus entry types */
1269 bus_data[bus_pci].bus_type = bus_data[bus_0].bus_type;
1270 bus_data[bus_0].bus_type = PCI;
1273 /* swap each relavant INTerrupt entry */
1274 id = bus_data[bus_pci].bus_id;
1275 for (x = 0; x < nintrs; ++x) {
1276 if (io_apic_ints[x].src_bus_id == id) {
1277 io_apic_ints[x].src_bus_id = 0;
1279 else if (io_apic_ints[x].src_bus_id == 0) {
1280 io_apic_ints[x].src_bus_id = id;
1287 /* Assign IO APIC IDs.
1289 * First try the existing ID. If a conflict is detected, try
1290 * the ID in the MP table. If a conflict is still detected, find
1293 * We cannot use the ID_TO_IO table before all conflicts has been
1294 * resolved and the table has been corrected.
1296 for (apic = 0; apic < mp_napics; ++apic) { /* For all IO APICs */
1298 /* First try to use the value set by the BIOS */
1299 physid = io_apic_get_id(apic);
1300 if (io_apic_id_acceptable(apic, physid)) {
1301 if (IO_TO_ID(apic) != physid)
1302 swap_apic_id(apic, IO_TO_ID(apic), physid);
1306 /* Then check if the value in the MP table is acceptable */
1307 if (io_apic_id_acceptable(apic, IO_TO_ID(apic)))
1310 /* Last resort, find a free APIC ID and use it */
1311 freeid = first_free_apic_id();
1312 if (freeid >= NAPICID)
1313 panic("No free physical APIC IDs found");
1315 if (io_apic_id_acceptable(apic, freeid)) {
1316 swap_apic_id(apic, IO_TO_ID(apic), freeid);
1319 panic("Free physical APIC ID not usable");
1321 fix_id_to_io_mapping();
1325 /* detect and fix broken Compaq MP table */
1326 if (apic_int_type(0, 0) == -1) {
1327 kprintf("APIC_IO: MP table broken: 8259->APIC entry missing!\n");
1328 io_apic_ints[nintrs].int_type = 3; /* ExtInt */
1329 io_apic_ints[nintrs].int_vector = 0xff; /* Unassigned */
1330 /* XXX fixme, set src bus id etc, but it doesn't seem to hurt */
1331 io_apic_ints[nintrs].dst_apic_id = IO_TO_ID(0);
1332 io_apic_ints[nintrs].dst_apic_int = 0; /* Pin 0 */
1334 } else if (apic_int_type(0, 0) == 0) {
1335 kprintf("APIC_IO: MP table broken: ExtINT entry corrupt!\n");
1336 for (x = 0; x < nintrs; ++x)
1337 if ((0 == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1338 (0 == io_apic_ints[x].dst_apic_int)) {
1339 io_apic_ints[x].int_type = 3;
1340 io_apic_ints[x].int_vector = 0xff;
1346 * Fix missing IRQ 15 when IRQ 14 is an ISA interrupt. IDE
1347 * controllers universally come in pairs. If IRQ 14 is specified
1348 * as an ISA interrupt, then IRQ 15 had better be too.
1350 * [ Shuttle XPC / AMD Athlon X2 ]
1351 * The MPTable is missing an entry for IRQ 15. Note that the
1352 * ACPI table has an entry for both 14 and 15.
1354 if (apic_int_type(0, 14) == 0 && apic_int_type(0, 15) == -1) {
1355 kprintf("APIC_IO: MP table broken: IRQ 15 not ISA when IRQ 14 is!\n");
1356 io14 = io_apic_find_int_entry(0, 14);
1357 io_apic_ints[nintrs] = *io14;
1358 io_apic_ints[nintrs].src_bus_irq = 15;
1359 io_apic_ints[nintrs].dst_apic_int = 15;
1367 /* Assign low level interrupt handlers */
1369 setup_apic_irq_mapping(void)
1375 for (x = 0; x < APIC_INTMAPSIZE; x++) {
1376 int_to_apicintpin[x].ioapic = -1;
1377 int_to_apicintpin[x].int_pin = 0;
1378 int_to_apicintpin[x].apic_address = NULL;
1379 int_to_apicintpin[x].redirindex = 0;
1382 /* First assign ISA/EISA interrupts */
1383 for (x = 0; x < nintrs; x++) {
1384 int_vector = io_apic_ints[x].src_bus_irq;
1385 if (int_vector < APIC_INTMAPSIZE &&
1386 io_apic_ints[x].int_vector == 0xff &&
1387 int_to_apicintpin[int_vector].ioapic == -1 &&
1388 (apic_int_is_bus_type(x, ISA) ||
1389 apic_int_is_bus_type(x, EISA)) &&
1390 io_apic_ints[x].int_type == 0) {
1391 assign_apic_irq(ID_TO_IO(io_apic_ints[x].dst_apic_id),
1392 io_apic_ints[x].dst_apic_int,
1397 /* Assign ExtInt entry if no ISA/EISA interrupt 0 entry */
1398 for (x = 0; x < nintrs; x++) {
1399 if (io_apic_ints[x].dst_apic_int == 0 &&
1400 io_apic_ints[x].dst_apic_id == IO_TO_ID(0) &&
1401 io_apic_ints[x].int_vector == 0xff &&
1402 int_to_apicintpin[0].ioapic == -1 &&
1403 io_apic_ints[x].int_type == 3) {
1404 assign_apic_irq(0, 0, 0);
1408 /* PCI interrupt assignment is deferred */
1414 processor_entry(proc_entry_ptr entry, int cpu)
1416 /* check for usability */
1417 if (!(entry->cpu_flags & PROCENTRY_FLAG_EN))
1420 if(entry->apic_id >= NAPICID)
1421 panic("CPU APIC ID out of range (0..%d)", NAPICID - 1);
1422 /* check for BSP flag */
1423 if (entry->cpu_flags & PROCENTRY_FLAG_BP) {
1424 boot_cpu_id = entry->apic_id;
1425 CPU_TO_ID(0) = entry->apic_id;
1426 ID_TO_CPU(entry->apic_id) = 0;
1427 return 0; /* its already been counted */
1430 /* add another AP to list, if less than max number of CPUs */
1431 else if (cpu < MAXCPU) {
1432 CPU_TO_ID(cpu) = entry->apic_id;
1433 ID_TO_CPU(entry->apic_id) = cpu;
1442 bus_entry(bus_entry_ptr entry, int bus)
1447 /* encode the name into an index */
1448 for (x = 0; x < 6; ++x) {
1449 if ((c = entry->bus_type[x]) == ' ')
1455 if ((x = lookup_bus_type(name)) == UNKNOWN_BUSTYPE)
1456 panic("unknown bus type: '%s'", name);
1458 bus_data[bus].bus_id = entry->bus_id;
1459 bus_data[bus].bus_type = x;
1467 io_apic_entry(io_apic_entry_ptr entry, int apic)
1469 if (!(entry->apic_flags & IOAPICENTRY_FLAG_EN))
1472 IO_TO_ID(apic) = entry->apic_id;
1473 if (entry->apic_id < NAPICID)
1474 ID_TO_IO(entry->apic_id) = apic;
1482 lookup_bus_type(char *name)
1486 for (x = 0; x < MAX_BUSTYPE; ++x)
1487 if (strcmp(bus_type_table[x].name, name) == 0)
1488 return bus_type_table[x].type;
1490 return UNKNOWN_BUSTYPE;
1496 int_entry(int_entry_ptr entry, int intr)
1500 io_apic_ints[intr].int_type = entry->int_type;
1501 io_apic_ints[intr].int_flags = entry->int_flags;
1502 io_apic_ints[intr].src_bus_id = entry->src_bus_id;
1503 io_apic_ints[intr].src_bus_irq = entry->src_bus_irq;
1504 if (entry->dst_apic_id == 255) {
1505 /* This signal goes to all IO APICS. Select an IO APIC
1506 with sufficient number of interrupt pins */
1507 for (apic = 0; apic < mp_napics; apic++)
1508 if (((io_apic_read(apic, IOAPIC_VER) &
1509 IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) >=
1510 entry->dst_apic_int)
1512 if (apic < mp_napics)
1513 io_apic_ints[intr].dst_apic_id = IO_TO_ID(apic);
1515 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1517 io_apic_ints[intr].dst_apic_id = entry->dst_apic_id;
1518 io_apic_ints[intr].dst_apic_int = entry->dst_apic_int;
1524 apic_int_is_bus_type(int intr, int bus_type)
1528 for (bus = 0; bus < mp_nbusses; ++bus)
1529 if ((bus_data[bus].bus_id == io_apic_ints[intr].src_bus_id)
1530 && ((int) bus_data[bus].bus_type == bus_type))
1537 * Given a traditional ISA INT mask, return an APIC mask.
1540 isa_apic_mask(u_int isa_mask)
1545 #if defined(SKIP_IRQ15_REDIRECT)
1546 if (isa_mask == (1 << 15)) {
1547 kprintf("skipping ISA IRQ15 redirect\n");
1550 #endif /* SKIP_IRQ15_REDIRECT */
1552 isa_irq = ffs(isa_mask); /* find its bit position */
1553 if (isa_irq == 0) /* doesn't exist */
1555 --isa_irq; /* make it zero based */
1557 apic_pin = isa_apic_irq(isa_irq); /* look for APIC connection */
1561 return (1 << apic_pin); /* convert pin# to a mask */
1565 * Determine which APIC pin an ISA/EISA INT is attached to.
1567 #define INTTYPE(I) (io_apic_ints[(I)].int_type)
1568 #define INTPIN(I) (io_apic_ints[(I)].dst_apic_int)
1569 #define INTIRQ(I) (io_apic_ints[(I)].int_vector)
1570 #define INTAPIC(I) (ID_TO_IO(io_apic_ints[(I)].dst_apic_id))
1572 #define SRCBUSIRQ(I) (io_apic_ints[(I)].src_bus_irq)
1574 isa_apic_irq(int isa_irq)
1578 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1579 if (INTTYPE(intr) == 0) { /* standard INT */
1580 if (SRCBUSIRQ(intr) == isa_irq) {
1581 if (apic_int_is_bus_type(intr, ISA) ||
1582 apic_int_is_bus_type(intr, EISA)) {
1583 if (INTIRQ(intr) == 0xff)
1584 return -1; /* unassigned */
1585 return INTIRQ(intr); /* found */
1590 return -1; /* NOT found */
1595 * Determine which APIC pin a PCI INT is attached to.
1597 #define SRCBUSID(I) (io_apic_ints[(I)].src_bus_id)
1598 #define SRCBUSDEVICE(I) ((io_apic_ints[(I)].src_bus_irq >> 2) & 0x1f)
1599 #define SRCBUSLINE(I) (io_apic_ints[(I)].src_bus_irq & 0x03)
1601 pci_apic_irq(int pciBus, int pciDevice, int pciInt)
1605 --pciInt; /* zero based */
1607 for (intr = 0; intr < nintrs; ++intr) { /* check each record */
1608 if ((INTTYPE(intr) == 0) /* standard INT */
1609 && (SRCBUSID(intr) == pciBus)
1610 && (SRCBUSDEVICE(intr) == pciDevice)
1611 && (SRCBUSLINE(intr) == pciInt)) { /* a candidate IRQ */
1612 if (apic_int_is_bus_type(intr, PCI)) {
1613 if (INTIRQ(intr) == 0xff)
1614 allocate_apic_irq(intr);
1615 if (INTIRQ(intr) == 0xff)
1616 return -1; /* unassigned */
1617 return INTIRQ(intr); /* exact match */
1622 return -1; /* NOT found */
1626 next_apic_irq(int irq)
1633 for (intr = 0; intr < nintrs; intr++) {
1634 if (INTIRQ(intr) != irq || INTTYPE(intr) != 0)
1636 bus = SRCBUSID(intr);
1637 bustype = apic_bus_type(bus);
1638 if (bustype != ISA &&
1644 if (intr >= nintrs) {
1647 for (ointr = intr + 1; ointr < nintrs; ointr++) {
1648 if (INTTYPE(ointr) != 0)
1650 if (bus != SRCBUSID(ointr))
1652 if (bustype == PCI) {
1653 if (SRCBUSDEVICE(intr) != SRCBUSDEVICE(ointr))
1655 if (SRCBUSLINE(intr) != SRCBUSLINE(ointr))
1658 if (bustype == ISA || bustype == EISA) {
1659 if (SRCBUSIRQ(intr) != SRCBUSIRQ(ointr))
1662 if (INTPIN(intr) == INTPIN(ointr))
1666 if (ointr >= nintrs) {
1669 return INTIRQ(ointr);
1684 * Reprogram the MB chipset to NOT redirect an ISA INTerrupt.
1687 * Exactly what this means is unclear at this point. It is a solution
1688 * for motherboards that redirect the MBIRQ0 pin. Generically a motherboard
1689 * could route any of the ISA INTs to upper (>15) IRQ values. But most would
1690 * NOT be redirected via MBIRQ0, thus "undirect()ing" them would NOT be an
1694 undirect_isa_irq(int rirq)
1698 kprintf("Freeing redirected ISA irq %d.\n", rirq);
1699 /** FIXME: tickle the MB redirector chip */
1703 kprintf("Freeing (NOT implemented) redirected ISA irq %d.\n", rirq);
1710 * Reprogram the MB chipset to NOT redirect a PCI INTerrupt
1713 undirect_pci_irq(int rirq)
1717 kprintf("Freeing redirected PCI irq %d.\n", rirq);
1719 /** FIXME: tickle the MB redirector chip */
1723 kprintf("Freeing (NOT implemented) redirected PCI irq %d.\n",
1731 * given a bus ID, return:
1732 * the bus type if found
1736 apic_bus_type(int id)
1740 for (x = 0; x < mp_nbusses; ++x)
1741 if (bus_data[x].bus_id == id)
1742 return bus_data[x].bus_type;
1750 * given a LOGICAL APIC# and pin#, return:
1751 * the associated src bus ID if found
1755 apic_src_bus_id(int apic, int pin)
1759 /* search each of the possible INTerrupt sources */
1760 for (x = 0; x < nintrs; ++x)
1761 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1762 (pin == io_apic_ints[x].dst_apic_int))
1763 return (io_apic_ints[x].src_bus_id);
1765 return -1; /* NOT found */
1769 * given a LOGICAL APIC# and pin#, return:
1770 * the associated src bus IRQ if found
1774 apic_src_bus_irq(int apic, int pin)
1778 for (x = 0; x < nintrs; x++)
1779 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1780 (pin == io_apic_ints[x].dst_apic_int))
1781 return (io_apic_ints[x].src_bus_irq);
1783 return -1; /* NOT found */
1788 * given a LOGICAL APIC# and pin#, return:
1789 * the associated INTerrupt type if found
1793 apic_int_type(int apic, int pin)
1797 /* search each of the possible INTerrupt sources */
1798 for (x = 0; x < nintrs; ++x) {
1799 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1800 (pin == io_apic_ints[x].dst_apic_int))
1801 return (io_apic_ints[x].int_type);
1803 return -1; /* NOT found */
1807 * Return the IRQ associated with an APIC pin
1810 apic_irq(int apic, int pin)
1815 for (x = 0; x < nintrs; ++x) {
1816 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1817 (pin == io_apic_ints[x].dst_apic_int)) {
1818 res = io_apic_ints[x].int_vector;
1821 if (apic != int_to_apicintpin[res].ioapic)
1822 panic("apic_irq: inconsistent table %d/%d", apic, int_to_apicintpin[res].ioapic);
1823 if (pin != int_to_apicintpin[res].int_pin)
1824 panic("apic_irq inconsistent table (2)");
1833 * given a LOGICAL APIC# and pin#, return:
1834 * the associated trigger mode if found
1838 apic_trigger(int apic, int pin)
1842 /* search each of the possible INTerrupt sources */
1843 for (x = 0; x < nintrs; ++x)
1844 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1845 (pin == io_apic_ints[x].dst_apic_int))
1846 return ((io_apic_ints[x].int_flags >> 2) & 0x03);
1848 return -1; /* NOT found */
1853 * given a LOGICAL APIC# and pin#, return:
1854 * the associated 'active' level if found
1858 apic_polarity(int apic, int pin)
1862 /* search each of the possible INTerrupt sources */
1863 for (x = 0; x < nintrs; ++x)
1864 if ((apic == ID_TO_IO(io_apic_ints[x].dst_apic_id)) &&
1865 (pin == io_apic_ints[x].dst_apic_int))
1866 return (io_apic_ints[x].int_flags & 0x03);
1868 return -1; /* NOT found */
1874 * set data according to MP defaults
1875 * FIXME: probably not complete yet...
1878 default_mp_table(int type)
1881 #if defined(APIC_IO)
1884 #endif /* APIC_IO */
1887 kprintf(" MP default config type: %d\n", type);
1890 kprintf(" bus: ISA, APIC: 82489DX\n");
1893 kprintf(" bus: EISA, APIC: 82489DX\n");
1896 kprintf(" bus: EISA, APIC: 82489DX\n");
1899 kprintf(" bus: MCA, APIC: 82489DX\n");
1902 kprintf(" bus: ISA+PCI, APIC: Integrated\n");
1905 kprintf(" bus: EISA+PCI, APIC: Integrated\n");
1908 kprintf(" bus: MCA+PCI, APIC: Integrated\n");
1911 kprintf(" future type\n");
1917 boot_cpu_id = (lapic.id & APIC_ID_MASK) >> 24;
1918 ap_cpu_id = (boot_cpu_id == 0) ? 1 : 0;
1921 CPU_TO_ID(0) = boot_cpu_id;
1922 ID_TO_CPU(boot_cpu_id) = 0;
1924 /* one and only AP */
1925 CPU_TO_ID(1) = ap_cpu_id;
1926 ID_TO_CPU(ap_cpu_id) = 1;
1928 #if defined(APIC_IO)
1929 /* one and only IO APIC */
1930 io_apic_id = (io_apic_read(0, IOAPIC_ID) & APIC_ID_MASK) >> 24;
1933 * sanity check, refer to MP spec section 3.6.6, last paragraph
1934 * necessary as some hardware isn't properly setting up the IO APIC
1936 #if defined(REALLY_ANAL_IOAPICID_VALUE)
1937 if (io_apic_id != 2) {
1939 if ((io_apic_id == 0) || (io_apic_id == 1) || (io_apic_id == 15)) {
1940 #endif /* REALLY_ANAL_IOAPICID_VALUE */
1941 io_apic_set_id(0, 2);
1944 IO_TO_ID(0) = io_apic_id;
1945 ID_TO_IO(io_apic_id) = 0;
1946 #endif /* APIC_IO */
1948 /* fill out bus entries */
1957 bus_data[0].bus_id = default_data[type - 1][1];
1958 bus_data[0].bus_type = default_data[type - 1][2];
1959 bus_data[1].bus_id = default_data[type - 1][3];
1960 bus_data[1].bus_type = default_data[type - 1][4];
1963 /* case 4: case 7: MCA NOT supported */
1964 default: /* illegal/reserved */
1965 panic("BAD default MP config: %d", type);
1969 #if defined(APIC_IO)
1970 /* general cases from MP v1.4, table 5-2 */
1971 for (pin = 0; pin < 16; ++pin) {
1972 io_apic_ints[pin].int_type = 0;
1973 io_apic_ints[pin].int_flags = 0x05; /* edge/active-hi */
1974 io_apic_ints[pin].src_bus_id = 0;
1975 io_apic_ints[pin].src_bus_irq = pin; /* IRQ2 caught below */
1976 io_apic_ints[pin].dst_apic_id = io_apic_id;
1977 io_apic_ints[pin].dst_apic_int = pin; /* 1-to-1 */
1980 /* special cases from MP v1.4, table 5-2 */
1982 io_apic_ints[2].int_type = 0xff; /* N/C */
1983 io_apic_ints[13].int_type = 0xff; /* N/C */
1984 #if !defined(APIC_MIXED_MODE)
1986 panic("sorry, can't support type 2 default yet");
1987 #endif /* APIC_MIXED_MODE */
1990 io_apic_ints[2].src_bus_irq = 0; /* ISA IRQ0 is on APIC INT 2 */
1993 io_apic_ints[0].int_type = 0xff; /* N/C */
1995 io_apic_ints[0].int_type = 3; /* vectored 8259 */
1996 #endif /* APIC_IO */
2000 * Map a physical memory address representing I/O into KVA. The I/O
2001 * block is assumed not to cross a page boundary.
2004 permanent_io_mapping(vm_paddr_t pa)
2010 KKASSERT(pa < 0x100000000LL);
2012 pgeflag = 0; /* not used for SMP yet */
2015 * If the requested physical address has already been incidently
2016 * mapped, just use the existing mapping. Otherwise create a new
2019 for (i = IO_MAPPING_START_INDEX; i < SMPpt_alloc_index; ++i) {
2020 if (((vm_offset_t)SMPpt[i] & PG_FRAME) ==
2021 ((vm_offset_t)pa & PG_FRAME)) {
2025 if (i == SMPpt_alloc_index) {
2026 if (i == NPTEPG - 2) {
2027 panic("permanent_io_mapping: We ran out of space"
2030 SMPpt[i] = (pt_entry_t)(PG_V | PG_RW | pgeflag |
2031 ((vm_offset_t)pa & PG_FRAME));
2032 ++SMPpt_alloc_index;
2034 vaddr = (vm_offset_t)CPU_prvspace + (i * PAGE_SIZE) +
2035 ((vm_offset_t)pa & PAGE_MASK);
2036 return ((void *)vaddr);
2040 * start each AP in our list
2043 start_all_aps(u_int boot_addr)
2047 u_char mpbiosreason;
2048 u_long mpbioswarmvec;
2049 struct mdglobaldata *gd;
2050 struct privatespace *ps;
2054 POSTCODE(START_ALL_APS_POST);
2056 /* Initialize BSP's local APIC */
2057 apic_initialize(TRUE);
2060 /* install the AP 1st level boot code */
2061 install_ap_tramp(boot_addr);
2064 /* save the current value of the warm-start vector */
2065 mpbioswarmvec = *((u_long *) WARMBOOT_OFF);
2066 outb(CMOS_REG, BIOS_RESET);
2067 mpbiosreason = inb(CMOS_DATA);
2069 /* set up temporary P==V mapping for AP boot */
2070 /* XXX this is a hack, we should boot the AP on its own stack/PTD */
2071 kptbase = (uintptr_t)(void *)KPTphys;
2072 for (x = 0; x < NKPT; x++) {
2073 PTD[x] = (pd_entry_t)(PG_V | PG_RW |
2074 ((kptbase + x * PAGE_SIZE) & PG_FRAME));
2079 for (x = 1; x <= mp_naps; ++x) {
2081 /* This is a bit verbose, it will go away soon. */
2083 /* first page of AP's private space */
2084 pg = x * i386_btop(sizeof(struct privatespace));
2086 /* allocate new private data page(s) */
2087 gd = (struct mdglobaldata *)kmem_alloc(&kernel_map,
2088 MDGLOBALDATA_BASEALLOC_SIZE);
2089 /* wire it into the private page table page */
2090 for (i = 0; i < MDGLOBALDATA_BASEALLOC_SIZE; i += PAGE_SIZE) {
2091 SMPpt[pg + i / PAGE_SIZE] = (pt_entry_t)
2092 (PG_V | PG_RW | vtophys_pte((char *)gd + i));
2094 pg += MDGLOBALDATA_BASEALLOC_PAGES;
2096 SMPpt[pg + 0] = 0; /* *gd_CMAP1 */
2097 SMPpt[pg + 1] = 0; /* *gd_CMAP2 */
2098 SMPpt[pg + 2] = 0; /* *gd_CMAP3 */
2099 SMPpt[pg + 3] = 0; /* *gd_PMAP1 */
2101 /* allocate and set up an idle stack data page */
2102 stack = (char *)kmem_alloc(&kernel_map, UPAGES*PAGE_SIZE);
2103 for (i = 0; i < UPAGES; i++) {
2104 SMPpt[pg + 4 + i] = (pt_entry_t)
2105 (PG_V | PG_RW | vtophys_pte(PAGE_SIZE * i + stack));
2108 gd = &CPU_prvspace[x].mdglobaldata; /* official location */
2109 bzero(gd, sizeof(*gd));
2110 gd->mi.gd_prvspace = ps = &CPU_prvspace[x];
2112 /* prime data page for it to use */
2113 mi_gdinit(&gd->mi, x);
2115 gd->gd_CMAP1 = &SMPpt[pg + 0];
2116 gd->gd_CMAP2 = &SMPpt[pg + 1];
2117 gd->gd_CMAP3 = &SMPpt[pg + 2];
2118 gd->gd_PMAP1 = &SMPpt[pg + 3];
2119 gd->gd_CADDR1 = ps->CPAGE1;
2120 gd->gd_CADDR2 = ps->CPAGE2;
2121 gd->gd_CADDR3 = ps->CPAGE3;
2122 gd->gd_PADDR1 = (unsigned *)ps->PPAGE1;
2123 gd->mi.gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * (mp_naps + 1));
2124 bzero(gd->mi.gd_ipiq, sizeof(lwkt_ipiq) * (mp_naps + 1));
2126 /* setup a vector to our boot code */
2127 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET;
2128 *((volatile u_short *) WARMBOOT_SEG) = (boot_addr >> 4);
2129 outb(CMOS_REG, BIOS_RESET);
2130 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */
2133 * Setup the AP boot stack
2135 bootSTK = &ps->idlestack[UPAGES*PAGE_SIZE/2];
2138 /* attempt to start the Application Processor */
2139 CHECK_INIT(99); /* setup checkpoints */
2140 if (!start_ap(gd, boot_addr)) {
2141 kprintf("AP #%d (PHY# %d) failed!\n", x, CPU_TO_ID(x));
2142 CHECK_PRINT("trace"); /* show checkpoints */
2143 /* better panic as the AP may be running loose */
2144 kprintf("panic y/n? [y] ");
2145 if (cngetc() != 'n')
2148 CHECK_PRINT("trace"); /* show checkpoints */
2150 /* record its version info */
2151 cpu_apic_versions[x] = cpu_apic_versions[0];
2154 /* set ncpus to 1 + highest logical cpu. Not all may have come up */
2157 /* ncpus2 -- ncpus rounded down to the nearest power of 2 */
2158 for (shift = 0; (1 << shift) <= ncpus; ++shift)
2161 ncpus2_shift = shift;
2162 ncpus2 = 1 << shift;
2163 ncpus2_mask = ncpus2 - 1;
2165 /* ncpus_fit -- ncpus rounded up to the nearest power of 2 */
2166 if ((1 << shift) < ncpus)
2168 ncpus_fit = 1 << shift;
2169 ncpus_fit_mask = ncpus_fit - 1;
2171 /* build our map of 'other' CPUs */
2172 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2173 mycpu->gd_ipiq = (void *)kmem_alloc(&kernel_map, sizeof(lwkt_ipiq) * ncpus);
2174 bzero(mycpu->gd_ipiq, sizeof(lwkt_ipiq) * ncpus);
2176 /* fill in our (BSP) APIC version */
2177 cpu_apic_versions[0] = lapic.version;
2179 /* restore the warmstart vector */
2180 *(u_long *) WARMBOOT_OFF = mpbioswarmvec;
2181 outb(CMOS_REG, BIOS_RESET);
2182 outb(CMOS_DATA, mpbiosreason);
2185 * NOTE! The idlestack for the BSP was setup by locore. Finish
2186 * up, clean out the P==V mapping we did earlier.
2188 for (x = 0; x < NKPT; x++)
2192 /* number of APs actually started */
2198 * load the 1st level AP boot code into base memory.
2201 /* targets for relocation */
2202 extern void bigJump(void);
2203 extern void bootCodeSeg(void);
2204 extern void bootDataSeg(void);
2205 extern void MPentry(void);
2206 extern u_int MP_GDT;
2207 extern u_int mp_gdtbase;
2210 install_ap_tramp(u_int boot_addr)
2213 int size = *(int *) ((u_long) & bootMP_size);
2214 u_char *src = (u_char *) ((u_long) bootMP);
2215 u_char *dst = (u_char *) boot_addr + KERNBASE;
2216 u_int boot_base = (u_int) bootMP;
2221 POSTCODE(INSTALL_AP_TRAMP_POST);
2223 for (x = 0; x < size; ++x)
2227 * modify addresses in code we just moved to basemem. unfortunately we
2228 * need fairly detailed info about mpboot.s for this to work. changes
2229 * to mpboot.s might require changes here.
2232 /* boot code is located in KERNEL space */
2233 dst = (u_char *) boot_addr + KERNBASE;
2235 /* modify the lgdt arg */
2236 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base));
2237 *dst32 = boot_addr + ((u_int) & MP_GDT - boot_base);
2239 /* modify the ljmp target for MPentry() */
2240 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1);
2241 *dst32 = ((u_int) MPentry - KERNBASE);
2243 /* modify the target for boot code segment */
2244 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base));
2245 dst8 = (u_int8_t *) (dst16 + 1);
2246 *dst16 = (u_int) boot_addr & 0xffff;
2247 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2249 /* modify the target for boot data segment */
2250 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base));
2251 dst8 = (u_int8_t *) (dst16 + 1);
2252 *dst16 = (u_int) boot_addr & 0xffff;
2253 *dst8 = ((u_int) boot_addr >> 16) & 0xff;
2258 * this function starts the AP (application processor) identified
2259 * by the APIC ID 'physicalCpu'. It does quite a "song and dance"
2260 * to accomplish this. This is necessary because of the nuances
2261 * of the different hardware we might encounter. It ain't pretty,
2262 * but it seems to work.
2264 * NOTE: eventually an AP gets to ap_init(), which is called just
2265 * before the AP goes into the LWKT scheduler's idle loop.
2268 start_ap(struct mdglobaldata *gd, u_int boot_addr)
2272 u_long icr_lo, icr_hi;
2274 POSTCODE(START_AP_POST);
2276 /* get the PHYSICAL APIC ID# */
2277 physical_cpu = CPU_TO_ID(gd->mi.gd_cpuid);
2279 /* calculate the vector */
2280 vector = (boot_addr >> 12) & 0xff;
2282 /* Make sure the target cpu sees everything */
2286 * first we do an INIT/RESET IPI this INIT IPI might be run, reseting
2287 * and running the target CPU. OR this INIT IPI might be latched (P5
2288 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be
2292 /* setup the address for the target AP */
2293 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
2294 icr_hi |= (physical_cpu << 24);
2295 lapic.icr_hi = icr_hi;
2297 /* do an INIT IPI: assert RESET */
2298 icr_lo = lapic.icr_lo & 0xfff00000;
2299 lapic.icr_lo = icr_lo | 0x0000c500;
2301 /* wait for pending status end */
2302 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2305 /* do an INIT IPI: deassert RESET */
2306 lapic.icr_lo = icr_lo | 0x00008500;
2308 /* wait for pending status end */
2309 u_sleep(10000); /* wait ~10mS */
2310 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2314 * next we do a STARTUP IPI: the previous INIT IPI might still be
2315 * latched, (P5 bug) this 1st STARTUP would then terminate
2316 * immediately, and the previously started INIT IPI would continue. OR
2317 * the previous INIT IPI has already run. and this STARTUP IPI will
2318 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI
2322 /* do a STARTUP IPI */
2323 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2324 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2326 u_sleep(200); /* wait ~200uS */
2329 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF
2330 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR
2331 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is
2332 * recognized after hardware RESET or INIT IPI.
2335 lapic.icr_lo = icr_lo | 0x00000600 | vector;
2336 while (lapic.icr_lo & APIC_DELSTAT_MASK)
2338 u_sleep(200); /* wait ~200uS */
2340 /* wait for it to start, see ap_init() */
2341 set_apic_timer(5000000);/* == 5 seconds */
2342 while (read_apic_timer()) {
2343 if (smp_startup_mask & (1 << gd->mi.gd_cpuid))
2344 return 1; /* return SUCCESS */
2346 return 0; /* return FAILURE */
2351 * Lazy flush the TLB on all other CPU's. DEPRECATED.
2353 * If for some reason we were unable to start all cpus we cannot safely
2354 * use broadcast IPIs.
2360 if (smp_startup_mask == smp_active_mask) {
2361 all_but_self_ipi(XINVLTLB_OFFSET);
2363 selected_apic_ipi(smp_active_mask, XINVLTLB_OFFSET,
2364 APIC_DELMODE_FIXED);
2370 * When called the executing CPU will send an IPI to all other CPUs
2371 * requesting that they halt execution.
2373 * Usually (but not necessarily) called with 'other_cpus' as its arg.
2375 * - Signals all CPUs in map to stop.
2376 * - Waits for each to stop.
2383 * XXX FIXME: this is not MP-safe, needs a lock to prevent multiple CPUs
2384 * from executing at same time.
2387 stop_cpus(u_int map)
2389 map &= smp_active_mask;
2391 /* send the Xcpustop IPI to all CPUs in map */
2392 selected_apic_ipi(map, XCPUSTOP_OFFSET, APIC_DELMODE_FIXED);
2394 while ((stopped_cpus & map) != map)
2402 * Called by a CPU to restart stopped CPUs.
2404 * Usually (but not necessarily) called with 'stopped_cpus' as its arg.
2406 * - Signals all CPUs in map to restart.
2407 * - Waits for each to restart.
2415 restart_cpus(u_int map)
2417 /* signal other cpus to restart */
2418 started_cpus = map & smp_active_mask;
2420 while ((stopped_cpus & map) != 0) /* wait for each to clear its bit */
2427 * This is called once the mpboot code has gotten us properly relocated
2428 * and the MMU turned on, etc. ap_init() is actually the idle thread,
2429 * and when it returns the scheduler will call the real cpu_idle() main
2430 * loop for the idlethread. Interrupts are disabled on entry and should
2431 * remain disabled at return.
2439 * Adjust smp_startup_mask to signal the BSP that we have started
2440 * up successfully. Note that we do not yet hold the BGL. The BSP
2441 * is waiting for our signal.
2443 * We can't set our bit in smp_active_mask yet because we are holding
2444 * interrupts physically disabled and remote cpus could deadlock
2445 * trying to send us an IPI.
2447 smp_startup_mask |= 1 << mycpu->gd_cpuid;
2451 * Interlock for finalization. Wait until mp_finish is non-zero,
2452 * then get the MP lock.
2454 * Note: We are in a critical section.
2456 * Note: We have to synchronize td_mpcount to our desired MP state
2457 * before calling cpu_try_mplock().
2459 * Note: we are the idle thread, we can only spin.
2461 * Note: The load fence is memory volatile and prevents the compiler
2462 * from improperly caching mp_finish, and the cpu from improperly
2465 while (mp_finish == 0)
2467 ++curthread->td_mpcount;
2468 while (cpu_try_mplock() == 0)
2471 if (cpu_feature & CPUID_TSC) {
2473 * The BSP is constantly updating tsc0_offset, figure out the
2474 * relative difference to synchronize ktrdump.
2476 tsc_offsets[mycpu->gd_cpuid] = rdtsc() - tsc0_offset;
2479 /* BSP may have changed PTD while we're waiting for the lock */
2482 #if defined(I586_CPU) && !defined(NO_F00F_HACK)
2486 /* Build our map of 'other' CPUs. */
2487 mycpu->gd_other_cpus = smp_startup_mask & ~(1 << mycpu->gd_cpuid);
2489 kprintf("SMP: AP CPU #%d Launched!\n", mycpu->gd_cpuid);
2491 /* A quick check from sanity claus */
2492 apic_id = (apic_id_to_logical[(lapic.id & 0x0f000000) >> 24]);
2493 if (mycpu->gd_cpuid != apic_id) {
2494 kprintf("SMP: cpuid = %d\n", mycpu->gd_cpuid);
2495 kprintf("SMP: apic_id = %d\n", apic_id);
2496 kprintf("PTD[MPPTDI] = %p\n", (void *)PTD[MPPTDI]);
2497 panic("cpuid mismatch! boom!!");
2500 /* Initialize AP's local APIC for irq's */
2501 apic_initialize(FALSE);
2503 /* Set memory range attributes for this CPU to match the BSP */
2504 mem_range_AP_init();
2507 * Once we go active we must process any IPIQ messages that may
2508 * have been queued, because no actual IPI will occur until we
2509 * set our bit in the smp_active_mask. If we don't the IPI
2510 * message interlock could be left set which would also prevent
2513 * The idle loop doesn't expect the BGL to be held and while
2514 * lwkt_switch() normally cleans things up this is a special case
2515 * because we returning almost directly into the idle loop.
2517 * The idle thread is never placed on the runq, make sure
2518 * nothing we've done put it there.
2520 KKASSERT(curthread->td_mpcount == 1);
2521 smp_active_mask |= 1 << mycpu->gd_cpuid;
2524 * Enable interrupts here. idle_restore will also do it, but
2525 * doing it here lets us clean up any strays that got posted to
2526 * the CPU during the AP boot while we are still in a critical
2529 __asm __volatile("sti; pause; pause"::);
2530 mdcpu->gd_fpending = 0;
2531 mdcpu->gd_ipending = 0;
2533 initclocks_pcpu(); /* clock interrupts (via IPIs) */
2534 lwkt_process_ipiq();
2537 * Releasing the mp lock lets the BSP finish up the SMP init
2540 KKASSERT((curthread->td_flags & TDF_RUNQ) == 0);
2544 * Get SMP fully working before we start initializing devices.
2552 kprintf("Finish MP startup\n");
2553 if (cpu_feature & CPUID_TSC)
2554 tsc0_offset = rdtsc();
2557 while (smp_active_mask != smp_startup_mask) {
2559 if (cpu_feature & CPUID_TSC)
2560 tsc0_offset = rdtsc();
2562 while (try_mplock() == 0)
2565 kprintf("Active CPU Mask: %08x\n", smp_active_mask);
2568 SYSINIT(finishsmp, SI_BOOT2_FINISH_SMP, SI_ORDER_FIRST, ap_finish, NULL)
2571 cpu_send_ipiq(int dcpu)
2573 if ((1 << dcpu) & smp_active_mask)
2574 single_apic_ipi(dcpu, XIPIQ_OFFSET, APIC_DELMODE_FIXED);
2577 #if 0 /* single_apic_ipi_passive() not working yet */
2579 * Returns 0 on failure, 1 on success
2582 cpu_send_ipiq_passive(int dcpu)
2585 if ((1 << dcpu) & smp_active_mask) {
2586 r = single_apic_ipi_passive(dcpu, XIPIQ_OFFSET,
2587 APIC_DELMODE_FIXED);