sys/dev/drm/radeon_cp.c

   1 /*-
   2  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
   3  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
   4  * Copyright 2007 Advanced Micro Devices, Inc.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the "Software"),
   9  * to deal in the Software without restriction, including without limitation
  10  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  11  * and/or sell copies of the Software, and to permit persons to whom the
  12  * Software is furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the next
  15  * paragraph) shall be included in all copies or substantial portions of the
  16  * Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  21  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  22  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  23  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  24  * DEALINGS IN THE SOFTWARE.
  25  *
  26  * Authors:
  27  *    Kevin E. Martin <martin@valinux.com>
  28  *    Gareth Hughes <gareth@valinux.com>
  29  */
  30
  31 #include "dev/drm/drmP.h"
  32 #include "dev/drm/drm.h"
  33 #include "dev/drm/drm_sarea.h"
  34 #include "dev/drm/radeon_drm.h"
  35 #include "dev/drm/radeon_drv.h"
  36 #include "dev/drm/r300_reg.h"
  37
  38 #include "dev/drm/radeon_microcode.h"
  39
  40 #define RADEON_FIFO_DEBUG       0
  41
  42 static int radeon_do_cleanup_cp(struct drm_device * dev);
  43 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
  44
  45 u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off)
  46 {
  47         u32 val;
  48
  49         if (dev_priv->flags & RADEON_IS_AGP) {
  50                 val = DRM_READ32(dev_priv->ring_rptr, off);
  51         } else {
  52                 val = *(((volatile u32 *)
  53                          dev_priv->ring_rptr->handle) +
  54                         (off / sizeof(u32)));
  55                 val = le32_to_cpu(val);
  56         }
  57         return val;
  58 }
  59
  60 u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv)
  61 {
  62         if (dev_priv->writeback_works)
  63                 return radeon_read_ring_rptr(dev_priv, 0);
  64         else {
  65                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
  66                         return RADEON_READ(R600_CP_RB_RPTR);
  67                 else
  68                         return RADEON_READ(RADEON_CP_RB_RPTR);
  69         }
  70 }
  71
  72 void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val)
  73 {
  74         if (dev_priv->flags & RADEON_IS_AGP)
  75                 DRM_WRITE32(dev_priv->ring_rptr, off, val);
  76         else
  77                 *(((volatile u32 *) dev_priv->ring_rptr->handle) +
  78                   (off / sizeof(u32))) = cpu_to_le32(val);
  79 }
  80
  81 void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val)
  82 {
  83         radeon_write_ring_rptr(dev_priv, 0, val);
  84 }
  85
  86 u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index)
  87 {
  88         if (dev_priv->writeback_works) {
  89                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
  90                         return radeon_read_ring_rptr(dev_priv,
  91                                                      R600_SCRATCHOFF(index));
  92                 else
  93                         return radeon_read_ring_rptr(dev_priv,
  94                                                      RADEON_SCRATCHOFF(index));
  95         } else {
  96                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
  97                         return RADEON_READ(R600_SCRATCH_REG0 + 4*index);
  98                 else
  99                         return RADEON_READ(RADEON_SCRATCH_REG0 + 4*index);
 100         }
 101 }
 102
 103 u32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr)
 104 {
 105         u32 ret;
 106
 107         if (addr < 0x10000)
 108                 ret = DRM_READ32(dev_priv->mmio, addr);
 109         else {
 110                 DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, addr);
 111                 ret = DRM_READ32(dev_priv->mmio, RADEON_MM_DATA);
 112         }
 113
 114         return ret;
 115 }
 116
 117 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 118 {
 119         u32 ret;
 120         RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
 121         ret = RADEON_READ(R520_MC_IND_DATA);
 122         RADEON_WRITE(R520_MC_IND_INDEX, 0);
 123         return ret;
 124 }
 125
 126 static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 127 {
 128         u32 ret;
 129         RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
 130         ret = RADEON_READ(RS480_NB_MC_DATA);
 131         RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
 132         return ret;
 133 }
 134
 135 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 136 {
 137         u32 ret;
 138         RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
 139         ret = RADEON_READ(RS690_MC_DATA);
 140         RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
 141         return ret;
 142 }
 143
 144 static u32 RS600_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 145 {
 146         u32 ret;
 147         RADEON_WRITE(RS600_MC_INDEX, ((addr & RS600_MC_ADDR_MASK) |
 148                                       RS600_MC_IND_CITF_ARB0));
 149         ret = RADEON_READ(RS600_MC_DATA);
 150         return ret;
 151 }
 152
 153 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
 154 {
 155         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 156             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 157                 return RS690_READ_MCIND(dev_priv, addr);
 158         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
 159                 return RS600_READ_MCIND(dev_priv, addr);
 160         else
 161                 return RS480_READ_MCIND(dev_priv, addr);
 162 }
 163
 164 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
 165 {
 166
 167         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
 168                 return RADEON_READ(R700_MC_VM_FB_LOCATION);
 169         else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 170                 return RADEON_READ(R600_MC_VM_FB_LOCATION);
 171         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 172                 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
 173         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 174                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 175                 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
 176         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
 177                 return RS600_READ_MCIND(dev_priv, RS600_MC_FB_LOCATION);
 178         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 179                 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
 180         else
 181                 return RADEON_READ(RADEON_MC_FB_LOCATION);
 182 }
 183
 184 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
 185 {
 186         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
 187                 RADEON_WRITE(R700_MC_VM_FB_LOCATION, fb_loc);
 188         else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 189                 RADEON_WRITE(R600_MC_VM_FB_LOCATION, fb_loc);
 190         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 191                 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
 192         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 193                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 194                 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
 195         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
 196                 RS600_WRITE_MCIND(RS600_MC_FB_LOCATION, fb_loc);
 197         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 198                 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
 199         else
 200                 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
 201 }
 202
 203 void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
 204 {
 205         /*R6xx/R7xx: AGP_TOP and BOT are actually 18 bits each */
 206         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
 207                 RADEON_WRITE(R700_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
 208                 RADEON_WRITE(R700_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
 209         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
 210                 RADEON_WRITE(R600_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
 211                 RADEON_WRITE(R600_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
 212         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
 213                 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
 214         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 215                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 216                 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
 217         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
 218                 RS600_WRITE_MCIND(RS600_MC_AGP_LOCATION, agp_loc);
 219         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
 220                 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
 221         else
 222                 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
 223 }
 224
 225 void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
 226 {
 227         u32 agp_base_hi = upper_32_bits(agp_base);
 228         u32 agp_base_lo = agp_base & 0xffffffff;
 229         u32 r6xx_agp_base = (agp_base >> 22) & 0x3ffff;
 230
 231         /* R6xx/R7xx must be aligned to a 4MB boundry */
 232         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
 233                 RADEON_WRITE(R700_MC_VM_AGP_BASE, r6xx_agp_base);
 234         else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
 235                 RADEON_WRITE(R600_MC_VM_AGP_BASE, r6xx_agp_base);
 236         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
 237                 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
 238                 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
 239         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 240                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
 241                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
 242                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
 243         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
 244                 RS600_WRITE_MCIND(RS600_AGP_BASE, agp_base_lo);
 245                 RS600_WRITE_MCIND(RS600_AGP_BASE_2, agp_base_hi);
 246         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
 247                 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
 248                 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
 249         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
 250                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
 251                 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
 252                 RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi);
 253         } else {
 254                 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
 255                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
 256                         RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
 257         }
 258 }
 259
 260 void radeon_enable_bm(struct drm_radeon_private *dev_priv)
 261 {
 262         u32 tmp;
 263         /* Turn on bus mastering */
 264         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 265             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
 266                 /* rs600/rs690/rs740 */
 267                 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
 268                 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
 269         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) ||
 270                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
 271                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
 272                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
 273                 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
 274                 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
 275                 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
 276         } /* PCIE cards appears to not need this */
 277 }
 278
 279 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
 280 {
 281         drm_radeon_private_t *dev_priv = dev->dev_private;
 282
 283         RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
 284         return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
 285 }
 286
 287 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
 288 {
 289         RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
 290         return RADEON_READ(RADEON_PCIE_DATA);
 291 }
 292
 293 #if RADEON_FIFO_DEBUG
 294 static void radeon_status(drm_radeon_private_t * dev_priv)
 295 {
 296         printk("%s:\n", __func__);
 297         printk("RBBM_STATUS = 0x%08x\n",
 298                (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
 299         printk("CP_RB_RTPR = 0x%08x\n",
 300                (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
 301         printk("CP_RB_WTPR = 0x%08x\n",
 302                (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
 303         printk("AIC_CNTL = 0x%08x\n",
 304                (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
 305         printk("AIC_STAT = 0x%08x\n",
 306                (unsigned int)RADEON_READ(RADEON_AIC_STAT));
 307         printk("AIC_PT_BASE = 0x%08x\n",
 308                (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
 309         printk("TLB_ADDR = 0x%08x\n",
 310                (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
 311         printk("TLB_DATA = 0x%08x\n",
 312                (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
 313 }
 314 #endif
 315
 316 /* ================================================================
 317  * Engine, FIFO control
 318  */
 319
 320 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
 321 {
 322         u32 tmp;
 323         int i;
 324
 325         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 326
 327         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
 328                 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
 329                 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
 330                 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
 331
 332                 for (i = 0; i < dev_priv->usec_timeout; i++) {
 333                         if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
 334                               & RADEON_RB3D_DC_BUSY)) {
 335                                 return 0;
 336                         }
 337                         DRM_UDELAY(1);
 338                 }
 339         } else {
 340                 /* don't flush or purge cache here or lockup */
 341                 return 0;
 342         }
 343
 344 #if RADEON_FIFO_DEBUG
 345         DRM_ERROR("failed!\n");
 346         radeon_status(dev_priv);
 347 #endif
 348         return -EBUSY;
 349 }
 350
 351 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
 352 {
 353         int i;
 354
 355         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 356
 357         for (i = 0; i < dev_priv->usec_timeout; i++) {
 358                 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
 359                              & RADEON_RBBM_FIFOCNT_MASK);
 360                 if (slots >= entries)
 361                         return 0;
 362                 DRM_UDELAY(1);
 363         }
 364         DRM_DEBUG("wait for fifo failed status : 0x%08X 0x%08X\n",
 365                  RADEON_READ(RADEON_RBBM_STATUS),
 366                  RADEON_READ(R300_VAP_CNTL_STATUS));
 367
 368 #if RADEON_FIFO_DEBUG
 369         DRM_ERROR("failed!\n");
 370         radeon_status(dev_priv);
 371 #endif
 372         return -EBUSY;
 373 }
 374
 375 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
 376 {
 377         int i, ret;
 378
 379         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
 380
 381         ret = radeon_do_wait_for_fifo(dev_priv, 64);
 382         if (ret)
 383                 return ret;
 384
 385         for (i = 0; i < dev_priv->usec_timeout; i++) {
 386                 if (!(RADEON_READ(RADEON_RBBM_STATUS)
 387                       & RADEON_RBBM_ACTIVE)) {
 388                         radeon_do_pixcache_flush(dev_priv);
 389                         return 0;
 390                 }
 391                 DRM_UDELAY(1);
 392         }
 393         DRM_DEBUG("wait idle failed status : 0x%08X 0x%08X\n",
 394                  RADEON_READ(RADEON_RBBM_STATUS),
 395                  RADEON_READ(R300_VAP_CNTL_STATUS));
 396
 397 #if RADEON_FIFO_DEBUG
 398         DRM_ERROR("failed!\n");
 399         radeon_status(dev_priv);
 400 #endif
 401         return -EBUSY;
 402 }
 403
 404 static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
 405 {
 406         uint32_t gb_tile_config, gb_pipe_sel = 0;
 407
 408         /* RS4xx/RS6xx/R4xx/R5xx */
 409         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
 410                 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
 411                 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
 412         } else {
 413                 /* R3xx */
 414                 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
 415                     ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) {
 416                         dev_priv->num_gb_pipes = 2;
 417                 } else {
 418                         /* R3Vxx */
 419                         dev_priv->num_gb_pipes = 1;
 420                 }
 421         }
 422         DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
 423
 424         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
 425
 426         switch (dev_priv->num_gb_pipes) {
 427         case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
 428         case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
 429         case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
 430         default:
 431         case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
 432         }
 433
 434         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
 435                 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
 436                 RADEON_WRITE(R500_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
 437         }
 438         RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
 439         radeon_do_wait_for_idle(dev_priv);
 440         RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
 441         RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
 442                                                R300_DC_AUTOFLUSH_ENABLE |
 443                                                R300_DC_DC_DISABLE_IGNORE_PE));
 444
 445
 446 }
 447
 448 /* ================================================================
 449  * CP control, initialization
 450  */
 451
 452 /* Load the microcode for the CP */
 453 static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
 454 {
 455         const u32 (*cp)[2];
 456         int i;
 457
 458         DRM_DEBUG("\n");
 459
 460         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
 461         case CHIP_R100:
 462         case CHIP_RV100:
 463         case CHIP_RV200:
 464         case CHIP_RS100:
 465         case CHIP_RS200:
 466                 DRM_INFO("Loading R100 Microcode\n");
 467                 cp = R100_cp_microcode;
 468                 break;
 469         case CHIP_R200:
 470         case CHIP_RV250:
 471         case CHIP_RV280:
 472         case CHIP_RS300:
 473                 DRM_INFO("Loading R200 Microcode\n");
 474                 cp = R200_cp_microcode;
 475                 break;
 476         case CHIP_R300:
 477         case CHIP_R350:
 478         case CHIP_RV350:
 479         case CHIP_RV380:
 480         case CHIP_RS400:
 481         case CHIP_RS480:
 482                 DRM_INFO("Loading R300 Microcode\n");
 483                 cp = R300_cp_microcode;
 484                 break;
 485         case CHIP_R420:
 486         case CHIP_R423:
 487         case CHIP_RV410:
 488                 DRM_INFO("Loading R400 Microcode\n");
 489                 cp = R420_cp_microcode;
 490                 break;
 491         case CHIP_RS690:
 492         case CHIP_RS740:
 493                 DRM_INFO("Loading RS690/RS740 Microcode\n");
 494                 cp = RS690_cp_microcode;
 495                 break;
 496         case CHIP_RS600:
 497                 DRM_INFO("Loading RS600 Microcode\n");
 498                 cp = RS600_cp_microcode;
 499                 break;
 500         case CHIP_RV515:
 501         case CHIP_R520:
 502         case CHIP_RV530:
 503         case CHIP_R580:
 504         case CHIP_RV560:
 505         case CHIP_RV570:
 506                 DRM_INFO("Loading R500 Microcode\n");
 507                 cp = R520_cp_microcode;
 508                 break;
 509         default:
 510                 return;
 511         }
 512
 513         radeon_do_wait_for_idle(dev_priv);
 514
 515         RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
 516
 517         for (i = 0; i != 256; i++) {
 518                 RADEON_WRITE(RADEON_CP_ME_RAM_DATAH, cp[i][1]);
 519                 RADEON_WRITE(RADEON_CP_ME_RAM_DATAL, cp[i][0]);
 520         }
 521 }
 522
 523 /* Flush any pending commands to the CP.  This should only be used just
 524  * prior to a wait for idle, as it informs the engine that the command
 525  * stream is ending.
 526  */
 527 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
 528 {
 529         DRM_DEBUG("\n");
 530 #if 0
 531         u32 tmp;
 532
 533         tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
 534         RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
 535 #endif
 536 }
 537
 538 /* Wait for the CP to go idle.
 539  */
 540 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
 541 {
 542         RING_LOCALS;
 543         DRM_DEBUG("\n");
 544
 545         BEGIN_RING(6);
 546
 547         RADEON_PURGE_CACHE();
 548         RADEON_PURGE_ZCACHE();
 549         RADEON_WAIT_UNTIL_IDLE();
 550
 551         ADVANCE_RING();
 552         COMMIT_RING();
 553
 554         return radeon_do_wait_for_idle(dev_priv);
 555 }
 556
 557 /* Start the Command Processor.
 558  */
 559 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
 560 {
 561         RING_LOCALS;
 562         DRM_DEBUG("\n");
 563
 564         radeon_do_wait_for_idle(dev_priv);
 565
 566         RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
 567
 568         dev_priv->cp_running = 1;
 569
 570         BEGIN_RING(8);
 571         /* isync can only be written through cp on r5xx write it here */
 572         OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
 573         OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D |
 574                  RADEON_ISYNC_ANY3D_IDLE2D |
 575                  RADEON_ISYNC_WAIT_IDLEGUI |
 576                  RADEON_ISYNC_CPSCRATCH_IDLEGUI);
 577         RADEON_PURGE_CACHE();
 578         RADEON_PURGE_ZCACHE();
 579         RADEON_WAIT_UNTIL_IDLE();
 580         ADVANCE_RING();
 581         COMMIT_RING();
 582
 583         dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
 584 }
 585
 586 /* Reset the Command Processor.  This will not flush any pending
 587  * commands, so you must wait for the CP command stream to complete
 588  * before calling this routine.
 589  */
 590 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
 591 {
 592         u32 cur_read_ptr;
 593         DRM_DEBUG("\n");
 594
 595         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
 596         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
 597         SET_RING_HEAD(dev_priv, cur_read_ptr);
 598         dev_priv->ring.tail = cur_read_ptr;
 599 }
 600
 601 /* Stop the Command Processor.  This will not flush any pending
 602  * commands, so you must flush the command stream and wait for the CP
 603  * to go idle before calling this routine.
 604  */
 605 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
 606 {
 607         DRM_DEBUG("\n");
 608
 609         RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
 610
 611         dev_priv->cp_running = 0;
 612 }
 613
 614 /* Reset the engine.  This will stop the CP if it is running.
 615  */
 616 static int radeon_do_engine_reset(struct drm_device * dev)
 617 {
 618         drm_radeon_private_t *dev_priv = dev->dev_private;
 619         u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
 620         DRM_DEBUG("\n");
 621
 622         radeon_do_pixcache_flush(dev_priv);
 623
 624         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
 625                 /* may need something similar for newer chips */
 626                 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
 627                 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
 628
 629                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
 630                                                     RADEON_FORCEON_MCLKA |
 631                                                     RADEON_FORCEON_MCLKB |
 632                                                     RADEON_FORCEON_YCLKA |
 633                                                     RADEON_FORCEON_YCLKB |
 634                                                     RADEON_FORCEON_MC |
 635                                                     RADEON_FORCEON_AIC));
 636         }
 637
 638         rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
 639
 640         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
 641                                               RADEON_SOFT_RESET_CP |
 642                                               RADEON_SOFT_RESET_HI |
 643                                               RADEON_SOFT_RESET_SE |
 644                                               RADEON_SOFT_RESET_RE |
 645                                               RADEON_SOFT_RESET_PP |
 646                                               RADEON_SOFT_RESET_E2 |
 647                                               RADEON_SOFT_RESET_RB));
 648         RADEON_READ(RADEON_RBBM_SOFT_RESET);
 649         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
 650                                               ~(RADEON_SOFT_RESET_CP |
 651                                                 RADEON_SOFT_RESET_HI |
 652                                                 RADEON_SOFT_RESET_SE |
 653                                                 RADEON_SOFT_RESET_RE |
 654                                                 RADEON_SOFT_RESET_PP |
 655                                                 RADEON_SOFT_RESET_E2 |
 656                                                 RADEON_SOFT_RESET_RB)));
 657         RADEON_READ(RADEON_RBBM_SOFT_RESET);
 658
 659         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
 660                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
 661                 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
 662                 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
 663         }
 664
 665         /* setup the raster pipes */
 666         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
 667             radeon_init_pipes(dev_priv);
 668
 669         /* Reset the CP ring */
 670         radeon_do_cp_reset(dev_priv);
 671
 672         /* The CP is no longer running after an engine reset */
 673         dev_priv->cp_running = 0;
 674
 675         /* Reset any pending vertex, indirect buffers */
 676         radeon_freelist_reset(dev);
 677
 678         return 0;
 679 }
 680
 681 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
 682                                        drm_radeon_private_t *dev_priv,
 683                                        struct drm_file *file_priv)
 684 {
 685         u32 ring_start, cur_read_ptr;
 686
 687         /* Initialize the memory controller. With new memory map, the fb location
 688          * is not changed, it should have been properly initialized already. Part
 689          * of the problem is that the code below is bogus, assuming the GART is
 690          * always appended to the fb which is not necessarily the case
 691          */
 692         if (!dev_priv->new_memmap)
 693                 radeon_write_fb_location(dev_priv,
 694                              ((dev_priv->gart_vm_start - 1) & 0xffff0000)
 695                              | (dev_priv->fb_location >> 16));
 696
 697 #if __OS_HAS_AGP
 698         if (dev_priv->flags & RADEON_IS_AGP) {
 699                 radeon_write_agp_base(dev_priv, dev->agp->base);
 700
 701                 radeon_write_agp_location(dev_priv,
 702                              (((dev_priv->gart_vm_start - 1 +
 703                                 dev_priv->gart_size) & 0xffff0000) |
 704                               (dev_priv->gart_vm_start >> 16)));
 705
 706                 ring_start = (dev_priv->cp_ring->offset
 707                               - dev->agp->base
 708                               + dev_priv->gart_vm_start);
 709         } else
 710 #endif
 711                 ring_start = (dev_priv->cp_ring->offset
 712                               - (unsigned long)dev->sg->virtual
 713                               + dev_priv->gart_vm_start);
 714
 715         RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
 716
 717         /* Set the write pointer delay */
 718         RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
 719
 720         /* Initialize the ring buffer's read and write pointers */
 721         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
 722         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
 723         SET_RING_HEAD(dev_priv, cur_read_ptr);
 724         dev_priv->ring.tail = cur_read_ptr;
 725
 726 #if __OS_HAS_AGP
 727         if (dev_priv->flags & RADEON_IS_AGP) {
 728                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
 729                              dev_priv->ring_rptr->offset
 730                              - dev->agp->base + dev_priv->gart_vm_start);
 731         } else
 732 #endif
 733         {
 734                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
 735                              dev_priv->ring_rptr->offset
 736                              - ((unsigned long) dev->sg->virtual)
 737                              + dev_priv->gart_vm_start);
 738         }
 739
 740         /* Set ring buffer size */
 741 #ifdef __BIG_ENDIAN
 742         RADEON_WRITE(RADEON_CP_RB_CNTL,
 743                      RADEON_BUF_SWAP_32BIT |
 744                      (dev_priv->ring.fetch_size_l2ow << 18) |
 745                      (dev_priv->ring.rptr_update_l2qw << 8) |
 746                      dev_priv->ring.size_l2qw);
 747 #else
 748         RADEON_WRITE(RADEON_CP_RB_CNTL,
 749                      (dev_priv->ring.fetch_size_l2ow << 18) |
 750                      (dev_priv->ring.rptr_update_l2qw << 8) |
 751                      dev_priv->ring.size_l2qw);
 752 #endif
 753
 754
 755         /* Initialize the scratch register pointer.  This will cause
 756          * the scratch register values to be written out to memory
 757          * whenever they are updated.
 758          *
 759          * We simply put this behind the ring read pointer, this works
 760          * with PCI GART as well as (whatever kind of) AGP GART
 761          */
 762         RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
 763                      + RADEON_SCRATCH_REG_OFFSET);
 764
 765         RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
 766
 767         radeon_enable_bm(dev_priv);
 768
 769         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(0), 0);
 770         RADEON_WRITE(RADEON_LAST_FRAME_REG, 0);
 771
 772         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
 773         RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0);
 774
 775         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(2), 0);
 776         RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0);
 777
 778         /* reset sarea copies of these */
 779         if (dev_priv->sarea_priv) {
 780                 dev_priv->sarea_priv->last_frame = 0;
 781                 dev_priv->sarea_priv->last_dispatch = 0;
 782                 dev_priv->sarea_priv->last_clear = 0;
 783         }
 784
 785         radeon_do_wait_for_idle(dev_priv);
 786
 787         /* Sync everything up */
 788         RADEON_WRITE(RADEON_ISYNC_CNTL,
 789                      (RADEON_ISYNC_ANY2D_IDLE3D |
 790                       RADEON_ISYNC_ANY3D_IDLE2D |
 791                       RADEON_ISYNC_WAIT_IDLEGUI |
 792                       RADEON_ISYNC_CPSCRATCH_IDLEGUI));
 793
 794 }
 795
 796 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
 797 {
 798         u32 tmp;
 799
 800         /* Start with assuming that writeback doesn't work */
 801         dev_priv->writeback_works = 0;
 802
 803         /* Writeback doesn't seem to work everywhere, test it here and possibly
 804          * enable it if it appears to work
 805          */
 806         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
 807
 808         RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
 809
 810         for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
 811                 u32 val;
 812
 813                 val = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1));
 814                 if (val == 0xdeadbeef)
 815                         break;
 816                 DRM_UDELAY(1);
 817         }
 818
 819         if (tmp < dev_priv->usec_timeout) {
 820                 dev_priv->writeback_works = 1;
 821                 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
 822         } else {
 823                 dev_priv->writeback_works = 0;
 824                 DRM_INFO("writeback test failed\n");
 825         }
 826         if (radeon_no_wb == 1) {
 827                 dev_priv->writeback_works = 0;
 828                 DRM_INFO("writeback forced off\n");
 829         }
 830
 831         if (!dev_priv->writeback_works) {
 832                 /* Disable writeback to avoid unnecessary bus master transfer */
 833                 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |
 834                              RADEON_RB_NO_UPDATE);
 835                 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
 836         }
 837 }
 838
 839 /* Enable or disable IGP GART on the chip */
 840 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
 841 {
 842         u32 temp;
 843
 844         if (on) {
 845                 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
 846                           dev_priv->gart_vm_start,
 847                           (long)dev_priv->gart_info.bus_addr,
 848                           dev_priv->gart_size);
 849
 850                 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
 851                 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
 852                     ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
 853                         IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
 854                                                              RS690_BLOCK_GFX_D3_EN));
 855                 else
 856                         IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
 857
 858                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
 859                                                                RS480_VA_SIZE_32MB));
 860
 861                 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
 862                 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
 863                                                         RS480_TLB_ENABLE |
 864                                                         RS480_GTW_LAC_EN |
 865                                                         RS480_1LEVEL_GART));
 866
 867                 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
 868                 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
 869                 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
 870
 871                 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
 872                 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
 873                                                       RS480_REQ_TYPE_SNOOP_DIS));
 874
 875                 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
 876
 877                 dev_priv->gart_size = 32*1024*1024;
 878                 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
 879                          0xffff0000) | (dev_priv->gart_vm_start >> 16));
 880
 881                 radeon_write_agp_location(dev_priv, temp);
 882
 883                 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
 884                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
 885                                                                RS480_VA_SIZE_32MB));
 886
 887                 do {
 888                         temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
 889                         if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
 890                                 break;
 891                         DRM_UDELAY(1);
 892                 } while (1);
 893
 894                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
 895                                 RS480_GART_CACHE_INVALIDATE);
 896
 897                 do {
 898                         temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
 899                         if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
 900                                 break;
 901                         DRM_UDELAY(1);
 902                 } while (1);
 903
 904                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
 905         } else {
 906                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
 907         }
 908 }
 909
 910 /* Enable or disable IGP GART on the chip */
 911 static void rs600_set_igpgart(drm_radeon_private_t *dev_priv, int on)
 912 {
 913         u32 temp;
 914         int i;
 915
 916         if (on) {
 917                 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
 918                          dev_priv->gart_vm_start,
 919                          (long)dev_priv->gart_info.bus_addr,
 920                          dev_priv->gart_size);
 921
 922                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (RS600_EFFECTIVE_L2_CACHE_SIZE(6) |
 923                                                     RS600_EFFECTIVE_L2_QUEUE_SIZE(6)));
 924
 925                 for (i = 0; i < 19; i++)
 926                         IGP_WRITE_MCIND(RS600_MC_PT0_CLIENT0_CNTL + i,
 927                                         (RS600_ENABLE_TRANSLATION_MODE_OVERRIDE |
 928                                          RS600_SYSTEM_ACCESS_MODE_IN_SYS |
 929                                          RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH |
 930                                          RS600_EFFECTIVE_L1_CACHE_SIZE(3) |
 931                                          RS600_ENABLE_FRAGMENT_PROCESSING |
 932                                          RS600_EFFECTIVE_L1_QUEUE_SIZE(3)));
 933
 934                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL, (RS600_ENABLE_PAGE_TABLE |
 935                                                              RS600_PAGE_TABLE_TYPE_FLAT));
 936
 937                 /* disable all other contexts */
 938                 for (i = 1; i < 8; i++)
 939                         IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL + i, 0);
 940
 941                 /* setup the page table aperture */
 942                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
 943                                 dev_priv->gart_info.bus_addr);
 944                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR,
 945                                 dev_priv->gart_vm_start);
 946                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR,
 947                                 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
 948                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
 949
 950                 /* setup the system aperture */
 951                 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR,
 952                                 dev_priv->gart_vm_start);
 953                 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR,
 954                                 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
 955
 956                 /* enable page tables */
 957                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
 958                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (temp | RS600_ENABLE_PT));
 959
 960                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
 961                 IGP_WRITE_MCIND(RS600_MC_CNTL1, (temp | RS600_ENABLE_PAGE_TABLES));
 962
 963                 /* invalidate the cache */
 964                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
 965
 966                 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
 967                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
 968                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
 969
 970                 temp |= RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE;
 971                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
 972                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
 973
 974                 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
 975                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
 976                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
 977
 978         } else {
 979                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, 0);
 980                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
 981                 temp &= ~RS600_ENABLE_PAGE_TABLES;
 982                 IGP_WRITE_MCIND(RS600_MC_CNTL1, temp);
 983         }
 984 }
 985
 986 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
 987 {
 988         u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
 989         if (on) {
 990
 991                 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
 992                           dev_priv->gart_vm_start,
 993                           (long)dev_priv->gart_info.bus_addr,
 994                           dev_priv->gart_size);
 995                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
 996                                   dev_priv->gart_vm_start);
 997                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
 998                                   dev_priv->gart_info.bus_addr);
 999                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
1000                                   dev_priv->gart_vm_start);
1001                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
1002                                   dev_priv->gart_vm_start +
1003                                   dev_priv->gart_size - 1);
1004
1005                 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
1006
1007                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1008                                   RADEON_PCIE_TX_GART_EN);
1009         } else {
1010                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1011                                   tmp & ~RADEON_PCIE_TX_GART_EN);
1012         }
1013 }
1014
1015 /* Enable or disable PCI GART on the chip */
1016 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
1017 {
1018         u32 tmp;
1019
1020         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
1021             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) ||
1022             (dev_priv->flags & RADEON_IS_IGPGART)) {
1023                 radeon_set_igpgart(dev_priv, on);
1024                 return;
1025         }
1026
1027         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
1028                 rs600_set_igpgart(dev_priv, on);
1029                 return;
1030         }
1031
1032         if (dev_priv->flags & RADEON_IS_PCIE) {
1033                 radeon_set_pciegart(dev_priv, on);
1034                 return;
1035         }
1036
1037         tmp = RADEON_READ(RADEON_AIC_CNTL);
1038
1039         if (on) {
1040                 RADEON_WRITE(RADEON_AIC_CNTL,
1041                              tmp | RADEON_PCIGART_TRANSLATE_EN);
1042
1043                 /* set PCI GART page-table base address
1044                  */
1045                 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
1046
1047                 /* set address range for PCI address translate
1048                  */
1049                 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
1050                 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
1051                              + dev_priv->gart_size - 1);
1052
1053                 /* Turn off AGP aperture -- is this required for PCI GART?
1054                  */
1055                 radeon_write_agp_location(dev_priv, 0xffffffc0);
1056                 RADEON_WRITE(RADEON_AGP_COMMAND, 0);    /* clear AGP_COMMAND */
1057         } else {
1058                 RADEON_WRITE(RADEON_AIC_CNTL,
1059                              tmp & ~RADEON_PCIGART_TRANSLATE_EN);
1060         }
1061 }
1062
1063 static int radeon_setup_pcigart_surface(drm_radeon_private_t *dev_priv)
1064 {
1065         struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info;
1066         struct radeon_virt_surface *vp;
1067         int i;
1068
1069         for (i = 0; i < RADEON_MAX_SURFACES * 2; i++) {
1070                 if (!dev_priv->virt_surfaces[i].file_priv ||
1071                     dev_priv->virt_surfaces[i].file_priv == PCIGART_FILE_PRIV)
1072                         break;
1073         }
1074         if (i >= 2 * RADEON_MAX_SURFACES)
1075                 return -ENOMEM;
1076         vp = &dev_priv->virt_surfaces[i];
1077
1078         for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1079                 struct radeon_surface *sp = &dev_priv->surfaces[i];
1080                 if (sp->refcount)
1081                         continue;
1082
1083                 vp->surface_index = i;
1084                 vp->lower = gart_info->bus_addr;
1085                 vp->upper = vp->lower + gart_info->table_size;
1086                 vp->flags = 0;
1087                 vp->file_priv = PCIGART_FILE_PRIV;
1088
1089                 sp->refcount = 1;
1090                 sp->lower = vp->lower;
1091                 sp->upper = vp->upper;
1092                 sp->flags = 0;
1093
1094                 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, sp->flags);
1095                 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * i, sp->lower);
1096                 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * i, sp->upper);
1097                 return 0;
1098         }
1099
1100         return -ENOMEM;
1101 }
1102
1103 static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
1104                              struct drm_file *file_priv)
1105 {
1106         drm_radeon_private_t *dev_priv = dev->dev_private;
1107
1108         DRM_DEBUG("\n");
1109
1110         /* if we require new memory map but we don't have it fail */
1111         if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1112                 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
1113                 radeon_do_cleanup_cp(dev);
1114                 return -EINVAL;
1115         }
1116
1117         if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
1118                 DRM_DEBUG("Forcing AGP card to PCI mode\n");
1119                 dev_priv->flags &= ~RADEON_IS_AGP;
1120         } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
1121                    && !init->is_pci) {
1122                 DRM_DEBUG("Restoring AGP flag\n");
1123                 dev_priv->flags |= RADEON_IS_AGP;
1124         }
1125
1126         if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
1127                 DRM_ERROR("PCI GART memory not allocated!\n");
1128                 radeon_do_cleanup_cp(dev);
1129                 return -EINVAL;
1130         }
1131
1132         dev_priv->usec_timeout = init->usec_timeout;
1133         if (dev_priv->usec_timeout < 1 ||
1134             dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1135                 DRM_DEBUG("TIMEOUT problem!\n");
1136                 radeon_do_cleanup_cp(dev);
1137                 return -EINVAL;
1138         }
1139
1140         /* Enable vblank on CRTC1 for older X servers
1141          */
1142         dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1143
1144         switch(init->func) {
1145         case RADEON_INIT_R200_CP:
1146                 dev_priv->microcode_version = UCODE_R200;
1147                 break;
1148         case RADEON_INIT_R300_CP:
1149                 dev_priv->microcode_version = UCODE_R300;
1150                 break;
1151         default:
1152                 dev_priv->microcode_version = UCODE_R100;
1153         }
1154
1155         dev_priv->do_boxes = 0;
1156         dev_priv->cp_mode = init->cp_mode;
1157
1158         /* We don't support anything other than bus-mastering ring mode,
1159          * but the ring can be in either AGP or PCI space for the ring
1160          * read pointer.
1161          */
1162         if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1163             (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1164                 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1165                 radeon_do_cleanup_cp(dev);
1166                 return -EINVAL;
1167         }
1168
1169         switch (init->fb_bpp) {
1170         case 16:
1171                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1172                 break;
1173         case 32:
1174         default:
1175                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1176                 break;
1177         }
1178         dev_priv->front_offset = init->front_offset;
1179         dev_priv->front_pitch = init->front_pitch;
1180         dev_priv->back_offset = init->back_offset;
1181         dev_priv->back_pitch = init->back_pitch;
1182
1183         switch (init->depth_bpp) {
1184         case 16:
1185                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1186                 break;
1187         case 32:
1188         default:
1189                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1190                 break;
1191         }
1192         dev_priv->depth_offset = init->depth_offset;
1193         dev_priv->depth_pitch = init->depth_pitch;
1194
1195         /* Hardware state for depth clears.  Remove this if/when we no
1196          * longer clear the depth buffer with a 3D rectangle.  Hard-code
1197          * all values to prevent unwanted 3D state from slipping through
1198          * and screwing with the clear operation.
1199          */
1200         dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1201                                            (dev_priv->color_fmt << 10) |
1202                                            (dev_priv->microcode_version ==
1203                                             UCODE_R100 ? RADEON_ZBLOCK16 : 0));
1204
1205         dev_priv->depth_clear.rb3d_zstencilcntl =
1206             (dev_priv->depth_fmt |
1207              RADEON_Z_TEST_ALWAYS |
1208              RADEON_STENCIL_TEST_ALWAYS |
1209              RADEON_STENCIL_S_FAIL_REPLACE |
1210              RADEON_STENCIL_ZPASS_REPLACE |
1211              RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
1212
1213         dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1214                                          RADEON_BFACE_SOLID |
1215                                          RADEON_FFACE_SOLID |
1216                                          RADEON_FLAT_SHADE_VTX_LAST |
1217                                          RADEON_DIFFUSE_SHADE_FLAT |
1218                                          RADEON_ALPHA_SHADE_FLAT |
1219                                          RADEON_SPECULAR_SHADE_FLAT |
1220                                          RADEON_FOG_SHADE_FLAT |
1221                                          RADEON_VTX_PIX_CENTER_OGL |
1222                                          RADEON_ROUND_MODE_TRUNC |
1223                                          RADEON_ROUND_PREC_8TH_PIX);
1224
1225
1226         dev_priv->ring_offset = init->ring_offset;
1227         dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1228         dev_priv->buffers_offset = init->buffers_offset;
1229         dev_priv->gart_textures_offset = init->gart_textures_offset;
1230
1231         dev_priv->sarea = drm_getsarea(dev);
1232         if (!dev_priv->sarea) {
1233                 DRM_ERROR("could not find sarea!\n");
1234                 radeon_do_cleanup_cp(dev);
1235                 return -EINVAL;
1236         }
1237
1238         dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1239         if (!dev_priv->cp_ring) {
1240                 DRM_ERROR("could not find cp ring region!\n");
1241                 radeon_do_cleanup_cp(dev);
1242                 return -EINVAL;
1243         }
1244         dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1245         if (!dev_priv->ring_rptr) {
1246                 DRM_ERROR("could not find ring read pointer!\n");
1247                 radeon_do_cleanup_cp(dev);
1248                 return -EINVAL;
1249         }
1250         dev->agp_buffer_token = init->buffers_offset;
1251         dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1252         if (!dev->agp_buffer_map) {
1253                 DRM_ERROR("could not find dma buffer region!\n");
1254                 radeon_do_cleanup_cp(dev);
1255                 return -EINVAL;
1256         }
1257
1258         if (init->gart_textures_offset) {
1259                 dev_priv->gart_textures =
1260                     drm_core_findmap(dev, init->gart_textures_offset);
1261                 if (!dev_priv->gart_textures) {
1262                         DRM_ERROR("could not find GART texture region!\n");
1263                         radeon_do_cleanup_cp(dev);
1264                         return -EINVAL;
1265                 }
1266         }
1267
1268         dev_priv->sarea_priv =
1269             (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle +
1270                                     init->sarea_priv_offset);
1271
1272 #if __OS_HAS_AGP
1273         if (dev_priv->flags & RADEON_IS_AGP) {
1274                 drm_core_ioremap_wc(dev_priv->cp_ring, dev);
1275                 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
1276                 drm_core_ioremap_wc(dev->agp_buffer_map, dev);
1277                 if (!dev_priv->cp_ring->handle ||
1278                     !dev_priv->ring_rptr->handle ||
1279                     !dev->agp_buffer_map->handle) {
1280                         DRM_ERROR("could not find ioremap agp regions!\n");
1281                         radeon_do_cleanup_cp(dev);
1282                         return -EINVAL;
1283                 }
1284         } else
1285 #endif
1286         {
1287                 dev_priv->cp_ring->handle =
1288                         (void *)(unsigned long)dev_priv->cp_ring->offset;
1289                 dev_priv->ring_rptr->handle =
1290                         (void *)(unsigned long)dev_priv->ring_rptr->offset;
1291                 dev->agp_buffer_map->handle =
1292                         (void *)(unsigned long)dev->agp_buffer_map->offset;
1293
1294                 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1295                           dev_priv->cp_ring->handle);
1296                 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1297                           dev_priv->ring_rptr->handle);
1298                 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1299                           dev->agp_buffer_map->handle);
1300         }
1301
1302         dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
1303         dev_priv->fb_size =
1304                 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
1305                 - dev_priv->fb_location;
1306
1307         dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1308                                         ((dev_priv->front_offset
1309                                           + dev_priv->fb_location) >> 10));
1310
1311         dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1312                                        ((dev_priv->back_offset
1313                                          + dev_priv->fb_location) >> 10));
1314
1315         dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1316                                         ((dev_priv->depth_offset
1317                                           + dev_priv->fb_location) >> 10));
1318
1319         dev_priv->gart_size = init->gart_size;
1320
1321         /* New let's set the memory map ... */
1322         if (dev_priv->new_memmap) {
1323                 u32 base = 0;
1324
1325                 DRM_INFO("Setting GART location based on new memory map\n");
1326
1327                 /* If using AGP, try to locate the AGP aperture at the same
1328                  * location in the card and on the bus, though we have to
1329                  * align it down.
1330                  */
1331 #if __OS_HAS_AGP
1332                 if (dev_priv->flags & RADEON_IS_AGP) {
1333                         base = dev->agp->base;
1334                         /* Check if valid */
1335                         if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1336                             base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1337                                 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1338                                          dev->agp->base);
1339                                 base = 0;
1340                         }
1341                 }
1342 #endif
1343                 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1344                 if (base == 0) {
1345                         base = dev_priv->fb_location + dev_priv->fb_size;
1346                         if (base < dev_priv->fb_location ||
1347                             ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1348                                 base = dev_priv->fb_location
1349                                         - dev_priv->gart_size;
1350                 }
1351                 dev_priv->gart_vm_start = base & 0xffc00000u;
1352                 if (dev_priv->gart_vm_start != base)
1353                         DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1354                                  base, dev_priv->gart_vm_start);
1355         } else {
1356                 DRM_INFO("Setting GART location based on old memory map\n");
1357                 dev_priv->gart_vm_start = dev_priv->fb_location +
1358                         RADEON_READ(RADEON_CONFIG_APER_SIZE);
1359         }
1360
1361 #if __OS_HAS_AGP
1362         if (dev_priv->flags & RADEON_IS_AGP)
1363                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1364                                                  - dev->agp->base
1365                                                  + dev_priv->gart_vm_start);
1366         else
1367 #endif
1368                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1369                                         - (unsigned long)dev->sg->virtual
1370                                         + dev_priv->gart_vm_start);
1371
1372         DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1373         DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1374         DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1375                   dev_priv->gart_buffers_offset);
1376
1377         dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1378         dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1379                               + init->ring_size / sizeof(u32));
1380         dev_priv->ring.size = init->ring_size;
1381         dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1382
1383         dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1384         dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1385
1386         dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1387         dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1388         dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1389
1390         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1391
1392 #if __OS_HAS_AGP
1393         if (dev_priv->flags & RADEON_IS_AGP) {
1394                 /* Turn off PCI GART */
1395                 radeon_set_pcigart(dev_priv, 0);
1396         } else
1397 #endif
1398         {
1399                 u32 sctrl;
1400                 int ret;
1401
1402                 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1403                 /* if we have an offset set from userspace */
1404                 if (dev_priv->pcigart_offset_set) {
1405                         dev_priv->gart_info.bus_addr =
1406                             dev_priv->pcigart_offset + dev_priv->fb_location;
1407                         dev_priv->gart_info.mapping.offset =
1408                             dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1409                         dev_priv->gart_info.mapping.size =
1410                             dev_priv->gart_info.table_size;
1411
1412                         drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
1413                         dev_priv->gart_info.addr =
1414                             dev_priv->gart_info.mapping.handle;
1415
1416                         if (dev_priv->flags & RADEON_IS_PCIE)
1417                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1418                         else
1419                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1420                         dev_priv->gart_info.gart_table_location =
1421                             DRM_ATI_GART_FB;
1422
1423                         DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1424                                   dev_priv->gart_info.addr,
1425                                   dev_priv->pcigart_offset);
1426                 } else {
1427                         if (dev_priv->flags & RADEON_IS_IGPGART)
1428                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1429                         else
1430                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1431                         dev_priv->gart_info.gart_table_location =
1432                             DRM_ATI_GART_MAIN;
1433                         dev_priv->gart_info.addr = NULL;
1434                         dev_priv->gart_info.bus_addr = 0;
1435                         if (dev_priv->flags & RADEON_IS_PCIE) {
1436                                 DRM_ERROR
1437                                     ("Cannot use PCI Express without GART in FB memory\n");
1438                                 radeon_do_cleanup_cp(dev);
1439                                 return -EINVAL;
1440                         }
1441                 }
1442
1443                 sctrl = RADEON_READ(RADEON_SURFACE_CNTL);
1444                 RADEON_WRITE(RADEON_SURFACE_CNTL, 0);
1445                 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1446                         ret = r600_page_table_init(dev);
1447                 else
1448                         ret = drm_ati_pcigart_init(dev, &dev_priv->gart_info);
1449                 RADEON_WRITE(RADEON_SURFACE_CNTL, sctrl);
1450
1451                 if (!ret) {
1452                         DRM_ERROR("failed to init PCI GART!\n");
1453                         radeon_do_cleanup_cp(dev);
1454                         return -ENOMEM;
1455                 }
1456
1457                 ret = radeon_setup_pcigart_surface(dev_priv);
1458                 if (ret) {
1459                         DRM_ERROR("failed to setup GART surface!\n");
1460                         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1461                                 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1462                         else
1463                                 drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info);
1464                         radeon_do_cleanup_cp(dev);
1465                         return ret;
1466                 }
1467
1468                 /* Turn on PCI GART */
1469                 radeon_set_pcigart(dev_priv, 1);
1470         }
1471
1472         radeon_cp_load_microcode(dev_priv);
1473         radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1474
1475         dev_priv->last_buf = 0;
1476
1477         radeon_do_engine_reset(dev);
1478         radeon_test_writeback(dev_priv);
1479
1480         return 0;
1481 }
1482
1483 static int radeon_do_cleanup_cp(struct drm_device * dev)
1484 {
1485         drm_radeon_private_t *dev_priv = dev->dev_private;
1486         DRM_DEBUG("\n");
1487
1488         /* Make sure interrupts are disabled here because the uninstall ioctl
1489          * may not have been called from userspace and after dev_private
1490          * is freed, it's too late.
1491          */
1492         if (dev->irq_enabled)
1493                 drm_irq_uninstall(dev);
1494
1495 #if __OS_HAS_AGP
1496         if (dev_priv->flags & RADEON_IS_AGP) {
1497                 if (dev_priv->cp_ring != NULL) {
1498                         drm_core_ioremapfree(dev_priv->cp_ring, dev);
1499                         dev_priv->cp_ring = NULL;
1500                 }
1501                 if (dev_priv->ring_rptr != NULL) {
1502                         drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1503                         dev_priv->ring_rptr = NULL;
1504                 }
1505                 if (dev->agp_buffer_map != NULL) {
1506                         drm_core_ioremapfree(dev->agp_buffer_map, dev);
1507                         dev->agp_buffer_map = NULL;
1508                 }
1509         } else
1510 #endif
1511         {
1512
1513                 if (dev_priv->gart_info.bus_addr) {
1514                         /* Turn off PCI GART */
1515                         radeon_set_pcigart(dev_priv, 0);
1516                         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1517                                 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1518                         else {
1519                                 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1520                                         DRM_ERROR("failed to cleanup PCI GART!\n");
1521                         }
1522                 }
1523
1524                 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1525                 {
1526                         drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1527                         dev_priv->gart_info.addr = 0;
1528                 }
1529         }
1530         /* only clear to the start of flags */
1531         memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1532
1533         return 0;
1534 }
1535
1536 /* This code will reinit the Radeon CP hardware after a resume from disc.
1537  * AFAIK, it would be very difficult to pickle the state at suspend time, so
1538  * here we make sure that all Radeon hardware initialisation is re-done without
1539  * affecting running applications.
1540  *
1541  * Charl P. Botha <http://cpbotha.net>
1542  */
1543 static int radeon_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv)
1544 {
1545         drm_radeon_private_t *dev_priv = dev->dev_private;
1546
1547         if (!dev_priv) {
1548                 DRM_ERROR("Called with no initialization\n");
1549                 return -EINVAL;
1550         }
1551
1552         DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1553
1554 #if __OS_HAS_AGP
1555         if (dev_priv->flags & RADEON_IS_AGP) {
1556                 /* Turn off PCI GART */
1557                 radeon_set_pcigart(dev_priv, 0);
1558         } else
1559 #endif
1560         {
1561                 /* Turn on PCI GART */
1562                 radeon_set_pcigart(dev_priv, 1);
1563         }
1564
1565         radeon_cp_load_microcode(dev_priv);
1566         radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1567
1568         radeon_do_engine_reset(dev);
1569         radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
1570
1571         DRM_DEBUG("radeon_do_resume_cp() complete\n");
1572
1573         return 0;
1574 }
1575
1576 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1577 {
1578         drm_radeon_private_t *dev_priv = dev->dev_private;
1579         drm_radeon_init_t *init = data;
1580
1581         LOCK_TEST_WITH_RETURN(dev, file_priv);
1582
1583         if (init->func == RADEON_INIT_R300_CP)
1584                 r300_init_reg_flags(dev);
1585
1586         switch (init->func) {
1587         case RADEON_INIT_CP:
1588         case RADEON_INIT_R200_CP:
1589         case RADEON_INIT_R300_CP:
1590                 return radeon_do_init_cp(dev, init, file_priv);
1591         case RADEON_INIT_R600_CP:
1592                 return r600_do_init_cp(dev, init, file_priv);
1593         case RADEON_CLEANUP_CP:
1594                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1595                         return r600_do_cleanup_cp(dev);
1596                 else
1597                         return radeon_do_cleanup_cp(dev);
1598         }
1599
1600         return -EINVAL;
1601 }
1602
1603 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1604 {
1605         drm_radeon_private_t *dev_priv = dev->dev_private;
1606         DRM_DEBUG("\n");
1607
1608         LOCK_TEST_WITH_RETURN(dev, file_priv);
1609
1610         if (dev_priv->cp_running) {
1611                 DRM_DEBUG("while CP running\n");
1612                 return 0;
1613         }
1614         if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1615                 DRM_DEBUG("called with bogus CP mode (%d)\n",
1616                           dev_priv->cp_mode);
1617                 return 0;
1618         }
1619
1620         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1621                 r600_do_cp_start(dev_priv);
1622         else
1623                 radeon_do_cp_start(dev_priv);
1624
1625         return 0;
1626 }
1627
1628 /* Stop the CP.  The engine must have been idled before calling this
1629  * routine.
1630  */
1631 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1632 {
1633         drm_radeon_private_t *dev_priv = dev->dev_private;
1634         drm_radeon_cp_stop_t *stop = data;
1635         int ret;
1636         DRM_DEBUG("\n");
1637
1638         LOCK_TEST_WITH_RETURN(dev, file_priv);
1639
1640         if (!dev_priv->cp_running)
1641                 return 0;
1642
1643         /* Flush any pending CP commands.  This ensures any outstanding
1644          * commands are exectuted by the engine before we turn it off.
1645          */
1646         if (stop->flush) {
1647                 radeon_do_cp_flush(dev_priv);
1648         }
1649
1650         /* If we fail to make the engine go idle, we return an error
1651          * code so that the DRM ioctl wrapper can try again.
1652          */
1653         if (stop->idle) {
1654                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1655                         ret = r600_do_cp_idle(dev_priv);
1656                 else
1657                         ret = radeon_do_cp_idle(dev_priv);
1658                 if (ret)
1659                         return ret;
1660         }
1661
1662         /* Finally, we can turn off the CP.  If the engine isn't idle,
1663          * we will get some dropped triangles as they won't be fully
1664          * rendered before the CP is shut down.
1665          */
1666         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1667                 r600_do_cp_stop(dev_priv);
1668         else
1669                 radeon_do_cp_stop(dev_priv);
1670
1671         /* Reset the engine */
1672         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1673                 r600_do_engine_reset(dev);
1674         else
1675                 radeon_do_engine_reset(dev);
1676
1677         return 0;
1678 }
1679
1680 void radeon_do_release(struct drm_device * dev)
1681 {
1682         drm_radeon_private_t *dev_priv = dev->dev_private;
1683         int i, ret;
1684
1685         if (dev_priv) {
1686                 if (dev_priv->cp_running) {
1687                         /* Stop the cp */
1688                         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1689                                 while ((ret = r600_do_cp_idle(dev_priv)) != 0) {
1690                                         DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1691                                         crit_enter();
1692                                         tsleep_interlock((void *)&dev->lock.lock_queue);
1693                                         DRM_UNLOCK();
1694                                         ret = tsleep((void *)&dev->lock.lock_queue, PCATCH,
1695                                             "rdnrel", 0);
1696                                         crit_exit();
1697                                         DRM_LOCK();
1698                                 }
1699                         } else {
1700                                 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1701                                         DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1702                                         crit_enter();
1703                                         tsleep_interlock((void *)&dev->lock.lock_queue);
1704                                         DRM_UNLOCK();
1705                                         ret = tsleep((void *)&dev->lock.lock_queue, PCATCH,
1706                                             "rdnrel", 0);
1707                                         crit_exit();
1708                                         DRM_LOCK();
1709                                 }
1710                         }
1711                         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1712                                 r600_do_cp_stop(dev_priv);
1713                                 r600_do_engine_reset(dev);
1714                         } else {
1715                                 radeon_do_cp_stop(dev_priv);
1716                                 radeon_do_engine_reset(dev);
1717                         }
1718                 }
1719
1720                 if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_R600) {
1721                         /* Disable *all* interrupts */
1722                         if (dev_priv->mmio)     /* remove this after permanent addmaps */
1723                                 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1724
1725                         if (dev_priv->mmio) {   /* remove all surfaces */
1726                                 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1727                                         RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1728                                         RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1729                                                      16 * i, 0);
1730                                         RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1731                                                      16 * i, 0);
1732                                 }
1733                         }
1734                 }
1735
1736                 /* Free memory heap structures */
1737                 radeon_mem_takedown(&(dev_priv->gart_heap));
1738                 radeon_mem_takedown(&(dev_priv->fb_heap));
1739
1740                 /* deallocate kernel resources */
1741                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1742                         r600_do_cleanup_cp(dev);
1743                 else
1744                         radeon_do_cleanup_cp(dev);
1745         }
1746 }
1747
1748 /* Just reset the CP ring.  Called as part of an X Server engine reset.
1749  */
1750 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1751 {
1752         drm_radeon_private_t *dev_priv = dev->dev_private;
1753         DRM_DEBUG("\n");
1754
1755         LOCK_TEST_WITH_RETURN(dev, file_priv);
1756
1757         if (!dev_priv) {
1758                 DRM_DEBUG("called before init done\n");
1759                 return -EINVAL;
1760         }
1761
1762         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1763                 r600_do_cp_reset(dev_priv);
1764         else
1765                 radeon_do_cp_reset(dev_priv);
1766
1767         /* The CP is no longer running after an engine reset */
1768         dev_priv->cp_running = 0;
1769
1770         return 0;
1771 }
1772
1773 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1774 {
1775         drm_radeon_private_t *dev_priv = dev->dev_private;
1776         DRM_DEBUG("\n");
1777
1778         LOCK_TEST_WITH_RETURN(dev, file_priv);
1779
1780         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1781                 return r600_do_cp_idle(dev_priv);
1782         else
1783                 return radeon_do_cp_idle(dev_priv);
1784 }
1785
1786 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1787  */
1788 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1789 {
1790         drm_radeon_private_t *dev_priv = dev->dev_private;
1791         DRM_DEBUG("\n");
1792
1793         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1794                 return r600_do_resume_cp(dev, file_priv);
1795         else
1796                 return radeon_do_resume_cp(dev, file_priv);
1797 }
1798
1799 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1800 {
1801         drm_radeon_private_t *dev_priv = dev->dev_private;
1802         DRM_DEBUG("\n");
1803
1804         LOCK_TEST_WITH_RETURN(dev, file_priv);
1805
1806         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1807                 return r600_do_engine_reset(dev);
1808         else
1809                 return radeon_do_engine_reset(dev);
1810 }
1811
1812 /* ================================================================
1813  * Fullscreen mode
1814  */
1815
1816 /* KW: Deprecated to say the least:
1817  */
1818 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1819 {
1820         return 0;
1821 }
1822
1823 /* ================================================================
1824  * Freelist management
1825  */
1826
1827 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1828  *   bufs until freelist code is used.  Note this hides a problem with
1829  *   the scratch register * (used to keep track of last buffer
1830  *   completed) being written to before * the last buffer has actually
1831  *   completed rendering.
1832  *
1833  * KW:  It's also a good way to find free buffers quickly.
1834  *
1835  * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1836  * sleep.  However, bugs in older versions of radeon_accel.c mean that
1837  * we essentially have to do this, else old clients will break.
1838  *
1839  * However, it does leave open a potential deadlock where all the
1840  * buffers are held by other clients, which can't release them because
1841  * they can't get the lock.
1842  */
1843
1844 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1845 {
1846         struct drm_device_dma *dma = dev->dma;
1847         drm_radeon_private_t *dev_priv = dev->dev_private;
1848         drm_radeon_buf_priv_t *buf_priv;
1849         struct drm_buf *buf;
1850         int i, t;
1851         int start;
1852
1853         if (++dev_priv->last_buf >= dma->buf_count)
1854                 dev_priv->last_buf = 0;
1855
1856         start = dev_priv->last_buf;
1857
1858         for (t = 0; t < dev_priv->usec_timeout; t++) {
1859                 u32 done_age = GET_SCRATCH(dev_priv, 1);
1860                 DRM_DEBUG("done_age = %d\n", done_age);
1861                 for (i = start; i < dma->buf_count; i++) {
1862                         buf = dma->buflist[i];
1863                         buf_priv = buf->dev_private;
1864                         if (buf->file_priv == NULL || (buf->pending &&
1865                                                        buf_priv->age <=
1866                                                        done_age)) {
1867                                 dev_priv->stats.requested_bufs++;
1868                                 buf->pending = 0;
1869                                 return buf;
1870                         }
1871                         start = 0;
1872                 }
1873
1874                 if (t) {
1875                         DRM_UDELAY(1);
1876                         dev_priv->stats.freelist_loops++;
1877                 }
1878         }
1879
1880         DRM_DEBUG("returning NULL!\n");
1881         return NULL;
1882 }
1883
1884 #if 0
1885 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1886 {
1887         struct drm_device_dma *dma = dev->dma;
1888         drm_radeon_private_t *dev_priv = dev->dev_private;
1889         drm_radeon_buf_priv_t *buf_priv;
1890         struct drm_buf *buf;
1891         int i, t;
1892         int start;
1893         u32 done_age;
1894
1895         done_age = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1));
1896         if (++dev_priv->last_buf >= dma->buf_count)
1897                 dev_priv->last_buf = 0;
1898
1899         start = dev_priv->last_buf;
1900         dev_priv->stats.freelist_loops++;
1901
1902         for (t = 0; t < 2; t++) {
1903                 for (i = start; i < dma->buf_count; i++) {
1904                         buf = dma->buflist[i];
1905                         buf_priv = buf->dev_private;
1906                         if (buf->file_priv == 0 || (buf->pending &&
1907                                                     buf_priv->age <=
1908                                                     done_age)) {
1909                                 dev_priv->stats.requested_bufs++;
1910                                 buf->pending = 0;
1911                                 return buf;
1912                         }
1913                 }
1914                 start = 0;
1915         }
1916
1917         return NULL;
1918 }
1919 #endif
1920
1921 void radeon_freelist_reset(struct drm_device * dev)
1922 {
1923         struct drm_device_dma *dma = dev->dma;
1924         drm_radeon_private_t *dev_priv = dev->dev_private;
1925         int i;
1926
1927         dev_priv->last_buf = 0;
1928         for (i = 0; i < dma->buf_count; i++) {
1929                 struct drm_buf *buf = dma->buflist[i];
1930                 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1931                 buf_priv->age = 0;
1932         }
1933 }
1934
1935 /* ================================================================
1936  * CP command submission
1937  */
1938
1939 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1940 {
1941         drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1942         int i;
1943         u32 last_head = GET_RING_HEAD(dev_priv);
1944
1945         for (i = 0; i < dev_priv->usec_timeout; i++) {
1946                 u32 head = GET_RING_HEAD(dev_priv);
1947
1948                 ring->space = (head - ring->tail) * sizeof(u32);
1949                 if (ring->space <= 0)
1950                         ring->space += ring->size;
1951                 if (ring->space > n)
1952                         return 0;
1953
1954                 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1955
1956                 if (head != last_head)
1957                         i = 0;
1958                 last_head = head;
1959
1960                 DRM_UDELAY(1);
1961         }
1962
1963         /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1964 #if RADEON_FIFO_DEBUG
1965         radeon_status(dev_priv);
1966         DRM_ERROR("failed!\n");
1967 #endif
1968         return -EBUSY;
1969 }
1970
1971 static int radeon_cp_get_buffers(struct drm_device *dev,
1972                                  struct drm_file *file_priv,
1973                                  struct drm_dma * d)
1974 {
1975         int i;
1976         struct drm_buf *buf;
1977
1978         for (i = d->granted_count; i < d->request_count; i++) {
1979                 buf = radeon_freelist_get(dev);
1980                 if (!buf)
1981                         return -EBUSY;  /* NOTE: broken client */
1982
1983                 buf->file_priv = file_priv;
1984
1985                 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
1986                                      sizeof(buf->idx)))
1987                         return -EFAULT;
1988                 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
1989                                      sizeof(buf->total)))
1990                         return -EFAULT;
1991
1992                 d->granted_count++;
1993         }
1994         return 0;
1995 }
1996
1997 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
1998 {
1999         struct drm_device_dma *dma = dev->dma;
2000         int ret = 0;
2001         struct drm_dma *d = data;
2002
2003         LOCK_TEST_WITH_RETURN(dev, file_priv);
2004
2005         /* Please don't send us buffers.
2006          */
2007         if (d->send_count != 0) {
2008                 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
2009                           DRM_CURRENTPID, d->send_count);
2010                 return -EINVAL;
2011         }
2012
2013         /* We'll send you buffers.
2014          */
2015         if (d->request_count < 0 || d->request_count > dma->buf_count) {
2016                 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
2017                           DRM_CURRENTPID, d->request_count, dma->buf_count);
2018                 return -EINVAL;
2019         }
2020
2021         d->granted_count = 0;
2022
2023         if (d->request_count) {
2024                 ret = radeon_cp_get_buffers(dev, file_priv, d);
2025         }
2026
2027         return ret;
2028 }
2029
2030 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
2031 {
2032         drm_radeon_private_t *dev_priv;
2033         int ret = 0;
2034
2035         dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
2036         if (dev_priv == NULL)
2037                 return -ENOMEM;
2038
2039         memset(dev_priv, 0, sizeof(drm_radeon_private_t));
2040         dev->dev_private = (void *)dev_priv;
2041         dev_priv->flags = flags;
2042
2043         switch (flags & RADEON_FAMILY_MASK) {
2044         case CHIP_R100:
2045         case CHIP_RV200:
2046         case CHIP_R200:
2047         case CHIP_R300:
2048         case CHIP_R350:
2049         case CHIP_R420:
2050         case CHIP_R423:
2051         case CHIP_RV410:
2052         case CHIP_RV515:
2053         case CHIP_R520:
2054         case CHIP_RV570:
2055         case CHIP_R580:
2056                 dev_priv->flags |= RADEON_HAS_HIERZ;
2057                 break;
2058         default:
2059                 /* all other chips have no hierarchical z buffer */
2060                 break;
2061         }
2062
2063         if (drm_device_is_agp(dev))
2064                 dev_priv->flags |= RADEON_IS_AGP;
2065         else if (drm_device_is_pcie(dev))
2066                 dev_priv->flags |= RADEON_IS_PCIE;
2067         else
2068                 dev_priv->flags |= RADEON_IS_PCI;
2069
2070         ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
2071                          drm_get_resource_len(dev, 2), _DRM_REGISTERS,
2072                          _DRM_READ_ONLY | _DRM_DRIVER, &dev_priv->mmio);
2073         if (ret != 0)
2074                 return ret;
2075
2076         ret = drm_vblank_init(dev, 2);
2077         if (ret) {
2078                 radeon_driver_unload(dev);
2079                 return ret;
2080         }
2081
2082         DRM_DEBUG("%s card detected\n",
2083                   ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
2084         return ret;
2085 }
2086
2087 /* Create mappings for registers and framebuffer so userland doesn't necessarily
2088  * have to find them.
2089  */
2090 int radeon_driver_firstopen(struct drm_device *dev)
2091 {
2092         int ret;
2093         drm_local_map_t *map;
2094         drm_radeon_private_t *dev_priv = dev->dev_private;
2095
2096         dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
2097
2098         dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
2099         ret = drm_addmap(dev, dev_priv->fb_aper_offset,
2100                          drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
2101                          _DRM_WRITE_COMBINING, &map);
2102         if (ret != 0)
2103                 return ret;
2104
2105         return 0;
2106 }
2107
2108 int radeon_driver_unload(struct drm_device *dev)
2109 {
2110         drm_radeon_private_t *dev_priv = dev->dev_private;
2111
2112         DRM_DEBUG("\n");
2113
2114         drm_rmmap(dev, dev_priv->mmio);
2115
2116         drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
2117
2118         dev->dev_private = NULL;
2119         return 0;
2120 }
2121
2122 void radeon_commit_ring(drm_radeon_private_t *dev_priv)
2123 {
2124         int i;
2125         u32 *ring;
2126         int tail_aligned;
2127
2128         /* check if the ring is padded out to 16-dword alignment */
2129
2130         tail_aligned = dev_priv->ring.tail & 0xf;
2131         if (tail_aligned) {
2132                 int num_p2 = 16 - tail_aligned;
2133
2134                 ring = dev_priv->ring.start;
2135                 /* pad with some CP_PACKET2 */
2136                 for (i = 0; i < num_p2; i++)
2137                         ring[dev_priv->ring.tail + i] = CP_PACKET2();
2138
2139                 dev_priv->ring.tail += i;
2140
2141                 dev_priv->ring.space -= num_p2 * sizeof(u32);
2142         }
2143
2144         dev_priv->ring.tail &= dev_priv->ring.tail_mask;
2145
2146         DRM_MEMORYBARRIER();
2147         GET_RING_HEAD( dev_priv );
2148
2149         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
2150                 RADEON_WRITE(R600_CP_RB_WPTR, dev_priv->ring.tail);
2151                 /* read from PCI bus to ensure correct posting */
2152                 RADEON_READ(R600_CP_RB_RPTR);
2153         } else {
2154                 RADEON_WRITE(RADEON_CP_RB_WPTR, dev_priv->ring.tail);
2155                 /* read from PCI bus to ensure correct posting */
2156                 RADEON_READ(RADEON_CP_RB_RPTR);
2157         }
2158 }