2 * Copyright (c) 2016 The DragonFly Project. All rights reserved.
4 * This code is derived from software contributed to The DragonFly Project
5 * by Imre Vadász <imre@vdsz.com>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
35 * Cherryview GPIO support.
38 #include <sys/param.h>
39 #include <sys/systm.h>
40 #include <sys/kernel.h>
41 #include <sys/module.h>
42 #include <sys/errno.h>
44 #include <sys/mutex.h>
51 #include <dev/acpica/acpivar.h>
53 #include "gpio_intel_var.h"
57 #define CHV_GPIO_REG_IS 0x300
58 #define CHV_GPIO_REG_MASK 0x380
59 #define CHV_GPIO_REG_PINS 0x4400 /* start of pin control registers */
61 #define CHV_GPIO_REGOFF_CTL0 0x0
62 #define CHV_GPIO_REGOFF_CTL1 0x4
64 #define CHV_GPIO_CTL0_RXSTATE 0x00000001u
65 #define CHV_GPIO_CTL0_TXSTATE 0x00000002u
66 #define CHV_GPIO_CTL0_GPIOCFG_MASK 0x00000700u
67 #define CHV_GPIO_CTL0_GPIOEN 0x00008000u
68 #define CHV_GPIO_CTL0_PULLUP 0x00800000u
69 #define CHV_GPIO_CTL1_INTCFG_MASK 0x00000007u
70 #define CHV_GPIO_CTL1_INVRXDATA 0x00000040u
72 #define CHV_GPIO_PINSIZE 0x8 /* 8 bytes for each pin */
73 #define CHV_GPIO_PINCHUNK 15 /* 15 pins at a time */
74 #define CHV_GPIO_PININC 0x400 /* every 0x400 bytes */
76 #define PIN_ADDRESS(x) \
77 (CHV_GPIO_REG_PINS + \
78 ((x) / CHV_GPIO_PINCHUNK) * CHV_GPIO_PININC + \
79 ((x) % CHV_GPIO_PINCHUNK) * CHV_GPIO_PINSIZE)
81 #define PIN_CTL0(x) (PIN_ADDRESS(x) + CHV_GPIO_REGOFF_CTL0)
82 #define PIN_CTL1(x) (PIN_ADDRESS(x) + CHV_GPIO_REGOFF_CTL1)
84 static void gpio_cherryview_init(struct gpio_intel_softc *sc);
85 static void gpio_cherryview_intr(void *arg);
86 static int gpio_cherryview_map_intr(struct gpio_intel_softc *sc,
87 uint16_t pin, int trigger, int polarity, int termination,
88 void *arg, driver_intr_t *handler);
89 static void gpio_cherryview_unmap_intr(struct gpio_intel_softc *sc,
91 static int gpio_cherryview_read_pin(struct gpio_intel_softc *sc,
93 static void gpio_cherryview_write_pin(struct gpio_intel_softc *sc,
94 uint16_t pin, int value);
96 static struct gpio_intel_fns gpio_cherryview_fns = {
97 .init = gpio_cherryview_init,
98 .intr = gpio_cherryview_intr,
99 .map_intr = gpio_cherryview_map_intr,
100 .unmap_intr = gpio_cherryview_unmap_intr,
101 .read_pin = gpio_cherryview_read_pin,
102 .write_pin = gpio_cherryview_write_pin,
106 static struct pinrange chv_sw_ranges[] = {
118 static struct pinrange chv_n_ranges[] = {
128 static struct pinrange chv_e_ranges[] = {
135 static struct pinrange chv_se_ranges[] = {
145 static struct lock gpio_lk;
146 LOCK_SYSINIT(chvgpiolk, &gpio_lk, "chvgpio", 0);
149 * Use global GPIO register lock to workaround erratum:
151 * CHT34 Multiple Drivers That Access the GPIO Registers Concurrently May
152 * Result in Unpredictable System Behaviour
154 static inline uint32_t
155 chvgpio_read(struct gpio_intel_softc *sc, bus_size_t offset)
159 lockmgr(&gpio_lk, LK_EXCLUSIVE);
160 val = bus_read_4(sc->mem_res, offset);
161 lockmgr(&gpio_lk, LK_RELEASE);
166 chvgpio_write(struct gpio_intel_softc *sc, bus_size_t offset, uint32_t val)
168 lockmgr(&gpio_lk, LK_EXCLUSIVE);
169 bus_write_4(sc->mem_res, offset, val);
170 lockmgr(&gpio_lk, LK_RELEASE);
174 gpio_cherryview_matchuid(struct gpio_intel_softc *sc)
178 handle = acpi_get_handle(sc->dev);
179 if (acpi_MatchUid(handle, "1")) {
180 sc->ranges = chv_sw_ranges;
181 } else if (acpi_MatchUid(handle, "2")) {
182 sc->ranges = chv_n_ranges;
183 } else if (acpi_MatchUid(handle, "3")) {
184 sc->ranges = chv_e_ranges;
185 } else if (acpi_MatchUid(handle, "4")) {
186 sc->ranges = chv_se_ranges;
191 sc->fns = &gpio_cherryview_fns;
197 gpio_cherryview_init(struct gpio_intel_softc *sc)
199 /* mask and clear all interrupt lines */
200 chvgpio_write(sc, CHV_GPIO_REG_MASK, 0);
201 chvgpio_write(sc, CHV_GPIO_REG_IS, 0xffff);
205 gpio_cherryview_intr(void *arg)
207 struct gpio_intel_softc *sc = (struct gpio_intel_softc *)arg;
208 struct pin_intr_map *mapping;
212 status = chvgpio_read(sc, CHV_GPIO_REG_IS);
213 for (i = 0; i < 16; i++) {
214 if (status & (1U << i)) {
215 mapping = &sc->intrmaps[i];
216 if (!mapping->is_level) {
217 chvgpio_write(sc, CHV_GPIO_REG_IS,
220 if (mapping->pin != -1 && mapping->handler != NULL)
221 mapping->handler(mapping->arg);
222 if (mapping->is_level) {
223 chvgpio_write(sc, CHV_GPIO_REG_IS,
230 /* XXX Add shared/exclusive argument. */
232 gpio_cherryview_map_intr(struct gpio_intel_softc *sc, uint16_t pin, int trigger,
233 int polarity, int termination, void *arg, driver_intr_t *handler)
235 uint32_t reg, reg1, reg2;
236 uint32_t intcfg, new_intcfg, gpiocfg, new_gpiocfg;
239 reg1 = chvgpio_read(sc, PIN_CTL0(pin));
240 reg2 = chvgpio_read(sc, PIN_CTL1(pin));
241 device_printf(sc->dev,
242 "pin=%d trigger=%d polarity=%d ctrl0=0x%08x ctrl1=0x%08x\n",
243 pin, trigger, polarity, reg1, reg2);
245 new_intcfg = intcfg = reg2 & CHV_GPIO_CTL1_INTCFG_MASK;
246 new_gpiocfg = gpiocfg = reg1 & CHV_GPIO_CTL0_GPIOCFG_MASK;
249 * Sanity Checks, for now we just abort if the configuration doesn't
250 * match our expectations.
252 if (!(reg1 & CHV_GPIO_CTL0_GPIOEN)) {
253 device_printf(sc->dev, "GPIO mode is disabled\n");
256 if (gpiocfg != 0x0 && gpiocfg != 0x200) {
257 device_printf(sc->dev, "RX is disabled\n");
258 if (gpiocfg == 0x100)
260 else if (gpiocfg == 0x300)
265 if (trigger == ACPI_LEVEL_SENSITIVE) {
267 device_printf(sc->dev,
268 "trigger is %x, should be 4 (Level)\n", intcfg);
271 if (polarity == ACPI_ACTIVE_BOTH) {
272 device_printf(sc->dev,
273 "ACTIVE_BOTH incompatible with level trigger\n");
275 } else if (polarity == ACPI_ACTIVE_LOW) {
276 if (!(reg2 & CHV_GPIO_CTL1_INVRXDATA)) {
277 device_printf(sc->dev,
278 "Invert RX not enabled (needed for "
279 "level/low trigger/polarity)\n");
283 if (reg2 & CHV_GPIO_CTL1_INVRXDATA) {
284 device_printf(sc->dev,
285 "Invert RX should not be enabled for "
286 "level/high trigger/polarity\n");
292 * For edge-triggered interrupts it's definitely harmless to
293 * change between rising-edge, falling-edge and both-edges
296 if (polarity == ACPI_ACTIVE_HIGH && intcfg != 2) {
297 device_printf(sc->dev,
298 "Wrong interrupt configuration, is 0x%x should "
299 "be 0x%x\n", intcfg, 2);
300 if (intcfg == 1 || intcfg == 3)
304 } else if (polarity == ACPI_ACTIVE_LOW && intcfg != 1) {
305 device_printf(sc->dev,
306 "Wrong interrupt configuration, is 0x%x should "
307 "be 0x%x\n", intcfg, 1);
308 if (intcfg == 2 || intcfg == 3)
312 } else if (polarity == ACPI_ACTIVE_BOTH && intcfg != 3) {
313 device_printf(sc->dev,
314 "Wrong interrupt configuration, is 0x%x should "
315 "be 0x%x\n", intcfg, 3);
316 if (intcfg == 1 || intcfg == 2)
322 if (termination == ACPI_PIN_CONFIG_PULLUP &&
323 !(reg1 & CHV_GPIO_CTL0_PULLUP)) {
324 device_printf(sc->dev,
325 "Wrong termination, is pull-down, should be pull-up\n");
327 } else if (termination == ACPI_PIN_CONFIG_PULLDOWN &&
328 (reg1 & CHV_GPIO_CTL0_PULLUP)) {
329 device_printf(sc->dev,
330 "Wrong termination, is pull-up, should be pull-down\n");
334 /* Check if the interrupt/line configured by BIOS/UEFI is unused */
335 i = (reg1 >> 28) & 0xf;
336 if (sc->intrmaps[i].pin != -1) {
337 device_printf(sc->dev, "Interrupt line %d already used\n", i);
341 if (new_intcfg != intcfg) {
342 device_printf(sc->dev,
343 "Switching interrupt configuration from 0x%x to 0x%x\n",
345 reg = reg2 & ~CHV_GPIO_CTL1_INTCFG_MASK;
346 reg |= (new_intcfg & CHV_GPIO_CTL1_INTCFG_MASK) << 0;
347 chvgpio_write(sc, PIN_CTL1(pin), reg);
350 if (new_gpiocfg != gpiocfg) {
351 device_printf(sc->dev,
352 "Switching gpio configuration from 0x%x to 0x%x\n",
353 gpiocfg, new_gpiocfg);
354 reg = reg1 & ~CHV_GPIO_CTL0_GPIOCFG_MASK;
355 reg |= (new_gpiocfg & CHV_GPIO_CTL0_GPIOCFG_MASK) << 0;
356 chvgpio_write(sc, PIN_CTL0(pin), reg);
359 sc->intrmaps[i].pin = pin;
360 sc->intrmaps[i].arg = arg;
361 sc->intrmaps[i].handler = handler;
362 sc->intrmaps[i].orig_intcfg = intcfg;
363 sc->intrmaps[i].orig_gpiocfg = gpiocfg;
365 if (trigger == ACPI_LEVEL_SENSITIVE)
366 sc->intrmaps[i].is_level = 1;
368 sc->intrmaps[i].is_level = 0;
370 /* unmask interrupt */
371 reg = chvgpio_read(sc, CHV_GPIO_REG_MASK);
373 chvgpio_write(sc, CHV_GPIO_REG_MASK, reg);
379 gpio_cherryview_unmap_intr(struct gpio_intel_softc *sc, uint16_t pin)
381 uint32_t reg, intcfg, gpiocfg;
384 for (i = 0; i < 16; i++) {
385 if (sc->intrmaps[i].pin == pin) {
386 intcfg = sc->intrmaps[i].orig_intcfg;
387 intcfg &= CHV_GPIO_CTL1_INTCFG_MASK;
389 gpiocfg = sc->intrmaps[i].orig_gpiocfg;
390 gpiocfg &= CHV_GPIO_CTL0_GPIOCFG_MASK;
392 sc->intrmaps[i].pin = -1;
393 sc->intrmaps[i].arg = NULL;
394 sc->intrmaps[i].handler = NULL;
395 sc->intrmaps[i].is_level = 0;
396 sc->intrmaps[i].orig_intcfg = 0;
397 sc->intrmaps[i].orig_gpiocfg = 0;
399 /* mask interrupt line */
400 reg = chvgpio_read(sc, CHV_GPIO_REG_MASK);
402 chvgpio_write(sc, CHV_GPIO_REG_MASK, reg);
404 /* Restore interrupt configuration if needed */
405 reg = chvgpio_read(sc, PIN_CTL1(pin));
406 if ((reg & CHV_GPIO_CTL1_INTCFG_MASK) != intcfg) {
407 reg &= ~CHV_GPIO_CTL1_INTCFG_MASK;
409 chvgpio_write(sc, PIN_CTL1(pin), reg);
412 /* Restore gpio configuration if needed */
413 reg = chvgpio_read(sc, PIN_CTL0(pin));
414 if ((reg & CHV_GPIO_CTL0_GPIOCFG_MASK) != gpiocfg) {
415 reg &= ~CHV_GPIO_CTL0_GPIOCFG_MASK;
417 chvgpio_write(sc, PIN_CTL0(pin), reg);
424 gpio_cherryview_read_pin(struct gpio_intel_softc *sc, uint16_t pin)
429 reg = chvgpio_read(sc, PIN_CTL0(pin));
430 /* Verify that RX is enabled */
431 KKASSERT((reg & CHV_GPIO_CTL0_GPIOCFG_MASK) == 0x0 ||
432 (reg & CHV_GPIO_CTL0_GPIOCFG_MASK) == 0x200);
434 if (reg & CHV_GPIO_CTL0_RXSTATE)
443 gpio_cherryview_write_pin(struct gpio_intel_softc *sc, uint16_t pin, int value)
447 reg2 = chvgpio_read(sc, PIN_CTL1(pin));
448 /* Verify that interrupt is disabled */
449 KKASSERT((reg2 & CHV_GPIO_CTL1_INTCFG_MASK) == 0);
451 reg1 = chvgpio_read(sc, PIN_CTL0(pin));
452 /* Verify that TX is enabled */
453 KKASSERT((reg1 & CHV_GPIO_CTL0_GPIOCFG_MASK) == 0 ||
454 (reg1 & CHV_GPIO_CTL0_GPIOCFG_MASK) == 0x100);
457 reg1 |= CHV_GPIO_CTL0_TXSTATE;
459 reg1 &= ~CHV_GPIO_CTL0_TXSTATE;
460 chvgpio_write(sc, PIN_CTL0(pin), reg1);