sys/dev/netif/igb/if_igb.c

   1 /*
   2  * Copyright (c) 2001-2011, Intel Corporation
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  *  1. Redistributions of source code must retain the above copyright notice,
   9  *     this list of conditions and the following disclaimer.
  10  *
  11  *  2. Redistributions in binary form must reproduce the above copyright
  12  *     notice, this list of conditions and the following disclaimer in the
  13  *     documentation and/or other materials provided with the distribution.
  14  *
  15  *  3. Neither the name of the Intel Corporation nor the names of its
  16  *     contributors may be used to endorse or promote products derived from
  17  *     this software without specific prior written permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  29  * POSSIBILITY OF SUCH DAMAGE.
  30  */
  31
  32 #include "opt_ifpoll.h"
  33 #include "opt_igb.h"
  34
  35 #include <sys/param.h>
  36 #include <sys/bus.h>
  37 #include <sys/endian.h>
  38 #include <sys/interrupt.h>
  39 #include <sys/kernel.h>
  40 #include <sys/malloc.h>
  41 #include <sys/mbuf.h>
  42 #include <sys/proc.h>
  43 #include <sys/rman.h>
  44 #include <sys/serialize.h>
  45 #include <sys/serialize2.h>
  46 #include <sys/socket.h>
  47 #include <sys/sockio.h>
  48 #include <sys/sysctl.h>
  49 #include <sys/systm.h>
  50
  51 #include <net/bpf.h>
  52 #include <net/ethernet.h>
  53 #include <net/if.h>
  54 #include <net/if_arp.h>
  55 #include <net/if_dl.h>
  56 #include <net/if_media.h>
  57 #include <net/ifq_var.h>
  58 #include <net/toeplitz.h>
  59 #include <net/toeplitz2.h>
  60 #include <net/vlan/if_vlan_var.h>
  61 #include <net/vlan/if_vlan_ether.h>
  62 #include <net/if_poll.h>
  63
  64 #include <netinet/in_systm.h>
  65 #include <netinet/in.h>
  66 #include <netinet/ip.h>
  67 #include <netinet/tcp.h>
  68 #include <netinet/udp.h>
  69
  70 #include <bus/pci/pcivar.h>
  71 #include <bus/pci/pcireg.h>
  72
  73 #include <dev/netif/ig_hal/e1000_api.h>
  74 #include <dev/netif/ig_hal/e1000_82575.h>
  75 #include <dev/netif/igb/if_igb.h>
  76
  77 #ifdef IGB_RSS_DEBUG
  78 #define IGB_RSS_DPRINTF(sc, lvl, fmt, ...) \
  79 do { \
  80         if (sc->rss_debug >= lvl) \
  81                 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
  82 } while (0)
  83 #else   /* !IGB_RSS_DEBUG */
  84 #define IGB_RSS_DPRINTF(sc, lvl, fmt, ...)      ((void)0)
  85 #endif  /* IGB_RSS_DEBUG */
  86
  87 #define IGB_NAME        "Intel(R) PRO/1000 "
  88 #define IGB_DEVICE(id)  \
  89         { IGB_VENDOR_ID, E1000_DEV_ID_##id, IGB_NAME #id }
  90 #define IGB_DEVICE_NULL { 0, 0, NULL }
  91
  92 static struct igb_device {
  93         uint16_t        vid;
  94         uint16_t        did;
  95         const char      *desc;
  96 } igb_devices[] = {
  97         IGB_DEVICE(82575EB_COPPER),
  98         IGB_DEVICE(82575EB_FIBER_SERDES),
  99         IGB_DEVICE(82575GB_QUAD_COPPER),
 100         IGB_DEVICE(82576),
 101         IGB_DEVICE(82576_NS),
 102         IGB_DEVICE(82576_NS_SERDES),
 103         IGB_DEVICE(82576_FIBER),
 104         IGB_DEVICE(82576_SERDES),
 105         IGB_DEVICE(82576_SERDES_QUAD),
 106         IGB_DEVICE(82576_QUAD_COPPER),
 107         IGB_DEVICE(82576_QUAD_COPPER_ET2),
 108         IGB_DEVICE(82576_VF),
 109         IGB_DEVICE(82580_COPPER),
 110         IGB_DEVICE(82580_FIBER),
 111         IGB_DEVICE(82580_SERDES),
 112         IGB_DEVICE(82580_SGMII),
 113         IGB_DEVICE(82580_COPPER_DUAL),
 114         IGB_DEVICE(82580_QUAD_FIBER),
 115         IGB_DEVICE(DH89XXCC_SERDES),
 116         IGB_DEVICE(DH89XXCC_SGMII),
 117         IGB_DEVICE(DH89XXCC_SFP),
 118         IGB_DEVICE(DH89XXCC_BACKPLANE),
 119         IGB_DEVICE(I350_COPPER),
 120         IGB_DEVICE(I350_FIBER),
 121         IGB_DEVICE(I350_SERDES),
 122         IGB_DEVICE(I350_SGMII),
 123         IGB_DEVICE(I350_VF),
 124
 125         /* required last entry */
 126         IGB_DEVICE_NULL
 127 };
 128
 129 static int      igb_probe(device_t);
 130 static int      igb_attach(device_t);
 131 static int      igb_detach(device_t);
 132 static int      igb_shutdown(device_t);
 133 static int      igb_suspend(device_t);
 134 static int      igb_resume(device_t);
 135
 136 static boolean_t igb_is_valid_ether_addr(const uint8_t *);
 137 static void     igb_setup_ifp(struct igb_softc *);
 138 static boolean_t igb_txcsum_ctx(struct igb_tx_ring *, struct mbuf *);
 139 static int      igb_tso_pullup(struct igb_tx_ring *, struct mbuf **);
 140 static void     igb_tso_ctx(struct igb_tx_ring *, struct mbuf *, uint32_t *);
 141 static void     igb_add_sysctl(struct igb_softc *);
 142 static int      igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS);
 143 static int      igb_sysctl_msix_rate(SYSCTL_HANDLER_ARGS);
 144 static int      igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS);
 145 static int      igb_sysctl_tx_wreg_nsegs(SYSCTL_HANDLER_ARGS);
 146 static int      igb_sysctl_rx_wreg_nsegs(SYSCTL_HANDLER_ARGS);
 147 static void     igb_set_ring_inuse(struct igb_softc *, boolean_t);
 148 static int      igb_get_rxring_inuse(const struct igb_softc *, boolean_t);
 149 static int      igb_get_txring_inuse(const struct igb_softc *, boolean_t);
 150 #ifdef IFPOLL_ENABLE
 151 static int      igb_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS);
 152 static int      igb_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS);
 153 #endif
 154
 155 static void     igb_vf_init_stats(struct igb_softc *);
 156 static void     igb_reset(struct igb_softc *);
 157 static void     igb_update_stats_counters(struct igb_softc *);
 158 static void     igb_update_vf_stats_counters(struct igb_softc *);
 159 static void     igb_update_link_status(struct igb_softc *);
 160 static void     igb_init_tx_unit(struct igb_softc *);
 161 static void     igb_init_rx_unit(struct igb_softc *);
 162
 163 static void     igb_set_vlan(struct igb_softc *);
 164 static void     igb_set_multi(struct igb_softc *);
 165 static void     igb_set_promisc(struct igb_softc *);
 166 static void     igb_disable_promisc(struct igb_softc *);
 167
 168 static int      igb_alloc_rings(struct igb_softc *);
 169 static void     igb_free_rings(struct igb_softc *);
 170 static int      igb_create_tx_ring(struct igb_tx_ring *);
 171 static int      igb_create_rx_ring(struct igb_rx_ring *);
 172 static void     igb_free_tx_ring(struct igb_tx_ring *);
 173 static void     igb_free_rx_ring(struct igb_rx_ring *);
 174 static void     igb_destroy_tx_ring(struct igb_tx_ring *, int);
 175 static void     igb_destroy_rx_ring(struct igb_rx_ring *, int);
 176 static void     igb_init_tx_ring(struct igb_tx_ring *);
 177 static int      igb_init_rx_ring(struct igb_rx_ring *);
 178 static int      igb_newbuf(struct igb_rx_ring *, int, boolean_t);
 179 static int      igb_encap(struct igb_tx_ring *, struct mbuf **, int *, int *);
 180 static void     igb_rx_refresh(struct igb_rx_ring *, int);
 181
 182 static void     igb_stop(struct igb_softc *);
 183 static void     igb_init(void *);
 184 static int      igb_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
 185 static void     igb_media_status(struct ifnet *, struct ifmediareq *);
 186 static int      igb_media_change(struct ifnet *);
 187 static void     igb_timer(void *);
 188 static void     igb_watchdog(struct ifaltq_subque *);
 189 static void     igb_start(struct ifnet *, struct ifaltq_subque *);
 190 #ifdef IFPOLL_ENABLE
 191 static void     igb_npoll(struct ifnet *, struct ifpoll_info *);
 192 static void     igb_npoll_rx(struct ifnet *, void *, int);
 193 static void     igb_npoll_tx(struct ifnet *, void *, int);
 194 static void     igb_npoll_status(struct ifnet *);
 195 #endif
 196 static void     igb_serialize(struct ifnet *, enum ifnet_serialize);
 197 static void     igb_deserialize(struct ifnet *, enum ifnet_serialize);
 198 static int      igb_tryserialize(struct ifnet *, enum ifnet_serialize);
 199 #ifdef INVARIANTS
 200 static void     igb_serialize_assert(struct ifnet *, enum ifnet_serialize,
 201                     boolean_t);
 202 #endif
 203
 204 static void     igb_intr(void *);
 205 static void     igb_intr_shared(void *);
 206 static void     igb_rxeof(struct igb_rx_ring *, int);
 207 static void     igb_txeof(struct igb_tx_ring *);
 208 static void     igb_set_eitr(struct igb_softc *, int, int);
 209 static void     igb_enable_intr(struct igb_softc *);
 210 static void     igb_disable_intr(struct igb_softc *);
 211 static void     igb_init_unshared_intr(struct igb_softc *);
 212 static void     igb_init_intr(struct igb_softc *);
 213 static int      igb_setup_intr(struct igb_softc *);
 214 static void     igb_set_txintr_mask(struct igb_tx_ring *, int *, int);
 215 static void     igb_set_rxintr_mask(struct igb_rx_ring *, int *, int);
 216 static void     igb_set_intr_mask(struct igb_softc *);
 217 static int      igb_alloc_intr(struct igb_softc *);
 218 static void     igb_free_intr(struct igb_softc *);
 219 static void     igb_teardown_intr(struct igb_softc *);
 220 static void     igb_msix_try_alloc(struct igb_softc *);
 221 static void     igb_msix_free(struct igb_softc *, boolean_t);
 222 static int      igb_msix_setup(struct igb_softc *);
 223 static void     igb_msix_teardown(struct igb_softc *, int);
 224 static void     igb_msix_rx(void *);
 225 static void     igb_msix_tx(void *);
 226 static void     igb_msix_status(void *);
 227
 228 /* Management and WOL Support */
 229 static void     igb_get_mgmt(struct igb_softc *);
 230 static void     igb_rel_mgmt(struct igb_softc *);
 231 static void     igb_get_hw_control(struct igb_softc *);
 232 static void     igb_rel_hw_control(struct igb_softc *);
 233 static void     igb_enable_wol(device_t);
 234
 235 static device_method_t igb_methods[] = {
 236         /* Device interface */
 237         DEVMETHOD(device_probe,         igb_probe),
 238         DEVMETHOD(device_attach,        igb_attach),
 239         DEVMETHOD(device_detach,        igb_detach),
 240         DEVMETHOD(device_shutdown,      igb_shutdown),
 241         DEVMETHOD(device_suspend,       igb_suspend),
 242         DEVMETHOD(device_resume,        igb_resume),
 243         { 0, 0 }
 244 };
 245
 246 static driver_t igb_driver = {
 247         "igb",
 248         igb_methods,
 249         sizeof(struct igb_softc),
 250 };
 251
 252 static devclass_t igb_devclass;
 253
 254 DECLARE_DUMMY_MODULE(if_igb);
 255 MODULE_DEPEND(igb, ig_hal, 1, 1, 1);
 256 DRIVER_MODULE(if_igb, pci, igb_driver, igb_devclass, NULL, NULL);
 257
 258 static int      igb_rxd = IGB_DEFAULT_RXD;
 259 static int      igb_txd = IGB_DEFAULT_TXD;
 260 static int      igb_rxr = 0;
 261 static int      igb_txr = 0;
 262 static int      igb_msi_enable = 1;
 263 static int      igb_msix_enable = 1;
 264 static int      igb_eee_disabled = 1;   /* Energy Efficient Ethernet */
 265 static int      igb_fc_setting = e1000_fc_full;
 266
 267 /*
 268  * DMA Coalescing, only for i350 - default to off,
 269  * this feature is for power savings
 270  */
 271 static int      igb_dma_coalesce = 0;
 272
 273 TUNABLE_INT("hw.igb.rxd", &igb_rxd);
 274 TUNABLE_INT("hw.igb.txd", &igb_txd);
 275 TUNABLE_INT("hw.igb.rxr", &igb_rxr);
 276 TUNABLE_INT("hw.igb.txr", &igb_txr);
 277 TUNABLE_INT("hw.igb.msi.enable", &igb_msi_enable);
 278 TUNABLE_INT("hw.igb.msix.enable", &igb_msix_enable);
 279 TUNABLE_INT("hw.igb.fc_setting", &igb_fc_setting);
 280
 281 /* i350 specific */
 282 TUNABLE_INT("hw.igb.eee_disabled", &igb_eee_disabled);
 283 TUNABLE_INT("hw.igb.dma_coalesce", &igb_dma_coalesce);
 284
 285 static __inline void
 286 igb_rxcsum(uint32_t staterr, struct mbuf *mp)
 287 {
 288         /* Ignore Checksum bit is set */
 289         if (staterr & E1000_RXD_STAT_IXSM)
 290                 return;
 291
 292         if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
 293             E1000_RXD_STAT_IPCS)
 294                 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
 295
 296         if (staterr & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)) {
 297                 if ((staterr & E1000_RXDEXT_STATERR_TCPE) == 0) {
 298                         mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
 299                             CSUM_PSEUDO_HDR | CSUM_FRAG_NOT_CHECKED;
 300                         mp->m_pkthdr.csum_data = htons(0xffff);
 301                 }
 302         }
 303 }
 304
 305 static __inline struct pktinfo *
 306 igb_rssinfo(struct mbuf *m, struct pktinfo *pi,
 307     uint32_t hash, uint32_t hashtype, uint32_t staterr)
 308 {
 309         switch (hashtype) {
 310         case E1000_RXDADV_RSSTYPE_IPV4_TCP:
 311                 pi->pi_netisr = NETISR_IP;
 312                 pi->pi_flags = 0;
 313                 pi->pi_l3proto = IPPROTO_TCP;
 314                 break;
 315
 316         case E1000_RXDADV_RSSTYPE_IPV4:
 317                 if (staterr & E1000_RXD_STAT_IXSM)
 318                         return NULL;
 319
 320                 if ((staterr &
 321                      (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
 322                     E1000_RXD_STAT_TCPCS) {
 323                         pi->pi_netisr = NETISR_IP;
 324                         pi->pi_flags = 0;
 325                         pi->pi_l3proto = IPPROTO_UDP;
 326                         break;
 327                 }
 328                 /* FALL THROUGH */
 329         default:
 330                 return NULL;
 331         }
 332
 333         m->m_flags |= M_HASH;
 334         m->m_pkthdr.hash = toeplitz_hash(hash);
 335         return pi;
 336 }
 337
 338 static int
 339 igb_probe(device_t dev)
 340 {
 341         const struct igb_device *d;
 342         uint16_t vid, did;
 343
 344         vid = pci_get_vendor(dev);
 345         did = pci_get_device(dev);
 346
 347         for (d = igb_devices; d->desc != NULL; ++d) {
 348                 if (vid == d->vid && did == d->did) {
 349                         device_set_desc(dev, d->desc);
 350                         return 0;
 351                 }
 352         }
 353         return ENXIO;
 354 }
 355
 356 static int
 357 igb_attach(device_t dev)
 358 {
 359         struct igb_softc *sc = device_get_softc(dev);
 360         uint16_t eeprom_data;
 361         int error = 0, i, j, ring_max;
 362 #ifdef IFPOLL_ENABLE
 363         int offset, offset_def;
 364 #endif
 365
 366 #ifdef notyet
 367         /* SYSCTL stuff */
 368         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 369             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 370             OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
 371             igb_sysctl_nvm_info, "I", "NVM Information");
 372         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
 373             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
 374             OID_AUTO, "flow_control", CTLTYPE_INT|CTLFLAG_RW,
 375             adapter, 0, igb_set_flowcntl, "I", "Flow Control");
 376 #endif
 377
 378         callout_init_mp(&sc->timer);
 379         lwkt_serialize_init(&sc->main_serialize);
 380
 381         if_initname(&sc->arpcom.ac_if, device_get_name(dev),
 382             device_get_unit(dev));
 383         sc->dev = sc->osdep.dev = dev;
 384
 385         /*
 386          * Determine hardware and mac type
 387          */
 388         sc->hw.vendor_id = pci_get_vendor(dev);
 389         sc->hw.device_id = pci_get_device(dev);
 390         sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
 391         sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2);
 392         sc->hw.subsystem_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
 393
 394         if (e1000_set_mac_type(&sc->hw))
 395                 return ENXIO;
 396
 397         /* Are we a VF device? */
 398         if (sc->hw.mac.type == e1000_vfadapt ||
 399             sc->hw.mac.type == e1000_vfadapt_i350)
 400                 sc->vf_ifp = 1;
 401         else
 402                 sc->vf_ifp = 0;
 403
 404         /*
 405          * Configure total supported RX/TX ring count
 406          */
 407         switch (sc->hw.mac.type) {
 408         case e1000_82575:
 409                 ring_max = IGB_MAX_RING_82575;
 410                 break;
 411         case e1000_82580:
 412                 ring_max = IGB_MAX_RING_82580;
 413                 break;
 414         case e1000_i350:
 415                 ring_max = IGB_MAX_RING_I350;
 416                 break;
 417         case e1000_82576:
 418                 ring_max = IGB_MAX_RING_82576;
 419                 break;
 420         default:
 421                 ring_max = IGB_MIN_RING;
 422                 break;
 423         }
 424
 425         sc->rx_ring_cnt = device_getenv_int(dev, "rxr", igb_rxr);
 426         sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, ring_max);
 427 #ifdef IGB_RSS_DEBUG
 428         sc->rx_ring_cnt = device_getenv_int(dev, "rxr_debug", sc->rx_ring_cnt);
 429 #endif
 430         sc->rx_ring_inuse = sc->rx_ring_cnt;
 431
 432         sc->tx_ring_cnt = device_getenv_int(dev, "txr", igb_txr);
 433         sc->tx_ring_cnt = if_ring_count2(sc->tx_ring_cnt, /* XXX ring_max */1);
 434 #ifdef IGB_TSS_DEBUG
 435         sc->tx_ring_cnt = device_getenv_int(dev, "txr_debug", sc->tx_ring_cnt);
 436 #endif
 437         sc->tx_ring_inuse = sc->tx_ring_cnt;
 438
 439         /* Enable bus mastering */
 440         pci_enable_busmaster(dev);
 441
 442         /*
 443          * Allocate IO memory
 444          */
 445         sc->mem_rid = PCIR_BAR(0);
 446         sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
 447             RF_ACTIVE);
 448         if (sc->mem_res == NULL) {
 449                 device_printf(dev, "Unable to allocate bus resource: memory\n");
 450                 error = ENXIO;
 451                 goto failed;
 452         }
 453         sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->mem_res);
 454         sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->mem_res);
 455
 456         sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
 457
 458         /* Save PCI command register for Shared Code */
 459         sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
 460         sc->hw.back = &sc->osdep;
 461
 462         /* Do Shared Code initialization */
 463         if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
 464                 device_printf(dev, "Setup of Shared code failed\n");
 465                 error = ENXIO;
 466                 goto failed;
 467         }
 468
 469         e1000_get_bus_info(&sc->hw);
 470
 471         sc->hw.mac.autoneg = DO_AUTO_NEG;
 472         sc->hw.phy.autoneg_wait_to_complete = FALSE;
 473         sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
 474
 475         /* Copper options */
 476         if (sc->hw.phy.media_type == e1000_media_type_copper) {
 477                 sc->hw.phy.mdix = AUTO_ALL_MODES;
 478                 sc->hw.phy.disable_polarity_correction = FALSE;
 479                 sc->hw.phy.ms_type = IGB_MASTER_SLAVE;
 480         }
 481
 482         /* Set the frame limits assuming  standard ethernet sized frames. */
 483         sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
 484
 485         /* Allocate RX/TX rings */
 486         error = igb_alloc_rings(sc);
 487         if (error)
 488                 goto failed;
 489
 490 #ifdef IFPOLL_ENABLE
 491         /*
 492          * NPOLLING RX CPU offset
 493          */
 494         if (sc->rx_ring_cnt == ncpus2) {
 495                 offset = 0;
 496         } else {
 497                 offset_def = (sc->rx_ring_cnt * device_get_unit(dev)) % ncpus2;
 498                 offset = device_getenv_int(dev, "npoll.rxoff", offset_def);
 499                 if (offset >= ncpus2 ||
 500                     offset % sc->rx_ring_cnt != 0) {
 501                         device_printf(dev, "invalid npoll.rxoff %d, use %d\n",
 502                             offset, offset_def);
 503                         offset = offset_def;
 504                 }
 505         }
 506         sc->rx_npoll_off = offset;
 507
 508         /*
 509          * NPOLLING TX CPU offset
 510          */
 511         if (sc->tx_ring_cnt == ncpus2) {
 512                 offset = 0;
 513         } else {
 514                 offset_def = (sc->tx_ring_cnt * device_get_unit(dev)) % ncpus2;
 515                 offset = device_getenv_int(dev, "npoll.txoff", offset_def);
 516                 if (offset >= ncpus2 ||
 517                     offset % sc->tx_ring_cnt != 0) {
 518                         device_printf(dev, "invalid npoll.txoff %d, use %d\n",
 519                             offset, offset_def);
 520                         offset = offset_def;
 521                 }
 522         }
 523         sc->tx_npoll_off = offset;
 524 #endif
 525
 526         /* Allocate interrupt */
 527         error = igb_alloc_intr(sc);
 528         if (error)
 529                 goto failed;
 530
 531         /*
 532          * Setup serializers
 533          */
 534         i = 0;
 535         sc->serializes[i++] = &sc->main_serialize;
 536
 537         sc->tx_serialize = i;
 538         for (j = 0; j < sc->tx_ring_cnt; ++j)
 539                 sc->serializes[i++] = &sc->tx_rings[j].tx_serialize;
 540
 541         sc->rx_serialize = i;
 542         for (j = 0; j < sc->rx_ring_cnt; ++j)
 543                 sc->serializes[i++] = &sc->rx_rings[j].rx_serialize;
 544
 545         sc->serialize_cnt = i;
 546         KKASSERT(sc->serialize_cnt <= IGB_NSERIALIZE);
 547
 548         /* Allocate the appropriate stats memory */
 549         if (sc->vf_ifp) {
 550                 sc->stats = kmalloc(sizeof(struct e1000_vf_stats), M_DEVBUF,
 551                     M_WAITOK | M_ZERO);
 552                 igb_vf_init_stats(sc);
 553         } else {
 554                 sc->stats = kmalloc(sizeof(struct e1000_hw_stats), M_DEVBUF,
 555                     M_WAITOK | M_ZERO);
 556         }
 557
 558         /* Allocate multicast array memory. */
 559         sc->mta = kmalloc(ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES,
 560             M_DEVBUF, M_WAITOK);
 561
 562         /* Some adapter-specific advanced features */
 563         if (sc->hw.mac.type >= e1000_i350) {
 564 #ifdef notyet
 565                 igb_set_sysctl_value(adapter, "dma_coalesce",
 566                     "configure dma coalesce",
 567                     &adapter->dma_coalesce, igb_dma_coalesce);
 568                 igb_set_sysctl_value(adapter, "eee_disabled",
 569                     "enable Energy Efficient Ethernet",
 570                     &adapter->hw.dev_spec._82575.eee_disable,
 571                     igb_eee_disabled);
 572 #else
 573                 sc->dma_coalesce = igb_dma_coalesce;
 574                 sc->hw.dev_spec._82575.eee_disable = igb_eee_disabled;
 575 #endif
 576                 e1000_set_eee_i350(&sc->hw);
 577         }
 578
 579         /*
 580          * Start from a known state, this is important in reading the nvm and
 581          * mac from that.
 582          */
 583         e1000_reset_hw(&sc->hw);
 584
 585         /* Make sure we have a good EEPROM before we read from it */
 586         if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
 587                 /*
 588                  * Some PCI-E parts fail the first check due to
 589                  * the link being in sleep state, call it again,
 590                  * if it fails a second time its a real issue.
 591                  */
 592                 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
 593                         device_printf(dev,
 594                             "The EEPROM Checksum Is Not Valid\n");
 595                         error = EIO;
 596                         goto failed;
 597                 }
 598         }
 599
 600         /* Copy the permanent MAC address out of the EEPROM */
 601         if (e1000_read_mac_addr(&sc->hw) < 0) {
 602                 device_printf(dev, "EEPROM read error while reading MAC"
 603                     " address\n");
 604                 error = EIO;
 605                 goto failed;
 606         }
 607         if (!igb_is_valid_ether_addr(sc->hw.mac.addr)) {
 608                 device_printf(dev, "Invalid MAC address\n");
 609                 error = EIO;
 610                 goto failed;
 611         }
 612
 613         /* Setup OS specific network interface */
 614         igb_setup_ifp(sc);
 615
 616         /* Add sysctl tree, must after igb_setup_ifp() */
 617         igb_add_sysctl(sc);
 618
 619         /* Now get a good starting state */
 620         igb_reset(sc);
 621
 622         /* Initialize statistics */
 623         igb_update_stats_counters(sc);
 624
 625         sc->hw.mac.get_link_status = 1;
 626         igb_update_link_status(sc);
 627
 628         /* Indicate SOL/IDER usage */
 629         if (e1000_check_reset_block(&sc->hw)) {
 630                 device_printf(dev,
 631                     "PHY reset is blocked due to SOL/IDER session.\n");
 632         }
 633
 634         /* Determine if we have to control management hardware */
 635         if (e1000_enable_mng_pass_thru(&sc->hw))
 636                 sc->flags |= IGB_FLAG_HAS_MGMT;
 637
 638         /*
 639          * Setup Wake-on-Lan
 640          */
 641         /* APME bit in EEPROM is mapped to WUC.APME */
 642         eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC) & E1000_WUC_APME;
 643         if (eeprom_data)
 644                 sc->wol = E1000_WUFC_MAG;
 645         /* XXX disable WOL */
 646         sc->wol = 0;
 647
 648 #ifdef notyet
 649         /* Register for VLAN events */
 650         adapter->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
 651              igb_register_vlan, adapter, EVENTHANDLER_PRI_FIRST);
 652         adapter->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
 653              igb_unregister_vlan, adapter, EVENTHANDLER_PRI_FIRST);
 654 #endif
 655
 656 #ifdef notyet
 657         igb_add_hw_stats(adapter);
 658 #endif
 659
 660         error = igb_setup_intr(sc);
 661         if (error) {
 662                 ether_ifdetach(&sc->arpcom.ac_if);
 663                 goto failed;
 664         }
 665
 666         for (i = 0; i < sc->tx_ring_cnt; ++i) {
 667                 struct ifaltq_subque *ifsq =
 668                     ifq_get_subq(&sc->arpcom.ac_if.if_snd, i);
 669                 struct igb_tx_ring *txr = &sc->tx_rings[i];
 670
 671                 ifsq_set_cpuid(ifsq, txr->tx_intr_cpuid);
 672                 ifsq_set_priv(ifsq, txr);
 673                 txr->ifsq = ifsq;
 674
 675                 ifsq_watchdog_init(&txr->tx_watchdog, ifsq, igb_watchdog);
 676         }
 677
 678         return 0;
 679
 680 failed:
 681         igb_detach(dev);
 682         return error;
 683 }
 684
 685 static int
 686 igb_detach(device_t dev)
 687 {
 688         struct igb_softc *sc = device_get_softc(dev);
 689
 690         if (device_is_attached(dev)) {
 691                 struct ifnet *ifp = &sc->arpcom.ac_if;
 692
 693                 ifnet_serialize_all(ifp);
 694
 695                 igb_stop(sc);
 696
 697                 e1000_phy_hw_reset(&sc->hw);
 698
 699                 /* Give control back to firmware */
 700                 igb_rel_mgmt(sc);
 701                 igb_rel_hw_control(sc);
 702
 703                 if (sc->wol) {
 704                         E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
 705                         E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
 706                         igb_enable_wol(dev);
 707                 }
 708
 709                 igb_teardown_intr(sc);
 710
 711                 ifnet_deserialize_all(ifp);
 712
 713                 ether_ifdetach(ifp);
 714         } else if (sc->mem_res != NULL) {
 715                 igb_rel_hw_control(sc);
 716         }
 717         bus_generic_detach(dev);
 718
 719         if (sc->sysctl_tree != NULL)
 720                 sysctl_ctx_free(&sc->sysctl_ctx);
 721
 722         igb_free_intr(sc);
 723
 724         if (sc->msix_mem_res != NULL) {
 725                 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_mem_rid,
 726                     sc->msix_mem_res);
 727         }
 728         if (sc->mem_res != NULL) {
 729                 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid,
 730                     sc->mem_res);
 731         }
 732
 733         igb_free_rings(sc);
 734
 735         if (sc->mta != NULL)
 736                 kfree(sc->mta, M_DEVBUF);
 737         if (sc->stats != NULL)
 738                 kfree(sc->stats, M_DEVBUF);
 739
 740         return 0;
 741 }
 742
 743 static int
 744 igb_shutdown(device_t dev)
 745 {
 746         return igb_suspend(dev);
 747 }
 748
 749 static int
 750 igb_suspend(device_t dev)
 751 {
 752         struct igb_softc *sc = device_get_softc(dev);
 753         struct ifnet *ifp = &sc->arpcom.ac_if;
 754
 755         ifnet_serialize_all(ifp);
 756
 757         igb_stop(sc);
 758
 759         igb_rel_mgmt(sc);
 760         igb_rel_hw_control(sc);
 761
 762         if (sc->wol) {
 763                 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
 764                 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
 765                 igb_enable_wol(dev);
 766         }
 767
 768         ifnet_deserialize_all(ifp);
 769
 770         return bus_generic_suspend(dev);
 771 }
 772
 773 static int
 774 igb_resume(device_t dev)
 775 {
 776         struct igb_softc *sc = device_get_softc(dev);
 777         struct ifnet *ifp = &sc->arpcom.ac_if;
 778         int i;
 779
 780         ifnet_serialize_all(ifp);
 781
 782         igb_init(sc);
 783         igb_get_mgmt(sc);
 784
 785         for (i = 0; i < sc->tx_ring_inuse; ++i)
 786                 ifsq_devstart_sched(sc->tx_rings[i].ifsq);
 787
 788         ifnet_deserialize_all(ifp);
 789
 790         return bus_generic_resume(dev);
 791 }
 792
 793 static int
 794 igb_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
 795 {
 796         struct igb_softc *sc = ifp->if_softc;
 797         struct ifreq *ifr = (struct ifreq *)data;
 798         int max_frame_size, mask, reinit;
 799         int error = 0;
 800
 801         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 802
 803         switch (command) {
 804         case SIOCSIFMTU:
 805                 max_frame_size = 9234;
 806                 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
 807                     ETHER_CRC_LEN) {
 808                         error = EINVAL;
 809                         break;
 810                 }
 811
 812                 ifp->if_mtu = ifr->ifr_mtu;
 813                 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
 814                     ETHER_CRC_LEN;
 815
 816                 if (ifp->if_flags & IFF_RUNNING)
 817                         igb_init(sc);
 818                 break;
 819
 820         case SIOCSIFFLAGS:
 821                 if (ifp->if_flags & IFF_UP) {
 822                         if (ifp->if_flags & IFF_RUNNING) {
 823                                 if ((ifp->if_flags ^ sc->if_flags) &
 824                                     (IFF_PROMISC | IFF_ALLMULTI)) {
 825                                         igb_disable_promisc(sc);
 826                                         igb_set_promisc(sc);
 827                                 }
 828                         } else {
 829                                 igb_init(sc);
 830                         }
 831                 } else if (ifp->if_flags & IFF_RUNNING) {
 832                         igb_stop(sc);
 833                 }
 834                 sc->if_flags = ifp->if_flags;
 835                 break;
 836
 837         case SIOCADDMULTI:
 838         case SIOCDELMULTI:
 839                 if (ifp->if_flags & IFF_RUNNING) {
 840                         igb_disable_intr(sc);
 841                         igb_set_multi(sc);
 842 #ifdef IFPOLL_ENABLE
 843                         if (!(ifp->if_flags & IFF_NPOLLING))
 844 #endif
 845                                 igb_enable_intr(sc);
 846                 }
 847                 break;
 848
 849         case SIOCSIFMEDIA:
 850                 /*
 851                  * As the speed/duplex settings are being
 852                  * changed, we need toreset the PHY.
 853                  */
 854                 sc->hw.phy.reset_disable = FALSE;
 855
 856                 /* Check SOL/IDER usage */
 857                 if (e1000_check_reset_block(&sc->hw)) {
 858                         if_printf(ifp, "Media change is "
 859                             "blocked due to SOL/IDER session.\n");
 860                         break;
 861                 }
 862                 /* FALL THROUGH */
 863
 864         case SIOCGIFMEDIA:
 865                 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
 866                 break;
 867
 868         case SIOCSIFCAP:
 869                 reinit = 0;
 870                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
 871                 if (mask & IFCAP_RXCSUM) {
 872                         ifp->if_capenable ^= IFCAP_RXCSUM;
 873                         reinit = 1;
 874                 }
 875                 if (mask & IFCAP_VLAN_HWTAGGING) {
 876                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
 877                         reinit = 1;
 878                 }
 879                 if (mask & IFCAP_TXCSUM) {
 880                         ifp->if_capenable ^= IFCAP_TXCSUM;
 881                         if (ifp->if_capenable & IFCAP_TXCSUM)
 882                                 ifp->if_hwassist |= IGB_CSUM_FEATURES;
 883                         else
 884                                 ifp->if_hwassist &= ~IGB_CSUM_FEATURES;
 885                 }
 886                 if (mask & IFCAP_TSO) {
 887                         ifp->if_capenable ^= IFCAP_TSO;
 888                         if (ifp->if_capenable & IFCAP_TSO)
 889                                 ifp->if_hwassist |= CSUM_TSO;
 890                         else
 891                                 ifp->if_hwassist &= ~CSUM_TSO;
 892                 }
 893                 if (mask & IFCAP_RSS)
 894                         ifp->if_capenable ^= IFCAP_RSS;
 895                 if (reinit && (ifp->if_flags & IFF_RUNNING))
 896                         igb_init(sc);
 897                 break;
 898
 899         default:
 900                 error = ether_ioctl(ifp, command, data);
 901                 break;
 902         }
 903         return error;
 904 }
 905
 906 static void
 907 igb_init(void *xsc)
 908 {
 909         struct igb_softc *sc = xsc;
 910         struct ifnet *ifp = &sc->arpcom.ac_if;
 911         boolean_t polling;
 912         int i;
 913
 914         ASSERT_IFNET_SERIALIZED_ALL(ifp);
 915
 916         igb_stop(sc);
 917
 918         /* Get the latest mac address, User can use a LAA */
 919         bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
 920
 921         /* Put the address into the Receive Address Array */
 922         e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
 923
 924         igb_reset(sc);
 925         igb_update_link_status(sc);
 926
 927         E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
 928
 929         /* Configure for OS presence */
 930         igb_get_mgmt(sc);
 931
 932         polling = FALSE;
 933 #ifdef IFPOLL_ENABLE
 934         if (ifp->if_flags & IFF_NPOLLING)
 935                 polling = TRUE;
 936 #endif
 937
 938         /* Configured used RX/TX rings */
 939         igb_set_ring_inuse(sc, polling);
 940
 941         /* Initialize interrupt */
 942         igb_init_intr(sc);
 943
 944         /* Prepare transmit descriptors and buffers */
 945         for (i = 0; i < sc->tx_ring_inuse; ++i)
 946                 igb_init_tx_ring(&sc->tx_rings[i]);
 947         igb_init_tx_unit(sc);
 948
 949         /* Setup Multicast table */
 950         igb_set_multi(sc);
 951
 952 #if 0
 953         /*
 954          * Figure out the desired mbuf pool
 955          * for doing jumbo/packetsplit
 956          */
 957         if (adapter->max_frame_size <= 2048)
 958                 adapter->rx_mbuf_sz = MCLBYTES;
 959         else if (adapter->max_frame_size <= 4096)
 960                 adapter->rx_mbuf_sz = MJUMPAGESIZE;
 961         else
 962                 adapter->rx_mbuf_sz = MJUM9BYTES;
 963 #endif
 964
 965         /* Prepare receive descriptors and buffers */
 966         for (i = 0; i < sc->rx_ring_inuse; ++i) {
 967                 int error;
 968
 969                 error = igb_init_rx_ring(&sc->rx_rings[i]);
 970                 if (error) {
 971                         if_printf(ifp, "Could not setup receive structures\n");
 972                         igb_stop(sc);
 973                         return;
 974                 }
 975         }
 976         igb_init_rx_unit(sc);
 977
 978         /* Enable VLAN support */
 979         if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
 980                 igb_set_vlan(sc);
 981
 982         /* Don't lose promiscuous settings */
 983         igb_set_promisc(sc);
 984
 985         ifp->if_flags |= IFF_RUNNING;
 986         for (i = 0; i < sc->tx_ring_inuse; ++i) {
 987                 ifsq_clr_oactive(sc->tx_rings[i].ifsq);
 988                 ifsq_watchdog_start(&sc->tx_rings[i].tx_watchdog);
 989         }
 990
 991         if (polling || sc->intr_type == PCI_INTR_TYPE_MSIX)
 992                 sc->timer_cpuid = 0; /* XXX fixed */
 993         else
 994                 sc->timer_cpuid = rman_get_cpuid(sc->intr_res);
 995         callout_reset_bycpu(&sc->timer, hz, igb_timer, sc, sc->timer_cpuid);
 996         e1000_clear_hw_cntrs_base_generic(&sc->hw);
 997
 998         /* This clears any pending interrupts */
 999         E1000_READ_REG(&sc->hw, E1000_ICR);
1000
1001         /*
1002          * Only enable interrupts if we are not polling, make sure
1003          * they are off otherwise.
1004          */
1005         if (polling) {
1006                 igb_disable_intr(sc);
1007         } else {
1008                 igb_enable_intr(sc);
1009                 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC);
1010         }
1011
1012         /* Set Energy Efficient Ethernet */
1013         e1000_set_eee_i350(&sc->hw);
1014
1015         /* Don't reset the phy next time init gets called */
1016         sc->hw.phy.reset_disable = TRUE;
1017 }
1018
1019 static void
1020 igb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1021 {
1022         struct igb_softc *sc = ifp->if_softc;
1023         u_char fiber_type = IFM_1000_SX;
1024
1025         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1026
1027         igb_update_link_status(sc);
1028
1029         ifmr->ifm_status = IFM_AVALID;
1030         ifmr->ifm_active = IFM_ETHER;
1031
1032         if (!sc->link_active)
1033                 return;
1034
1035         ifmr->ifm_status |= IFM_ACTIVE;
1036
1037         if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1038             sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1039                 ifmr->ifm_active |= fiber_type | IFM_FDX;
1040         } else {
1041                 switch (sc->link_speed) {
1042                 case 10:
1043                         ifmr->ifm_active |= IFM_10_T;
1044                         break;
1045
1046                 case 100:
1047                         ifmr->ifm_active |= IFM_100_TX;
1048                         break;
1049
1050                 case 1000:
1051                         ifmr->ifm_active |= IFM_1000_T;
1052                         break;
1053                 }
1054                 if (sc->link_duplex == FULL_DUPLEX)
1055                         ifmr->ifm_active |= IFM_FDX;
1056                 else
1057                         ifmr->ifm_active |= IFM_HDX;
1058         }
1059 }
1060
1061 static int
1062 igb_media_change(struct ifnet *ifp)
1063 {
1064         struct igb_softc *sc = ifp->if_softc;
1065         struct ifmedia *ifm = &sc->media;
1066
1067         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1068
1069         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1070                 return EINVAL;
1071
1072         switch (IFM_SUBTYPE(ifm->ifm_media)) {
1073         case IFM_AUTO:
1074                 sc->hw.mac.autoneg = DO_AUTO_NEG;
1075                 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1076                 break;
1077
1078         case IFM_1000_LX:
1079         case IFM_1000_SX:
1080         case IFM_1000_T:
1081                 sc->hw.mac.autoneg = DO_AUTO_NEG;
1082                 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1083                 break;
1084
1085         case IFM_100_TX:
1086                 sc->hw.mac.autoneg = FALSE;
1087                 sc->hw.phy.autoneg_advertised = 0;
1088                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1089                         sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1090                 else
1091                         sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1092                 break;
1093
1094         case IFM_10_T:
1095                 sc->hw.mac.autoneg = FALSE;
1096                 sc->hw.phy.autoneg_advertised = 0;
1097                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1098                         sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1099                 else
1100                         sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1101                 break;
1102
1103         default:
1104                 if_printf(ifp, "Unsupported media type\n");
1105                 break;
1106         }
1107
1108         igb_init(sc);
1109
1110         return 0;
1111 }
1112
1113 static void
1114 igb_set_promisc(struct igb_softc *sc)
1115 {
1116         struct ifnet *ifp = &sc->arpcom.ac_if;
1117         struct e1000_hw *hw = &sc->hw;
1118         uint32_t reg;
1119
1120         if (sc->vf_ifp) {
1121                 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
1122                 return;
1123         }
1124
1125         reg = E1000_READ_REG(hw, E1000_RCTL);
1126         if (ifp->if_flags & IFF_PROMISC) {
1127                 reg |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1128                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1129         } else if (ifp->if_flags & IFF_ALLMULTI) {
1130                 reg |= E1000_RCTL_MPE;
1131                 reg &= ~E1000_RCTL_UPE;
1132                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1133         }
1134 }
1135
1136 static void
1137 igb_disable_promisc(struct igb_softc *sc)
1138 {
1139         struct e1000_hw *hw = &sc->hw;
1140         uint32_t reg;
1141
1142         if (sc->vf_ifp) {
1143                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
1144                 return;
1145         }
1146         reg = E1000_READ_REG(hw, E1000_RCTL);
1147         reg &= ~E1000_RCTL_UPE;
1148         reg &= ~E1000_RCTL_MPE;
1149         E1000_WRITE_REG(hw, E1000_RCTL, reg);
1150 }
1151
1152 static void
1153 igb_set_multi(struct igb_softc *sc)
1154 {
1155         struct ifnet *ifp = &sc->arpcom.ac_if;
1156         struct ifmultiaddr *ifma;
1157         uint32_t reg_rctl = 0;
1158         uint8_t *mta;
1159         int mcnt = 0;
1160
1161         mta = sc->mta;
1162         bzero(mta, ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1163
1164         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1165                 if (ifma->ifma_addr->sa_family != AF_LINK)
1166                         continue;
1167
1168                 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
1169                         break;
1170
1171                 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1172                     &mta[mcnt * ETH_ADDR_LEN], ETH_ADDR_LEN);
1173                 mcnt++;
1174         }
1175
1176         if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1177                 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1178                 reg_rctl |= E1000_RCTL_MPE;
1179                 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1180         } else {
1181                 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1182         }
1183 }
1184
1185 static void
1186 igb_timer(void *xsc)
1187 {
1188         struct igb_softc *sc = xsc;
1189
1190         lwkt_serialize_enter(&sc->main_serialize);
1191
1192         igb_update_link_status(sc);
1193         igb_update_stats_counters(sc);
1194
1195         callout_reset_bycpu(&sc->timer, hz, igb_timer, sc, sc->timer_cpuid);
1196
1197         lwkt_serialize_exit(&sc->main_serialize);
1198 }
1199
1200 static void
1201 igb_update_link_status(struct igb_softc *sc)
1202 {
1203         struct ifnet *ifp = &sc->arpcom.ac_if;
1204         struct e1000_hw *hw = &sc->hw;
1205         uint32_t link_check, thstat, ctrl;
1206
1207         link_check = thstat = ctrl = 0;
1208
1209         /* Get the cached link value or read for real */
1210         switch (hw->phy.media_type) {
1211         case e1000_media_type_copper:
1212                 if (hw->mac.get_link_status) {
1213                         /* Do the work to read phy */
1214                         e1000_check_for_link(hw);
1215                         link_check = !hw->mac.get_link_status;
1216                 } else {
1217                         link_check = TRUE;
1218                 }
1219                 break;
1220
1221         case e1000_media_type_fiber:
1222                 e1000_check_for_link(hw);
1223                 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1224                 break;
1225
1226         case e1000_media_type_internal_serdes:
1227                 e1000_check_for_link(hw);
1228                 link_check = hw->mac.serdes_has_link;
1229                 break;
1230
1231         /* VF device is type_unknown */
1232         case e1000_media_type_unknown:
1233                 e1000_check_for_link(hw);
1234                 link_check = !hw->mac.get_link_status;
1235                 /* Fall thru */
1236         default:
1237                 break;
1238         }
1239
1240         /* Check for thermal downshift or shutdown */
1241         if (hw->mac.type == e1000_i350) {
1242                 thstat = E1000_READ_REG(hw, E1000_THSTAT);
1243                 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1244         }
1245
1246         /* Now we check if a transition has happened */
1247         if (link_check && sc->link_active == 0) {
1248                 e1000_get_speed_and_duplex(hw,
1249                     &sc->link_speed, &sc->link_duplex);
1250                 if (bootverbose) {
1251                         if_printf(ifp, "Link is up %d Mbps %s\n",
1252                             sc->link_speed,
1253                             sc->link_duplex == FULL_DUPLEX ?
1254                             "Full Duplex" : "Half Duplex");
1255                 }
1256                 sc->link_active = 1;
1257
1258                 ifp->if_baudrate = sc->link_speed * 1000000;
1259                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1260                     (thstat & E1000_THSTAT_LINK_THROTTLE))
1261                         if_printf(ifp, "Link: thermal downshift\n");
1262                 /* This can sleep */
1263                 ifp->if_link_state = LINK_STATE_UP;
1264                 if_link_state_change(ifp);
1265         } else if (!link_check && sc->link_active == 1) {
1266                 ifp->if_baudrate = sc->link_speed = 0;
1267                 sc->link_duplex = 0;
1268                 if (bootverbose)
1269                         if_printf(ifp, "Link is Down\n");
1270                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1271                     (thstat & E1000_THSTAT_PWR_DOWN))
1272                         if_printf(ifp, "Link: thermal shutdown\n");
1273                 sc->link_active = 0;
1274                 /* This can sleep */
1275                 ifp->if_link_state = LINK_STATE_DOWN;
1276                 if_link_state_change(ifp);
1277         }
1278 }
1279
1280 static void
1281 igb_stop(struct igb_softc *sc)
1282 {
1283         struct ifnet *ifp = &sc->arpcom.ac_if;
1284         int i;
1285
1286         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1287
1288         igb_disable_intr(sc);
1289
1290         callout_stop(&sc->timer);
1291
1292         ifp->if_flags &= ~IFF_RUNNING;
1293         for (i = 0; i < sc->tx_ring_cnt; ++i) {
1294                 ifsq_clr_oactive(sc->tx_rings[i].ifsq);
1295                 ifsq_watchdog_stop(&sc->tx_rings[i].tx_watchdog);
1296                 sc->tx_rings[i].tx_flags &= ~IGB_TXFLAG_ENABLED;
1297         }
1298
1299         e1000_reset_hw(&sc->hw);
1300         E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1301
1302         e1000_led_off(&sc->hw);
1303         e1000_cleanup_led(&sc->hw);
1304
1305         for (i = 0; i < sc->tx_ring_cnt; ++i)
1306                 igb_free_tx_ring(&sc->tx_rings[i]);
1307         for (i = 0; i < sc->rx_ring_cnt; ++i)
1308                 igb_free_rx_ring(&sc->rx_rings[i]);
1309 }
1310
1311 static void
1312 igb_reset(struct igb_softc *sc)
1313 {
1314         struct ifnet *ifp = &sc->arpcom.ac_if;
1315         struct e1000_hw *hw = &sc->hw;
1316         struct e1000_fc_info *fc = &hw->fc;
1317         uint32_t pba = 0;
1318         uint16_t hwm;
1319
1320         /* Let the firmware know the OS is in control */
1321         igb_get_hw_control(sc);
1322
1323         /*
1324          * Packet Buffer Allocation (PBA)
1325          * Writing PBA sets the receive portion of the buffer
1326          * the remainder is used for the transmit buffer.
1327          */
1328         switch (hw->mac.type) {
1329         case e1000_82575:
1330                 pba = E1000_PBA_32K;
1331                 break;
1332
1333         case e1000_82576:
1334         case e1000_vfadapt:
1335                 pba = E1000_READ_REG(hw, E1000_RXPBS);
1336                 pba &= E1000_RXPBS_SIZE_MASK_82576;
1337                 break;
1338
1339         case e1000_82580:
1340         case e1000_i350:
1341         case e1000_vfadapt_i350:
1342                 pba = E1000_READ_REG(hw, E1000_RXPBS);
1343                 pba = e1000_rxpbs_adjust_82580(pba);
1344                 break;
1345                 /* XXX pba = E1000_PBA_35K; */
1346
1347         default:
1348                 break;
1349         }
1350
1351         /* Special needs in case of Jumbo frames */
1352         if (hw->mac.type == e1000_82575 && ifp->if_mtu > ETHERMTU) {
1353                 uint32_t tx_space, min_tx, min_rx;
1354
1355                 pba = E1000_READ_REG(hw, E1000_PBA);
1356                 tx_space = pba >> 16;
1357                 pba &= 0xffff;
1358
1359                 min_tx = (sc->max_frame_size +
1360                     sizeof(struct e1000_tx_desc) - ETHER_CRC_LEN) * 2;
1361                 min_tx = roundup2(min_tx, 1024);
1362                 min_tx >>= 10;
1363                 min_rx = sc->max_frame_size;
1364                 min_rx = roundup2(min_rx, 1024);
1365                 min_rx >>= 10;
1366                 if (tx_space < min_tx && (min_tx - tx_space) < pba) {
1367                         pba = pba - (min_tx - tx_space);
1368                         /*
1369                          * if short on rx space, rx wins
1370                          * and must trump tx adjustment
1371                          */
1372                         if (pba < min_rx)
1373                                 pba = min_rx;
1374                 }
1375                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1376         }
1377
1378         /*
1379          * These parameters control the automatic generation (Tx) and
1380          * response (Rx) to Ethernet PAUSE frames.
1381          * - High water mark should allow for at least two frames to be
1382          *   received after sending an XOFF.
1383          * - Low water mark works best when it is very near the high water mark.
1384          *   This allows the receiver to restart by sending XON when it has
1385          *   drained a bit.
1386          */
1387         hwm = min(((pba << 10) * 9 / 10),
1388             ((pba << 10) - 2 * sc->max_frame_size));
1389
1390         if (hw->mac.type < e1000_82576) {
1391                 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1392                 fc->low_water = fc->high_water - 8;
1393         } else {
1394                 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1395                 fc->low_water = fc->high_water - 16;
1396         }
1397         fc->pause_time = IGB_FC_PAUSE_TIME;
1398         fc->send_xon = TRUE;
1399
1400         /* Issue a global reset */
1401         e1000_reset_hw(hw);
1402         E1000_WRITE_REG(hw, E1000_WUC, 0);
1403
1404         if (e1000_init_hw(hw) < 0)
1405                 if_printf(ifp, "Hardware Initialization Failed\n");
1406
1407         /* Setup DMA Coalescing */
1408         if (hw->mac.type == e1000_i350 && sc->dma_coalesce) {
1409                 uint32_t reg;
1410
1411                 hwm = (pba - 4) << 10;
1412                 reg = ((pba - 6) << E1000_DMACR_DMACTHR_SHIFT)
1413                     & E1000_DMACR_DMACTHR_MASK;
1414
1415                 /* transition to L0x or L1 if available..*/
1416                 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
1417
1418                 /* timer = +-1000 usec in 32usec intervals */
1419                 reg |= (1000 >> 5);
1420                 E1000_WRITE_REG(hw, E1000_DMACR, reg);
1421
1422                 /* No lower threshold */
1423                 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
1424
1425                 /* set hwm to PBA -  2 * max frame size */
1426                 E1000_WRITE_REG(hw, E1000_FCRTC, hwm);
1427
1428                 /* Set the interval before transition */
1429                 reg = E1000_READ_REG(hw, E1000_DMCTLX);
1430                 reg |= 0x800000FF; /* 255 usec */
1431                 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
1432
1433                 /* free space in tx packet buffer to wake from DMA coal */
1434                 E1000_WRITE_REG(hw, E1000_DMCTXTH,
1435                     (20480 - (2 * sc->max_frame_size)) >> 6);
1436
1437                 /* make low power state decision controlled by DMA coal */
1438                 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
1439                 E1000_WRITE_REG(hw, E1000_PCIEMISC,
1440                     reg | E1000_PCIEMISC_LX_DECISION);
1441                 if_printf(ifp, "DMA Coalescing enabled\n");
1442         }
1443
1444         E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1445         e1000_get_phy_info(hw);
1446         e1000_check_for_link(hw);
1447 }
1448
1449 static void
1450 igb_setup_ifp(struct igb_softc *sc)
1451 {
1452         struct ifnet *ifp = &sc->arpcom.ac_if;
1453
1454         ifp->if_softc = sc;
1455         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1456         ifp->if_init = igb_init;
1457         ifp->if_ioctl = igb_ioctl;
1458         ifp->if_start = igb_start;
1459         ifp->if_serialize = igb_serialize;
1460         ifp->if_deserialize = igb_deserialize;
1461         ifp->if_tryserialize = igb_tryserialize;
1462 #ifdef INVARIANTS
1463         ifp->if_serialize_assert = igb_serialize_assert;
1464 #endif
1465 #ifdef IFPOLL_ENABLE
1466         ifp->if_npoll = igb_npoll;
1467 #endif
1468
1469         ifq_set_maxlen(&ifp->if_snd, sc->tx_rings[0].num_tx_desc - 1);
1470         ifq_set_ready(&ifp->if_snd);
1471
1472         ether_ifattach(ifp, sc->hw.mac.addr, NULL);
1473
1474         ifp->if_capabilities =
1475             IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_TSO;
1476         if (IGB_ENABLE_HWRSS(sc))
1477                 ifp->if_capabilities |= IFCAP_RSS;
1478         ifp->if_capenable = ifp->if_capabilities;
1479         ifp->if_hwassist = IGB_CSUM_FEATURES | CSUM_TSO;
1480
1481         /*
1482          * Tell the upper layer(s) we support long frames
1483          */
1484         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1485
1486         /*
1487          * Specify the media types supported by this adapter and register
1488          * callbacks to update media and link information
1489          */
1490         ifmedia_init(&sc->media, IFM_IMASK, igb_media_change, igb_media_status);
1491         if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1492             sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1493                 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1494                     0, NULL);
1495                 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1496         } else {
1497                 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1498                 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1499                     0, NULL);
1500                 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1501                 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1502                     0, NULL);
1503                 if (sc->hw.phy.type != e1000_phy_ife) {
1504                         ifmedia_add(&sc->media,
1505                             IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1506                         ifmedia_add(&sc->media,
1507                             IFM_ETHER | IFM_1000_T, 0, NULL);
1508                 }
1509         }
1510         ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1511         ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1512 }
1513
1514 static void
1515 igb_add_sysctl(struct igb_softc *sc)
1516 {
1517         char node[32];
1518         int i;
1519
1520         sysctl_ctx_init(&sc->sysctl_ctx);
1521         sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
1522             SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1523             device_get_nameunit(sc->dev), CTLFLAG_RD, 0, "");
1524         if (sc->sysctl_tree == NULL) {
1525                 device_printf(sc->dev, "can't add sysctl node\n");
1526                 return;
1527         }
1528
1529         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1530             OID_AUTO, "rxr", CTLFLAG_RD, &sc->rx_ring_cnt, 0, "# of RX rings");
1531         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1532             OID_AUTO, "rxr_inuse", CTLFLAG_RD, &sc->rx_ring_inuse, 0,
1533             "# of RX rings used");
1534         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1535             OID_AUTO, "txr", CTLFLAG_RD, &sc->tx_ring_cnt, 0, "# of TX rings");
1536         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1537             OID_AUTO, "txr_inuse", CTLFLAG_RD, &sc->tx_ring_inuse, 0,
1538             "# of TX rings used");
1539         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1540             OID_AUTO, "rxd", CTLFLAG_RD, &sc->rx_rings[0].num_rx_desc, 0,
1541             "# of RX descs");
1542         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1543             OID_AUTO, "txd", CTLFLAG_RD, &sc->tx_rings[0].num_tx_desc, 0,
1544             "# of TX descs");
1545
1546         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
1547                 SYSCTL_ADD_PROC(&sc->sysctl_ctx,
1548                     SYSCTL_CHILDREN(sc->sysctl_tree),
1549                     OID_AUTO, "intr_rate", CTLTYPE_INT | CTLFLAG_RW,
1550                     sc, 0, igb_sysctl_intr_rate, "I", "interrupt rate");
1551         } else {
1552                 for (i = 0; i < sc->msix_cnt; ++i) {
1553                         struct igb_msix_data *msix = &sc->msix_data[i];
1554
1555                         ksnprintf(node, sizeof(node), "msix%d_rate", i);
1556                         SYSCTL_ADD_PROC(&sc->sysctl_ctx,
1557                             SYSCTL_CHILDREN(sc->sysctl_tree),
1558                             OID_AUTO, node, CTLTYPE_INT | CTLFLAG_RW,
1559                             msix, 0, igb_sysctl_msix_rate, "I",
1560                             msix->msix_rate_desc);
1561                 }
1562         }
1563
1564         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1565             OID_AUTO, "tx_intr_nsegs", CTLTYPE_INT | CTLFLAG_RW,
1566             sc, 0, igb_sysctl_tx_intr_nsegs, "I",
1567             "# of segments per TX interrupt");
1568
1569         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1570             OID_AUTO, "tx_wreg_nsegs", CTLTYPE_INT | CTLFLAG_RW,
1571             sc, 0, igb_sysctl_tx_wreg_nsegs, "I",
1572             "# of segments sent before write to hardware register");
1573
1574         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1575             OID_AUTO, "rx_wreg_nsegs", CTLTYPE_INT | CTLFLAG_RW,
1576             sc, 0, igb_sysctl_rx_wreg_nsegs, "I",
1577             "# of segments received before write to hardware register");
1578
1579 #ifdef IFPOLL_ENABLE
1580         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1581             OID_AUTO, "npoll_rxoff", CTLTYPE_INT|CTLFLAG_RW,
1582             sc, 0, igb_sysctl_npoll_rxoff, "I", "NPOLLING RX cpu offset");
1583         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1584             OID_AUTO, "npoll_txoff", CTLTYPE_INT|CTLFLAG_RW,
1585             sc, 0, igb_sysctl_npoll_txoff, "I", "NPOLLING TX cpu offset");
1586 #endif
1587
1588 #ifdef IGB_RSS_DEBUG
1589         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1590             OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug, 0,
1591             "RSS debug level");
1592         for (i = 0; i < sc->rx_ring_cnt; ++i) {
1593                 ksnprintf(node, sizeof(node), "rx%d_pkt", i);
1594                 SYSCTL_ADD_ULONG(&sc->sysctl_ctx,
1595                     SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, node,
1596                     CTLFLAG_RW, &sc->rx_rings[i].rx_packets, "RXed packets");
1597         }
1598 #endif
1599 #ifdef IGB_TSS_DEBUG
1600         for  (i = 0; i < sc->tx_ring_cnt; ++i) {
1601                 ksnprintf(node, sizeof(node), "tx%d_pkt", i);
1602                 SYSCTL_ADD_ULONG(&sc->sysctl_ctx,
1603                     SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, node,
1604                     CTLFLAG_RW, &sc->tx_rings[i].tx_packets, "TXed packets");
1605         }
1606 #endif
1607 }
1608
1609 static int
1610 igb_alloc_rings(struct igb_softc *sc)
1611 {
1612         int error, i;
1613
1614         /*
1615          * Create top level busdma tag
1616          */
1617         error = bus_dma_tag_create(NULL, 1, 0,
1618             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1619             BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
1620             &sc->parent_tag);
1621         if (error) {
1622                 device_printf(sc->dev, "could not create top level DMA tag\n");
1623                 return error;
1624         }
1625
1626         /*
1627          * Allocate TX descriptor rings and buffers
1628          */
1629         sc->tx_rings = kmalloc_cachealign(
1630             sizeof(struct igb_tx_ring) * sc->tx_ring_cnt,
1631             M_DEVBUF, M_WAITOK | M_ZERO);
1632         for (i = 0; i < sc->tx_ring_cnt; ++i) {
1633                 struct igb_tx_ring *txr = &sc->tx_rings[i];
1634
1635                 /* Set up some basics */
1636                 txr->sc = sc;
1637                 txr->me = i;
1638                 lwkt_serialize_init(&txr->tx_serialize);
1639
1640                 error = igb_create_tx_ring(txr);
1641                 if (error)
1642                         return error;
1643         }
1644
1645         /*
1646          * Allocate RX descriptor rings and buffers
1647          */
1648         sc->rx_rings = kmalloc_cachealign(
1649             sizeof(struct igb_rx_ring) * sc->rx_ring_cnt,
1650             M_DEVBUF, M_WAITOK | M_ZERO);
1651         for (i = 0; i < sc->rx_ring_cnt; ++i) {
1652                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
1653
1654                 /* Set up some basics */
1655                 rxr->sc = sc;
1656                 rxr->me = i;
1657                 lwkt_serialize_init(&rxr->rx_serialize);
1658
1659                 error = igb_create_rx_ring(rxr);
1660                 if (error)
1661                         return error;
1662         }
1663
1664         return 0;
1665 }
1666
1667 static void
1668 igb_free_rings(struct igb_softc *sc)
1669 {
1670         int i;
1671
1672         if (sc->tx_rings != NULL) {
1673                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1674                         struct igb_tx_ring *txr = &sc->tx_rings[i];
1675
1676                         igb_destroy_tx_ring(txr, txr->num_tx_desc);
1677                 }
1678                 kfree(sc->tx_rings, M_DEVBUF);
1679         }
1680
1681         if (sc->rx_rings != NULL) {
1682                 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1683                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
1684
1685                         igb_destroy_rx_ring(rxr, rxr->num_rx_desc);
1686                 }
1687                 kfree(sc->rx_rings, M_DEVBUF);
1688         }
1689 }
1690
1691 static int
1692 igb_create_tx_ring(struct igb_tx_ring *txr)
1693 {
1694         int tsize, error, i, ntxd;
1695
1696         /*
1697          * Validate number of transmit descriptors. It must not exceed
1698          * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
1699          */
1700         ntxd = device_getenv_int(txr->sc->dev, "txd", igb_txd);
1701         if ((ntxd * sizeof(struct e1000_tx_desc)) % IGB_DBA_ALIGN != 0 ||
1702             ntxd > IGB_MAX_TXD || ntxd < IGB_MIN_TXD) {
1703                 device_printf(txr->sc->dev,
1704                     "Using %d TX descriptors instead of %d!\n",
1705                     IGB_DEFAULT_TXD, ntxd);
1706                 txr->num_tx_desc = IGB_DEFAULT_TXD;
1707         } else {
1708                 txr->num_tx_desc = ntxd;
1709         }
1710
1711         /*
1712          * Allocate TX descriptor ring
1713          */
1714         tsize = roundup2(txr->num_tx_desc * sizeof(union e1000_adv_tx_desc),
1715             IGB_DBA_ALIGN);
1716         txr->txdma.dma_vaddr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1717             IGB_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
1718             &txr->txdma.dma_tag, &txr->txdma.dma_map, &txr->txdma.dma_paddr);
1719         if (txr->txdma.dma_vaddr == NULL) {
1720                 device_printf(txr->sc->dev,
1721                     "Unable to allocate TX Descriptor memory\n");
1722                 return ENOMEM;
1723         }
1724         txr->tx_base = txr->txdma.dma_vaddr;
1725         bzero(txr->tx_base, tsize);
1726
1727         tsize = __VM_CACHELINE_ALIGN(
1728             sizeof(struct igb_tx_buf) * txr->num_tx_desc);
1729         txr->tx_buf = kmalloc_cachealign(tsize, M_DEVBUF, M_WAITOK | M_ZERO);
1730
1731         /*
1732          * Allocate TX head write-back buffer
1733          */
1734         txr->tx_hdr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1735             __VM_CACHELINE_SIZE, __VM_CACHELINE_SIZE, BUS_DMA_WAITOK,
1736             &txr->tx_hdr_dtag, &txr->tx_hdr_dmap, &txr->tx_hdr_paddr);
1737         if (txr->tx_hdr == NULL) {
1738                 device_printf(txr->sc->dev,
1739                     "Unable to allocate TX head write-back buffer\n");
1740                 return ENOMEM;
1741         }
1742
1743         /*
1744          * Create DMA tag for TX buffers
1745          */
1746         error = bus_dma_tag_create(txr->sc->parent_tag,
1747             1, 0,               /* alignment, bounds */
1748             BUS_SPACE_MAXADDR,  /* lowaddr */
1749             BUS_SPACE_MAXADDR,  /* highaddr */
1750             NULL, NULL,         /* filter, filterarg */
1751             IGB_TSO_SIZE,       /* maxsize */
1752             IGB_MAX_SCATTER,    /* nsegments */
1753             PAGE_SIZE,          /* maxsegsize */
1754             BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
1755             BUS_DMA_ONEBPAGE,   /* flags */
1756             &txr->tx_tag);
1757         if (error) {
1758                 device_printf(txr->sc->dev, "Unable to allocate TX DMA tag\n");
1759                 kfree(txr->tx_buf, M_DEVBUF);
1760                 txr->tx_buf = NULL;
1761                 return error;
1762         }
1763
1764         /*
1765          * Create DMA maps for TX buffers
1766          */
1767         for (i = 0; i < txr->num_tx_desc; ++i) {
1768                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1769
1770                 error = bus_dmamap_create(txr->tx_tag,
1771                     BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, &txbuf->map);
1772                 if (error) {
1773                         device_printf(txr->sc->dev,
1774                             "Unable to create TX DMA map\n");
1775                         igb_destroy_tx_ring(txr, i);
1776                         return error;
1777                 }
1778         }
1779
1780         if (txr->sc->hw.mac.type == e1000_82575)
1781                 txr->tx_flags |= IGB_TXFLAG_TSO_IPLEN0;
1782
1783         /*
1784          * Initialize various watermark
1785          */
1786         txr->spare_desc = IGB_TX_SPARE;
1787         txr->intr_nsegs = txr->num_tx_desc / 16;
1788         txr->wreg_nsegs = IGB_DEF_TXWREG_NSEGS;
1789         txr->oact_hi_desc = txr->num_tx_desc / 2;
1790         txr->oact_lo_desc = txr->num_tx_desc / 8;
1791         if (txr->oact_lo_desc > IGB_TX_OACTIVE_MAX)
1792                 txr->oact_lo_desc = IGB_TX_OACTIVE_MAX;
1793         if (txr->oact_lo_desc < txr->spare_desc + IGB_TX_RESERVED)
1794                 txr->oact_lo_desc = txr->spare_desc + IGB_TX_RESERVED;
1795
1796         return 0;
1797 }
1798
1799 static void
1800 igb_free_tx_ring(struct igb_tx_ring *txr)
1801 {
1802         int i;
1803
1804         for (i = 0; i < txr->num_tx_desc; ++i) {
1805                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1806
1807                 if (txbuf->m_head != NULL) {
1808                         bus_dmamap_unload(txr->tx_tag, txbuf->map);
1809                         m_freem(txbuf->m_head);
1810                         txbuf->m_head = NULL;
1811                 }
1812         }
1813 }
1814
1815 static void
1816 igb_destroy_tx_ring(struct igb_tx_ring *txr, int ndesc)
1817 {
1818         int i;
1819
1820         if (txr->txdma.dma_vaddr != NULL) {
1821                 bus_dmamap_unload(txr->txdma.dma_tag, txr->txdma.dma_map);
1822                 bus_dmamem_free(txr->txdma.dma_tag, txr->txdma.dma_vaddr,
1823                     txr->txdma.dma_map);
1824                 bus_dma_tag_destroy(txr->txdma.dma_tag);
1825                 txr->txdma.dma_vaddr = NULL;
1826         }
1827
1828         if (txr->tx_hdr != NULL) {
1829                 bus_dmamap_unload(txr->tx_hdr_dtag, txr->tx_hdr_dmap);
1830                 bus_dmamem_free(txr->tx_hdr_dtag, txr->tx_hdr,
1831                     txr->tx_hdr_dmap);
1832                 bus_dma_tag_destroy(txr->tx_hdr_dtag);
1833                 txr->tx_hdr = NULL;
1834         }
1835
1836         if (txr->tx_buf == NULL)
1837                 return;
1838
1839         for (i = 0; i < ndesc; ++i) {
1840                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1841
1842                 KKASSERT(txbuf->m_head == NULL);
1843                 bus_dmamap_destroy(txr->tx_tag, txbuf->map);
1844         }
1845         bus_dma_tag_destroy(txr->tx_tag);
1846
1847         kfree(txr->tx_buf, M_DEVBUF);
1848         txr->tx_buf = NULL;
1849 }
1850
1851 static void
1852 igb_init_tx_ring(struct igb_tx_ring *txr)
1853 {
1854         /* Clear the old descriptor contents */
1855         bzero(txr->tx_base,
1856             sizeof(union e1000_adv_tx_desc) * txr->num_tx_desc);
1857
1858         /* Clear TX head write-back buffer */
1859         *(txr->tx_hdr) = 0;
1860
1861         /* Reset indices */
1862         txr->next_avail_desc = 0;
1863         txr->next_to_clean = 0;
1864         txr->tx_nsegs = 0;
1865
1866         /* Set number of descriptors available */
1867         txr->tx_avail = txr->num_tx_desc;
1868
1869         /* Enable this TX ring */
1870         txr->tx_flags |= IGB_TXFLAG_ENABLED;
1871 }
1872
1873 static void
1874 igb_init_tx_unit(struct igb_softc *sc)
1875 {
1876         struct e1000_hw *hw = &sc->hw;
1877         uint32_t tctl;
1878         int i;
1879
1880         /* Setup the Tx Descriptor Rings */
1881         for (i = 0; i < sc->tx_ring_inuse; ++i) {
1882                 struct igb_tx_ring *txr = &sc->tx_rings[i];
1883                 uint64_t bus_addr = txr->txdma.dma_paddr;
1884                 uint64_t hdr_paddr = txr->tx_hdr_paddr;
1885                 uint32_t txdctl = 0;
1886                 uint32_t dca_txctrl;
1887
1888                 E1000_WRITE_REG(hw, E1000_TDLEN(i),
1889                     txr->num_tx_desc * sizeof(struct e1000_tx_desc));
1890                 E1000_WRITE_REG(hw, E1000_TDBAH(i),
1891                     (uint32_t)(bus_addr >> 32));
1892                 E1000_WRITE_REG(hw, E1000_TDBAL(i),
1893                     (uint32_t)bus_addr);
1894
1895                 /* Setup the HW Tx Head and Tail descriptor pointers */
1896                 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
1897                 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
1898
1899                 dca_txctrl = E1000_READ_REG(hw, E1000_DCA_TXCTRL(i));
1900                 dca_txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1901                 E1000_WRITE_REG(hw, E1000_DCA_TXCTRL(i), dca_txctrl);
1902
1903                 /*
1904                  * Don't set WB_on_EITR:
1905                  * - 82575 does not have it
1906                  * - It almost has no effect on 82576, see:
1907                  *   82576 specification update errata #26
1908                  * - It causes unnecessary bus traffic
1909                  */
1910                 E1000_WRITE_REG(hw, E1000_TDWBAH(i),
1911                     (uint32_t)(hdr_paddr >> 32));
1912                 E1000_WRITE_REG(hw, E1000_TDWBAL(i),
1913                     ((uint32_t)hdr_paddr) | E1000_TX_HEAD_WB_ENABLE);
1914
1915                 /*
1916                  * WTHRESH is ignored by the hardware, since header
1917                  * write back mode is used.
1918                  */
1919                 txdctl |= IGB_TX_PTHRESH;
1920                 txdctl |= IGB_TX_HTHRESH << 8;
1921                 txdctl |= IGB_TX_WTHRESH << 16;
1922                 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1923                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
1924         }
1925
1926         if (sc->vf_ifp)
1927                 return;
1928
1929         e1000_config_collision_dist(hw);
1930
1931         /* Program the Transmit Control Register */
1932         tctl = E1000_READ_REG(hw, E1000_TCTL);
1933         tctl &= ~E1000_TCTL_CT;
1934         tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
1935             (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
1936
1937         /* This write will effectively turn on the transmit unit. */
1938         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1939 }
1940
1941 static boolean_t
1942 igb_txcsum_ctx(struct igb_tx_ring *txr, struct mbuf *mp)
1943 {
1944         struct e1000_adv_tx_context_desc *TXD;
1945         uint32_t vlan_macip_lens, type_tucmd_mlhl, mss_l4len_idx;
1946         int ehdrlen, ctxd, ip_hlen = 0;
1947         boolean_t offload = TRUE;
1948
1949         if ((mp->m_pkthdr.csum_flags & IGB_CSUM_FEATURES) == 0)
1950                 offload = FALSE;
1951
1952         vlan_macip_lens = type_tucmd_mlhl = mss_l4len_idx = 0;
1953
1954         ctxd = txr->next_avail_desc;
1955         TXD = (struct e1000_adv_tx_context_desc *)&txr->tx_base[ctxd];
1956
1957         /*
1958          * In advanced descriptors the vlan tag must
1959          * be placed into the context descriptor, thus
1960          * we need to be here just for that setup.
1961          */
1962         if (mp->m_flags & M_VLANTAG) {
1963                 uint16_t vlantag;
1964
1965                 vlantag = htole16(mp->m_pkthdr.ether_vlantag);
1966                 vlan_macip_lens |= (vlantag << E1000_ADVTXD_VLAN_SHIFT);
1967         } else if (!offload) {
1968                 return FALSE;
1969         }
1970
1971         ehdrlen = mp->m_pkthdr.csum_lhlen;
1972         KASSERT(ehdrlen > 0, ("invalid ether hlen"));
1973
1974         /* Set the ether header length */
1975         vlan_macip_lens |= ehdrlen << E1000_ADVTXD_MACLEN_SHIFT;
1976         if (mp->m_pkthdr.csum_flags & CSUM_IP) {
1977                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4;
1978                 ip_hlen = mp->m_pkthdr.csum_iphlen;
1979                 KASSERT(ip_hlen > 0, ("invalid ip hlen"));
1980         }
1981         vlan_macip_lens |= ip_hlen;
1982
1983         type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
1984         if (mp->m_pkthdr.csum_flags & CSUM_TCP)
1985                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP;
1986         else if (mp->m_pkthdr.csum_flags & CSUM_UDP)
1987                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_UDP;
1988
1989         /* 82575 needs the queue index added */
1990         if (txr->sc->hw.mac.type == e1000_82575)
1991                 mss_l4len_idx = txr->me << 4;
1992
1993         /* Now copy bits into descriptor */
1994         TXD->vlan_macip_lens = htole32(vlan_macip_lens);
1995         TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
1996         TXD->seqnum_seed = htole32(0);
1997         TXD->mss_l4len_idx = htole32(mss_l4len_idx);
1998
1999         /* We've consumed the first desc, adjust counters */
2000         if (++ctxd == txr->num_tx_desc)
2001                 ctxd = 0;
2002         txr->next_avail_desc = ctxd;
2003         --txr->tx_avail;
2004
2005         return offload;
2006 }
2007
2008 static void
2009 igb_txeof(struct igb_tx_ring *txr)
2010 {
2011         struct ifnet *ifp = &txr->sc->arpcom.ac_if;
2012         int first, hdr, avail;
2013
2014         if (txr->tx_avail == txr->num_tx_desc)
2015                 return;
2016
2017         first = txr->next_to_clean;
2018         hdr = *(txr->tx_hdr);
2019
2020         if (first == hdr)
2021                 return;
2022
2023         avail = txr->tx_avail;
2024         while (first != hdr) {
2025                 struct igb_tx_buf *txbuf = &txr->tx_buf[first];
2026
2027                 ++avail;
2028                 if (txbuf->m_head) {
2029                         bus_dmamap_unload(txr->tx_tag, txbuf->map);
2030                         m_freem(txbuf->m_head);
2031                         txbuf->m_head = NULL;
2032                         ++ifp->if_opackets;
2033                 }
2034                 if (++first == txr->num_tx_desc)
2035                         first = 0;
2036         }
2037         txr->next_to_clean = first;
2038         txr->tx_avail = avail;
2039
2040         /*
2041          * If we have a minimum free, clear OACTIVE
2042          * to tell the stack that it is OK to send packets.
2043          */
2044         if (IGB_IS_NOT_OACTIVE(txr)) {
2045                 ifsq_clr_oactive(txr->ifsq);
2046
2047                 /*
2048                  * We have enough TX descriptors, turn off
2049                  * the watchdog.  We allow small amount of
2050                  * packets (roughly intr_nsegs) pending on
2051                  * the transmit ring.
2052                  */
2053                 txr->tx_watchdog.wd_timer = 0;
2054         }
2055 }
2056
2057 static int
2058 igb_create_rx_ring(struct igb_rx_ring *rxr)
2059 {
2060         int rsize, i, error, nrxd;
2061
2062         /*
2063          * Validate number of receive descriptors. It must not exceed
2064          * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
2065          */
2066         nrxd = device_getenv_int(rxr->sc->dev, "rxd", igb_rxd);
2067         if ((nrxd * sizeof(struct e1000_rx_desc)) % IGB_DBA_ALIGN != 0 ||
2068             nrxd > IGB_MAX_RXD || nrxd < IGB_MIN_RXD) {
2069                 device_printf(rxr->sc->dev,
2070                     "Using %d RX descriptors instead of %d!\n",
2071                     IGB_DEFAULT_RXD, nrxd);
2072                 rxr->num_rx_desc = IGB_DEFAULT_RXD;
2073         } else {
2074                 rxr->num_rx_desc = nrxd;
2075         }
2076
2077         /*
2078          * Allocate RX descriptor ring
2079          */
2080         rsize = roundup2(rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc),
2081             IGB_DBA_ALIGN);
2082         rxr->rxdma.dma_vaddr = bus_dmamem_coherent_any(rxr->sc->parent_tag,
2083             IGB_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
2084             &rxr->rxdma.dma_tag, &rxr->rxdma.dma_map,
2085             &rxr->rxdma.dma_paddr);
2086         if (rxr->rxdma.dma_vaddr == NULL) {
2087                 device_printf(rxr->sc->dev,
2088                     "Unable to allocate RxDescriptor memory\n");
2089                 return ENOMEM;
2090         }
2091         rxr->rx_base = rxr->rxdma.dma_vaddr;
2092         bzero(rxr->rx_base, rsize);
2093
2094         rsize = __VM_CACHELINE_ALIGN(
2095             sizeof(struct igb_rx_buf) * rxr->num_rx_desc);
2096         rxr->rx_buf = kmalloc_cachealign(rsize, M_DEVBUF, M_WAITOK | M_ZERO);
2097
2098         /*
2099          * Create DMA tag for RX buffers
2100          */
2101         error = bus_dma_tag_create(rxr->sc->parent_tag,
2102             1, 0,               /* alignment, bounds */
2103             BUS_SPACE_MAXADDR,  /* lowaddr */
2104             BUS_SPACE_MAXADDR,  /* highaddr */
2105             NULL, NULL,         /* filter, filterarg */
2106             MCLBYTES,           /* maxsize */
2107             1,                  /* nsegments */
2108             MCLBYTES,           /* maxsegsize */
2109             BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
2110             &rxr->rx_tag);
2111         if (error) {
2112                 device_printf(rxr->sc->dev,
2113                     "Unable to create RX payload DMA tag\n");
2114                 kfree(rxr->rx_buf, M_DEVBUF);
2115                 rxr->rx_buf = NULL;
2116                 return error;
2117         }
2118
2119         /*
2120          * Create spare DMA map for RX buffers
2121          */
2122         error = bus_dmamap_create(rxr->rx_tag, BUS_DMA_WAITOK,
2123             &rxr->rx_sparemap);
2124         if (error) {
2125                 device_printf(rxr->sc->dev,
2126                     "Unable to create spare RX DMA maps\n");
2127                 bus_dma_tag_destroy(rxr->rx_tag);
2128                 kfree(rxr->rx_buf, M_DEVBUF);
2129                 rxr->rx_buf = NULL;
2130                 return error;
2131         }
2132
2133         /*
2134          * Create DMA maps for RX buffers
2135          */
2136         for (i = 0; i < rxr->num_rx_desc; i++) {
2137                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2138
2139                 error = bus_dmamap_create(rxr->rx_tag,
2140                     BUS_DMA_WAITOK, &rxbuf->map);
2141                 if (error) {
2142                         device_printf(rxr->sc->dev,
2143                             "Unable to create RX DMA maps\n");
2144                         igb_destroy_rx_ring(rxr, i);
2145                         return error;
2146                 }
2147         }
2148
2149         /*
2150          * Initialize various watermark
2151          */
2152         rxr->wreg_nsegs = IGB_DEF_RXWREG_NSEGS;
2153
2154         return 0;
2155 }
2156
2157 static void
2158 igb_free_rx_ring(struct igb_rx_ring *rxr)
2159 {
2160         int i;
2161
2162         for (i = 0; i < rxr->num_rx_desc; ++i) {
2163                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2164
2165                 if (rxbuf->m_head != NULL) {
2166                         bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2167                         m_freem(rxbuf->m_head);
2168                         rxbuf->m_head = NULL;
2169                 }
2170         }
2171
2172         if (rxr->fmp != NULL)
2173                 m_freem(rxr->fmp);
2174         rxr->fmp = NULL;
2175         rxr->lmp = NULL;
2176 }
2177
2178 static void
2179 igb_destroy_rx_ring(struct igb_rx_ring *rxr, int ndesc)
2180 {
2181         int i;
2182
2183         if (rxr->rxdma.dma_vaddr != NULL) {
2184                 bus_dmamap_unload(rxr->rxdma.dma_tag, rxr->rxdma.dma_map);
2185                 bus_dmamem_free(rxr->rxdma.dma_tag, rxr->rxdma.dma_vaddr,
2186                     rxr->rxdma.dma_map);
2187                 bus_dma_tag_destroy(rxr->rxdma.dma_tag);
2188                 rxr->rxdma.dma_vaddr = NULL;
2189         }
2190
2191         if (rxr->rx_buf == NULL)
2192                 return;
2193
2194         for (i = 0; i < ndesc; ++i) {
2195                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2196
2197                 KKASSERT(rxbuf->m_head == NULL);
2198                 bus_dmamap_destroy(rxr->rx_tag, rxbuf->map);
2199         }
2200         bus_dmamap_destroy(rxr->rx_tag, rxr->rx_sparemap);
2201         bus_dma_tag_destroy(rxr->rx_tag);
2202
2203         kfree(rxr->rx_buf, M_DEVBUF);
2204         rxr->rx_buf = NULL;
2205 }
2206
2207 static void
2208 igb_setup_rxdesc(union e1000_adv_rx_desc *rxd, const struct igb_rx_buf *rxbuf)
2209 {
2210         rxd->read.pkt_addr = htole64(rxbuf->paddr);
2211         rxd->wb.upper.status_error = 0;
2212 }
2213
2214 static int
2215 igb_newbuf(struct igb_rx_ring *rxr, int i, boolean_t wait)
2216 {
2217         struct mbuf *m;
2218         bus_dma_segment_t seg;
2219         bus_dmamap_t map;
2220         struct igb_rx_buf *rxbuf;
2221         int error, nseg;
2222
2223         m = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2224         if (m == NULL) {
2225                 if (wait) {
2226                         if_printf(&rxr->sc->arpcom.ac_if,
2227                             "Unable to allocate RX mbuf\n");
2228                 }
2229                 return ENOBUFS;
2230         }
2231         m->m_len = m->m_pkthdr.len = MCLBYTES;
2232
2233         if (rxr->sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2234                 m_adj(m, ETHER_ALIGN);
2235
2236         error = bus_dmamap_load_mbuf_segment(rxr->rx_tag,
2237             rxr->rx_sparemap, m, &seg, 1, &nseg, BUS_DMA_NOWAIT);
2238         if (error) {
2239                 m_freem(m);
2240                 if (wait) {
2241                         if_printf(&rxr->sc->arpcom.ac_if,
2242                             "Unable to load RX mbuf\n");
2243                 }
2244                 return error;
2245         }
2246
2247         rxbuf = &rxr->rx_buf[i];
2248         if (rxbuf->m_head != NULL)
2249                 bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2250
2251         map = rxbuf->map;
2252         rxbuf->map = rxr->rx_sparemap;
2253         rxr->rx_sparemap = map;
2254
2255         rxbuf->m_head = m;
2256         rxbuf->paddr = seg.ds_addr;
2257
2258         igb_setup_rxdesc(&rxr->rx_base[i], rxbuf);
2259         return 0;
2260 }
2261
2262 static int
2263 igb_init_rx_ring(struct igb_rx_ring *rxr)
2264 {
2265         int i;
2266
2267         /* Clear the ring contents */
2268         bzero(rxr->rx_base,
2269             rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc));
2270
2271         /* Now replenish the ring mbufs */
2272         for (i = 0; i < rxr->num_rx_desc; ++i) {
2273                 int error;
2274
2275                 error = igb_newbuf(rxr, i, TRUE);
2276                 if (error)
2277                         return error;
2278         }
2279
2280         /* Setup our descriptor indices */
2281         rxr->next_to_check = 0;
2282
2283         rxr->fmp = NULL;
2284         rxr->lmp = NULL;
2285         rxr->discard = FALSE;
2286
2287         return 0;
2288 }
2289
2290 static void
2291 igb_init_rx_unit(struct igb_softc *sc)
2292 {
2293         struct ifnet *ifp = &sc->arpcom.ac_if;
2294         struct e1000_hw *hw = &sc->hw;
2295         uint32_t rctl, rxcsum, srrctl = 0;
2296         int i;
2297
2298         /*
2299          * Make sure receives are disabled while setting
2300          * up the descriptor ring
2301          */
2302         rctl = E1000_READ_REG(hw, E1000_RCTL);
2303         E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2304
2305 #if 0
2306         /*
2307         ** Set up for header split
2308         */
2309         if (igb_header_split) {
2310                 /* Use a standard mbuf for the header */
2311                 srrctl |= IGB_HDR_BUF << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2312                 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2313         } else
2314 #endif
2315                 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2316
2317         /*
2318         ** Set up for jumbo frames
2319         */
2320         if (ifp->if_mtu > ETHERMTU) {
2321                 rctl |= E1000_RCTL_LPE;
2322 #if 0
2323                 if (adapter->rx_mbuf_sz == MJUMPAGESIZE) {
2324                         srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2325                         rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
2326                 } else if (adapter->rx_mbuf_sz > MJUMPAGESIZE) {
2327                         srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2328                         rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
2329                 }
2330                 /* Set maximum packet len */
2331                 psize = adapter->max_frame_size;
2332                 /* are we on a vlan? */
2333                 if (adapter->ifp->if_vlantrunk != NULL)
2334                         psize += VLAN_TAG_SIZE;
2335                 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize);
2336 #else
2337                 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2338                 rctl |= E1000_RCTL_SZ_2048;
2339 #endif
2340         } else {
2341                 rctl &= ~E1000_RCTL_LPE;
2342                 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2343                 rctl |= E1000_RCTL_SZ_2048;
2344         }
2345
2346         /* Setup the Base and Length of the Rx Descriptor Rings */
2347         for (i = 0; i < sc->rx_ring_inuse; ++i) {
2348                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2349                 uint64_t bus_addr = rxr->rxdma.dma_paddr;
2350                 uint32_t rxdctl;
2351
2352                 E1000_WRITE_REG(hw, E1000_RDLEN(i),
2353                     rxr->num_rx_desc * sizeof(struct e1000_rx_desc));
2354                 E1000_WRITE_REG(hw, E1000_RDBAH(i),
2355                     (uint32_t)(bus_addr >> 32));
2356                 E1000_WRITE_REG(hw, E1000_RDBAL(i),
2357                     (uint32_t)bus_addr);
2358                 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
2359                 /* Enable this Queue */
2360                 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
2361                 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2362                 rxdctl &= 0xFFF00000;
2363                 rxdctl |= IGB_RX_PTHRESH;
2364                 rxdctl |= IGB_RX_HTHRESH << 8;
2365                 /*
2366                  * Don't set WTHRESH to a value above 1 on 82576, see:
2367                  * 82576 specification update errata #26
2368                  */
2369                 rxdctl |= IGB_RX_WTHRESH << 16;
2370                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
2371         }
2372
2373         rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
2374         rxcsum &= ~(E1000_RXCSUM_PCSS_MASK | E1000_RXCSUM_IPPCSE);
2375
2376         /*
2377          * Receive Checksum Offload for TCP and UDP
2378          *
2379          * Checksum offloading is also enabled if multiple receive
2380          * queue is to be supported, since we need it to figure out
2381          * fragments.
2382          */
2383         if ((ifp->if_capenable & IFCAP_RXCSUM) || IGB_ENABLE_HWRSS(sc)) {
2384                 /*
2385                  * NOTE:
2386                  * PCSD must be enabled to enable multiple
2387                  * receive queues.
2388                  */
2389                 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2390                     E1000_RXCSUM_PCSD;
2391         } else {
2392                 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2393                     E1000_RXCSUM_PCSD);
2394         }
2395         E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2396
2397         if (IGB_ENABLE_HWRSS(sc)) {
2398                 uint8_t key[IGB_NRSSRK * IGB_RSSRK_SIZE];
2399                 uint32_t reta_shift;
2400                 int j, r;
2401
2402                 /*
2403                  * NOTE:
2404                  * When we reach here, RSS has already been disabled
2405                  * in igb_stop(), so we could safely configure RSS key
2406                  * and redirect table.
2407                  */
2408
2409                 /*
2410                  * Configure RSS key
2411                  */
2412                 toeplitz_get_key(key, sizeof(key));
2413                 for (i = 0; i < IGB_NRSSRK; ++i) {
2414                         uint32_t rssrk;
2415
2416                         rssrk = IGB_RSSRK_VAL(key, i);
2417                         IGB_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2418
2419                         E1000_WRITE_REG(hw, E1000_RSSRK(i), rssrk);
2420                 }
2421
2422                 /*
2423                  * Configure RSS redirect table in following fashion:
2424                  * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2425                  */
2426                 reta_shift = IGB_RETA_SHIFT;
2427                 if (hw->mac.type == e1000_82575)
2428                         reta_shift = IGB_RETA_SHIFT_82575;
2429
2430                 r = 0;
2431                 for (j = 0; j < IGB_NRETA; ++j) {
2432                         uint32_t reta = 0;
2433
2434                         for (i = 0; i < IGB_RETA_SIZE; ++i) {
2435                                 uint32_t q;
2436
2437                                 q = (r % sc->rx_ring_inuse) << reta_shift;
2438                                 reta |= q << (8 * i);
2439                                 ++r;
2440                         }
2441                         IGB_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2442                         E1000_WRITE_REG(hw, E1000_RETA(j), reta);
2443                 }
2444
2445                 /*
2446                  * Enable multiple receive queues.
2447                  * Enable IPv4 RSS standard hash functions.
2448                  * Disable RSS interrupt on 82575
2449                  */
2450                 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
2451                                 E1000_MRQC_ENABLE_RSS_4Q |
2452                                 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2453                                 E1000_MRQC_RSS_FIELD_IPV4);
2454         }
2455
2456         /* Setup the Receive Control Register */
2457         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2458         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2459             E1000_RCTL_RDMTS_HALF |
2460             (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2461         /* Strip CRC bytes. */
2462         rctl |= E1000_RCTL_SECRC;
2463         /* Make sure VLAN Filters are off */
2464         rctl &= ~E1000_RCTL_VFE;
2465         /* Don't store bad packets */
2466         rctl &= ~E1000_RCTL_SBP;
2467
2468         /* Enable Receives */
2469         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2470
2471         /*
2472          * Setup the HW Rx Head and Tail Descriptor Pointers
2473          *   - needs to be after enable
2474          */
2475         for (i = 0; i < sc->rx_ring_inuse; ++i) {
2476                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2477
2478                 E1000_WRITE_REG(hw, E1000_RDH(i), rxr->next_to_check);
2479                 E1000_WRITE_REG(hw, E1000_RDT(i), rxr->num_rx_desc - 1);
2480         }
2481 }
2482
2483 static void
2484 igb_rx_refresh(struct igb_rx_ring *rxr, int i)
2485 {
2486         if (--i < 0)
2487                 i = rxr->num_rx_desc - 1;
2488         E1000_WRITE_REG(&rxr->sc->hw, E1000_RDT(rxr->me), i);
2489 }
2490
2491 static void
2492 igb_rxeof(struct igb_rx_ring *rxr, int count)
2493 {
2494         struct ifnet *ifp = &rxr->sc->arpcom.ac_if;
2495         union e1000_adv_rx_desc *cur;
2496         uint32_t staterr;
2497         int i, ncoll = 0;
2498
2499         i = rxr->next_to_check;
2500         cur = &rxr->rx_base[i];
2501         staterr = le32toh(cur->wb.upper.status_error);
2502
2503         if ((staterr & E1000_RXD_STAT_DD) == 0)
2504                 return;
2505
2506         while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
2507                 struct pktinfo *pi = NULL, pi0;
2508                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2509                 struct mbuf *m = NULL;
2510                 boolean_t eop;
2511
2512                 eop = (staterr & E1000_RXD_STAT_EOP) ? TRUE : FALSE;
2513                 if (eop)
2514                         --count;
2515
2516                 ++ncoll;
2517                 if ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) == 0 &&
2518                     !rxr->discard) {
2519                         struct mbuf *mp = rxbuf->m_head;
2520                         uint32_t hash, hashtype;
2521                         uint16_t vlan;
2522                         int len;
2523
2524                         len = le16toh(cur->wb.upper.length);
2525                         if (rxr->sc->hw.mac.type == e1000_i350 &&
2526                             (staterr & E1000_RXDEXT_STATERR_LB))
2527                                 vlan = be16toh(cur->wb.upper.vlan);
2528                         else
2529                                 vlan = le16toh(cur->wb.upper.vlan);
2530
2531                         hash = le32toh(cur->wb.lower.hi_dword.rss);
2532                         hashtype = le32toh(cur->wb.lower.lo_dword.data) &
2533                             E1000_RXDADV_RSSTYPE_MASK;
2534
2535                         IGB_RSS_DPRINTF(rxr->sc, 10,
2536                             "ring%d, hash 0x%08x, hashtype %u\n",
2537                             rxr->me, hash, hashtype);
2538
2539                         bus_dmamap_sync(rxr->rx_tag, rxbuf->map,
2540                             BUS_DMASYNC_POSTREAD);
2541
2542                         if (igb_newbuf(rxr, i, FALSE) != 0) {
2543                                 ifp->if_iqdrops++;
2544                                 goto discard;
2545                         }
2546
2547                         mp->m_len = len;
2548                         if (rxr->fmp == NULL) {
2549                                 mp->m_pkthdr.len = len;
2550                                 rxr->fmp = mp;
2551                                 rxr->lmp = mp;
2552                         } else {
2553                                 rxr->lmp->m_next = mp;
2554                                 rxr->lmp = rxr->lmp->m_next;
2555                                 rxr->fmp->m_pkthdr.len += len;
2556                         }
2557
2558                         if (eop) {
2559                                 m = rxr->fmp;
2560                                 rxr->fmp = NULL;
2561                                 rxr->lmp = NULL;
2562
2563                                 m->m_pkthdr.rcvif = ifp;
2564                                 ifp->if_ipackets++;
2565
2566                                 if (ifp->if_capenable & IFCAP_RXCSUM)
2567                                         igb_rxcsum(staterr, m);
2568
2569                                 if (staterr & E1000_RXD_STAT_VP) {
2570                                         m->m_pkthdr.ether_vlantag = vlan;
2571                                         m->m_flags |= M_VLANTAG;
2572                                 }
2573
2574                                 if (ifp->if_capenable & IFCAP_RSS) {
2575                                         pi = igb_rssinfo(m, &pi0,
2576                                             hash, hashtype, staterr);
2577                                 }
2578 #ifdef IGB_RSS_DEBUG
2579                                 rxr->rx_packets++;
2580 #endif
2581                         }
2582                 } else {
2583                         ifp->if_ierrors++;
2584 discard:
2585                         igb_setup_rxdesc(cur, rxbuf);
2586                         if (!eop)
2587                                 rxr->discard = TRUE;
2588                         else
2589                                 rxr->discard = FALSE;
2590                         if (rxr->fmp != NULL) {
2591                                 m_freem(rxr->fmp);
2592                                 rxr->fmp = NULL;
2593                                 rxr->lmp = NULL;
2594                         }
2595                         m = NULL;
2596                 }
2597
2598                 if (m != NULL)
2599                         ether_input_pkt(ifp, m, pi);
2600
2601                 /* Advance our pointers to the next descriptor. */
2602                 if (++i == rxr->num_rx_desc)
2603                         i = 0;
2604
2605                 if (ncoll >= rxr->wreg_nsegs) {
2606                         igb_rx_refresh(rxr, i);
2607                         ncoll = 0;
2608                 }
2609
2610                 cur = &rxr->rx_base[i];
2611                 staterr = le32toh(cur->wb.upper.status_error);
2612         }
2613         rxr->next_to_check = i;
2614
2615         if (ncoll > 0)
2616                 igb_rx_refresh(rxr, i);
2617 }
2618
2619
2620 static void
2621 igb_set_vlan(struct igb_softc *sc)
2622 {
2623         struct e1000_hw *hw = &sc->hw;
2624         uint32_t reg;
2625 #if 0
2626         struct ifnet *ifp = sc->arpcom.ac_if;
2627 #endif
2628
2629         if (sc->vf_ifp) {
2630                 e1000_rlpml_set_vf(hw, sc->max_frame_size + VLAN_TAG_SIZE);
2631                 return;
2632         }
2633
2634         reg = E1000_READ_REG(hw, E1000_CTRL);
2635         reg |= E1000_CTRL_VME;
2636         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2637
2638 #if 0
2639         /* Enable the Filter Table */
2640         if (ifp->if_capenable & IFCAP_VLAN_HWFILTER) {
2641                 reg = E1000_READ_REG(hw, E1000_RCTL);
2642                 reg &= ~E1000_RCTL_CFIEN;
2643                 reg |= E1000_RCTL_VFE;
2644                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2645         }
2646 #endif
2647
2648         /* Update the frame size */
2649         E1000_WRITE_REG(&sc->hw, E1000_RLPML,
2650             sc->max_frame_size + VLAN_TAG_SIZE);
2651
2652 #if 0
2653         /* Don't bother with table if no vlans */
2654         if ((adapter->num_vlans == 0) ||
2655             ((ifp->if_capenable & IFCAP_VLAN_HWFILTER) == 0))
2656                 return;
2657         /*
2658         ** A soft reset zero's out the VFTA, so
2659         ** we need to repopulate it now.
2660         */
2661         for (int i = 0; i < IGB_VFTA_SIZE; i++)
2662                 if (adapter->shadow_vfta[i] != 0) {
2663                         if (adapter->vf_ifp)
2664                                 e1000_vfta_set_vf(hw,
2665                                     adapter->shadow_vfta[i], TRUE);
2666                         else
2667                                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,
2668                                  i, adapter->shadow_vfta[i]);
2669                 }
2670 #endif
2671 }
2672
2673 static void
2674 igb_enable_intr(struct igb_softc *sc)
2675 {
2676         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
2677                 lwkt_serialize_handler_enable(&sc->main_serialize);
2678         } else {
2679                 int i;
2680
2681                 for (i = 0; i < sc->msix_cnt; ++i) {
2682                         lwkt_serialize_handler_enable(
2683                             sc->msix_data[i].msix_serialize);
2684                 }
2685         }
2686
2687         if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
2688                 if (sc->intr_type == PCI_INTR_TYPE_MSIX)
2689                         E1000_WRITE_REG(&sc->hw, E1000_EIAC, sc->intr_mask);
2690                 else
2691                         E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2692                 E1000_WRITE_REG(&sc->hw, E1000_EIAM, sc->intr_mask);
2693                 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
2694                 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC);
2695         } else {
2696                 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
2697         }
2698         E1000_WRITE_FLUSH(&sc->hw);
2699 }
2700
2701 static void
2702 igb_disable_intr(struct igb_softc *sc)
2703 {
2704         if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
2705                 E1000_WRITE_REG(&sc->hw, E1000_EIMC, 0xffffffff);
2706                 E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2707         }
2708         E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
2709         E1000_WRITE_FLUSH(&sc->hw);
2710
2711         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
2712                 lwkt_serialize_handler_disable(&sc->main_serialize);
2713         } else {
2714                 int i;
2715
2716                 for (i = 0; i < sc->msix_cnt; ++i) {
2717                         lwkt_serialize_handler_disable(
2718                             sc->msix_data[i].msix_serialize);
2719                 }
2720         }
2721 }
2722
2723 /*
2724  * Bit of a misnomer, what this really means is
2725  * to enable OS management of the system... aka
2726  * to disable special hardware management features
2727  */
2728 static void
2729 igb_get_mgmt(struct igb_softc *sc)
2730 {
2731         if (sc->flags & IGB_FLAG_HAS_MGMT) {
2732                 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
2733                 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2734
2735                 /* disable hardware interception of ARP */
2736                 manc &= ~E1000_MANC_ARP_EN;
2737
2738                 /* enable receiving management packets to the host */
2739                 manc |= E1000_MANC_EN_MNG2HOST;
2740                 manc2h |= 1 << 5; /* Mng Port 623 */
2741                 manc2h |= 1 << 6; /* Mng Port 664 */
2742                 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
2743                 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2744         }
2745 }
2746
2747 /*
2748  * Give control back to hardware management controller
2749  * if there is one.
2750  */
2751 static void
2752 igb_rel_mgmt(struct igb_softc *sc)
2753 {
2754         if (sc->flags & IGB_FLAG_HAS_MGMT) {
2755                 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2756
2757                 /* Re-enable hardware interception of ARP */
2758                 manc |= E1000_MANC_ARP_EN;
2759                 manc &= ~E1000_MANC_EN_MNG2HOST;
2760
2761                 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2762         }
2763 }
2764
2765 /*
2766  * Sets CTRL_EXT:DRV_LOAD bit.
2767  *
2768  * For ASF and Pass Through versions of f/w this means that
2769  * the driver is loaded.
2770  */
2771 static void
2772 igb_get_hw_control(struct igb_softc *sc)
2773 {
2774         uint32_t ctrl_ext;
2775
2776         if (sc->vf_ifp)
2777                 return;
2778
2779         /* Let firmware know the driver has taken over */
2780         ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2781         E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2782             ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2783 }
2784
2785 /*
2786  * Resets CTRL_EXT:DRV_LOAD bit.
2787  *
2788  * For ASF and Pass Through versions of f/w this means that the
2789  * driver is no longer loaded.
2790  */
2791 static void
2792 igb_rel_hw_control(struct igb_softc *sc)
2793 {
2794         uint32_t ctrl_ext;
2795
2796         if (sc->vf_ifp)
2797                 return;
2798
2799         /* Let firmware taken over control of h/w */
2800         ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2801         E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2802             ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2803 }
2804
2805 static int
2806 igb_is_valid_ether_addr(const uint8_t *addr)
2807 {
2808         uint8_t zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
2809
2810         if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
2811                 return FALSE;
2812         return TRUE;
2813 }
2814
2815 /*
2816  * Enable PCI Wake On Lan capability
2817  */
2818 static void
2819 igb_enable_wol(device_t dev)
2820 {
2821         uint16_t cap, status;
2822         uint8_t id;
2823
2824         /* First find the capabilities pointer*/
2825         cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
2826
2827         /* Read the PM Capabilities */
2828         id = pci_read_config(dev, cap, 1);
2829         if (id != PCIY_PMG)     /* Something wrong */
2830                 return;
2831
2832         /*
2833          * OK, we have the power capabilities,
2834          * so now get the status register
2835          */
2836         cap += PCIR_POWER_STATUS;
2837         status = pci_read_config(dev, cap, 2);
2838         status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2839         pci_write_config(dev, cap, status, 2);
2840 }
2841
2842 static void
2843 igb_update_stats_counters(struct igb_softc *sc)
2844 {
2845         struct e1000_hw *hw = &sc->hw;
2846         struct e1000_hw_stats *stats;
2847         struct ifnet *ifp = &sc->arpcom.ac_if;
2848
2849         /*
2850          * The virtual function adapter has only a
2851          * small controlled set of stats, do only
2852          * those and return.
2853          */
2854         if (sc->vf_ifp) {
2855                 igb_update_vf_stats_counters(sc);
2856                 return;
2857         }
2858         stats = sc->stats;
2859
2860         if (sc->hw.phy.media_type == e1000_media_type_copper ||
2861             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
2862                 stats->symerrs +=
2863                     E1000_READ_REG(hw,E1000_SYMERRS);
2864                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
2865         }
2866
2867         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
2868         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
2869         stats->scc += E1000_READ_REG(hw, E1000_SCC);
2870         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
2871
2872         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
2873         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
2874         stats->colc += E1000_READ_REG(hw, E1000_COLC);
2875         stats->dc += E1000_READ_REG(hw, E1000_DC);
2876         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
2877         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
2878         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
2879
2880         /*
2881          * For watchdog management we need to know if we have been
2882          * paused during the last interval, so capture that here.
2883          */
2884         sc->pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
2885         stats->xoffrxc += sc->pause_frames;
2886         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
2887         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
2888         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
2889         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
2890         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
2891         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
2892         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
2893         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
2894         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
2895         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
2896         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
2897         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
2898
2899         /* For the 64-bit byte counters the low dword must be read first. */
2900         /* Both registers clear on the read of the high dword */
2901
2902         stats->gorc += E1000_READ_REG(hw, E1000_GORCL) +
2903             ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
2904         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL) +
2905             ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
2906
2907         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
2908         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
2909         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
2910         stats->roc += E1000_READ_REG(hw, E1000_ROC);
2911         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
2912
2913         stats->tor += E1000_READ_REG(hw, E1000_TORH);
2914         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
2915
2916         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
2917         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
2918         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
2919         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
2920         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
2921         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
2922         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
2923         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
2924         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
2925         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
2926
2927         /* Interrupt Counts */
2928
2929         stats->iac += E1000_READ_REG(hw, E1000_IAC);
2930         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
2931         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
2932         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
2933         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
2934         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
2935         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
2936         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
2937         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
2938
2939         /* Host to Card Statistics */
2940
2941         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
2942         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
2943         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
2944         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
2945         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
2946         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
2947         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
2948         stats->hgorc += (E1000_READ_REG(hw, E1000_HGORCL) +
2949             ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32));
2950         stats->hgotc += (E1000_READ_REG(hw, E1000_HGOTCL) +
2951             ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32));
2952         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
2953         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
2954         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
2955
2956         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
2957         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
2958         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
2959         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
2960         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
2961         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
2962
2963         ifp->if_collisions = stats->colc;
2964
2965         /* Rx Errors */
2966         ifp->if_ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
2967             stats->ruc + stats->roc + stats->mpc + stats->cexterr;
2968
2969         /* Tx Errors */
2970         ifp->if_oerrors = stats->ecol + stats->latecol + sc->watchdog_events;
2971
2972         /* Driver specific counters */
2973         sc->device_control = E1000_READ_REG(hw, E1000_CTRL);
2974         sc->rx_control = E1000_READ_REG(hw, E1000_RCTL);
2975         sc->int_mask = E1000_READ_REG(hw, E1000_IMS);
2976         sc->eint_mask = E1000_READ_REG(hw, E1000_EIMS);
2977         sc->packet_buf_alloc_tx =
2978             ((E1000_READ_REG(hw, E1000_PBA) & 0xffff0000) >> 16);
2979         sc->packet_buf_alloc_rx =
2980             (E1000_READ_REG(hw, E1000_PBA) & 0xffff);
2981 }
2982
2983 static void
2984 igb_vf_init_stats(struct igb_softc *sc)
2985 {
2986         struct e1000_hw *hw = &sc->hw;
2987         struct e1000_vf_stats *stats;
2988
2989         stats = sc->stats;
2990         stats->last_gprc = E1000_READ_REG(hw, E1000_VFGPRC);
2991         stats->last_gorc = E1000_READ_REG(hw, E1000_VFGORC);
2992         stats->last_gptc = E1000_READ_REG(hw, E1000_VFGPTC);
2993         stats->last_gotc = E1000_READ_REG(hw, E1000_VFGOTC);
2994         stats->last_mprc = E1000_READ_REG(hw, E1000_VFMPRC);
2995 }
2996
2997 static void
2998 igb_update_vf_stats_counters(struct igb_softc *sc)
2999 {
3000         struct e1000_hw *hw = &sc->hw;
3001         struct e1000_vf_stats *stats;
3002
3003         if (sc->link_speed == 0)
3004                 return;
3005
3006         stats = sc->stats;
3007         UPDATE_VF_REG(E1000_VFGPRC, stats->last_gprc, stats->gprc);
3008         UPDATE_VF_REG(E1000_VFGORC, stats->last_gorc, stats->gorc);
3009         UPDATE_VF_REG(E1000_VFGPTC, stats->last_gptc, stats->gptc);
3010         UPDATE_VF_REG(E1000_VFGOTC, stats->last_gotc, stats->gotc);
3011         UPDATE_VF_REG(E1000_VFMPRC, stats->last_mprc, stats->mprc);
3012 }
3013
3014 #ifdef IFPOLL_ENABLE
3015
3016 static void
3017 igb_npoll_status(struct ifnet *ifp)
3018 {
3019         struct igb_softc *sc = ifp->if_softc;
3020         uint32_t reg_icr;
3021
3022         ASSERT_SERIALIZED(&sc->main_serialize);
3023
3024         reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3025         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3026                 sc->hw.mac.get_link_status = 1;
3027                 igb_update_link_status(sc);
3028         }
3029 }
3030
3031 static void
3032 igb_npoll_tx(struct ifnet *ifp, void *arg, int cycle __unused)
3033 {
3034         struct igb_tx_ring *txr = arg;
3035
3036         ASSERT_SERIALIZED(&txr->tx_serialize);
3037
3038         igb_txeof(txr);
3039         if (!ifsq_is_empty(txr->ifsq))
3040                 ifsq_devstart(txr->ifsq);
3041 }
3042
3043 static void
3044 igb_npoll_rx(struct ifnet *ifp __unused, void *arg, int cycle)
3045 {
3046         struct igb_rx_ring *rxr = arg;
3047
3048         ASSERT_SERIALIZED(&rxr->rx_serialize);
3049
3050         igb_rxeof(rxr, cycle);
3051 }
3052
3053 static void
3054 igb_npoll(struct ifnet *ifp, struct ifpoll_info *info)
3055 {
3056         struct igb_softc *sc = ifp->if_softc;
3057         int i, txr_cnt, rxr_cnt;
3058
3059         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3060
3061         if (info) {
3062                 int off;
3063
3064                 info->ifpi_status.status_func = igb_npoll_status;
3065                 info->ifpi_status.serializer = &sc->main_serialize;
3066
3067                 txr_cnt = igb_get_txring_inuse(sc, TRUE);
3068                 off = sc->tx_npoll_off;
3069                 for (i = 0; i < txr_cnt; ++i) {
3070                         struct igb_tx_ring *txr = &sc->tx_rings[i];
3071                         int idx = i + off;
3072
3073                         KKASSERT(idx < ncpus2);
3074                         info->ifpi_tx[idx].poll_func = igb_npoll_tx;
3075                         info->ifpi_tx[idx].arg = txr;
3076                         info->ifpi_tx[idx].serializer = &txr->tx_serialize;
3077                         ifsq_set_cpuid(txr->ifsq, idx);
3078                 }
3079
3080                 rxr_cnt = igb_get_rxring_inuse(sc, TRUE);
3081                 off = sc->rx_npoll_off;
3082                 for (i = 0; i < rxr_cnt; ++i) {
3083                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
3084                         int idx = i + off;
3085
3086                         KKASSERT(idx < ncpus2);
3087                         info->ifpi_rx[idx].poll_func = igb_npoll_rx;
3088                         info->ifpi_rx[idx].arg = rxr;
3089                         info->ifpi_rx[idx].serializer = &rxr->rx_serialize;
3090                 }
3091
3092                 if (ifp->if_flags & IFF_RUNNING) {
3093                         if (rxr_cnt == sc->rx_ring_inuse &&
3094                             txr_cnt == sc->tx_ring_inuse)
3095                                 igb_disable_intr(sc);
3096                         else
3097                                 igb_init(sc);
3098                 }
3099         } else {
3100                 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3101                         struct igb_tx_ring *txr = &sc->tx_rings[i];
3102
3103                         ifsq_set_cpuid(txr->ifsq, txr->tx_intr_cpuid);
3104                 }
3105
3106                 if (ifp->if_flags & IFF_RUNNING) {
3107                         txr_cnt = igb_get_txring_inuse(sc, FALSE);
3108                         rxr_cnt = igb_get_rxring_inuse(sc, FALSE);
3109
3110                         if (rxr_cnt == sc->rx_ring_inuse &&
3111                             txr_cnt == sc->tx_ring_inuse)
3112                                 igb_enable_intr(sc);
3113                         else
3114                                 igb_init(sc);
3115                 }
3116         }
3117 }
3118
3119 #endif /* IFPOLL_ENABLE */
3120
3121 static void
3122 igb_intr(void *xsc)
3123 {
3124         struct igb_softc *sc = xsc;
3125         struct ifnet *ifp = &sc->arpcom.ac_if;
3126         uint32_t eicr;
3127
3128         ASSERT_SERIALIZED(&sc->main_serialize);
3129
3130         eicr = E1000_READ_REG(&sc->hw, E1000_EICR);
3131
3132         if (eicr == 0)
3133                 return;
3134
3135         if (ifp->if_flags & IFF_RUNNING) {
3136                 struct igb_tx_ring *txr = &sc->tx_rings[0];
3137                 int i;
3138
3139                 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3140                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
3141
3142                         if (eicr & rxr->rx_intr_mask) {
3143                                 lwkt_serialize_enter(&rxr->rx_serialize);
3144                                 igb_rxeof(rxr, -1);
3145                                 lwkt_serialize_exit(&rxr->rx_serialize);
3146                         }
3147                 }
3148
3149                 if (eicr & txr->tx_intr_mask) {
3150                         lwkt_serialize_enter(&txr->tx_serialize);
3151                         igb_txeof(txr);
3152                         if (!ifsq_is_empty(txr->ifsq))
3153                                 ifsq_devstart(txr->ifsq);
3154                         lwkt_serialize_exit(&txr->tx_serialize);
3155                 }
3156         }
3157
3158         if (eicr & E1000_EICR_OTHER) {
3159                 uint32_t icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3160
3161                 /* Link status change */
3162                 if (icr & E1000_ICR_LSC) {
3163                         sc->hw.mac.get_link_status = 1;
3164                         igb_update_link_status(sc);
3165                 }
3166         }
3167
3168         /*
3169          * Reading EICR has the side effect to clear interrupt mask,
3170          * so all interrupts need to be enabled here.
3171          */
3172         E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
3173 }
3174
3175 static void
3176 igb_intr_shared(void *xsc)
3177 {
3178         struct igb_softc *sc = xsc;
3179         struct ifnet *ifp = &sc->arpcom.ac_if;
3180         uint32_t reg_icr;
3181
3182         ASSERT_SERIALIZED(&sc->main_serialize);
3183
3184         reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3185
3186         /* Hot eject?  */
3187         if (reg_icr == 0xffffffff)
3188                 return;
3189
3190         /* Definitely not our interrupt.  */
3191         if (reg_icr == 0x0)
3192                 return;
3193
3194         if ((reg_icr & E1000_ICR_INT_ASSERTED) == 0)
3195                 return;
3196
3197         if (ifp->if_flags & IFF_RUNNING) {
3198                 if (reg_icr &
3199                     (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
3200                         int i;
3201
3202                         for (i = 0; i < sc->rx_ring_inuse; ++i) {
3203                                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
3204
3205                                 lwkt_serialize_enter(&rxr->rx_serialize);
3206                                 igb_rxeof(rxr, -1);
3207                                 lwkt_serialize_exit(&rxr->rx_serialize);
3208                         }
3209                 }
3210
3211                 if (reg_icr & E1000_ICR_TXDW) {
3212                         struct igb_tx_ring *txr = &sc->tx_rings[0];
3213
3214                         lwkt_serialize_enter(&txr->tx_serialize);
3215                         igb_txeof(txr);
3216                         if (!ifsq_is_empty(txr->ifsq))
3217                                 ifsq_devstart(txr->ifsq);
3218                         lwkt_serialize_exit(&txr->tx_serialize);
3219                 }
3220         }
3221
3222         /* Link status change */
3223         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3224                 sc->hw.mac.get_link_status = 1;
3225                 igb_update_link_status(sc);
3226         }
3227
3228         if (reg_icr & E1000_ICR_RXO)
3229                 sc->rx_overruns++;
3230 }
3231
3232 static int
3233 igb_encap(struct igb_tx_ring *txr, struct mbuf **m_headp,
3234     int *segs_used, int *idx)
3235 {
3236         bus_dma_segment_t segs[IGB_MAX_SCATTER];
3237         bus_dmamap_t map;
3238         struct igb_tx_buf *tx_buf, *tx_buf_mapped;
3239         union e1000_adv_tx_desc *txd = NULL;
3240         struct mbuf *m_head = *m_headp;
3241         uint32_t olinfo_status = 0, cmd_type_len = 0, cmd_rs = 0;
3242         int maxsegs, nsegs, i, j, error;
3243         uint32_t hdrlen = 0;
3244
3245         if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3246                 error = igb_tso_pullup(txr, m_headp);
3247                 if (error)
3248                         return error;
3249                 m_head = *m_headp;
3250         }
3251
3252         /* Set basic descriptor constants */
3253         cmd_type_len |= E1000_ADVTXD_DTYP_DATA;
3254         cmd_type_len |= E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT;
3255         if (m_head->m_flags & M_VLANTAG)
3256                 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3257
3258         /*
3259          * Map the packet for DMA.
3260          */
3261         tx_buf = &txr->tx_buf[txr->next_avail_desc];
3262         tx_buf_mapped = tx_buf;
3263         map = tx_buf->map;
3264
3265         maxsegs = txr->tx_avail - IGB_TX_RESERVED;
3266         KASSERT(maxsegs >= txr->spare_desc, ("not enough spare TX desc\n"));
3267         if (maxsegs > IGB_MAX_SCATTER)
3268                 maxsegs = IGB_MAX_SCATTER;
3269
3270         error = bus_dmamap_load_mbuf_defrag(txr->tx_tag, map, m_headp,
3271             segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
3272         if (error) {
3273                 if (error == ENOBUFS)
3274                         txr->sc->mbuf_defrag_failed++;
3275                 else
3276                         txr->sc->no_tx_dma_setup++;
3277
3278                 m_freem(*m_headp);
3279                 *m_headp = NULL;
3280                 return error;
3281         }
3282         bus_dmamap_sync(txr->tx_tag, map, BUS_DMASYNC_PREWRITE);
3283
3284         m_head = *m_headp;
3285
3286         /*
3287          * Set up the TX context descriptor, if any hardware offloading is
3288          * needed.  This includes CSUM, VLAN, and TSO.  It will consume one
3289          * TX descriptor.
3290          *
3291          * Unlike these chips' predecessors (em/emx), TX context descriptor
3292          * will _not_ interfere TX data fetching pipelining.
3293          */
3294         if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3295                 igb_tso_ctx(txr, m_head, &hdrlen);
3296                 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3297                 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3298                 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3299                 txr->tx_nsegs++;
3300                 (*segs_used)++;
3301         } else if (igb_txcsum_ctx(txr, m_head)) {
3302                 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
3303                         olinfo_status |= (E1000_TXD_POPTS_IXSM << 8);
3304                 if (m_head->m_pkthdr.csum_flags & (CSUM_UDP | CSUM_TCP))
3305                         olinfo_status |= (E1000_TXD_POPTS_TXSM << 8);
3306                 txr->tx_nsegs++;
3307                 (*segs_used)++;
3308         }
3309
3310         *segs_used += nsegs;
3311         txr->tx_nsegs += nsegs;
3312         if (txr->tx_nsegs >= txr->intr_nsegs) {
3313                 /*
3314                  * Report Status (RS) is turned on every intr_nsegs
3315                  * descriptors (roughly).
3316                  */
3317                 txr->tx_nsegs = 0;
3318                 cmd_rs = E1000_ADVTXD_DCMD_RS;
3319         }
3320
3321         /* Calculate payload length */
3322         olinfo_status |= ((m_head->m_pkthdr.len - hdrlen)
3323             << E1000_ADVTXD_PAYLEN_SHIFT);
3324
3325         /* 82575 needs the queue index added */
3326         if (txr->sc->hw.mac.type == e1000_82575)
3327                 olinfo_status |= txr->me << 4;
3328
3329         /* Set up our transmit descriptors */
3330         i = txr->next_avail_desc;
3331         for (j = 0; j < nsegs; j++) {
3332                 bus_size_t seg_len;
3333                 bus_addr_t seg_addr;
3334
3335                 tx_buf = &txr->tx_buf[i];
3336                 txd = (union e1000_adv_tx_desc *)&txr->tx_base[i];
3337                 seg_addr = segs[j].ds_addr;
3338                 seg_len = segs[j].ds_len;
3339
3340                 txd->read.buffer_addr = htole64(seg_addr);
3341                 txd->read.cmd_type_len = htole32(cmd_type_len | seg_len);
3342                 txd->read.olinfo_status = htole32(olinfo_status);
3343                 if (++i == txr->num_tx_desc)
3344                         i = 0;
3345                 tx_buf->m_head = NULL;
3346         }
3347
3348         KASSERT(txr->tx_avail > nsegs, ("invalid avail TX desc\n"));
3349         txr->next_avail_desc = i;
3350         txr->tx_avail -= nsegs;
3351
3352         tx_buf->m_head = m_head;
3353         tx_buf_mapped->map = tx_buf->map;
3354         tx_buf->map = map;
3355
3356         /*
3357          * Last Descriptor of Packet needs End Of Packet (EOP)
3358          */
3359         txd->read.cmd_type_len |= htole32(E1000_ADVTXD_DCMD_EOP | cmd_rs);
3360
3361         /*
3362          * Defer TDT updating, until enough descrptors are setup
3363          */
3364         *idx = i;
3365 #ifdef IGB_TSS_DEBUG
3366         ++txr->tx_packets;
3367 #endif
3368
3369         return 0;
3370 }
3371
3372 static void
3373 igb_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
3374 {
3375         struct igb_softc *sc = ifp->if_softc;
3376         struct igb_tx_ring *txr = ifsq_get_priv(ifsq);
3377         struct mbuf *m_head;
3378         int idx = -1, nsegs = 0;
3379
3380         KKASSERT(txr->ifsq == ifsq);
3381         ASSERT_SERIALIZED(&txr->tx_serialize);
3382
3383         if ((ifp->if_flags & IFF_RUNNING) == 0 || ifsq_is_oactive(ifsq))
3384                 return;
3385
3386         if (!sc->link_active || (txr->tx_flags & IGB_TXFLAG_ENABLED) == 0) {
3387                 ifsq_purge(ifsq);
3388                 return;
3389         }
3390
3391         if (!IGB_IS_NOT_OACTIVE(txr))
3392                 igb_txeof(txr);
3393
3394         while (!ifsq_is_empty(ifsq)) {
3395                 if (IGB_IS_OACTIVE(txr)) {
3396                         ifsq_set_oactive(ifsq);
3397                         /* Set watchdog on */
3398                         txr->tx_watchdog.wd_timer = 5;
3399                         break;
3400                 }
3401
3402                 m_head = ifsq_dequeue(ifsq, NULL);
3403                 if (m_head == NULL)
3404                         break;
3405
3406                 if (igb_encap(txr, &m_head, &nsegs, &idx)) {
3407                         ifp->if_oerrors++;
3408                         continue;
3409                 }
3410
3411                 if (nsegs >= txr->wreg_nsegs) {
3412                         E1000_WRITE_REG(&txr->sc->hw, E1000_TDT(txr->me), idx);
3413                         idx = -1;
3414                         nsegs = 0;
3415                 }
3416
3417                 /* Send a copy of the frame to the BPF listener */
3418                 ETHER_BPF_MTAP(ifp, m_head);
3419         }
3420         if (idx >= 0)
3421                 E1000_WRITE_REG(&txr->sc->hw, E1000_TDT(txr->me), idx);
3422 }
3423
3424 static void
3425 igb_watchdog(struct ifaltq_subque *ifsq)
3426 {
3427         struct igb_tx_ring *txr = ifsq_get_priv(ifsq);
3428         struct ifnet *ifp = ifsq_get_ifp(ifsq);
3429         struct igb_softc *sc = ifp->if_softc;
3430         int i;
3431
3432         KKASSERT(txr->ifsq == ifsq);
3433         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3434
3435         /*
3436          * If flow control has paused us since last checking
3437          * it invalidates the watchdog timing, so dont run it.
3438          */
3439         if (sc->pause_frames) {
3440                 sc->pause_frames = 0;
3441                 txr->tx_watchdog.wd_timer = 5;
3442                 return;
3443         }
3444
3445         if_printf(ifp, "Watchdog timeout -- resetting\n");
3446         if_printf(ifp, "Queue(%d) tdh = %d, hw tdt = %d\n", txr->me,
3447             E1000_READ_REG(&sc->hw, E1000_TDH(txr->me)),
3448             E1000_READ_REG(&sc->hw, E1000_TDT(txr->me)));
3449         if_printf(ifp, "TX(%d) desc avail = %d, "
3450             "Next TX to Clean = %d\n",
3451             txr->me, txr->tx_avail, txr->next_to_clean);
3452
3453         ifp->if_oerrors++;
3454         sc->watchdog_events++;
3455
3456         igb_init(sc);
3457         for (i = 0; i < sc->tx_ring_inuse; ++i)
3458                 ifsq_devstart_sched(sc->tx_rings[i].ifsq);
3459 }
3460
3461 static void
3462 igb_set_eitr(struct igb_softc *sc, int idx, int rate)
3463 {
3464         uint32_t eitr = 0;
3465
3466         if (rate > 0) {
3467                 if (sc->hw.mac.type == e1000_82575) {
3468                         eitr = 1000000000 / 256 / rate;
3469                         /*
3470                          * NOTE:
3471                          * Document is wrong on the 2 bits left shift
3472                          */
3473                 } else {
3474                         eitr = 1000000 / rate;
3475                         eitr <<= IGB_EITR_INTVL_SHIFT;
3476                 }
3477
3478                 if (eitr == 0) {
3479                         /* Don't disable it */
3480                         eitr = 1 << IGB_EITR_INTVL_SHIFT;
3481                 } else if (eitr > IGB_EITR_INTVL_MASK) {
3482                         /* Don't allow it to be too large */
3483                         eitr = IGB_EITR_INTVL_MASK;
3484                 }
3485         }
3486         if (sc->hw.mac.type == e1000_82575)
3487                 eitr |= eitr << 16;
3488         else
3489                 eitr |= E1000_EITR_CNT_IGNR;
3490         E1000_WRITE_REG(&sc->hw, E1000_EITR(idx), eitr);
3491 }
3492
3493 static int
3494 igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS)
3495 {
3496         struct igb_softc *sc = (void *)arg1;
3497         struct ifnet *ifp = &sc->arpcom.ac_if;
3498         int error, intr_rate;
3499
3500         intr_rate = sc->intr_rate;
3501         error = sysctl_handle_int(oidp, &intr_rate, 0, req);
3502         if (error || req->newptr == NULL)
3503                 return error;
3504         if (intr_rate < 0)
3505                 return EINVAL;
3506
3507         ifnet_serialize_all(ifp);
3508
3509         sc->intr_rate = intr_rate;
3510         if (ifp->if_flags & IFF_RUNNING)
3511                 igb_set_eitr(sc, 0, sc->intr_rate);
3512
3513         if (bootverbose)
3514                 if_printf(ifp, "interrupt rate set to %d/sec\n", sc->intr_rate);
3515
3516         ifnet_deserialize_all(ifp);
3517
3518         return 0;
3519 }
3520
3521 static int
3522 igb_sysctl_msix_rate(SYSCTL_HANDLER_ARGS)
3523 {
3524         struct igb_msix_data *msix = (void *)arg1;
3525         struct igb_softc *sc = msix->msix_sc;
3526         struct ifnet *ifp = &sc->arpcom.ac_if;
3527         int error, msix_rate;
3528
3529         msix_rate = msix->msix_rate;
3530         error = sysctl_handle_int(oidp, &msix_rate, 0, req);
3531         if (error || req->newptr == NULL)
3532                 return error;
3533         if (msix_rate < 0)
3534                 return EINVAL;
3535
3536         lwkt_serialize_enter(msix->msix_serialize);
3537
3538         msix->msix_rate = msix_rate;
3539         if (ifp->if_flags & IFF_RUNNING)
3540                 igb_set_eitr(sc, msix->msix_vector, msix->msix_rate);
3541
3542         if (bootverbose) {
3543                 if_printf(ifp, "%s set to %d/sec\n", msix->msix_rate_desc,
3544                     msix->msix_rate);
3545         }
3546
3547         lwkt_serialize_exit(msix->msix_serialize);
3548
3549         return 0;
3550 }
3551
3552 static int
3553 igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS)
3554 {
3555         struct igb_softc *sc = (void *)arg1;
3556         struct ifnet *ifp = &sc->arpcom.ac_if;
3557         struct igb_tx_ring *txr = &sc->tx_rings[0];
3558         int error, nsegs;
3559
3560         nsegs = txr->intr_nsegs;
3561         error = sysctl_handle_int(oidp, &nsegs, 0, req);
3562         if (error || req->newptr == NULL)
3563                 return error;
3564         if (nsegs <= 0)
3565                 return EINVAL;
3566
3567         ifnet_serialize_all(ifp);
3568
3569         if (nsegs >= txr->num_tx_desc - txr->oact_lo_desc ||
3570             nsegs >= txr->oact_hi_desc - IGB_MAX_SCATTER) {
3571                 error = EINVAL;
3572         } else {
3573                 int i;
3574
3575                 error = 0;
3576                 for (i = 0; i < sc->tx_ring_cnt; ++i)
3577                         sc->tx_rings[i].intr_nsegs = nsegs;
3578         }
3579
3580         ifnet_deserialize_all(ifp);
3581
3582         return error;
3583 }
3584
3585 static int
3586 igb_sysctl_rx_wreg_nsegs(SYSCTL_HANDLER_ARGS)
3587 {
3588         struct igb_softc *sc = (void *)arg1;
3589         struct ifnet *ifp = &sc->arpcom.ac_if;
3590         int error, nsegs, i;
3591
3592         nsegs = sc->rx_rings[0].wreg_nsegs;
3593         error = sysctl_handle_int(oidp, &nsegs, 0, req);
3594         if (error || req->newptr == NULL)
3595                 return error;
3596
3597         ifnet_serialize_all(ifp);
3598         for (i = 0; i < sc->rx_ring_cnt; ++i)
3599                 sc->rx_rings[i].wreg_nsegs =nsegs;
3600         ifnet_deserialize_all(ifp);
3601
3602         return 0;
3603 }
3604
3605 static int
3606 igb_sysctl_tx_wreg_nsegs(SYSCTL_HANDLER_ARGS)
3607 {
3608         struct igb_softc *sc = (void *)arg1;
3609         struct ifnet *ifp = &sc->arpcom.ac_if;
3610         int error, nsegs, i;
3611
3612         nsegs = sc->tx_rings[0].wreg_nsegs;
3613         error = sysctl_handle_int(oidp, &nsegs, 0, req);
3614         if (error || req->newptr == NULL)
3615                 return error;
3616
3617         ifnet_serialize_all(ifp);
3618         for (i = 0; i < sc->tx_ring_cnt; ++i)
3619                 sc->tx_rings[i].wreg_nsegs =nsegs;
3620         ifnet_deserialize_all(ifp);
3621
3622         return 0;
3623 }
3624
3625 #ifdef IFPOLL_ENABLE
3626
3627 static int
3628 igb_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS)
3629 {
3630         struct igb_softc *sc = (void *)arg1;
3631         struct ifnet *ifp = &sc->arpcom.ac_if;
3632         int error, off;
3633
3634         off = sc->rx_npoll_off;
3635         error = sysctl_handle_int(oidp, &off, 0, req);
3636         if (error || req->newptr == NULL)
3637                 return error;
3638         if (off < 0)
3639                 return EINVAL;
3640
3641         ifnet_serialize_all(ifp);
3642         if (off >= ncpus2 || off % sc->rx_ring_cnt != 0) {
3643                 error = EINVAL;
3644         } else {
3645                 error = 0;
3646                 sc->rx_npoll_off = off;
3647         }
3648         ifnet_deserialize_all(ifp);
3649
3650         return error;
3651 }
3652
3653 static int
3654 igb_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS)
3655 {
3656         struct igb_softc *sc = (void *)arg1;
3657         struct ifnet *ifp = &sc->arpcom.ac_if;
3658         int error, off;
3659
3660         off = sc->tx_npoll_off;
3661         error = sysctl_handle_int(oidp, &off, 0, req);
3662         if (error || req->newptr == NULL)
3663                 return error;
3664         if (off < 0)
3665                 return EINVAL;
3666
3667         ifnet_serialize_all(ifp);
3668         if (off >= ncpus2 || off % sc->tx_ring_cnt != 0) {
3669                 error = EINVAL;
3670         } else {
3671                 error = 0;
3672                 sc->tx_npoll_off = off;
3673         }
3674         ifnet_deserialize_all(ifp);
3675
3676         return error;
3677 }
3678
3679 #endif  /* IFPOLL_ENABLE */
3680
3681 static void
3682 igb_init_intr(struct igb_softc *sc)
3683 {
3684         igb_set_intr_mask(sc);
3685
3686         if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0)
3687                 igb_init_unshared_intr(sc);
3688
3689         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
3690                 igb_set_eitr(sc, 0, sc->intr_rate);
3691         } else {
3692                 int i;
3693
3694                 for (i = 0; i < sc->msix_cnt; ++i)
3695                         igb_set_eitr(sc, i, sc->msix_data[i].msix_rate);
3696         }
3697 }
3698
3699 static void
3700 igb_init_unshared_intr(struct igb_softc *sc)
3701 {
3702         struct e1000_hw *hw = &sc->hw;
3703         const struct igb_rx_ring *rxr;
3704         const struct igb_tx_ring *txr;
3705         uint32_t ivar, index;
3706         int i;
3707
3708         /*
3709          * Enable extended mode
3710          */
3711         if (sc->hw.mac.type != e1000_82575) {
3712                 uint32_t gpie;
3713                 int ivar_max;
3714
3715                 gpie = E1000_GPIE_NSICR;
3716                 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3717                         gpie |= E1000_GPIE_MSIX_MODE |
3718                             E1000_GPIE_EIAME |
3719                             E1000_GPIE_PBA;
3720                 }
3721                 E1000_WRITE_REG(hw, E1000_GPIE, gpie);
3722
3723                 /*
3724                  * Clear IVARs
3725                  */
3726                 switch (sc->hw.mac.type) {
3727                 case e1000_82580:
3728                         ivar_max = IGB_MAX_IVAR_82580;
3729                         break;
3730
3731                 case e1000_i350:
3732                         ivar_max = IGB_MAX_IVAR_I350;
3733                         break;
3734
3735                 case e1000_vfadapt:
3736                 case e1000_vfadapt_i350:
3737                         ivar_max = IGB_MAX_IVAR_VF;
3738                         break;
3739
3740                 case e1000_82576:
3741                         ivar_max = IGB_MAX_IVAR_82576;
3742                         break;
3743
3744                 default:
3745                         panic("unknown mac type %d\n", sc->hw.mac.type);
3746                 }
3747                 for (i = 0; i < ivar_max; ++i)
3748                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, 0);
3749                 E1000_WRITE_REG(hw, E1000_IVAR_MISC, 0);
3750         } else {
3751                 uint32_t tmp;
3752
3753                 KASSERT(sc->intr_type != PCI_INTR_TYPE_MSIX,
3754                     ("82575 w/ MSI-X"));
3755                 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
3756                 tmp |= E1000_CTRL_EXT_IRCA;
3757                 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
3758         }
3759
3760         /*
3761          * Map TX/RX interrupts to EICR
3762          */
3763         switch (sc->hw.mac.type) {
3764         case e1000_82580:
3765         case e1000_i350:
3766         case e1000_vfadapt:
3767         case e1000_vfadapt_i350:
3768                 /* RX entries */
3769                 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3770                         rxr = &sc->rx_rings[i];
3771
3772                         index = i >> 1;
3773                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3774
3775                         if (i & 1) {
3776                                 ivar &= 0xff00ffff;
3777                                 ivar |=
3778                                 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3779                         } else {
3780                                 ivar &= 0xffffff00;
3781                                 ivar |=
3782                                 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3783                         }
3784                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3785                 }
3786                 /* TX entries */
3787                 for (i = 0; i < sc->tx_ring_inuse; ++i) {
3788                         txr = &sc->tx_rings[i];
3789
3790                         index = i >> 1;
3791                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3792
3793                         if (i & 1) {
3794                                 ivar &= 0x00ffffff;
3795                                 ivar |=
3796                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3797                         } else {
3798                                 ivar &= 0xffff00ff;
3799                                 ivar |=
3800                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3801                         }
3802                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3803                 }
3804                 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3805                         ivar = (sc->sts_intr_bit | E1000_IVAR_VALID) << 8;
3806                         E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
3807                 }
3808                 break;
3809
3810         case e1000_82576:
3811                 /* RX entries */
3812                 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3813                         rxr = &sc->rx_rings[i];
3814
3815                         index = i & 0x7; /* Each IVAR has two entries */
3816                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3817
3818                         if (i < 8) {
3819                                 ivar &= 0xffffff00;
3820                                 ivar |=
3821                                 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3822                         } else {
3823                                 ivar &= 0xff00ffff;
3824                                 ivar |=
3825                                 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3826                         }
3827                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3828                 }
3829                 /* TX entries */
3830                 for (i = 0; i < sc->tx_ring_inuse; ++i) {
3831                         txr = &sc->tx_rings[i];
3832
3833                         index = i & 0x7; /* Each IVAR has two entries */
3834                         ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3835
3836                         if (i < 8) {
3837                                 ivar &= 0xffff00ff;
3838                                 ivar |=
3839                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3840                         } else {
3841                                 ivar &= 0x00ffffff;
3842                                 ivar |=
3843                                 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3844                         }
3845                         E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3846                 }
3847                 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3848                         ivar = (sc->sts_intr_bit | E1000_IVAR_VALID) << 8;
3849                         E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
3850                 }
3851                 break;
3852
3853         case e1000_82575:
3854                 /*
3855                  * Enable necessary interrupt bits.
3856                  *
3857                  * The name of the register is confusing; in addition to
3858                  * configuring the first vector of MSI-X, it also configures
3859                  * which bits of EICR could be set by the hardware even when
3860                  * MSI or line interrupt is used; it thus controls interrupt
3861                  * generation.  It MUST be configured explicitly; the default
3862                  * value mentioned in the datasheet is wrong: RX queue0 and
3863                  * TX queue0 are NOT enabled by default.
3864                  */
3865                 E1000_WRITE_REG(&sc->hw, E1000_MSIXBM(0), sc->intr_mask);
3866                 break;
3867
3868         default:
3869                 panic("unknown mac type %d\n", sc->hw.mac.type);
3870         }
3871 }
3872
3873 static int
3874 igb_setup_intr(struct igb_softc *sc)
3875 {
3876         int error;
3877
3878         if (sc->intr_type == PCI_INTR_TYPE_MSIX)
3879                 return igb_msix_setup(sc);
3880
3881         error = bus_setup_intr(sc->dev, sc->intr_res, INTR_MPSAFE,
3882             (sc->flags & IGB_FLAG_SHARED_INTR) ? igb_intr_shared : igb_intr,
3883             sc, &sc->intr_tag, &sc->main_serialize);
3884         if (error) {
3885                 device_printf(sc->dev, "Failed to register interrupt handler");
3886                 return error;
3887         }
3888         sc->tx_rings[0].tx_intr_cpuid = rman_get_cpuid(sc->intr_res);
3889
3890         return 0;
3891 }
3892
3893 static void
3894 igb_set_txintr_mask(struct igb_tx_ring *txr, int *intr_bit0, int intr_bitmax)
3895 {
3896         if (txr->sc->hw.mac.type == e1000_82575) {
3897                 txr->tx_intr_bit = 0;   /* unused */
3898                 switch (txr->me) {
3899                 case 0:
3900                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE0;
3901                         break;
3902                 case 1:
3903                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE1;
3904                         break;
3905                 case 2:
3906                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE2;
3907                         break;
3908                 case 3:
3909                         txr->tx_intr_mask = E1000_EICR_TX_QUEUE3;
3910                         break;
3911                 default:
3912                         panic("unsupported # of TX ring, %d\n", txr->me);
3913                 }
3914         } else {
3915                 int intr_bit = *intr_bit0;
3916
3917                 txr->tx_intr_bit = intr_bit % intr_bitmax;
3918                 txr->tx_intr_mask = 1 << txr->tx_intr_bit;
3919
3920                 *intr_bit0 = intr_bit + 1;
3921         }
3922 }
3923
3924 static void
3925 igb_set_rxintr_mask(struct igb_rx_ring *rxr, int *intr_bit0, int intr_bitmax)
3926 {
3927         if (rxr->sc->hw.mac.type == e1000_82575) {
3928                 rxr->rx_intr_bit = 0;   /* unused */
3929                 switch (rxr->me) {
3930                 case 0:
3931                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE0;
3932                         break;
3933                 case 1:
3934                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE1;
3935                         break;
3936                 case 2:
3937                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE2;
3938                         break;
3939                 case 3:
3940                         rxr->rx_intr_mask = E1000_EICR_RX_QUEUE3;
3941                         break;
3942                 default:
3943                         panic("unsupported # of RX ring, %d\n", rxr->me);
3944                 }
3945         } else {
3946                 int intr_bit = *intr_bit0;
3947
3948                 rxr->rx_intr_bit = intr_bit % intr_bitmax;
3949                 rxr->rx_intr_mask = 1 << rxr->rx_intr_bit;
3950
3951                 *intr_bit0 = intr_bit + 1;
3952         }
3953 }
3954
3955 static void
3956 igb_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3957 {
3958         struct igb_softc *sc = ifp->if_softc;
3959
3960         ifnet_serialize_array_enter(sc->serializes, sc->serialize_cnt,
3961             sc->tx_serialize, sc->rx_serialize, slz);
3962 }
3963
3964 static void
3965 igb_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3966 {
3967         struct igb_softc *sc = ifp->if_softc;
3968
3969         ifnet_serialize_array_exit(sc->serializes, sc->serialize_cnt,
3970             sc->tx_serialize, sc->rx_serialize, slz);
3971 }
3972
3973 static int
3974 igb_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3975 {
3976         struct igb_softc *sc = ifp->if_softc;
3977
3978         return ifnet_serialize_array_try(sc->serializes, sc->serialize_cnt,
3979             sc->tx_serialize, sc->rx_serialize, slz);
3980 }
3981
3982 #ifdef INVARIANTS
3983
3984 static void
3985 igb_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3986     boolean_t serialized)
3987 {
3988         struct igb_softc *sc = ifp->if_softc;
3989
3990         ifnet_serialize_array_assert(sc->serializes, sc->serialize_cnt,
3991             sc->tx_serialize, sc->rx_serialize, slz, serialized);
3992 }
3993
3994 #endif  /* INVARIANTS */
3995
3996 static void
3997 igb_set_intr_mask(struct igb_softc *sc)
3998 {
3999         int i;
4000
4001         sc->intr_mask = sc->sts_intr_mask;
4002         for (i = 0; i < sc->rx_ring_inuse; ++i)
4003                 sc->intr_mask |= sc->rx_rings[i].rx_intr_mask;
4004         for (i = 0; i < sc->tx_ring_inuse; ++i)
4005                 sc->intr_mask |= sc->tx_rings[i].tx_intr_mask;
4006         if (bootverbose) {
4007                 if_printf(&sc->arpcom.ac_if, "intr mask 0x%08x\n",
4008                     sc->intr_mask);
4009         }
4010 }
4011
4012 static int
4013 igb_alloc_intr(struct igb_softc *sc)
4014 {
4015         int i, intr_bit, intr_bitmax;
4016         u_int intr_flags;
4017
4018         igb_msix_try_alloc(sc);
4019         if (sc->intr_type == PCI_INTR_TYPE_MSIX)
4020                 goto done;
4021
4022         /*
4023          * Allocate MSI/legacy interrupt resource
4024          */
4025         sc->intr_type = pci_alloc_1intr(sc->dev, igb_msi_enable,
4026             &sc->intr_rid, &intr_flags);
4027
4028         if (sc->intr_type == PCI_INTR_TYPE_LEGACY) {
4029                 int unshared;
4030
4031                 unshared = device_getenv_int(sc->dev, "irq.unshared", 0);
4032                 if (!unshared) {
4033                         sc->flags |= IGB_FLAG_SHARED_INTR;
4034                         if (bootverbose)
4035                                 device_printf(sc->dev, "IRQ shared\n");
4036                 } else {
4037                         intr_flags &= ~RF_SHAREABLE;
4038                         if (bootverbose)
4039                                 device_printf(sc->dev, "IRQ unshared\n");
4040                 }
4041         }
4042
4043         sc->intr_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
4044             &sc->intr_rid, intr_flags);
4045         if (sc->intr_res == NULL) {
4046                 device_printf(sc->dev, "Unable to allocate bus resource: "
4047                     "interrupt\n");
4048                 return ENXIO;
4049         }
4050
4051         /*
4052          * Setup MSI/legacy interrupt mask
4053          */
4054         switch (sc->hw.mac.type) {
4055         case e1000_82575:
4056                 intr_bitmax = IGB_MAX_TXRXINT_82575;
4057                 break;
4058         case e1000_82580:
4059                 intr_bitmax = IGB_MAX_TXRXINT_82580;
4060                 break;
4061         case e1000_i350:
4062                 intr_bitmax = IGB_MAX_TXRXINT_I350;
4063                 break;
4064         case e1000_82576:
4065                 intr_bitmax = IGB_MAX_TXRXINT_82576;
4066                 break;
4067         default:
4068                 intr_bitmax = IGB_MIN_TXRXINT;
4069                 break;
4070         }
4071         intr_bit = 0;
4072         for (i = 0; i < sc->tx_ring_cnt; ++i)
4073                 igb_set_txintr_mask(&sc->tx_rings[i], &intr_bit, intr_bitmax);
4074         for (i = 0; i < sc->rx_ring_cnt; ++i)
4075                 igb_set_rxintr_mask(&sc->rx_rings[i], &intr_bit, intr_bitmax);
4076         sc->sts_intr_bit = 0;
4077         sc->sts_intr_mask = E1000_EICR_OTHER;
4078
4079         /* Initialize interrupt rate */
4080         sc->intr_rate = IGB_INTR_RATE;
4081 done:
4082         igb_set_ring_inuse(sc, FALSE);
4083         igb_set_intr_mask(sc);
4084         return 0;
4085 }
4086
4087 static void
4088 igb_free_intr(struct igb_softc *sc)
4089 {
4090         if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
4091                 if (sc->intr_res != NULL) {
4092                         bus_release_resource(sc->dev, SYS_RES_IRQ, sc->intr_rid,
4093                             sc->intr_res);
4094                 }
4095                 if (sc->intr_type == PCI_INTR_TYPE_MSI)
4096                         pci_release_msi(sc->dev);
4097         } else {
4098                 igb_msix_free(sc, TRUE);
4099         }
4100 }
4101
4102 static void
4103 igb_teardown_intr(struct igb_softc *sc)
4104 {
4105         if (sc->intr_type != PCI_INTR_TYPE_MSIX)
4106                 bus_teardown_intr(sc->dev, sc->intr_res, sc->intr_tag);
4107         else
4108                 igb_msix_teardown(sc, sc->msix_cnt);
4109 }
4110
4111 static void
4112 igb_msix_try_alloc(struct igb_softc *sc)
4113 {
4114         int msix_enable, msix_cnt, msix_cnt2, alloc_cnt;
4115         int i, x, error;
4116         struct igb_msix_data *msix;
4117         boolean_t aggregate, setup = FALSE;
4118
4119         /*
4120          * Don't enable MSI-X on 82575, see:
4121          * 82575 specification update errata #25
4122          */
4123         if (sc->hw.mac.type == e1000_82575)
4124                 return;
4125
4126         /* Don't enable MSI-X on VF */
4127         if (sc->vf_ifp)
4128                 return;
4129
4130         msix_enable = device_getenv_int(sc->dev, "msix.enable",
4131             igb_msix_enable);
4132         if (!msix_enable)
4133                 return;
4134
4135         msix_cnt = pci_msix_count(sc->dev);
4136 #ifdef IGB_MSIX_DEBUG
4137         msix_cnt = device_getenv_int(sc->dev, "msix.count", msix_cnt);
4138 #endif
4139         if (msix_cnt <= 1) {
4140                 /* One MSI-X model does not make sense */
4141                 return;
4142         }
4143
4144         i = 0;
4145         while ((1 << (i + 1)) <= msix_cnt)
4146                 ++i;
4147         msix_cnt2 = 1 << i;
4148
4149         if (bootverbose) {
4150                 device_printf(sc->dev, "MSI-X count %d/%d\n",
4151                     msix_cnt2, msix_cnt);
4152         }
4153
4154         KKASSERT(msix_cnt2 <= msix_cnt);
4155         if (msix_cnt == msix_cnt2) {
4156                 /* We need at least one MSI-X for link status */
4157                 msix_cnt2 >>= 1;
4158                 if (msix_cnt2 <= 1) {
4159                         /* One MSI-X for RX/TX does not make sense */
4160                         device_printf(sc->dev, "not enough MSI-X for TX/RX, "
4161                             "MSI-X count %d/%d\n", msix_cnt2, msix_cnt);
4162                         return;
4163                 }
4164                 KKASSERT(msix_cnt > msix_cnt2);
4165
4166                 if (bootverbose) {
4167                         device_printf(sc->dev, "MSI-X count fixup %d/%d\n",
4168                             msix_cnt2, msix_cnt);
4169                 }
4170         }
4171
4172         sc->rx_ring_msix = sc->rx_ring_cnt;
4173         if (sc->rx_ring_msix > msix_cnt2)
4174                 sc->rx_ring_msix = msix_cnt2;
4175
4176         sc->tx_ring_msix = sc->tx_ring_cnt;
4177         if (sc->tx_ring_msix > msix_cnt2)
4178                 sc->tx_ring_msix = msix_cnt2;
4179
4180         if (msix_cnt >= sc->tx_ring_msix + sc->rx_ring_msix + 1) {
4181                 /*
4182                  * Independent TX/RX MSI-X
4183                  */
4184                 aggregate = FALSE;
4185                 if (bootverbose)
4186                         device_printf(sc->dev, "independent TX/RX MSI-X\n");
4187                 alloc_cnt = sc->tx_ring_msix + sc->rx_ring_msix;
4188         } else {
4189                 /*
4190                  * Aggregate TX/RX MSI-X
4191                  */
4192                 aggregate = TRUE;
4193                 if (bootverbose)
4194                         device_printf(sc->dev, "aggregate TX/RX MSI-X\n");
4195                 alloc_cnt = msix_cnt2;
4196                 if (alloc_cnt > ncpus2)
4197                         alloc_cnt = ncpus2;
4198                 if (sc->rx_ring_msix > alloc_cnt)
4199                         sc->rx_ring_msix = alloc_cnt;
4200         }
4201         ++alloc_cnt;    /* For link status */
4202
4203         if (bootverbose) {
4204                 device_printf(sc->dev, "MSI-X alloc %d, RX ring %d\n",
4205                     alloc_cnt, sc->rx_ring_msix);
4206         }
4207
4208         sc->msix_mem_rid = PCIR_BAR(IGB_MSIX_BAR);
4209         sc->msix_mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
4210             &sc->msix_mem_rid, RF_ACTIVE);
4211         if (sc->msix_mem_res == NULL) {
4212                 device_printf(sc->dev, "Unable to map MSI-X table\n");
4213                 return;
4214         }
4215
4216         sc->msix_cnt = alloc_cnt;
4217         sc->msix_data = kmalloc_cachealign(
4218             sizeof(struct igb_msix_data) * sc->msix_cnt,
4219             M_DEVBUF, M_WAITOK | M_ZERO);
4220         for (x = 0; x < sc->msix_cnt; ++x) {
4221                 msix = &sc->msix_data[x];
4222
4223                 lwkt_serialize_init(&msix->msix_serialize0);
4224                 msix->msix_sc = sc;
4225                 msix->msix_rid = -1;
4226                 msix->msix_vector = x;
4227                 msix->msix_mask = 1 << msix->msix_vector;
4228                 msix->msix_rate = IGB_INTR_RATE;
4229         }
4230
4231         x = 0;
4232         if (!aggregate) {
4233                 int offset, offset_def;
4234
4235                 if (sc->rx_ring_msix == ncpus2) {
4236                         offset = 0;
4237                 } else {
4238                         offset_def = (sc->rx_ring_msix *
4239                             device_get_unit(sc->dev)) % ncpus2;
4240
4241                         offset = device_getenv_int(sc->dev,
4242                             "msix.rxoff", offset_def);
4243                         if (offset >= ncpus2 ||
4244                             offset % sc->rx_ring_msix != 0) {
4245                                 device_printf(sc->dev,
4246                                     "invalid msix.rxoff %d, use %d\n",
4247                                     offset, offset_def);
4248                                 offset = offset_def;
4249                         }
4250                 }
4251
4252                 /* RX rings */
4253                 for (i = 0; i < sc->rx_ring_msix; ++i) {
4254                         struct igb_rx_ring *rxr = &sc->rx_rings[i];
4255
4256                         KKASSERT(x < sc->msix_cnt);
4257                         msix = &sc->msix_data[x++];
4258                         rxr->rx_intr_bit = msix->msix_vector;
4259                         rxr->rx_intr_mask = msix->msix_mask;
4260
4261                         msix->msix_serialize = &rxr->rx_serialize;
4262                         msix->msix_func = igb_msix_rx;
4263                         msix->msix_arg = rxr;
4264                         msix->msix_cpuid = i + offset;
4265                         KKASSERT(msix->msix_cpuid < ncpus2);
4266                         ksnprintf(msix->msix_desc, sizeof(msix->msix_desc),
4267                             "%s rx%d", device_get_nameunit(sc->dev), i);
4268                         msix->msix_rate = IGB_MSIX_RX_RATE;
4269                         ksnprintf(msix->msix_rate_desc,
4270                             sizeof(msix->msix_rate_desc),
4271                             "RX%d interrupt rate", i);
4272                 }
4273
4274                 offset_def = device_get_unit(sc->dev) % ncpus2;
4275                 offset = device_getenv_int(sc->dev, "msix.txoff", offset_def);
4276                 if (offset >= ncpus2) {
4277                         device_printf(sc->dev, "invalid msix.txoff %d, "
4278                             "use %d\n", offset, offset_def);
4279                         offset = offset_def;
4280                 }
4281
4282                 /* TX rings */
4283                 for (i = 0; i < sc->tx_ring_msix; ++i) {
4284                         struct igb_tx_ring *txr = &sc->tx_rings[i];
4285
4286                         KKASSERT(x < sc->msix_cnt);
4287                         msix = &sc->msix_data[x++];
4288                         txr->tx_intr_bit = msix->msix_vector;
4289                         txr->tx_intr_mask = msix->msix_mask;
4290
4291                         msix->msix_serialize = &txr->tx_serialize;
4292                         msix->msix_func = igb_msix_tx;
4293                         msix->msix_arg = txr;
4294                         msix->msix_cpuid = i + offset;
4295                         txr->tx_intr_cpuid = msix->msix_cpuid;
4296                         KKASSERT(msix->msix_cpuid < ncpus2);
4297                         ksnprintf(msix->msix_desc, sizeof(msix->msix_desc),
4298                             "%s tx%d", device_get_nameunit(sc->dev), i);
4299                         msix->msix_rate = IGB_MSIX_TX_RATE;
4300                         ksnprintf(msix->msix_rate_desc,
4301                             sizeof(msix->msix_rate_desc),
4302                             "TX%d interrupt rate", i);
4303                 }
4304         } else {
4305                 /* TODO */
4306                 error = EOPNOTSUPP;
4307                 goto back;
4308         }
4309
4310         /*
4311          * Link status
4312          */
4313         KKASSERT(x < sc->msix_cnt);
4314         msix = &sc->msix_data[x++];
4315         sc->sts_intr_bit = msix->msix_vector;
4316         sc->sts_intr_mask = msix->msix_mask;
4317
4318         msix->msix_serialize = &sc->main_serialize;
4319         msix->msix_func = igb_msix_status;
4320         msix->msix_arg = sc;
4321         msix->msix_cpuid = 0; /* TODO tunable */
4322         ksnprintf(msix->msix_desc, sizeof(msix->msix_desc), "%s sts",
4323             device_get_nameunit(sc->dev));
4324         ksnprintf(msix->msix_rate_desc, sizeof(msix->msix_rate_desc),
4325             "status interrupt rate");
4326
4327         KKASSERT(x == sc->msix_cnt);
4328
4329         error = pci_setup_msix(sc->dev);
4330         if (error) {
4331                 device_printf(sc->dev, "Setup MSI-X failed\n");
4332                 goto back;
4333         }
4334         setup = TRUE;
4335
4336         for (i = 0; i < sc->msix_cnt; ++i) {
4337                 msix = &sc->msix_data[i];
4338
4339                 error = pci_alloc_msix_vector(sc->dev, msix->msix_vector,
4340                     &msix->msix_rid, msix->msix_cpuid);
4341                 if (error) {
4342                         device_printf(sc->dev,
4343                             "Unable to allocate MSI-X %d on cpu%d\n",
4344                             msix->msix_vector, msix->msix_cpuid);
4345                         goto back;
4346                 }
4347
4348                 msix->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
4349                     &msix->msix_rid, RF_ACTIVE);
4350                 if (msix->msix_res == NULL) {
4351                         device_printf(sc->dev,
4352                             "Unable to allocate MSI-X %d resource\n",
4353                             msix->msix_vector);
4354                         error = ENOMEM;
4355                         goto back;
4356                 }
4357         }
4358
4359         pci_enable_msix(sc->dev);
4360         sc->intr_type = PCI_INTR_TYPE_MSIX;
4361 back:
4362         if (error)
4363                 igb_msix_free(sc, setup);
4364 }
4365
4366 static void
4367 igb_msix_free(struct igb_softc *sc, boolean_t setup)
4368 {
4369         int i;
4370
4371         KKASSERT(sc->msix_cnt > 1);
4372
4373         for (i = 0; i < sc->msix_cnt; ++i) {
4374                 struct igb_msix_data *msix = &sc->msix_data[i];
4375
4376                 if (msix->msix_res != NULL) {
4377                         bus_release_resource(sc->dev, SYS_RES_IRQ,
4378                             msix->msix_rid, msix->msix_res);
4379                 }
4380                 if (msix->msix_rid >= 0)
4381                         pci_release_msix_vector(sc->dev, msix->msix_rid);
4382         }
4383         if (setup)
4384                 pci_teardown_msix(sc->dev);
4385
4386         sc->msix_cnt = 0;
4387         kfree(sc->msix_data, M_DEVBUF);
4388         sc->msix_data = NULL;
4389 }
4390
4391 static int
4392 igb_msix_setup(struct igb_softc *sc)
4393 {
4394         int i;
4395
4396         for (i = 0; i < sc->msix_cnt; ++i) {
4397                 struct igb_msix_data *msix = &sc->msix_data[i];
4398                 int error;
4399
4400                 error = bus_setup_intr_descr(sc->dev, msix->msix_res,
4401                     INTR_MPSAFE, msix->msix_func, msix->msix_arg,
4402                     &msix->msix_handle, msix->msix_serialize, msix->msix_desc);
4403                 if (error) {
4404                         device_printf(sc->dev, "could not set up %s "
4405                             "interrupt handler.\n", msix->msix_desc);
4406                         igb_msix_teardown(sc, i);
4407                         return error;
4408                 }
4409         }
4410         return 0;
4411 }
4412
4413 static void
4414 igb_msix_teardown(struct igb_softc *sc, int msix_cnt)
4415 {
4416         int i;
4417
4418         for (i = 0; i < msix_cnt; ++i) {
4419                 struct igb_msix_data *msix = &sc->msix_data[i];
4420
4421                 bus_teardown_intr(sc->dev, msix->msix_res, msix->msix_handle);
4422         }
4423 }
4424
4425 static void
4426 igb_msix_rx(void *arg)
4427 {
4428         struct igb_rx_ring *rxr = arg;
4429
4430         ASSERT_SERIALIZED(&rxr->rx_serialize);
4431         igb_rxeof(rxr, -1);
4432
4433         E1000_WRITE_REG(&rxr->sc->hw, E1000_EIMS, rxr->rx_intr_mask);
4434 }
4435
4436 static void
4437 igb_msix_tx(void *arg)
4438 {
4439         struct igb_tx_ring *txr = arg;
4440
4441         ASSERT_SERIALIZED(&txr->tx_serialize);
4442
4443         igb_txeof(txr);
4444         if (!ifsq_is_empty(txr->ifsq))
4445                 ifsq_devstart(txr->ifsq);
4446
4447         E1000_WRITE_REG(&txr->sc->hw, E1000_EIMS, txr->tx_intr_mask);
4448 }
4449
4450 static void
4451 igb_msix_status(void *arg)
4452 {
4453         struct igb_softc *sc = arg;
4454         uint32_t icr;
4455
4456         ASSERT_SERIALIZED(&sc->main_serialize);
4457
4458         icr = E1000_READ_REG(&sc->hw, E1000_ICR);
4459         if (icr & E1000_ICR_LSC) {
4460                 sc->hw.mac.get_link_status = 1;
4461                 igb_update_link_status(sc);
4462         }
4463
4464         E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->sts_intr_mask);
4465 }
4466
4467 static void
4468 igb_set_ring_inuse(struct igb_softc *sc, boolean_t polling)
4469 {
4470         sc->rx_ring_inuse = igb_get_rxring_inuse(sc, polling);
4471         sc->tx_ring_inuse = igb_get_txring_inuse(sc, polling);
4472         if (bootverbose) {
4473                 if_printf(&sc->arpcom.ac_if, "RX rings %d/%d, TX rings %d/%d\n",
4474                     sc->rx_ring_inuse, sc->rx_ring_cnt,
4475                     sc->tx_ring_inuse, sc->tx_ring_cnt);
4476         }
4477 }
4478
4479 static int
4480 igb_get_rxring_inuse(const struct igb_softc *sc, boolean_t polling)
4481 {
4482         if (!IGB_ENABLE_HWRSS(sc))
4483                 return 1;
4484
4485         if (polling)
4486                 return sc->rx_ring_cnt;
4487         else if (sc->intr_type != PCI_INTR_TYPE_MSIX)
4488                 return IGB_MIN_RING_RSS;
4489         else
4490                 return sc->rx_ring_msix;
4491 }
4492
4493 static int
4494 igb_get_txring_inuse(const struct igb_softc *sc, boolean_t polling)
4495 {
4496         if (!IGB_ENABLE_HWTSS(sc))
4497                 return 1;
4498
4499         if (polling)
4500                 return sc->tx_ring_cnt;
4501         else if (sc->intr_type != PCI_INTR_TYPE_MSIX)
4502                 return IGB_MIN_RING;
4503         else
4504                 return sc->tx_ring_msix;
4505 }
4506
4507 static int
4508 igb_tso_pullup(struct igb_tx_ring *txr, struct mbuf **mp)
4509 {
4510         int hoff, iphlen, thoff;
4511         struct mbuf *m;
4512
4513         m = *mp;
4514         KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
4515
4516         iphlen = m->m_pkthdr.csum_iphlen;
4517         thoff = m->m_pkthdr.csum_thlen;
4518         hoff = m->m_pkthdr.csum_lhlen;
4519
4520         KASSERT(iphlen > 0, ("invalid ip hlen"));
4521         KASSERT(thoff > 0, ("invalid tcp hlen"));
4522         KASSERT(hoff > 0, ("invalid ether hlen"));
4523
4524         if (__predict_false(m->m_len < hoff + iphlen + thoff)) {
4525                 m = m_pullup(m, hoff + iphlen + thoff);
4526                 if (m == NULL) {
4527                         *mp = NULL;
4528                         return ENOBUFS;
4529                 }
4530                 *mp = m;
4531         }
4532         if (txr->tx_flags & IGB_TXFLAG_TSO_IPLEN0) {
4533                 struct ip *ip;
4534
4535                 ip = mtodoff(m, struct ip *, hoff);
4536                 ip->ip_len = 0;
4537         }
4538
4539         return 0;
4540 }
4541
4542 static void
4543 igb_tso_ctx(struct igb_tx_ring *txr, struct mbuf *m, uint32_t *hlen)
4544 {
4545         struct e1000_adv_tx_context_desc *TXD;
4546         uint32_t vlan_macip_lens, type_tucmd_mlhl, mss_l4len_idx;
4547         int hoff, ctxd, iphlen, thoff;
4548
4549         iphlen = m->m_pkthdr.csum_iphlen;
4550         thoff = m->m_pkthdr.csum_thlen;
4551         hoff = m->m_pkthdr.csum_lhlen;
4552
4553         vlan_macip_lens = type_tucmd_mlhl = mss_l4len_idx = 0;
4554
4555         ctxd = txr->next_avail_desc;
4556         TXD = (struct e1000_adv_tx_context_desc *)&txr->tx_base[ctxd];
4557
4558         if (m->m_flags & M_VLANTAG) {
4559                 uint16_t vlantag;
4560
4561                 vlantag = htole16(m->m_pkthdr.ether_vlantag);
4562                 vlan_macip_lens |= (vlantag << E1000_ADVTXD_VLAN_SHIFT);
4563         }
4564
4565         vlan_macip_lens |= (hoff << E1000_ADVTXD_MACLEN_SHIFT);
4566         vlan_macip_lens |= iphlen;
4567
4568         type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4569         type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP;
4570         type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4;
4571
4572         mss_l4len_idx |= (m->m_pkthdr.tso_segsz << E1000_ADVTXD_MSS_SHIFT);
4573         mss_l4len_idx |= (thoff << E1000_ADVTXD_L4LEN_SHIFT);
4574         /* 82575 needs the queue index added */
4575         if (txr->sc->hw.mac.type == e1000_82575)
4576                 mss_l4len_idx |= txr->me << 4;
4577
4578         TXD->vlan_macip_lens = htole32(vlan_macip_lens);
4579         TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
4580         TXD->seqnum_seed = htole32(0);
4581         TXD->mss_l4len_idx = htole32(mss_l4len_idx);
4582
4583         /* We've consumed the first desc, adjust counters */
4584         if (++ctxd == txr->num_tx_desc)
4585                 ctxd = 0;
4586         txr->next_avail_desc = ctxd;
4587         --txr->tx_avail;
4588
4589         *hlen = hoff + iphlen + thoff;
4590 }