1 .\" Copyright (c) 2001-2008, Intel Corporation
2 .\" All rights reserved.
4 .\" Redistribution and use in source and binary forms, with or without
5 .\" modification, are permitted provided that the following conditions are met:
7 .\" 1. Redistributions of source code must retain the above copyright notice,
8 .\" this list of conditions and the following disclaimer.
10 .\" 2. Redistributions in binary form must reproduce the above copyright
11 .\" notice, this list of conditions and the following disclaimer in the
12 .\" documentation and/or other materials provided with the distribution.
14 .\" 3. Neither the name of the Intel Corporation nor the names of its
15 .\" contributors may be used to endorse or promote products derived from
16 .\" this software without specific prior written permission.
18 .\" THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 .\" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 .\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 .\" ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
22 .\" LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 .\" CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 .\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 .\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 .\" CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 .\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 .\" POSSIBILITY OF SUCH DAMAGE.
30 .\" * Other names and brands may be claimed as the property of others.
32 .\" $FreeBSD: src/share/man/man4/ixgbe.4,v 1.2 2008/06/17 21:14:02 brueffer Exp $
39 .Nd "Intel(R) 10Gb Ethernet driver"
41 To compile this driver into the kernel,
42 place the following line in your
43 kernel configuration file:
44 .Bd -ragged -offset indent
48 Alternatively, to load the driver as a
49 module at boot time, place the following line in
51 .Bd -literal -offset indent
57 driver provides support for PCI Express 10Gb Ethernet adapters based on
63 Ethernet controller chips.
68 .Bl -item -offset indent -compact
70 Transmit/Receive checksum offload for IP/UDP/TCP.
75 TCP segmentation offload (TSO)
77 Receive side scaling (RSS)
79 Multiple tranmission queues
83 VLAN tag stripping and inserting
92 driver will try enabling as many reception queues and transmission queues
93 as are allowed by the number of CPUs in the system.
95 If multiple transmission queues are used,
96 the round-robin arbitration is performed among the transmission queues.
97 And the round-robin arbitration between transmission queues is done at the
98 TCP segment boundary after the hardware segmentation is performed.
100 82598 supports 16 reception queues and 32 transmission queues.
101 MSI-X is not enabled due to hardware errata.
102 Under MSI or legacy interrupt mode,
103 2 reception queues are enabled for hardware RSS hash
104 and only 1 transmission queue is enable.
106 82599 and X540 supports 16 reception queues and 64 transmission queues.
107 MSI-X is enable by default.
109 due to the number of MSI-X vectors is 64,
110 at most 16 reception queues and 32 transmission queues will be enabled
113 For more information on configuring this device, see
122 driver supports Gigabit Ethernet adapters based on the Intel
131 Intel 10 Gigabit AF DA Dual Port Server Adapter
133 Intel 10 Gigabit AT Server Adapter
135 Intel 10 Gigabit AT2 Server Adapter
137 Intel 10 Gigabit CX4 Dual Port Server Adapter
139 Intel 10 Gigabit XF LR Server Adapter
141 Intel 10 Gigabit XF SR Dual Port Server Adapter
143 Intel 10 Gigabit XF SR Server Adapter
145 Intel 82598 10 Gigabit Ethernet Controller
147 Intel 82599 10 Gigabit Ethernet Controller
149 Intel Ethernet Controller X540-AT2
151 Intel Ethernet Converged Network Adapter X520 Series
153 Intel Ethernet Converged Network Adapter X540-T1
155 Intel Ethernet Converged Network Adapter X540-T2
157 Intel Ethernet Server Adapter X520 Series
159 Intel Ethernet Server Adapter X520-DA2
161 Intel Ethernet Server Adapter X520-LR1
163 Intel Ethernet Server Adapter X520-SR1
165 Intel Ethernet Server Adapter X520-SR2
167 Intel Ethernet Server Adapter X520-T2
170 Tunables can be set at the
172 prompt before booting the kernel or stored in
175 is the device unit number.
176 .Bl -tag -width ".Va hw.ixX.unsupported_sfp"
177 .It Va hw.ix.rxd Va hw.ixX.rxd
178 Number of receive descriptors allocated by the driver.
179 The default value is 2048.
181 and the maximum is 4096.
182 .It Va hw.ix.txd Va hw.ixX.txd
183 Number of transmit descriptors allocated by the driver.
184 The default value is 2048.
186 and the maximum is 4096.
187 .It Va hw.ix.rxr Va hw.ixX.rxr
188 This tunable specifies the number of reception queues could be enabled.
189 Maximum allowed value for these tunables is device specific
190 and it must be power of 2 aligned.
191 Setting these tunables to 0 allows the driver to make
192 as many reception queues ready-for-use as allowed by the number of CPUs.
193 .It Va hw.ix.txr Va hw.ixX.txr
194 This tunable specifies the number of transmission queues could be enabled.
195 Maximum allowed value for these tunables is device specific
196 and it must be power of 2 aligned.
197 Setting these tunables to 0 allows the driver to make
198 as many transmission queues ready-for-use as allowed by the number of CPUs.
199 .It Va hw.ix.msix.enable Va hw.ixX.msix.enable
201 the driver will use MSI-X if it is supported.
202 This behaviour can be turned off by setting this tunable to 0.
203 .It Va hw.ix.msix.agg_rxtx Va hw.ixX.msix.agg_rxtx
205 the driver aggregates transmission queue and reception queue processing
207 This behaviour could be turned off by setting this tunable to 0.
208 If the number of MSI-X vectors is not enough to
209 put transmission queue processing and reception queue processing
210 onto independent MSI-X vector,
211 then transmission queue and reception queue processing are always
213 .It Va hw.ixX.msix.off
215 and transmission queue and reception queue processing are aggregated,
216 this tunable specifies the leading target CPU for
217 transmission and reception queues processing.
218 The value specificed must be aligned to the maximum of
219 the number of reception queues
220 and the number of transmission queues enabled,
221 and must be less than the power of 2 number of CPUs.
222 .It Va hw.ixX.msix.rxoff
224 and transmission queue and reception queue processing are not aggregated,
225 this tunable specifies the leading target CPU for reception queues processing.
226 The value specificed must be aligned to the number of reception queues enabled
227 and must be less than the power of 2 number of CPUs.
228 .It Va hw.ixX.msix.txoff
230 and transmission queue and reception queue processing are not aggregated,
231 this tunable specifies the leading target CPU
232 for transmission queues processing.
233 The value specificed must be aligned to
234 the number of transmission queues enabled
235 and must be less than the power of 2 number of CPUs.
236 .It Va hw.ix.msi.enable Va hw.ixX.msi.enable
237 If MSI-X is disabled and MSI is supported,
238 the driver will use MSI.
239 This behavior can be turned off by setting this tunable to 0.
240 .It Va hw.ixX.msi.cpu
242 it specifies the MSI's target CPU.
243 .It Va hw.ixX.npoll.txoff
244 This tunable specifies the leading target CPU for
248 The value specificed must be aligned to the number of transmission queues
249 enabled and must be less than the power of 2 number of CPUs.
250 .It Va hw.ixX.npoll.rxoff
251 This tunable specifies the leading target CPU for
255 The value specificed must be aligned to the number of reception queues
256 enabled and must be less than the power of 2 number of CPUs.
257 .It Va hw.ix.unsupported_sfp
259 this driver does not allow "unsupported" SFP modules.
260 This behavior can be changed by setting this tunable to 1.
263 A number of per-interface variables are implemented in the
268 .Bl -tag -width "rxtx_intr_rate"
270 Number of reception queues could be enabled (read-only).
277 Number of reception queues being used (read-only).
279 Number of transmission queues could be enabled (read-only).
286 Number of transmission queues being used (read-only).
288 Number of descriptors per reception queue (read-only).
295 Number of descriptors per transmission queue (read-only).
301 .It Va rxtx_intr_rate
302 If MSI or legacy interrupt is used,
303 this sysctl controls the highest possible frequency
304 that interrupt could be generated by the device.
306 this sysctl controls the highest possible frequency
307 that interrupt could be generated by the MSI-X vectors,
308 which aggregate transmission queue and reception queue procecssing.
309 It is 8000 by default (125us).
312 this sysctl controls the highest possible frequency
313 that interrupt could be generated by the MSI-X vectors,
314 which only process reception queue.
315 It is 8000 by default (125us).
318 this sysctl controls the highest possible frequency
319 that interrupt could be generated by the MSI-X vectors,
320 which only process transmission queue.
321 It is 6000 by default (~150us).
324 this sysctl controls the highest possible frequency
325 that interrupt could be generated by the MSI-X vectors,
326 which only process chip status changes.
327 It is 8000 by default (125us).
329 Transmission interrupt is asked to be generated upon every
331 transmission descritors having been setup.
332 The default value is 1/16 of the number of transmission descriptors per queue.
334 The number of transmission descriptors should be setup
335 before the hardware register is written.
336 Setting this value too high will have negative effect
337 on transmission timeliness.
338 Setting this value too low will hurt overall transmission performance
339 due to the frequent hardware register writing.
340 The default value is 8.
342 The number of reception descriptors should be setup
343 before the hardware register is written.
344 Setting this value too high will make device drop incoming packets.
345 Setting this value too low will hurt overall reception performance
346 due to the frequent hardware register writing.
347 The default value is 32.
350 .Va hw.ixX.npoll.rxoff .
351 The set value will take effect the next time
353 is enabled on the device.
356 .Va hw.ixX.npoll.txoff .
357 The set value will take effect the next time
359 is enabled on the device.
361 Flow control setting.
362 Set it to 0 to turn off flow control.
363 Set it to 1 to enable only the reception of pause frames.
364 Set it to 2 to enable only the generation of pause frames.
365 Set it to 3 to enable both the reception of pause frames
366 and generation of pause frames,
367 i.e. full flow control.
381 device driver first appeared in
386 driver was written by
387 .An Intel Corporation Aq Mt freebsdnic@mailbox.intel.com .