2 * Copyright (c) 2007 The DragonFly Project. All rights reserved.
4 * This code is derived from software contributed to The DragonFly Project
5 * by Sepherosa Ziehau <sepherosa@gmail.com>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 #define BWI_ALIGN 0x1000
39 #define BWI_RING_ALIGN BWI_ALIGN
40 #define BWI_BUS_SPACE_MAXADDR 0x3fffffff
42 #define BWI_TX_NRING 6
43 #define BWI_TXRX_NRING 6
44 #define BWI_TX_NDESC 128
45 #define BWI_RX_NDESC 64
46 #define BWI_TXSTATS_NDESC 64
47 #define BWI_TX_NSPRDESC 2
48 #define BWI_TX_DATA_RING 1
50 /* XXX Onoe/Sample/AMRR probably need different configuration */
53 #define BWI_SHRETRY_FB 3
54 #define BWI_LGRETRY_FB 2
56 #define BWI_LED_EVENT_NONE -1
57 #define BWI_LED_EVENT_POLL 0
58 #define BWI_LED_EVENT_TX 1
59 #define BWI_LED_EVENT_RX 2
60 #define BWI_LED_SLOWDOWN(dur) (dur) = (((dur) * 3) / 2)
62 enum bwi_txpwrcb_type {
68 #define BWI_NOISE_FLOOR -95 /* TODO: noise floor calc */
69 #define BWI_FRAME_MIN_LEN(hdr) \
70 ((hdr) + sizeof(struct ieee80211_frame_ack) + IEEE80211_CRC_LEN)
72 #define CSR_READ_4(sc, reg) \
73 bus_space_read_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg))
74 #define CSR_READ_2(sc, reg) \
75 bus_space_read_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg))
77 #define CSR_WRITE_4(sc, reg, val) \
78 bus_space_write_4((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))
79 #define CSR_WRITE_2(sc, reg, val) \
80 bus_space_write_2((sc)->sc_mem_bt, (sc)->sc_mem_bh, (reg), (val))
82 #define CSR_SETBITS_4(sc, reg, bits) \
83 CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) | (bits))
84 #define CSR_SETBITS_2(sc, reg, bits) \
85 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) | (bits))
87 #define CSR_FILT_SETBITS_4(sc, reg, filt, bits) \
88 CSR_WRITE_4((sc), (reg), (CSR_READ_4((sc), (reg)) & (filt)) | (bits))
89 #define CSR_FILT_SETBITS_2(sc, reg, filt, bits) \
90 CSR_WRITE_2((sc), (reg), (CSR_READ_2((sc), (reg)) & (filt)) | (bits))
92 #define CSR_CLRBITS_4(sc, reg, bits) \
93 CSR_WRITE_4((sc), (reg), CSR_READ_4((sc), (reg)) & ~(bits))
94 #define CSR_CLRBITS_2(sc, reg, bits) \
95 CSR_WRITE_2((sc), (reg), CSR_READ_2((sc), (reg)) & ~(bits))
100 #define DPRINTF(sc, dbg, fmt, ...) \
102 if ((sc)->sc_debug & (dbg)) \
103 if_printf(&(sc)->sc_ic.ic_if, fmt, __VA_ARGS__); \
106 #define _DPRINTF(sc, dbg, fmt, ...) \
108 if ((sc)->sc_debug & (dbg)) \
109 kprintf(fmt, __VA_ARGS__); \
112 #else /* !BWI_DEBUG */
114 #define DPRINTF(sc, dbg, fmt, ...) ((void)0)
115 #define _DPRINTF(sc, dbg, fmt, ...) ((void)0)
117 #endif /* BWI_DEBUG */
122 uint32_t addr; /* BWI_DESC32_A_ */
125 #define BWI_DESC32_A_FUNC_TXRX 0x1
126 #define BWI_DESC32_A_FUNC_MASK __BITS(31, 30)
127 #define BWI_DESC32_A_ADDR_MASK __BITS(29, 0)
129 #define BWI_DESC32_C_BUFLEN_MASK __BITS(12, 0)
130 #define BWI_DESC32_C_ADDRHI_MASK __BITS(17, 16)
131 #define BWI_DESC32_C_EOR __BIT(28)
132 #define BWI_DESC32_C_INTR __BIT(29)
133 #define BWI_DESC32_C_FRAME_END __BIT(30)
134 #define BWI_DESC32_C_FRAME_START __BIT(31)
144 struct bwi_rxbuf_hdr {
146 uint16_t rxh_buflen; /* exclude bwi_rxbuf_hdr */
148 uint16_t rxh_flags1; /* BWI_RXH_F1_ */
151 uint16_t rxh_phyinfo; /* BWI_RXH_PHYINFO_ */
152 uint16_t rxh_flags3; /* BWI_RXH_F3_ */
153 uint16_t rxh_flags2; /* BWI_RXH_F2_ */
155 uint8_t rxh_pad3[14]; /* Padded to 30bytes */
158 #define BWI_RXH_F1_BCM2053_RSSI __BIT(14)
159 #define BWI_RXH_F1_SHPREAMBLE __BIT(7)
160 #define BWI_RXH_F1_OFDM __BIT(0)
162 #define BWI_RXH_F2_TYPE2FRAME __BIT(2)
164 #define BWI_RXH_F3_BCM2050_RSSI __BIT(10)
166 #define BWI_RXH_PHYINFO_LNAGAIN __BITS(15, 14)
168 struct bwi_txbuf_hdr {
170 uint32_t txh_mac_ctrl; /* BWI_TXH_MAC_C_ */
172 uint16_t txh_unknown1;
173 uint16_t txh_phy_ctrl; /* BWI_TXH_PHY_C_ */
175 uint8_t txh_addr1[IEEE80211_ADDR_LEN];
176 uint16_t txh_unknown2;
177 uint8_t txh_rts_fb_plcp[4];
178 uint16_t txh_rts_fb_duration;
179 uint8_t txh_fb_plcp[4];
180 uint16_t txh_fb_duration;
182 uint16_t txh_id; /* BWI_TXH_ID_ */
183 uint16_t txh_unknown3;
184 uint8_t txh_rts_plcp[6];
185 uint8_t txh_rts_fc[2];
186 uint16_t txh_rts_duration;
187 uint8_t txh_rts_ra[IEEE80211_ADDR_LEN];
188 uint8_t txh_rts_ta[IEEE80211_ADDR_LEN];
193 #define BWI_TXH_ID_RING_MASK __BITS(15, 13)
194 #define BWI_TXH_ID_IDX_MASK __BITS(12, 0)
196 #define BWI_TXH_PHY_C_OFDM __BIT(0)
197 #define BWI_TXH_PHY_C_SHPREAMBLE __BIT(4)
198 #define BWI_TXH_PHY_C_ANTMODE_MASK __BITS(9, 8)
200 #define BWI_TXH_MAC_C_ACK __BIT(0)
201 #define BWI_TXH_MAC_C_FIRST_FRAG __BIT(3)
202 #define BWI_TXH_MAC_C_HWSEQ __BIT(4)
203 #define BWI_TXH_MAC_C_FB_OFDM __BIT(8)
209 uint8_t txs_flags; /* BWI_TXS_F_ */
210 uint8_t txs_txcnt; /* BWI_TXS_TXCNT_ */
213 uint16_t txs_unknown;
214 uint8_t txs_pad3[2]; /* Padded to 16bytes */
217 #define BWI_TXS_TXCNT_DATA __BITS(7, 4)
219 #define BWI_TXS_F_ACKED __BIT(0)
220 #define BWI_TXS_F_PENDING __BIT(5)
222 struct bwi_ring_data {
223 uint32_t rdata_txrx_ctrl;
224 bus_dmamap_t rdata_dmap;
225 bus_addr_t rdata_paddr;
230 struct mbuf *tb_mbuf;
231 bus_dmamap_t tb_dmap;
233 struct ieee80211_node *tb_ni;
235 #define BWI_NTXRATE 2
237 int tb_rateidx[BWI_NTXRATE];
240 struct bwi_txbuf_data {
241 struct bwi_txbuf tbd_buf[BWI_TX_NDESC];
247 struct mbuf *rb_mbuf;
249 bus_dmamap_t rb_dmap;
252 struct bwi_rxbuf_data {
253 struct bwi_rxbuf rbd_buf[BWI_RX_NDESC];
254 bus_dmamap_t rbd_tmp_dmap;
258 struct bwi_txstats_data {
259 bus_dma_tag_t stats_ring_dtag;
260 bus_dmamap_t stats_ring_dmap;
261 bus_addr_t stats_ring_paddr;
264 bus_dma_tag_t stats_dtag;
265 bus_dmamap_t stats_dmap;
266 bus_addr_t stats_paddr;
267 struct bwi_txstats *stats;
269 uint32_t stats_ctrl_base;
275 uint8_t fw_type; /* BWI_FW_T_ */
276 uint8_t fw_gen; /* BWI_FW_GEN */
279 #define fw_iv_cnt fw_size
282 #define BWI_FWHDR_SZ sizeof(struct bwi_fwhdr)
284 #define BWI_FW_T_UCODE 'u'
285 #define BWI_FW_T_PCM 'p'
286 #define BWI_FW_T_IV 'i'
288 #define BWI_FW_GEN_1 1
290 #define BWI_FW_VERSION3 3
291 #define BWI_FW_VERSION4 4
292 #define BWI_FW_VERSION3_REVMAX 0x128
294 #define BWI_FW_PATH "bwi/v%d/"
295 #define BWI_FW_UCODE_PATH BWI_FW_PATH "ucode%d.fw"
296 #define BWI_FW_PCM_PATH BWI_FW_PATH "pcm%d.fw"
297 #define BWI_FW_IV_PATH BWI_FW_PATH "b0g0initvals%d.fw"
298 #define BWI_FW_IV_EXT_PATH BWI_FW_PATH "b0g0bsinitvals%d.fw"
309 #define BWI_FW_IV_OFS_MASK __BITS(14, 0)
310 #define BWI_FW_IV_IS_32BIT __BIT(15)
313 uint8_t l_flags; /* BWI_LED_F_ */
314 uint8_t l_act; /* BWI_LED_ACT_ */
318 #define BWI_LED_F_ACTLOW 0x1
319 #define BWI_LED_F_BLINK 0x2
320 #define BWI_LED_F_POLLABLE 0x4
321 #define BWI_LED_F_SLOW 0x8
323 enum bwi_clock_mode {
330 uint32_t rw_flags; /* BWI_REGWIN_F_ */
331 uint16_t rw_type; /* BWI_REGWIN_T_ */
336 #define BWI_REGWIN_F_EXIST 0x1
338 #define BWI_CREATE_REGWIN(rw, id, type, rev) \
340 (rw)->rw_flags = BWI_REGWIN_F_EXIST; \
341 (rw)->rw_type = (type); \
342 (rw)->rw_id = (id); \
343 (rw)->rw_rev = (rev); \
346 #define BWI_REGWIN_EXIST(rw) ((rw)->rw_flags & BWI_REGWIN_F_EXIST)
347 #define BWI_GPIO_REGWIN(sc) \
348 (BWI_REGWIN_EXIST(&(sc)->sc_com_regwin) ? \
349 &(sc)->sc_com_regwin : &(sc)->sc_bus_regwin)
354 enum ieee80211_phymode phy_mode;
358 uint32_t phy_flags; /* BWI_PHY_F_ */
359 uint16_t phy_tbl_ctrl;
360 uint16_t phy_tbl_data_lo;
361 uint16_t phy_tbl_data_hi;
363 void (*phy_init)(struct bwi_mac *);
366 #define BWI_PHY_F_CALIBRATED 0x1
367 #define BWI_PHY_F_LINKED 0x2
368 #define BWI_CLEAR_PHY_FLAGS (BWI_PHY_F_CALIBRATED)
370 /* TX power control */
372 uint16_t bbp_atten; /* BBP attenuation: 4bits */
373 uint16_t rf_atten; /* RF attenuation */
374 uint16_t tp_ctrl1; /* ??: 3bits */
375 uint16_t tp_ctrl2; /* ??: 4bits */
378 #define BWI_RF_ATTEN_FACTOR 4
379 #define BWI_RF_ATTEN_MAX0 9
380 #define BWI_RF_ATTEN_MAX1 31
381 #define BWI_BBP_ATTEN_MAX 11
382 #define BWI_TPCTL1_MAX 7
390 uint16_t rf_type; /* BWI_RF_T_ */
394 uint32_t rf_flags; /* BWI_RF_F_ */
396 #define BWI_RFLO_MAX 56
397 struct bwi_rf_lo rf_lo[BWI_RFLO_MAX];
398 uint8_t rf_lo_used[8];
400 #define BWI_INVALID_NRSSI -1000
401 int16_t rf_nrssi[2]; /* Narrow RSSI */
402 int32_t rf_nrssi_slope;
404 #define BWI_NRSSI_TBLSZ 64
405 int8_t rf_nrssi_table[BWI_NRSSI_TBLSZ];
407 uint16_t rf_lo_gain; /* loopback gain */
408 uint16_t rf_rx_gain; /* TRSW RX gain */
410 uint16_t rf_calib; /* RF calibration value */
411 u_int rf_curchan; /* current channel */
415 void (*rf_off)(struct bwi_mac *);
416 void (*rf_on)(struct bwi_mac *);
418 void (*rf_set_nrssi_thr)(struct bwi_mac *);
419 void (*rf_calc_nrssi_slope)(struct bwi_mac *);
422 const struct bwi_rxbuf_hdr *);
424 void (*rf_lo_update)(struct bwi_mac *);
426 #define BWI_TSSI_MAX 64
427 int8_t rf_txpower_map0[BWI_TSSI_MAX];
428 /* Indexed by TSSI */
431 int8_t rf_txpower_map[BWI_TSSI_MAX];
436 int rf_txpower_max; /* dBm */
438 int rf_ant_mode; /* BWI_ANT_MODE_ */
441 #define BWI_RF_F_INITED 0x1
442 #define BWI_RF_F_ON 0x2
443 #define BWI_RF_CLEAR_FLAGS (BWI_RF_F_INITED)
445 #define BWI_ANT_MODE_0 0
446 #define BWI_ANT_MODE_1 1
447 #define BWI_ANT_MODE_UNKN 2
448 #define BWI_ANT_MODE_AUTO 3
454 struct bwi_regwin mac_regwin; /* MUST be first field */
455 #define mac_rw_flags mac_regwin.rw_flags
456 #define mac_type mac_regwin.rw_type
457 #define mac_id mac_regwin.rw_id
458 #define mac_rev mac_regwin.rw_rev
460 struct bwi_softc *mac_sc;
462 struct bwi_phy mac_phy; /* PHY I/F */
463 struct bwi_rf mac_rf; /* RF I/F */
465 struct bwi_tpctl mac_tpctl; /* TX power control */
466 uint32_t mac_flags; /* BWI_MAC_F_ */
468 struct fw_image *mac_ucode;
469 struct fw_image *mac_pcm;
470 struct fw_image *mac_iv;
471 struct fw_image *mac_iv_ext;
474 #define BWI_MAC_F_BSWAP 0x1
475 #define BWI_MAC_F_TPCTL_INITED 0x2
476 #define BWI_MAC_F_HAS_TXSTATS 0x4
477 #define BWI_MAC_F_INITED 0x8
478 #define BWI_MAC_F_ENABLED 0x10
479 #define BWI_MAC_F_LOCKED 0x20 /* for debug */
480 #define BWI_MAC_F_TPCTL_ERROR 0x40
481 #define BWI_MAC_F_PHYE_RESET 0x80
483 #define BWI_CREATE_MAC(mac, sc, id, rev) \
485 BWI_CREATE_REGWIN(&(mac)->mac_regwin, \
489 (mac)->mac_sc = (sc); \
492 #define BWI_MAC_MAX 2
493 #define BWI_LED_MAX 4
496 BWI_BUS_SPACE_30BIT = 1,
501 #define BWI_TX_RADIOTAP_PRESENT \
502 ((1 << IEEE80211_RADIOTAP_FLAGS) | \
503 (1 << IEEE80211_RADIOTAP_RATE) | \
504 (1 << IEEE80211_RADIOTAP_CHANNEL))
506 struct bwi_tx_radiotap_hdr {
507 struct ieee80211_radiotap_header wt_ihdr;
510 uint16_t wt_chan_freq;
511 uint16_t wt_chan_flags;
514 #define BWI_RX_RADIOTAP_PRESENT \
515 ((1 << IEEE80211_RADIOTAP_TSFT) | \
516 (1 << IEEE80211_RADIOTAP_FLAGS) | \
517 (1 << IEEE80211_RADIOTAP_RATE) | \
518 (1 << IEEE80211_RADIOTAP_CHANNEL) | \
519 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) | \
520 (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE))
522 struct bwi_rx_radiotap_hdr {
523 struct ieee80211_radiotap_header wr_ihdr;
527 uint16_t wr_chan_freq;
528 uint16_t wr_chan_flags;
535 struct ieee80211com sc_ic;
536 uint32_t sc_flags; /* BWI_F_ */
539 uint32_t sc_cap; /* BWI_CAP_ */
540 uint16_t sc_bbp_id; /* BWI_BBPID_ */
544 uint8_t sc_pci_revid;
545 uint16_t sc_pci_subvid;
546 uint16_t sc_pci_subdid;
548 uint16_t sc_card_flags; /* BWI_CARD_F_ */
549 uint16_t sc_pwron_delay;
553 struct resource *sc_irq_res;
557 struct resource *sc_mem_res;
558 bus_space_tag_t sc_mem_bt;
559 bus_space_handle_t sc_mem_bh;
561 struct callout sc_scan_ch;
562 struct callout sc_calib_ch;
564 struct bwi_regwin *sc_cur_regwin;
565 struct bwi_regwin sc_com_regwin;
566 struct bwi_regwin sc_bus_regwin;
569 struct bwi_mac sc_mac[BWI_MAC_MAX];
573 enum bwi_txpwrcb_type sc_txpwrcb_type;
577 struct bwi_led *sc_blink_led;
578 struct callout sc_led_blink_ch;
579 int sc_led_blink_offdur;
580 struct bwi_led sc_leds[BWI_LED_MAX];
582 enum bwi_bus_space sc_bus_space;
583 bus_dma_tag_t sc_parent_dtag;
585 bus_dma_tag_t sc_buf_dtag;
586 struct bwi_txbuf_data sc_tx_bdata[BWI_TX_NRING];
587 struct bwi_rxbuf_data sc_rx_bdata;
589 bus_dma_tag_t sc_txring_dtag;
590 struct bwi_ring_data sc_tx_rdata[BWI_TX_NRING];
591 bus_dma_tag_t sc_rxring_dtag;
592 struct bwi_ring_data sc_rx_rdata;
594 struct bwi_txstats_data *sc_txstats;
598 struct bpf_if *sc_drvbpf;
601 struct bwi_tx_radiotap_hdr u_tx_th;
602 uint8_t u_pad[IEEE80211_RADIOTAP_HDRLEN];
604 #define sc_tx_th sc_u_tx_th.u_tx_th
608 struct bwi_rx_radiotap_hdr u_rx_th;
609 uint8_t u_pad[IEEE80211_RADIOTAP_HDRLEN];
611 #define sc_rx_th sc_u_rx_th.u_rx_th
615 (struct ieee80211com *,
616 enum ieee80211_state, int);
618 int (*sc_init_tx_ring)(struct bwi_softc *, int);
619 void (*sc_free_tx_ring)(struct bwi_softc *, int);
621 int (*sc_init_rx_ring)(struct bwi_softc *);
622 void (*sc_free_rx_ring)(struct bwi_softc *);
624 int (*sc_init_txstats)(struct bwi_softc *);
625 void (*sc_free_txstats)(struct bwi_softc *);
627 void (*sc_setup_rxdesc)
628 (struct bwi_softc *, int, bus_addr_t, int);
629 int (*sc_rxeof)(struct bwi_softc *);
631 void (*sc_setup_txdesc)
632 (struct bwi_softc *, struct bwi_ring_data *,
633 int, bus_addr_t, int);
635 (struct bwi_softc *, uint32_t, int);
637 void (*sc_txeof_status)(struct bwi_softc *);
639 struct ieee80211_onoe_param sc_onoe_param;
644 int sc_fw_version; /* BWI_FW_VERSION[34] */
645 int sc_dwell_time; /* milliseconds */
646 uint32_t sc_debug; /* BWI_DBG_ */
652 #define BWI_F_BUS_INITED 0x1
653 #define BWI_F_PROMISC 0x2
655 #define BWI_DBG_MAC 0x00000001
656 #define BWI_DBG_RF 0x00000002
657 #define BWI_DBG_PHY 0x00000004
658 #define BWI_DBG_MISC 0x00000008
660 #define BWI_DBG_ATTACH 0x00000010
661 #define BWI_DBG_INIT 0x00000020
662 #define BWI_DBG_FIRMWARE 0x00000040
663 #define BWI_DBG_80211 0x00000080
664 #define BWI_DBG_TXPOWER 0x00000100
665 #define BWI_DBG_INTR 0x00000200
666 #define BWI_DBG_RX 0x00000400
667 #define BWI_DBG_TX 0x00000800
668 #define BWI_DBG_TXEOF 0x00001000
669 #define BWI_DBG_LED 0x00002000
671 uint16_t bwi_read_sprom(struct bwi_softc *, uint16_t);
672 int bwi_regwin_switch(struct bwi_softc *, struct bwi_regwin *,
673 struct bwi_regwin **);
674 int bwi_regwin_is_enabled(struct bwi_softc *, struct bwi_regwin *);
675 void bwi_regwin_enable(struct bwi_softc *, struct bwi_regwin *,
677 void bwi_regwin_disable(struct bwi_softc *, struct bwi_regwin *,
679 int bwi_bus_init(struct bwi_softc *, struct bwi_mac *);
680 uint8_t bwi_rate2plcp(uint8_t); /* XXX belongs to 802.11 */
682 #define abs(a) __builtin_abs(a)
684 #endif /* !_IF_BWIVAR_H */