sys/dev/drm/i915/i915_dma.c

   1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #include <linux/async.h>
  30 #include <drm/drmP.h>
  31 #include "intel_drv.h"
  32 #include <drm/i915_drm.h>
  33 #include <drm/drm_legacy.h>
  34 #include "i915_drv.h"
  35 #include "i915_vgpu.h"
  36 #include "intel_ringbuffer.h"
  37 #include <linux/workqueue.h>
  38
  39
  40 static int i915_getparam(struct drm_device *dev, void *data,
  41                          struct drm_file *file_priv)
  42 {
  43         struct drm_i915_private *dev_priv = dev->dev_private;
  44         drm_i915_getparam_t *param = data;
  45         int value;
  46
  47         switch (param->param) {
  48         case I915_PARAM_IRQ_ACTIVE:
  49         case I915_PARAM_ALLOW_BATCHBUFFER:
  50         case I915_PARAM_LAST_DISPATCH:
  51                 /* Reject all old ums/dri params. */
  52                 return -ENODEV;
  53         case I915_PARAM_CHIPSET_ID:
  54                 value = dev->pdev->device;
  55                 break;
  56         case I915_PARAM_REVISION:
  57                 value = dev->pdev->revision;
  58                 break;
  59         case I915_PARAM_HAS_GEM:
  60                 value = 1;
  61                 break;
  62         case I915_PARAM_NUM_FENCES_AVAIL:
  63                 value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
  64                 break;
  65         case I915_PARAM_HAS_OVERLAY:
  66                 value = dev_priv->overlay ? 1 : 0;
  67                 break;
  68         case I915_PARAM_HAS_PAGEFLIPPING:
  69                 value = 1;
  70                 break;
  71         case I915_PARAM_HAS_EXECBUF2:
  72                 /* depends on GEM */
  73                 value = 1;
  74                 break;
  75         case I915_PARAM_HAS_BSD:
  76                 value = intel_ring_initialized(&dev_priv->ring[VCS]);
  77                 break;
  78         case I915_PARAM_HAS_BLT:
  79                 value = intel_ring_initialized(&dev_priv->ring[BCS]);
  80                 break;
  81         case I915_PARAM_HAS_VEBOX:
  82                 value = intel_ring_initialized(&dev_priv->ring[VECS]);
  83                 break;
  84         case I915_PARAM_HAS_BSD2:
  85                 value = intel_ring_initialized(&dev_priv->ring[VCS2]);
  86                 break;
  87         case I915_PARAM_HAS_RELAXED_FENCING:
  88                 value = 1;
  89                 break;
  90         case I915_PARAM_HAS_COHERENT_RINGS:
  91                 value = 1;
  92                 break;
  93         case I915_PARAM_HAS_EXEC_CONSTANTS:
  94                 value = INTEL_INFO(dev)->gen >= 4;
  95                 break;
  96         case I915_PARAM_HAS_RELAXED_DELTA:
  97                 value = 1;
  98                 break;
  99         case I915_PARAM_HAS_GEN7_SOL_RESET:
 100                 value = 1;
 101                 break;
 102         case I915_PARAM_HAS_LLC:
 103                 value = HAS_LLC(dev);
 104                 break;
 105         case I915_PARAM_HAS_WT:
 106                 value = HAS_WT(dev);
 107                 break;
 108         case I915_PARAM_HAS_ALIASING_PPGTT:
 109                 value = USES_PPGTT(dev);
 110                 break;
 111         case I915_PARAM_HAS_WAIT_TIMEOUT:
 112                 value = 1;
 113                 break;
 114         case I915_PARAM_HAS_SEMAPHORES:
 115                 value = i915_semaphore_is_enabled(dev);
 116                 break;
 117         case I915_PARAM_HAS_PINNED_BATCHES:
 118                 value = 1;
 119                 break;
 120         case I915_PARAM_HAS_EXEC_NO_RELOC:
 121                 value = 1;
 122                 break;
 123         case I915_PARAM_HAS_EXEC_HANDLE_LUT:
 124                 value = 1;
 125                 break;
 126         case I915_PARAM_CMD_PARSER_VERSION:
 127                 value = i915_cmd_parser_get_version();
 128                 break;
 129         case I915_PARAM_HAS_COHERENT_PHYS_GTT:
 130                 value = 1;
 131                 break;
 132         case I915_PARAM_SUBSLICE_TOTAL:
 133                 value = INTEL_INFO(dev)->subslice_total;
 134                 if (!value)
 135                         return -ENODEV;
 136                 break;
 137         case I915_PARAM_EU_TOTAL:
 138                 value = INTEL_INFO(dev)->eu_total;
 139                 if (!value)
 140                         return -ENODEV;
 141                 break;
 142         case I915_PARAM_HAS_GPU_RESET:
 143                 value = i915.enable_hangcheck &&
 144                         intel_has_gpu_reset(dev);
 145                 break;
 146         case I915_PARAM_HAS_RESOURCE_STREAMER:
 147                 value = HAS_RESOURCE_STREAMER(dev);
 148                 break;
 149         default:
 150                 DRM_DEBUG("Unknown parameter %d\n", param->param);
 151                 return -EINVAL;
 152         }
 153
 154         if (copy_to_user(param->value, &value, sizeof(int))) {
 155                 DRM_ERROR("copy_to_user failed\n");
 156                 return -EFAULT;
 157         }
 158
 159         return 0;
 160 }
 161
 162 static int i915_setparam(struct drm_device *dev, void *data,
 163                          struct drm_file *file_priv)
 164 {
 165         struct drm_i915_private *dev_priv = dev->dev_private;
 166         drm_i915_setparam_t *param = data;
 167
 168         switch (param->param) {
 169         case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
 170         case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
 171         case I915_SETPARAM_ALLOW_BATCHBUFFER:
 172                 /* Reject all old ums/dri params. */
 173                 return -ENODEV;
 174
 175         case I915_SETPARAM_NUM_USED_FENCES:
 176                 if (param->value > dev_priv->num_fence_regs ||
 177                     param->value < 0)
 178                         return -EINVAL;
 179                 /* Userspace can use first N regs */
 180                 dev_priv->fence_reg_start = param->value;
 181                 break;
 182         default:
 183                 DRM_DEBUG_DRIVER("unknown parameter %d\n",
 184                                         param->param);
 185                 return -EINVAL;
 186         }
 187
 188         return 0;
 189 }
 190
 191 static int i915_get_bridge_dev(struct drm_device *dev)
 192 {
 193         struct drm_i915_private *dev_priv = dev->dev_private;
 194         static struct pci_dev i915_bridge_dev;
 195
 196         i915_bridge_dev.dev = pci_find_dbsf(0, 0, 0, 0);
 197         if (!i915_bridge_dev.dev) {
 198                 DRM_ERROR("bridge device not found\n");
 199                 return -1;
 200         }
 201
 202         dev_priv->bridge_dev = &i915_bridge_dev;
 203         return 0;
 204 }
 205
 206 #define MCHBAR_I915 0x44
 207 #define MCHBAR_I965 0x48
 208 #define MCHBAR_SIZE (4*4096)
 209
 210 #define DEVEN_REG 0x54
 211 #define   DEVEN_MCHBAR_EN (1 << 28)
 212
 213 /* Allocate space for the MCH regs if needed, return nonzero on error */
 214 static int
 215 intel_alloc_mchbar_resource(struct drm_device *dev)
 216 {
 217         struct drm_i915_private *dev_priv = dev->dev_private;
 218         int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 219         device_t vga;
 220         u32 temp_lo, temp_hi = 0;
 221         u64 mchbar_addr;
 222
 223         if (INTEL_INFO(dev)->gen >= 4)
 224                 pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
 225         pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
 226         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
 227
 228         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
 229 #ifdef CONFIG_PNP
 230         if (mchbar_addr &&
 231             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
 232                 return 0;
 233 #endif
 234
 235         /* Get some space for it */
 236         vga = device_get_parent(dev->dev);
 237         dev_priv->mch_res_rid = 0x100;
 238         dev_priv->mch_res = BUS_ALLOC_RESOURCE(device_get_parent(vga),
 239             dev->dev, SYS_RES_MEMORY, &dev_priv->mch_res_rid, 0, ~0UL,
 240             MCHBAR_SIZE, RF_ACTIVE | RF_SHAREABLE, -1);
 241         if (dev_priv->mch_res == NULL) {
 242                 DRM_ERROR("failed mchbar resource alloc\n");
 243                 return (-ENOMEM);
 244         }
 245
 246         if (INTEL_INFO(dev)->gen >= 4)
 247                 pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
 248                                        upper_32_bits(rman_get_start(dev_priv->mch_res)));
 249
 250         pci_write_config_dword(dev_priv->bridge_dev, reg,
 251                                lower_32_bits(rman_get_start(dev_priv->mch_res)));
 252         return 0;
 253 }
 254
 255 /* Setup MCHBAR if possible, return true if we should disable it again */
 256 static void
 257 intel_setup_mchbar(struct drm_device *dev)
 258 {
 259         struct drm_i915_private *dev_priv = dev->dev_private;
 260         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 261         u32 temp;
 262         bool enabled;
 263
 264         if (IS_VALLEYVIEW(dev))
 265                 return;
 266
 267         dev_priv->mchbar_need_disable = false;
 268
 269         if (IS_I915G(dev) || IS_I915GM(dev)) {
 270                 pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
 271                 enabled = !!(temp & DEVEN_MCHBAR_EN);
 272         } else {
 273                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 274                 enabled = temp & 1;
 275         }
 276
 277         /* If it's already enabled, don't have to do anything */
 278         if (enabled)
 279                 return;
 280
 281         if (intel_alloc_mchbar_resource(dev))
 282                 return;
 283
 284         dev_priv->mchbar_need_disable = true;
 285
 286         /* Space is allocated or reserved, so enable it. */
 287         if (IS_I915G(dev) || IS_I915GM(dev)) {
 288                 pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
 289                                        temp | DEVEN_MCHBAR_EN);
 290         } else {
 291                 pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 292                 pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
 293         }
 294 }
 295
 296 static void
 297 intel_teardown_mchbar(struct drm_device *dev)
 298 {
 299         struct drm_i915_private *dev_priv = dev->dev_private;
 300         int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 301         device_t vga;
 302         u32 temp;
 303
 304         if (dev_priv->mchbar_need_disable) {
 305                 if (IS_I915G(dev) || IS_I915GM(dev)) {
 306                         pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
 307                         temp &= ~DEVEN_MCHBAR_EN;
 308                         pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
 309                 } else {
 310                         pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
 311                         temp &= ~1;
 312                         pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
 313                 }
 314         }
 315
 316         if (dev_priv->mch_res != NULL) {
 317                 vga = device_get_parent(dev->dev);
 318                 BUS_DEACTIVATE_RESOURCE(device_get_parent(vga), dev->dev,
 319                     SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
 320                 BUS_RELEASE_RESOURCE(device_get_parent(vga), dev->dev,
 321                     SYS_RES_MEMORY, dev_priv->mch_res_rid, dev_priv->mch_res);
 322                 dev_priv->mch_res = NULL;
 323         }
 324 }
 325
 326 #if 0
 327 /* true = enable decode, false = disable decoder */
 328 static unsigned int i915_vga_set_decode(void *cookie, bool state)
 329 {
 330         struct drm_device *dev = cookie;
 331
 332         intel_modeset_vga_set_state(dev, state);
 333         if (state)
 334                 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
 335                        VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 336         else
 337                 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
 338 }
 339
 340 static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
 341 {
 342         struct drm_device *dev = pci_get_drvdata(pdev);
 343         pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
 344
 345         if (state == VGA_SWITCHEROO_ON) {
 346                 pr_info("switched on\n");
 347                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 348                 /* i915 resume handler doesn't set to D0 */
 349                 pci_set_power_state(dev->pdev, PCI_D0);
 350                 i915_resume_legacy(dev);
 351                 dev->switch_power_state = DRM_SWITCH_POWER_ON;
 352         } else {
 353                 pr_err("switched off\n");
 354                 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
 355                 i915_suspend_legacy(dev, pmm);
 356                 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
 357         }
 358 }
 359
 360 static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
 361 {
 362         struct drm_device *dev = pci_get_drvdata(pdev);
 363
 364         /*
 365          * FIXME: open_count is protected by drm_global_mutex but that would lead to
 366          * locking inversion with the driver load path. And the access here is
 367          * completely racy anyway. So don't bother with locking for now.
 368          */
 369         return dev->open_count == 0;
 370 }
 371
 372 static const struct vga_switcheroo_client_ops i915_switcheroo_ops = {
 373         .set_gpu_state = i915_switcheroo_set_state,
 374         .reprobe = NULL,
 375         .can_switch = i915_switcheroo_can_switch,
 376 };
 377 #endif
 378
 379 static int i915_load_modeset_init(struct drm_device *dev)
 380 {
 381         struct drm_i915_private *dev_priv = dev->dev_private;
 382         int ret;
 383
 384         ret = intel_parse_bios(dev);
 385         if (ret)
 386                 DRM_INFO("failed to find VBIOS tables\n");
 387
 388 #if 0
 389         /* If we have > 1 VGA cards, then we need to arbitrate access
 390          * to the common VGA resources.
 391          *
 392          * If we are a secondary display controller (!PCI_DISPLAY_CLASS_VGA),
 393          * then we do not take part in VGA arbitration and the
 394          * vga_client_register() fails with -ENODEV.
 395          */
 396         ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
 397         if (ret && ret != -ENODEV)
 398                 goto out;
 399
 400         intel_register_dsm_handler();
 401
 402         ret = vga_switcheroo_register_client(dev->pdev, &i915_switcheroo_ops, false);
 403         if (ret)
 404                 goto cleanup_vga_client;
 405
 406         /* Initialise stolen first so that we may reserve preallocated
 407          * objects for the BIOS to KMS transition.
 408          */
 409         ret = i915_gem_init_stolen(dev);
 410         if (ret)
 411                 goto cleanup_vga_switcheroo;
 412 #endif
 413
 414         intel_power_domains_init_hw(dev_priv);
 415
 416 #ifdef __DragonFly__
 417         dev_priv->dev->pdev->irq = dev->irq;
 418 #endif
 419         ret = intel_irq_install(dev_priv);
 420         if (ret)
 421                 goto cleanup_gem_stolen;
 422
 423         /* Important: The output setup functions called by modeset_init need
 424          * working irqs for e.g. gmbus and dp aux transfers. */
 425         intel_modeset_init(dev);
 426
 427         ret = i915_gem_init(dev);
 428         if (ret)
 429                 goto cleanup_irq;
 430
 431         intel_modeset_gem_init(dev);
 432
 433         /* Always safe in the mode setting case. */
 434         /* FIXME: do pre/post-mode set stuff in core KMS code */
 435         dev->vblank_disable_allowed = 1;
 436         if (INTEL_INFO(dev)->num_pipes == 0)
 437                 return 0;
 438
 439         ret = intel_fbdev_init(dev);
 440         if (ret)
 441                 goto cleanup_gem;
 442
 443         /* Only enable hotplug handling once the fbdev is fully set up. */
 444         intel_hpd_init(dev_priv);
 445
 446         /*
 447          * Some ports require correctly set-up hpd registers for detection to
 448          * work properly (leading to ghost connected connector status), e.g. VGA
 449          * on gm45.  Hence we can only set up the initial fbdev config after hpd
 450          * irqs are fully enabled. Now we should scan for the initial config
 451          * only once hotplug handling is enabled, but due to screwed-up locking
 452          * around kms/fbdev init we can't protect the fdbev initial config
 453          * scanning against hotplug events. Hence do this first and ignore the
 454          * tiny window where we will loose hotplug notifactions.
 455          */
 456         async_schedule(intel_fbdev_initial_config, dev_priv);
 457
 458         drm_kms_helper_poll_init(dev);
 459
 460         return 0;
 461
 462 cleanup_gem:
 463         mutex_lock(&dev->struct_mutex);
 464         i915_gem_cleanup_ringbuffer(dev);
 465         i915_gem_context_fini(dev);
 466         mutex_unlock(&dev->struct_mutex);
 467 cleanup_irq:
 468         drm_irq_uninstall(dev);
 469 cleanup_gem_stolen:
 470         i915_gem_cleanup_stolen(dev);
 471 #if 0
 472 cleanup_vga_switcheroo:
 473         vga_switcheroo_unregister_client(dev->pdev);
 474 cleanup_vga_client:
 475         vga_client_register(dev->pdev, NULL, NULL, NULL);
 476 out:
 477 #endif
 478         return ret;
 479 }
 480
 481 #if IS_ENABLED(CONFIG_FB)
 482 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 483 {
 484         struct apertures_struct *ap;
 485         struct pci_dev *pdev = dev_priv->dev->pdev;
 486         bool primary;
 487         int ret;
 488
 489         ap = alloc_apertures(1);
 490         if (!ap)
 491                 return -ENOMEM;
 492
 493         ap->ranges[0].base = dev_priv->gtt.mappable_base;
 494         ap->ranges[0].size = dev_priv->gtt.mappable_end;
 495
 496         primary =
 497                 pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
 498
 499         ret = remove_conflicting_framebuffers(ap, "inteldrmfb", primary);
 500
 501         kfree(ap);
 502
 503         return ret;
 504 }
 505 #else
 506 static int i915_kick_out_firmware_fb(struct drm_i915_private *dev_priv)
 507 {
 508         return 0;
 509 }
 510 #endif
 511
 512 #if !defined(CONFIG_VGA_CONSOLE)
 513 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 514 {
 515         return 0;
 516 }
 517 #elif !defined(CONFIG_DUMMY_CONSOLE)
 518 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 519 {
 520         return -ENODEV;
 521 }
 522 #else
 523 static int i915_kick_out_vgacon(struct drm_i915_private *dev_priv)
 524 {
 525         int ret = 0;
 526
 527         DRM_INFO("Replacing VGA console driver\n");
 528
 529         console_lock();
 530         if (con_is_bound(&vga_con))
 531                 ret = do_take_over_console(&dummy_con, 0, MAX_NR_CONSOLES - 1, 1);
 532         if (ret == 0) {
 533                 ret = do_unregister_con_driver(&vga_con);
 534
 535                 /* Ignore "already unregistered". */
 536                 if (ret == -ENODEV)
 537                         ret = 0;
 538         }
 539         console_unlock();
 540
 541         return ret;
 542 }
 543 #endif
 544
 545 static void i915_dump_device_info(struct drm_i915_private *dev_priv)
 546 {
 547 #if 0
 548         const struct intel_device_info *info = &dev_priv->info;
 549
 550 #define PRINT_S(name) "%s"
 551 #define SEP_EMPTY
 552 #define PRINT_FLAG(name) info->name ? #name "," : ""
 553 #define SEP_COMMA ,
 554         DRM_DEBUG_DRIVER("i915 device info: gen=%i, pciid=0x%04x rev=0x%02x flags="
 555                          DEV_INFO_FOR_EACH_FLAG(PRINT_S, SEP_EMPTY),
 556                          info->gen,
 557                          dev_priv->dev->pdev->device,
 558                          dev_priv->dev->pdev->revision,
 559                          DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG, SEP_COMMA));
 560 #undef PRINT_S
 561 #undef SEP_EMPTY
 562 #undef PRINT_FLAG
 563 #undef SEP_COMMA
 564 #endif
 565 }
 566
 567 static void cherryview_sseu_info_init(struct drm_device *dev)
 568 {
 569         struct drm_i915_private *dev_priv = dev->dev_private;
 570         struct intel_device_info *info;
 571         u32 fuse, eu_dis;
 572
 573         info = (struct intel_device_info *)&dev_priv->info;
 574         fuse = I915_READ(CHV_FUSE_GT);
 575
 576         info->slice_total = 1;
 577
 578         if (!(fuse & CHV_FGT_DISABLE_SS0)) {
 579                 info->subslice_per_slice++;
 580                 eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK |
 581                                  CHV_FGT_EU_DIS_SS0_R1_MASK);
 582                 info->eu_total += 8 - hweight32(eu_dis);
 583         }
 584
 585         if (!(fuse & CHV_FGT_DISABLE_SS1)) {
 586                 info->subslice_per_slice++;
 587                 eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK |
 588                                  CHV_FGT_EU_DIS_SS1_R1_MASK);
 589                 info->eu_total += 8 - hweight32(eu_dis);
 590         }
 591
 592         info->subslice_total = info->subslice_per_slice;
 593         /*
 594          * CHV expected to always have a uniform distribution of EU
 595          * across subslices.
 596         */
 597         info->eu_per_subslice = info->subslice_total ?
 598                                 info->eu_total / info->subslice_total :
 599                                 0;
 600         /*
 601          * CHV supports subslice power gating on devices with more than
 602          * one subslice, and supports EU power gating on devices with
 603          * more than one EU pair per subslice.
 604         */
 605         info->has_slice_pg = 0;
 606         info->has_subslice_pg = (info->subslice_total > 1);
 607         info->has_eu_pg = (info->eu_per_subslice > 2);
 608 }
 609
 610 static void gen9_sseu_info_init(struct drm_device *dev)
 611 {
 612         struct drm_i915_private *dev_priv = dev->dev_private;
 613         struct intel_device_info *info;
 614         int s_max = 3, ss_max = 4, eu_max = 8;
 615         int s, ss;
 616         u32 fuse2, s_enable, ss_disable, eu_disable;
 617         u8 eu_mask = 0xff;
 618
 619         /*
 620          * BXT has a single slice. BXT also has at most 6 EU per subslice,
 621          * and therefore only the lowest 6 bits of the 8-bit EU disable
 622          * fields are valid.
 623         */
 624         if (IS_BROXTON(dev)) {
 625                 s_max = 1;
 626                 eu_max = 6;
 627                 eu_mask = 0x3f;
 628         }
 629
 630         info = (struct intel_device_info *)&dev_priv->info;
 631         fuse2 = I915_READ(GEN8_FUSE2);
 632         s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >>
 633                    GEN8_F2_S_ENA_SHIFT;
 634         ss_disable = (fuse2 & GEN9_F2_SS_DIS_MASK) >>
 635                      GEN9_F2_SS_DIS_SHIFT;
 636
 637         info->slice_total = hweight32(s_enable);
 638         /*
 639          * The subslice disable field is global, i.e. it applies
 640          * to each of the enabled slices.
 641         */
 642         info->subslice_per_slice = ss_max - hweight32(ss_disable);
 643         info->subslice_total = info->slice_total *
 644                                info->subslice_per_slice;
 645
 646         /*
 647          * Iterate through enabled slices and subslices to
 648          * count the total enabled EU.
 649         */
 650         for (s = 0; s < s_max; s++) {
 651                 if (!(s_enable & (0x1 << s)))
 652                         /* skip disabled slice */
 653                         continue;
 654
 655                 eu_disable = I915_READ(GEN9_EU_DISABLE(s));
 656                 for (ss = 0; ss < ss_max; ss++) {
 657                         int eu_per_ss;
 658
 659                         if (ss_disable & (0x1 << ss))
 660                                 /* skip disabled subslice */
 661                                 continue;
 662
 663                         eu_per_ss = eu_max - hweight8((eu_disable >> (ss*8)) &
 664                                                       eu_mask);
 665
 666                         /*
 667                          * Record which subslice(s) has(have) 7 EUs. we
 668                          * can tune the hash used to spread work among
 669                          * subslices if they are unbalanced.
 670                          */
 671                         if (eu_per_ss == 7)
 672                                 info->subslice_7eu[s] |= 1 << ss;
 673
 674                         info->eu_total += eu_per_ss;
 675                 }
 676         }
 677
 678         /*
 679          * SKL is expected to always have a uniform distribution
 680          * of EU across subslices with the exception that any one
 681          * EU in any one subslice may be fused off for die
 682          * recovery. BXT is expected to be perfectly uniform in EU
 683          * distribution.
 684         */
 685         info->eu_per_subslice = info->subslice_total ?
 686                                 DIV_ROUND_UP(info->eu_total,
 687                                              info->subslice_total) : 0;
 688         /*
 689          * SKL supports slice power gating on devices with more than
 690          * one slice, and supports EU power gating on devices with
 691          * more than one EU pair per subslice. BXT supports subslice
 692          * power gating on devices with more than one subslice, and
 693          * supports EU power gating on devices with more than one EU
 694          * pair per subslice.
 695         */
 696         info->has_slice_pg = (IS_SKYLAKE(dev) && (info->slice_total > 1));
 697         info->has_subslice_pg = (IS_BROXTON(dev) && (info->subslice_total > 1));
 698         info->has_eu_pg = (info->eu_per_subslice > 2);
 699 }
 700
 701 /*
 702  * Determine various intel_device_info fields at runtime.
 703  *
 704  * Use it when either:
 705  *   - it's judged too laborious to fill n static structures with the limit
 706  *     when a simple if statement does the job,
 707  *   - run-time checks (eg read fuse/strap registers) are needed.
 708  *
 709  * This function needs to be called:
 710  *   - after the MMIO has been setup as we are reading registers,
 711  *   - after the PCH has been detected,
 712  *   - before the first usage of the fields it can tweak.
 713  */
 714 static void intel_device_info_runtime_init(struct drm_device *dev)
 715 {
 716         struct drm_i915_private *dev_priv = dev->dev_private;
 717         struct intel_device_info *info;
 718         enum i915_pipe pipe;
 719
 720         info = (struct intel_device_info *)&dev_priv->info;
 721
 722         /*
 723          * Skylake and Broxton currently don't expose the topmost plane as its
 724          * use is exclusive with the legacy cursor and we only want to expose
 725          * one of those, not both. Until we can safely expose the topmost plane
 726          * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
 727          * we don't expose the topmost plane at all to prevent ABI breakage
 728          * down the line.
 729          */
 730         if (IS_BROXTON(dev)) {
 731                 info->num_sprites[PIPE_A] = 2;
 732                 info->num_sprites[PIPE_B] = 2;
 733                 info->num_sprites[PIPE_C] = 1;
 734         } else if (IS_VALLEYVIEW(dev))
 735                 for_each_pipe(dev_priv, pipe)
 736                         info->num_sprites[pipe] = 2;
 737         else
 738                 for_each_pipe(dev_priv, pipe)
 739                         info->num_sprites[pipe] = 1;
 740
 741         if (i915.disable_display) {
 742                 DRM_INFO("Display disabled (module parameter)\n");
 743                 info->num_pipes = 0;
 744         } else if (info->num_pipes > 0 &&
 745                    (INTEL_INFO(dev)->gen == 7 || INTEL_INFO(dev)->gen == 8) &&
 746                    !IS_VALLEYVIEW(dev)) {
 747                 u32 fuse_strap = I915_READ(FUSE_STRAP);
 748                 u32 sfuse_strap = I915_READ(SFUSE_STRAP);
 749
 750                 /*
 751                  * SFUSE_STRAP is supposed to have a bit signalling the display
 752                  * is fused off. Unfortunately it seems that, at least in
 753                  * certain cases, fused off display means that PCH display
 754                  * reads don't land anywhere. In that case, we read 0s.
 755                  *
 756                  * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
 757                  * should be set when taking over after the firmware.
 758                  */
 759                 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
 760                     sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
 761                     (dev_priv->pch_type == PCH_CPT &&
 762                      !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
 763                         DRM_INFO("Display fused off, disabling\n");
 764                         info->num_pipes = 0;
 765                 }
 766         }
 767
 768         /* Initialize slice/subslice/EU info */
 769         if (IS_CHERRYVIEW(dev))
 770                 cherryview_sseu_info_init(dev);
 771         else if (INTEL_INFO(dev)->gen >= 9)
 772                 gen9_sseu_info_init(dev);
 773
 774         DRM_DEBUG_DRIVER("slice total: %u\n", info->slice_total);
 775         DRM_DEBUG_DRIVER("subslice total: %u\n", info->subslice_total);
 776         DRM_DEBUG_DRIVER("subslice per slice: %u\n", info->subslice_per_slice);
 777         DRM_DEBUG_DRIVER("EU total: %u\n", info->eu_total);
 778         DRM_DEBUG_DRIVER("EU per subslice: %u\n", info->eu_per_subslice);
 779         DRM_DEBUG_DRIVER("has slice power gating: %s\n",
 780                          info->has_slice_pg ? "y" : "n");
 781         DRM_DEBUG_DRIVER("has subslice power gating: %s\n",
 782                          info->has_subslice_pg ? "y" : "n");
 783         DRM_DEBUG_DRIVER("has EU power gating: %s\n",
 784                          info->has_eu_pg ? "y" : "n");
 785 }
 786
 787 /**
 788  * i915_driver_load - setup chip and create an initial config
 789  * @dev: DRM device
 790  * @flags: startup flags
 791  *
 792  * The driver load routine has to do several things:
 793  *   - drive output discovery via intel_modeset_init()
 794  *   - initialize the memory manager
 795  *   - allocate initial config memory
 796  *   - setup the DRM framebuffer with the allocated memory
 797  */
 798 int i915_driver_load(struct drm_device *dev, unsigned long flags)
 799 {
 800         struct drm_i915_private *dev_priv = dev->dev_private;
 801         struct intel_device_info *info, *device_info;
 802         unsigned long base, size;
 803         int ret = 0, mmio_bar, mmio_size;
 804         uint32_t aperture_size;
 805
 806         /* XXX: struct pci_dev */
 807         info = i915_get_device_id(dev->pdev->device);
 808
 809         dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
 810         if (dev_priv == NULL)
 811                 return -ENOMEM;
 812
 813         dev->dev_private = dev_priv;
 814         dev_priv->dev = dev;
 815
 816         /* Setup the write-once "constant" device info */
 817         device_info = (struct intel_device_info *)&dev_priv->info;
 818         memcpy(device_info, info, sizeof(dev_priv->info));
 819         device_info->device_id = dev->pdev->device;
 820
 821         lockinit(&dev_priv->irq_lock, "userirq", 0, LK_CANRECURSE);
 822         lockinit(&dev_priv->gpu_error.lock, "915err", 0, LK_CANRECURSE);
 823         lockinit(&dev_priv->backlight_lock, "i915bl", 0, LK_CANRECURSE);
 824         lockinit(&dev_priv->uncore.lock, "915gt", 0, LK_CANRECURSE);
 825         spin_init(&dev_priv->mm.object_stat_lock, "i915osl");
 826         spin_init(&dev_priv->mmio_flip_lock, "i915mfl");
 827         lockinit(&dev_priv->sb_lock, "i915sbl", 0, LK_CANRECURSE);
 828         lockinit(&dev_priv->modeset_restore_lock, "i915mrl", 0, LK_CANRECURSE);
 829         lockinit(&dev_priv->csr_lock, "i915csr", 0, LK_CANRECURSE);
 830
 831         intel_pm_setup(dev);
 832
 833         intel_display_crc_init(dev);
 834
 835         i915_dump_device_info(dev_priv);
 836
 837         /* Not all pre-production machines fall into this category, only the
 838          * very first ones. Almost everything should work, except for maybe
 839          * suspend/resume. And we don't implement workarounds that affect only
 840          * pre-production machines. */
 841         if (IS_HSW_EARLY_SDV(dev))
 842                 DRM_INFO("This is an early pre-production Haswell machine. "
 843                          "It may not be fully functional.\n");
 844
 845         if (i915_get_bridge_dev(dev)) {
 846                 ret = -EIO;
 847                 goto free_priv;
 848         }
 849
 850         mmio_bar = IS_GEN2(dev) ? 1 : 0;
 851         /* Before gen4, the registers and the GTT are behind different BARs.
 852          * However, from gen4 onwards, the registers and the GTT are shared
 853          * in the same BAR, so we want to restrict this ioremap from
 854          * clobbering the GTT which we want ioremap_wc instead. Fortunately,
 855          * the register BAR remains the same size for all the earlier
 856          * generations up to Ironlake.
 857          */
 858         if (info->gen < 5)
 859                 mmio_size = 512*1024;
 860         else
 861                 mmio_size = 2*1024*1024;
 862
 863         dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, mmio_size);
 864         if (!dev_priv->regs) {
 865                 DRM_ERROR("failed to map registers\n");
 866                 ret = -EIO;
 867                 goto put_bridge;
 868         }
 869 #ifdef __DragonFly__
 870         base = drm_get_resource_start(dev, mmio_bar);
 871         size = drm_get_resource_len(dev, mmio_bar);
 872
 873         ret = drm_legacy_addmap(dev, base, size, _DRM_REGISTERS,
 874             _DRM_KERNEL | _DRM_DRIVER, &dev_priv->mmio_map);
 875 #endif
 876
 877         /* This must be called before any calls to HAS_PCH_* */
 878         intel_detect_pch(dev);
 879
 880         intel_uncore_init(dev);
 881
 882         /* Load CSR Firmware for SKL */
 883         intel_csr_ucode_init(dev);
 884
 885         ret = i915_gem_gtt_init(dev);
 886         if (ret)
 887                 goto out_freecsr;
 888
 889         /* WARNING: Apparently we must kick fbdev drivers before vgacon,
 890          * otherwise the vga fbdev driver falls over. */
 891         ret = i915_kick_out_firmware_fb(dev_priv);
 892         if (ret) {
 893                 DRM_ERROR("failed to remove conflicting framebuffer drivers\n");
 894                 goto out_gtt;
 895         }
 896
 897         ret = i915_kick_out_vgacon(dev_priv);
 898         if (ret) {
 899                 DRM_ERROR("failed to remove conflicting VGA console\n");
 900                 goto out_gtt;
 901         }
 902
 903 #if 0
 904         pci_set_master(dev->pdev);
 905
 906         /* overlay on gen2 is broken and can't address above 1G */
 907         if (IS_GEN2(dev))
 908                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
 909
 910         /* 965GM sometimes incorrectly writes to hardware status page (HWS)
 911          * using 32bit addressing, overwriting memory if HWS is located
 912          * above 4GB.
 913          *
 914          * The documentation also mentions an issue with undefined
 915          * behaviour if any general state is accessed within a page above 4GB,
 916          * which also needs to be handled carefully.
 917          */
 918         if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
 919                 dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(32));
 920 #endif
 921
 922         aperture_size = dev_priv->gtt.mappable_end;
 923
 924         dev_priv->gtt.mappable =
 925                 io_mapping_create_wc(dev_priv->gtt.mappable_base,
 926                                      aperture_size);
 927         if (dev_priv->gtt.mappable == NULL) {
 928                 ret = -EIO;
 929                 goto out_gtt;
 930         }
 931
 932         dev_priv->gtt.mtrr = arch_phys_wc_add(dev_priv->gtt.mappable_base,
 933                                               aperture_size);
 934
 935         /* The i915 workqueue is primarily used for batched retirement of
 936          * requests (and thus managing bo) once the task has been completed
 937          * by the GPU. i915_gem_retire_requests() is called directly when we
 938          * need high-priority retirement, such as waiting for an explicit
 939          * bo.
 940          *
 941          * It is also used for periodic low-priority events, such as
 942          * idle-timers and recording error state.
 943          *
 944          * All tasks on the workqueue are expected to acquire the dev mutex
 945          * so there is no point in running more than one instance of the
 946          * workqueue at any time.  Use an ordered one.
 947          */
 948         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 949         if (dev_priv->wq == NULL) {
 950                 DRM_ERROR("Failed to create our workqueue.\n");
 951                 ret = -ENOMEM;
 952                 goto out_mtrrfree;
 953         }
 954
 955         dev_priv->hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 956         if (dev_priv->hotplug.dp_wq == NULL) {
 957                 DRM_ERROR("Failed to create our dp workqueue.\n");
 958                 ret = -ENOMEM;
 959                 goto out_freewq;
 960         }
 961
 962         dev_priv->gpu_error.hangcheck_wq =
 963                 alloc_ordered_workqueue("i915-hangcheck", 0);
 964         if (dev_priv->gpu_error.hangcheck_wq == NULL) {
 965                 DRM_ERROR("Failed to create our hangcheck workqueue.\n");
 966                 ret = -ENOMEM;
 967                 goto out_freedpwq;
 968         }
 969
 970         intel_irq_init(dev_priv);
 971         intel_uncore_sanitize(dev);
 972
 973         /* Try to make sure MCHBAR is enabled before poking at it */
 974         intel_setup_mchbar(dev);
 975         intel_setup_gmbus(dev);
 976         intel_opregion_setup(dev);
 977
 978         intel_setup_bios(dev);
 979
 980         i915_gem_load(dev);
 981
 982         /* On the 945G/GM, the chipset reports the MSI capability on the
 983          * integrated graphics even though the support isn't actually there
 984          * according to the published specs.  It doesn't appear to function
 985          * correctly in testing on 945G.
 986          * This may be a side effect of MSI having been made available for PEG
 987          * and the registers being closely associated.
 988          *
 989          * According to chipset errata, on the 965GM, MSI interrupts may
 990          * be lost or delayed, but we use them anyways to avoid
 991          * stuck interrupts on some machines.
 992          */
 993 #if 0
 994         if (!IS_I945G(dev) && !IS_I945GM(dev))
 995                 pci_enable_msi(dev->pdev);
 996 #endif
 997
 998         intel_device_info_runtime_init(dev);
 999
1000         if (INTEL_INFO(dev)->num_pipes) {
1001                 ret = drm_vblank_init(dev, INTEL_INFO(dev)->num_pipes);
1002                 if (ret)
1003                         goto out_gem_unload;
1004         }
1005
1006         intel_power_domains_init(dev_priv);
1007
1008         ret = i915_load_modeset_init(dev);
1009         if (ret < 0) {
1010                 DRM_ERROR("failed to init modeset\n");
1011                 goto out_power_well;
1012         }
1013
1014         /*
1015          * Notify a valid surface after modesetting,
1016          * when running inside a VM.
1017          */
1018         if (intel_vgpu_active(dev))
1019                 I915_WRITE(vgtif_reg(display_ready), VGT_DRV_DISPLAY_READY);
1020
1021         i915_setup_sysfs(dev);
1022
1023         if (INTEL_INFO(dev)->num_pipes) {
1024                 /* Must be done after probing outputs */
1025                 intel_opregion_init(dev);
1026 #if 0
1027                 acpi_video_register();
1028 #endif
1029         }
1030
1031         if (IS_GEN5(dev))
1032                 intel_gpu_ips_init(dev_priv);
1033
1034         intel_runtime_pm_enable(dev_priv);
1035
1036         i915_audio_component_init(dev_priv);
1037
1038         return 0;
1039
1040 out_power_well:
1041         intel_power_domains_fini(dev_priv);
1042         drm_vblank_cleanup(dev);
1043 out_gem_unload:
1044
1045         intel_teardown_gmbus(dev);
1046         intel_teardown_mchbar(dev);
1047         pm_qos_remove_request(&dev_priv->pm_qos);
1048         destroy_workqueue(dev_priv->gpu_error.hangcheck_wq);
1049 out_freedpwq:
1050         destroy_workqueue(dev_priv->hotplug.dp_wq);
1051 out_freewq:
1052         destroy_workqueue(dev_priv->wq);
1053 out_mtrrfree:
1054         arch_phys_wc_del(dev_priv->gtt.mtrr);
1055 #if 0
1056         io_mapping_free(dev_priv->gtt.mappable);
1057 #endif
1058 out_gtt:
1059         i915_global_gtt_cleanup(dev);
1060 out_freecsr:
1061         intel_csr_ucode_fini(dev);
1062         intel_uncore_fini(dev);
1063 #if 0
1064         pci_iounmap(dev->pdev, dev_priv->regs);
1065 #endif
1066 put_bridge:
1067         pci_dev_put(dev_priv->bridge_dev);
1068 free_priv:
1069         kfree(dev_priv);
1070         return ret;
1071 }
1072
1073 int i915_driver_unload(struct drm_device *dev)
1074 {
1075         struct drm_i915_private *dev_priv = dev->dev_private;
1076         int ret;
1077
1078         i915_audio_component_cleanup(dev_priv);
1079
1080         ret = i915_gem_suspend(dev);
1081         if (ret) {
1082                 DRM_ERROR("failed to idle hardware: %d\n", ret);
1083                 return ret;
1084         }
1085
1086         intel_power_domains_fini(dev_priv);
1087
1088         intel_gpu_ips_teardown();
1089
1090         i915_teardown_sysfs(dev);
1091
1092 #if 0
1093         WARN_ON(unregister_oom_notifier(&dev_priv->mm.oom_notifier));
1094         unregister_shrinker(&dev_priv->mm.shrinker);
1095
1096         io_mapping_free(dev_priv->gtt.mappable);
1097 #endif
1098         arch_phys_wc_del(dev_priv->gtt.mtrr);
1099
1100 #if 0
1101         acpi_video_unregister();
1102 #endif
1103
1104         intel_fbdev_fini(dev);
1105
1106         drm_vblank_cleanup(dev);
1107
1108         intel_modeset_cleanup(dev);
1109
1110         /*
1111          * free the memory space allocated for the child device
1112          * config parsed from VBT
1113          */
1114         if (dev_priv->vbt.child_dev && dev_priv->vbt.child_dev_num) {
1115                 kfree(dev_priv->vbt.child_dev);
1116                 dev_priv->vbt.child_dev = NULL;
1117                 dev_priv->vbt.child_dev_num = 0;
1118         }
1119
1120 #if 0
1121         vga_switcheroo_unregister_client(dev->pdev);
1122         vga_client_register(dev->pdev, NULL, NULL, NULL);
1123 #endif
1124
1125         /* Free error state after interrupts are fully disabled. */
1126         cancel_delayed_work_sync(&dev_priv->gpu_error.hangcheck_work);
1127 #if 0
1128         i915_destroy_error_state(dev);
1129
1130         if (dev->pdev->msi_enabled)
1131                 pci_disable_msi(dev->pdev);
1132 #endif
1133
1134         intel_opregion_fini(dev);
1135
1136         /* Flush any outstanding unpin_work. */
1137         flush_workqueue(dev_priv->wq);
1138
1139         mutex_lock(&dev->struct_mutex);
1140         i915_gem_cleanup_ringbuffer(dev);
1141         i915_gem_context_fini(dev);
1142         mutex_unlock(&dev->struct_mutex);
1143         intel_fbc_cleanup_cfb(dev_priv);
1144         i915_gem_cleanup_stolen(dev);
1145
1146         intel_csr_ucode_fini(dev);
1147
1148         intel_teardown_gmbus(dev);
1149         intel_teardown_mchbar(dev);
1150
1151         destroy_workqueue(dev_priv->hotplug.dp_wq);
1152         destroy_workqueue(dev_priv->wq);
1153         destroy_workqueue(dev_priv->gpu_error.hangcheck_wq);
1154         pm_qos_remove_request(&dev_priv->pm_qos);
1155
1156         i915_global_gtt_cleanup(dev);
1157
1158         intel_uncore_fini(dev);
1159 #if 0
1160         if (dev_priv->regs != NULL)
1161                 pci_iounmap(dev->pdev, dev_priv->regs);
1162
1163         if (dev_priv->slab)
1164                 kmem_cache_destroy(dev_priv->slab);
1165 #endif
1166
1167         pci_dev_put(dev_priv->bridge_dev);
1168         kfree(dev_priv);
1169
1170         return 0;
1171 }
1172
1173 int i915_driver_open(struct drm_device *dev, struct drm_file *file)
1174 {
1175         int ret;
1176
1177         ret = i915_gem_open(dev, file);
1178         if (ret)
1179                 return ret;
1180
1181         return 0;
1182 }
1183
1184 /**
1185  * i915_driver_lastclose - clean up after all DRM clients have exited
1186  * @dev: DRM device
1187  *
1188  * Take care of cleaning up after all DRM clients have exited.  In the
1189  * mode setting case, we want to restore the kernel's initial mode (just
1190  * in case the last client left us in a bad state).
1191  *
1192  * Additionally, in the non-mode setting case, we'll tear down the GTT
1193  * and DMA structures, since the kernel won't be using them, and clea
1194  * up any GEM state.
1195  */
1196 void i915_driver_lastclose(struct drm_device *dev)
1197 {
1198         intel_fbdev_restore_mode(dev);
1199 #if 0
1200         vga_switcheroo_process_delayed_switch();
1201 #endif
1202 }
1203
1204 void i915_driver_preclose(struct drm_device *dev, struct drm_file *file)
1205 {
1206         mutex_lock(&dev->struct_mutex);
1207         i915_gem_context_close(dev, file);
1208         i915_gem_release(dev, file);
1209         mutex_unlock(&dev->struct_mutex);
1210
1211         intel_modeset_preclose(dev, file);
1212 }
1213
1214 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
1215 {
1216         struct drm_i915_file_private *file_priv = file->driver_priv;
1217
1218         if (file_priv && file_priv->bsd_ring)
1219                 file_priv->bsd_ring = NULL;
1220         kfree(file_priv);
1221 }
1222
1223 static int
1224 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
1225                           struct drm_file *file)
1226 {
1227         return -ENODEV;
1228 }
1229
1230 const struct drm_ioctl_desc i915_ioctls[] = {
1231         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1232         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
1233         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
1234         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
1235         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
1236         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
1237         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH|DRM_RENDER_ALLOW),
1238         DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1239         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1240         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1241         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1242         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
1243         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1244         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1245         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
1246         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
1247         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1248         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1249         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
1250         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1251         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1252         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
1253         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1254         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1255         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1256         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1257         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1258         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
1259         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1260         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1261         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1262         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1263         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1264         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1265         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1266         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1267         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1268         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1269         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
1270         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1271         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1272         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1273         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1274         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
1275         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_AUTH|DRM_UNLOCKED|DRM_RENDER_ALLOW),
1276         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE, i915_gem_context_create_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1277         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1278         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1279         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_get_reset_stats_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1280 #if 0
1281         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1282 #endif
1283         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1284         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_UNLOCKED|DRM_RENDER_ALLOW),
1285 };
1286
1287 int i915_max_ioctl = ARRAY_SIZE(i915_ioctls);