2 * Copyright (c) 1991 The Regents of the University of California.
3 * Copyright (c) 2005,2008 The DragonFly Project.
6 * This code is derived from software contributed to The DragonFly Project
7 * by Matthew Dillon <dillon@backplane.com>
9 * This code is derived from software contributed to Berkeley by
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in
20 * the documentation and/or other materials provided with the
22 * 3. Neither the name of The DragonFly Project nor the names of its
23 * contributors may be used to endorse or promote products derived
24 * from this software without specific, prior written permission.
26 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
27 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
28 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
29 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
30 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
31 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
32 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
33 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
34 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
35 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
36 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
39 * $DragonFly: src/sys/platform/pc64/icu/icu_abi.c,v 1.1 2008/08/29 17:07:16 dillon Exp $
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/kernel.h>
45 #include <sys/machintr.h>
46 #include <sys/interrupt.h>
50 #include <machine/segments.h>
51 #include <machine/md_var.h>
52 #include <machine/intr_machdep.h>
53 #include <machine/globaldata.h>
54 #include <machine/smp.h>
55 #include <machine/msi_var.h>
57 #include <sys/thread2.h>
59 #include <machine_base/icu/elcr_var.h>
61 #include <machine_base/icu/icu.h>
62 #include <machine_base/icu/icu_ipl.h>
63 #include <machine_base/apic/ioapic.h>
66 IDTVEC(icu_intr0), IDTVEC(icu_intr1),
67 IDTVEC(icu_intr2), IDTVEC(icu_intr3),
68 IDTVEC(icu_intr4), IDTVEC(icu_intr5),
69 IDTVEC(icu_intr6), IDTVEC(icu_intr7),
70 IDTVEC(icu_intr8), IDTVEC(icu_intr9),
71 IDTVEC(icu_intr10), IDTVEC(icu_intr11),
72 IDTVEC(icu_intr12), IDTVEC(icu_intr13),
73 IDTVEC(icu_intr14), IDTVEC(icu_intr15);
75 static inthand_t *icu_intr[ICU_HWI_VECTORS] = {
76 &IDTVEC(icu_intr0), &IDTVEC(icu_intr1),
77 &IDTVEC(icu_intr2), &IDTVEC(icu_intr3),
78 &IDTVEC(icu_intr4), &IDTVEC(icu_intr5),
79 &IDTVEC(icu_intr6), &IDTVEC(icu_intr7),
80 &IDTVEC(icu_intr8), &IDTVEC(icu_intr9),
81 &IDTVEC(icu_intr10), &IDTVEC(icu_intr11),
82 &IDTVEC(icu_intr12), &IDTVEC(icu_intr13),
83 &IDTVEC(icu_intr14), &IDTVEC(icu_intr15)
86 static struct icu_irqmap {
87 int im_type; /* ICU_IMT_ */
88 enum intr_trigger im_trig;
90 } icu_irqmaps[MAXCPU][IDT_HWI_VECTORS];
92 static struct lwkt_token icu_irqmap_tok =
93 LWKT_TOKEN_INITIALIZER(icu_irqmap_token);
95 #define ICU_IMT_UNUSED 0 /* KEEP THIS */
96 #define ICU_IMT_RESERVED 1
97 #define ICU_IMT_LEGACY 2
98 #define ICU_IMT_SYSCALL 3
100 #define ICU_IMT_MSIX 5
102 #define ICU_IMT_ISHWI(map) ((map)->im_type != ICU_IMT_RESERVED && \
103 (map)->im_type != ICU_IMT_SYSCALL)
105 extern void ICU_INTREN(int);
106 extern void ICU_INTRDIS(int);
108 extern int imcr_present;
110 static void icu_abi_intr_enable(int);
111 static void icu_abi_intr_disable(int);
112 static void icu_abi_intr_setup(int, int);
113 static void icu_abi_intr_teardown(int);
115 static void icu_abi_legacy_intr_config(int, enum intr_trigger,
117 static int icu_abi_legacy_intr_cpuid(int);
119 static int icu_abi_msi_alloc(int [], int, int);
120 static void icu_abi_msi_release(const int [], int, int);
121 static void icu_abi_msi_map(int, uint64_t *, uint32_t *, int);
122 static int icu_abi_msix_alloc(int *, int);
123 static void icu_abi_msix_release(int, int);
125 static int icu_abi_msi_alloc_intern(int, const char *,
127 static void icu_abi_msi_release_intern(int, const char *,
128 const int [], int, int);
130 static void icu_abi_finalize(void);
131 static void icu_abi_cleanup(void);
132 static void icu_abi_setdefault(void);
133 static void icu_abi_stabilize(void);
134 static void icu_abi_initmap(void);
135 static void icu_abi_rman_setup(struct rman *);
137 struct machintr_abi MachIntrABI_ICU = {
139 .intr_disable = icu_abi_intr_disable,
140 .intr_enable = icu_abi_intr_enable,
141 .intr_setup = icu_abi_intr_setup,
142 .intr_teardown = icu_abi_intr_teardown,
144 .legacy_intr_config = icu_abi_legacy_intr_config,
145 .legacy_intr_cpuid = icu_abi_legacy_intr_cpuid,
147 .msi_alloc = icu_abi_msi_alloc,
148 .msi_release = icu_abi_msi_release,
149 .msi_map = icu_abi_msi_map,
150 .msix_alloc = icu_abi_msix_alloc,
151 .msix_release = icu_abi_msix_release,
153 .finalize = icu_abi_finalize,
154 .cleanup = icu_abi_cleanup,
155 .setdefault = icu_abi_setdefault,
156 .stabilize = icu_abi_stabilize,
157 .initmap = icu_abi_initmap,
158 .rman_setup = icu_abi_rman_setup
161 static int icu_abi_msi_start; /* NOTE: for testing only */
164 * WARNING! SMP builds can use the ICU now so this code must be MP safe.
168 icu_abi_intr_enable(int irq)
170 const struct icu_irqmap *map;
172 KASSERT(irq >= 0 && irq < IDT_HWI_VECTORS,
173 ("icu enable, invalid irq %d\n", irq));
175 map = &icu_irqmaps[mycpuid][irq];
176 KASSERT(ICU_IMT_ISHWI(map),
177 ("icu enable, not hwi irq %d, type %d, cpu%d\n",
178 irq, map->im_type, mycpuid));
179 if (map->im_type != ICU_IMT_LEGACY)
186 icu_abi_intr_disable(int irq)
188 const struct icu_irqmap *map;
190 KASSERT(irq >= 0 && irq < IDT_HWI_VECTORS,
191 ("icu disable, invalid irq %d\n", irq));
193 map = &icu_irqmaps[mycpuid][irq];
194 KASSERT(ICU_IMT_ISHWI(map),
195 ("icu disable, not hwi irq %d, type %d, cpu%d\n",
196 irq, map->im_type, mycpuid));
197 if (map->im_type != ICU_IMT_LEGACY)
204 * Called before interrupts are physically enabled
207 icu_abi_stabilize(void)
211 for (intr = 0; intr < ICU_HWI_VECTORS; ++intr)
213 ICU_INTREN(ICU_IRQ_SLAVE);
217 * Called after interrupts physically enabled but before the
218 * critical section is released.
221 icu_abi_cleanup(void)
223 bzero(mdcpu->gd_ipending, sizeof(mdcpu->gd_ipending));
227 * Called after stablize and cleanup; critical section is not
228 * held and interrupts are not physically disabled.
231 icu_abi_finalize(void)
233 KKASSERT(MachIntrABI.type == MACHINTR_ICU);
234 KKASSERT(!ioapic_enable);
237 * If an IMCR is present, programming bit 0 disconnects the 8259
238 * from the BSP. The 8259 may still be connected to LINT0 on the
241 * If we are running SMP the LAPIC is active, try to use virtual
242 * wire mode so we can use other interrupt sources within the LAPIC
243 * in addition to the 8259.
252 icu_abi_intr_setup(int intr, int flags)
254 const struct icu_irqmap *map;
257 KASSERT(intr >= 0 && intr < IDT_HWI_VECTORS,
258 ("icu setup, invalid irq %d\n", intr));
260 map = &icu_irqmaps[mycpuid][intr];
261 KASSERT(ICU_IMT_ISHWI(map),
262 ("icu setup, not hwi irq %d, type %d, cpu%d\n",
263 intr, map->im_type, mycpuid));
264 if (map->im_type != ICU_IMT_LEGACY)
276 icu_abi_intr_teardown(int intr)
278 const struct icu_irqmap *map;
281 KASSERT(intr >= 0 && intr < IDT_HWI_VECTORS,
282 ("icu teardown, invalid irq %d\n", intr));
284 map = &icu_irqmaps[mycpuid][intr];
285 KASSERT(ICU_IMT_ISHWI(map),
286 ("icu teardown, not hwi irq %d, type %d, cpu%d\n",
287 intr, map->im_type, mycpuid));
288 if (map->im_type != ICU_IMT_LEGACY)
300 icu_abi_setdefault(void)
304 for (intr = 0; intr < ICU_HWI_VECTORS; ++intr) {
305 if (intr == ICU_IRQ_SLAVE)
307 setidt_global(IDT_OFFSET + intr, icu_intr[intr],
308 SDT_SYSIGT, SEL_KPL, 0);
313 icu_abi_initmap(void)
317 kgetenv_int("hw.icu.msi_start", &icu_abi_msi_start);
318 icu_abi_msi_start &= ~0x1f; /* MUST be 32 aligned */
321 * NOTE: ncpus is not ready yet
323 for (cpu = 0; cpu < MAXCPU; ++cpu) {
327 for (i = 0; i < ICU_HWI_VECTORS; ++i)
328 icu_irqmaps[cpu][i].im_type = ICU_IMT_RESERVED;
330 for (i = 0; i < ICU_HWI_VECTORS; ++i)
331 icu_irqmaps[cpu][i].im_type = ICU_IMT_LEGACY;
332 icu_irqmaps[cpu][ICU_IRQ_SLAVE].im_type =
336 for (i = 0; i < ICU_HWI_VECTORS; ++i) {
337 icu_irqmaps[cpu][i].im_trig =
338 elcr_read_trigger(i);
342 * NOTE: Trigger mode does not matter at all
344 for (i = 0; i < ICU_HWI_VECTORS; ++i) {
345 icu_irqmaps[cpu][i].im_trig =
351 for (i = 0; i < IDT_HWI_VECTORS; ++i)
352 icu_irqmaps[cpu][i].im_msi_base = -1;
354 icu_irqmaps[cpu][IDT_OFFSET_SYSCALL - IDT_OFFSET].im_type =
360 icu_abi_legacy_intr_config(int irq, enum intr_trigger trig,
361 enum intr_polarity pola __unused)
363 struct icu_irqmap *map;
365 KKASSERT(trig == INTR_TRIGGER_EDGE || trig == INTR_TRIGGER_LEVEL);
367 KKASSERT(irq >= 0 && irq < IDT_HWI_VECTORS);
368 map = &icu_irqmaps[0][irq];
370 KKASSERT(map->im_type == ICU_IMT_LEGACY);
372 /* TODO: Check whether it is configured or not */
374 if (trig == map->im_trig)
378 kprintf("ICU: irq %d, %s -> %s\n", irq,
379 intr_str_trigger(map->im_trig),
380 intr_str_trigger(trig));
386 kprintf("ICU: no ELCR, skip irq %d config\n", irq);
389 elcr_write_trigger(irq, map->im_trig);
393 icu_abi_legacy_intr_cpuid(int irq __unused)
399 icu_abi_rman_setup(struct rman *rm)
403 KASSERT(rm->rm_cpuid >= 0 && rm->rm_cpuid < MAXCPU,
404 ("invalid rman cpuid %d", rm->rm_cpuid));
407 for (i = 0; i < IDT_HWI_VECTORS; ++i) {
408 const struct icu_irqmap *map = &icu_irqmaps[rm->rm_cpuid][i];
411 if (ICU_IMT_ISHWI(map))
414 if (ICU_IMT_ISHWI(map)) {
419 kprintf("ICU: rman cpu%d %d - %d\n",
420 rm->rm_cpuid, start, end);
422 if (rman_manage_region(rm, start, end)) {
423 panic("rman_manage_region"
424 "(cpu%d %d - %d)", rm->rm_cpuid,
434 kprintf("ICU: rman cpu%d %d - %d\n",
435 rm->rm_cpuid, start, end);
437 if (rman_manage_region(rm, start, end)) {
438 panic("rman_manage_region(cpu%d %d - %d)",
439 rm->rm_cpuid, start, end);
445 icu_abi_msi_alloc_intern(int type, const char *desc,
446 int intrs[], int count, int cpuid)
450 KASSERT(cpuid >= 0 && cpuid < ncpus,
451 ("invalid cpuid %d", cpuid));
453 KASSERT(count > 0 && count <= 32, ("invalid count %d\n", count));
454 KASSERT((count & (count - 1)) == 0,
455 ("count %d is not power of 2\n", count));
457 lwkt_gettoken(&icu_irqmap_tok);
461 * Since IDT_OFFSET is 32, which is the maximum valid 'count',
462 * we do not need to find out the first properly aligned
467 for (i = icu_abi_msi_start; i < IDT_HWI_VECTORS; i += count) {
470 if (icu_irqmaps[cpuid][i].im_type != ICU_IMT_UNUSED)
473 for (j = 1; j < count; ++j) {
474 if (icu_irqmaps[cpuid][i + j].im_type != ICU_IMT_UNUSED)
480 for (j = 0; j < count; ++j) {
481 struct icu_irqmap *map;
484 map = &icu_irqmaps[cpuid][intr];
485 KASSERT(map->im_msi_base < 0,
486 ("intr %d, stale %s-base %d\n",
487 intr, desc, map->im_msi_base));
490 map->im_msi_base = i;
493 msi_setup(intr, cpuid);
496 kprintf("alloc %s intr %d on cpu%d\n",
504 lwkt_reltoken(&icu_irqmap_tok);
510 icu_abi_msi_release_intern(int type, const char *desc,
511 const int intrs[], int count, int cpuid)
513 int i, msi_base = -1, intr_next = -1, mask;
515 KASSERT(cpuid >= 0 && cpuid < ncpus,
516 ("invalid cpuid %d", cpuid));
518 KASSERT(count > 0 && count <= 32, ("invalid count %d\n", count));
521 KASSERT((count & mask) == 0, ("count %d is not power of 2\n", count));
523 lwkt_gettoken(&icu_irqmap_tok);
525 for (i = 0; i < count; ++i) {
526 struct icu_irqmap *map;
529 KASSERT(intr >= 0 && intr < IDT_HWI_VECTORS,
530 ("invalid intr %d\n", intr));
532 map = &icu_irqmaps[cpuid][intr];
533 KASSERT(map->im_type == type,
534 ("try release non-%s intr %d, type %d\n", desc,
535 intr, map->im_type));
536 KASSERT(map->im_msi_base >= 0 && map->im_msi_base <= intr,
537 ("intr %d, invalid %s-base %d\n", intr, desc,
539 KASSERT((map->im_msi_base & mask) == 0,
540 ("intr %d, %s-base %d is not proper aligned %d\n",
541 intr, desc, map->im_msi_base, count));
544 msi_base = map->im_msi_base;
546 KASSERT(map->im_msi_base == msi_base,
547 ("intr %d, inconsistent %s-base, "
549 intr, desc, msi_base, map->im_msi_base));
552 if (intr_next < intr)
555 map->im_type = ICU_IMT_UNUSED;
556 map->im_msi_base = -1;
559 kprintf("release %s intr %d on cpu%d\n",
564 KKASSERT(intr_next > 0);
565 KKASSERT(msi_base >= 0);
568 if (intr_next < IDT_HWI_VECTORS) {
569 const struct icu_irqmap *map = &icu_irqmaps[cpuid][intr_next];
571 if (map->im_type == type) {
572 KASSERT(map->im_msi_base != msi_base,
573 ("more than %d %s was allocated\n", count, desc));
577 lwkt_reltoken(&icu_irqmap_tok);
581 icu_abi_msi_alloc(int intrs[], int count, int cpuid)
583 return icu_abi_msi_alloc_intern(ICU_IMT_MSI, "MSI",
584 intrs, count, cpuid);
588 icu_abi_msi_release(const int intrs[], int count, int cpuid)
590 icu_abi_msi_release_intern(ICU_IMT_MSI, "MSI",
591 intrs, count, cpuid);
595 icu_abi_msix_alloc(int *intr, int cpuid)
597 return icu_abi_msi_alloc_intern(ICU_IMT_MSIX, "MSI-X",
602 icu_abi_msix_release(int intr, int cpuid)
604 icu_abi_msi_release_intern(ICU_IMT_MSIX, "MXI-X",
609 icu_abi_msi_map(int intr, uint64_t *addr, uint32_t *data, int cpuid)
611 const struct icu_irqmap *map;
613 KASSERT(cpuid >= 0 && cpuid < ncpus,
614 ("invalid cpuid %d", cpuid));
616 KASSERT(intr >= 0 && intr < IDT_HWI_VECTORS,
617 ("invalid intr %d\n", intr));
619 lwkt_gettoken(&icu_irqmap_tok);
621 map = &icu_irqmaps[cpuid][intr];
622 KASSERT(map->im_type == ICU_IMT_MSI ||
623 map->im_type == ICU_IMT_MSIX,
624 ("try map non-MSI/MSI-X intr %d, type %d\n", intr, map->im_type));
625 KASSERT(map->im_msi_base >= 0 && map->im_msi_base <= intr,
626 ("intr %d, invalid %s-base %d\n", intr,
627 map->im_type == ICU_IMT_MSI ? "MSI" : "MSI-X",
630 msi_map(map->im_msi_base, addr, data, cpuid);
633 kprintf("map %s intr %d on cpu%d\n",
634 map->im_type == ICU_IMT_MSI ? "MSI" : "MSI-X",
638 lwkt_reltoken(&icu_irqmap_tok);