1 /* $OpenBSD: brgphy.c,v 1.48 2006/05/20 23:03:53 brad Exp $ */
5 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Bill Paul.
18 * 4. Neither the name of the author nor the names of any co-contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
32 * THE POSSIBILITY OF SUCH DAMAGE.
34 * $FreeBSD: src/sys/dev/mii/brgphy.c,v 1.1.2.7 2003/05/11 18:00:55 ps Exp $
38 * Driver for the Broadcom BCR5400 1000baseT PHY. Speed is always
39 * 1000mbps; all we need to negotiate here is full or half duplex.
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/kernel.h>
45 #include <sys/socket.h>
47 #include <sys/sysctl.h>
49 #include <net/ethernet.h>
51 #include <net/if_media.h>
52 #include <net/if_arp.h>
57 #include "brgphyreg.h"
59 #include "miibus_if.h"
61 static int brgphy_probe(device_t);
62 static int brgphy_attach(device_t);
64 static const struct mii_phydesc brgphys[] = {
65 MII_PHYDESC(xxBROADCOM, BCM5400),
66 MII_PHYDESC(xxBROADCOM, BCM5401),
67 MII_PHYDESC(xxBROADCOM, BCM5411),
68 MII_PHYDESC(xxBROADCOM, BCM5421),
69 MII_PHYDESC(xxBROADCOM, BCM54K2),
70 MII_PHYDESC(xxBROADCOM, BCM5461),
71 MII_PHYDESC(xxBROADCOM, BCM5462),
72 MII_PHYDESC(xxBROADCOM, BCM5464),
74 MII_PHYDESC(xxBROADCOM, BCM5701),
75 MII_PHYDESC(xxBROADCOM, BCM5703),
76 MII_PHYDESC(xxBROADCOM, BCM5704),
77 MII_PHYDESC(xxBROADCOM, BCM5705),
78 MII_PHYDESC(xxBROADCOM, BCM5714),
79 MII_PHYDESC(xxBROADCOM, BCM5750),
80 MII_PHYDESC(xxBROADCOM, BCM5752),
81 MII_PHYDESC(xxBROADCOM, BCM5780),
83 MII_PHYDESC(xxBROADCOM2,BCM54XX),
84 MII_PHYDESC(xxBROADCOM2,BCM5481),
85 MII_PHYDESC(xxBROADCOM2,BCM5482),
86 MII_PHYDESC(xxBROADCOM2,BCM5722),
87 MII_PHYDESC(xxBROADCOM2,BCM5755),
88 MII_PHYDESC(xxBROADCOM2,BCM5761),
89 MII_PHYDESC(xxBROADCOM2,BCM5784),
90 MII_PHYDESC(xxBROADCOM2,BCM5787),
92 MII_PHYDESC(xxBROADCOM, BCM5706C),
93 MII_PHYDESC(xxBROADCOM, BCM5708C),
94 MII_PHYDESC(xxBROADCOM2, BCM5709CAX),
95 MII_PHYDESC(xxBROADCOM2, BCM5709C),
97 MII_PHYDESC(xxBROADCOM3, BCM5717C),
98 MII_PHYDESC(xxBROADCOM3, BCM5719C),
99 MII_PHYDESC(xxBROADCOM3, BCM57765),
100 MII_PHYDESC(xxBROADCOM3, BCM57780),
102 MII_PHYDESC(BROADCOM2, BCM5906),
107 static device_method_t brgphy_methods[] = {
108 /* device interface */
109 DEVMETHOD(device_probe, brgphy_probe),
110 DEVMETHOD(device_attach, brgphy_attach),
111 DEVMETHOD(device_detach, ukphy_detach),
112 DEVMETHOD(device_shutdown, bus_generic_shutdown),
116 static devclass_t brgphy_devclass;
118 static driver_t brgphy_driver = {
121 sizeof(struct mii_softc)
124 DRIVER_MODULE(brgphy, miibus, brgphy_driver, brgphy_devclass, NULL, NULL);
126 static int brgphy_service(struct mii_softc *, struct mii_data *, int);
127 static void brgphy_status(struct mii_softc *);
128 static void brgphy_mii_phy_auto(struct mii_softc *);
129 static void brgphy_reset(struct mii_softc *);
130 static void brgphy_loop(struct mii_softc *);
132 static void brgphy_bcm5401_dspcode(struct mii_softc *);
133 static void brgphy_bcm5411_dspcode(struct mii_softc *);
134 static void brgphy_bcm5421_dspcode(struct mii_softc *);
135 static void brgphy_bcm54k2_dspcode(struct mii_softc *);
137 static void brgphy_adc_bug(struct mii_softc *);
138 static void brgphy_5704_a0_bug(struct mii_softc *);
139 static void brgphy_ber_bug(struct mii_softc *);
140 static void brgphy_crc_bug(struct mii_softc *);
142 static void brgphy_disable_early_dac(struct mii_softc *);
143 static void brgphy_jumbo_settings(struct mii_softc *, u_long);
144 static void brgphy_eth_wirespeed(struct mii_softc *);
147 brgphy_probe(device_t dev)
149 struct mii_attach_args *ma = device_get_ivars(dev);
150 const struct mii_phydesc *mpd;
152 mpd = mii_phy_match(ma, brgphys);
154 device_set_desc(dev, mpd->mpd_name);
161 brgphy_attach(device_t dev)
163 struct mii_softc *sc;
164 struct mii_attach_args *ma;
165 struct mii_data *mii;
167 sc = device_get_softc(dev);
168 ma = device_get_ivars(dev);
169 mii_softc_init(sc, ma);
170 sc->mii_dev = device_get_parent(dev);
171 mii = device_get_softc(sc->mii_dev);
172 LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
174 sc->mii_inst = mii->mii_instance;
175 sc->mii_service = brgphy_service;
176 sc->mii_reset = brgphy_reset;
179 sc->mii_flags |= MIIF_NOISOLATE;
184 #define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL)
186 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst),
189 ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst),
195 sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
196 if (sc->mii_capabilities & BMSR_EXTSTAT)
197 sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
199 device_printf(dev, " ");
200 if ((sc->mii_capabilities & BMSR_MEDIAMASK) ||
201 (sc->mii_extcapabilities & EXTSR_MEDIAMASK))
202 mii_phy_add_media(sc);
204 kprintf("no media present");
207 MIIBUS_MEDIAINIT(sc->mii_dev);
212 brgphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
214 struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
220 * If we're not polling our PHY instance, just return.
222 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
228 * If the media indicates a different PHY instance,
231 if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
232 reg = PHY_READ(sc, MII_BMCR);
233 PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
238 * If the interface is not up, don't do anything.
240 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
243 brgphy_reset(sc); /* XXX hardware bug work-around */
245 switch (IFM_SUBTYPE(ife->ifm_media)) {
249 * If we're already in auto mode, just return.
251 if (PHY_READ(sc, BRGPHY_MII_BMCR) & BRGPHY_BMCR_AUTOEN)
254 brgphy_mii_phy_auto(sc);
257 speed = BRGPHY_S1000;
266 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
267 speed |= BRGPHY_BMCR_FDX;
268 gig = BRGPHY_1000CTL_AFD;
270 gig = BRGPHY_1000CTL_AHD;
273 PHY_WRITE(sc, BRGPHY_MII_1000CTL, 0);
274 PHY_WRITE(sc, BRGPHY_MII_ANAR, BRGPHY_SEL_TYPE);
275 PHY_WRITE(sc, BRGPHY_MII_BMCR, speed);
277 if (IFM_SUBTYPE(ife->ifm_media) != IFM_1000_T)
280 PHY_WRITE(sc, BRGPHY_MII_1000CTL, gig);
281 PHY_WRITE(sc, BRGPHY_MII_BMCR,
282 speed|BRGPHY_BMCR_AUTOEN|BRGPHY_BMCR_STARTNEG);
284 if (sc->mii_model != MII_MODEL_xxBROADCOM_BCM5701)
288 * When settning the link manually, one side must
289 * be the master and the other the slave. However
290 * ifmedia doesn't give us a good way to specify
291 * this, so we fake it by using one of the LINK
292 * flags. If LINK0 is set, we program the PHY to
293 * be a master, otherwise it's a slave.
295 if ((mii->mii_ifp->if_flags & IFF_LINK0)) {
296 PHY_WRITE(sc, BRGPHY_MII_1000CTL,
297 gig|BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC);
299 PHY_WRITE(sc, BRGPHY_MII_1000CTL,
300 gig|BRGPHY_1000CTL_MSE);
305 PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN);
316 * If we're not currently selected, just return.
318 if (IFM_INST(ife->ifm_media) != sc->mii_inst)
322 * Is the interface even up?
324 if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
328 * Only used for autonegotiation.
330 if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
334 * Check to see if we have link. If we do, we don't
335 * need to restart the autonegotiation process. Read
336 * the BMSR twice in case it's latched.
338 reg = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
339 if (reg & BMSR_LINK) {
345 * Only retry autonegotiation every 5 seconds.
347 if (++sc->mii_ticks <= sc->mii_anegticks)
351 brgphy_mii_phy_auto(sc);
355 /* Update the media status. */
359 * Callback if something changed. Note that we need to poke
360 * the DSP on the Broadcom PHYs if the media changes.
362 if (sc->mii_media_active != mii->mii_media_active ||
363 sc->mii_media_status != mii->mii_media_status ||
364 cmd == MII_MEDIACHG) {
365 switch (sc->mii_model) {
366 case MII_MODEL_xxBROADCOM_BCM5400:
367 brgphy_bcm5401_dspcode(sc);
369 case MII_MODEL_xxBROADCOM_BCM5401:
370 if (sc->mii_rev == 1 || sc->mii_rev == 3)
371 brgphy_bcm5401_dspcode(sc);
373 case MII_MODEL_xxBROADCOM_BCM5411:
374 brgphy_bcm5411_dspcode(sc);
378 mii_phy_update(sc, cmd);
383 brgphy_status(struct mii_softc *sc)
385 struct mii_data *mii = sc->mii_pdata;
388 mii->mii_media_status = IFM_AVALID;
389 mii->mii_media_active = IFM_ETHER;
391 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR) | PHY_READ(sc, BRGPHY_MII_BMSR);
392 if (bmsr & BRGPHY_BMSR_LINK)
393 mii->mii_media_status |= IFM_ACTIVE;
395 bmcr = PHY_READ(sc, BRGPHY_MII_BMCR);
396 if (bmcr & BRGPHY_BMCR_LOOP)
397 mii->mii_media_active |= IFM_LOOP;
399 if (bmcr & BRGPHY_BMCR_AUTOEN) {
402 if ((bmsr & BRGPHY_BMSR_ACOMP) == 0) {
403 /* Erg, still trying, I guess... */
404 mii->mii_media_active |= IFM_NONE;
408 auxsts = PHY_READ(sc, BRGPHY_MII_AUXSTS);
410 switch (auxsts & BRGPHY_AUXSTS_AN_RES) {
411 case BRGPHY_RES_1000FD:
412 mii->mii_media_active |= IFM_1000_T | IFM_FDX;
414 case BRGPHY_RES_1000HD:
415 mii->mii_media_active |= IFM_1000_T | IFM_HDX;
417 case BRGPHY_RES_100FD:
418 mii->mii_media_active |= IFM_100_TX | IFM_FDX;
420 case BRGPHY_RES_100T4:
421 mii->mii_media_active |= IFM_100_T4;
423 case BRGPHY_RES_100HD:
424 mii->mii_media_active |= IFM_100_TX | IFM_HDX;
426 case BRGPHY_RES_10FD:
427 mii->mii_media_active |= IFM_10_T | IFM_FDX;
429 case BRGPHY_RES_10HD:
430 mii->mii_media_active |= IFM_10_T | IFM_HDX;
433 if (sc->mii_model == MII_MODEL_BROADCOM2_BCM5906) {
434 mii->mii_media_active |= (auxsts &
435 BRGPHY_RES_100) ? IFM_100_TX : IFM_10_T;
436 mii->mii_media_active |= (auxsts &
437 BRGPHY_RES_FULL) ? IFM_FDX : IFM_HDX;
440 mii->mii_media_active |= IFM_NONE;
444 mii->mii_media_active = mii->mii_media.ifm_cur->ifm_media;
450 brgphy_mii_phy_auto(struct mii_softc *sc)
456 PHY_WRITE(sc, BRGPHY_MII_ANAR,
457 BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA);
460 ktcr = BRGPHY_1000CTL_AFD|BRGPHY_1000CTL_AHD;
461 if (sc->mii_model == MII_MODEL_xxBROADCOM_BCM5701)
462 ktcr |= BRGPHY_1000CTL_MSE|BRGPHY_1000CTL_MSC;
463 PHY_WRITE(sc, BRGPHY_MII_1000CTL, ktcr);
464 ktcr = PHY_READ(sc, BRGPHY_MII_1000CTL);
467 PHY_WRITE(sc, BRGPHY_MII_BMCR,
468 BRGPHY_BMCR_AUTOEN | BRGPHY_BMCR_STARTNEG);
469 PHY_WRITE(sc, BRGPHY_MII_IMR, 0xFF00);
473 brgphy_loop(struct mii_softc *sc)
478 PHY_WRITE(sc, BRGPHY_MII_BMCR, BRGPHY_BMCR_LOOP);
479 for (i = 0; i < 15000; i++) {
480 bmsr = PHY_READ(sc, BRGPHY_MII_BMSR);
481 if (!(bmsr & BRGPHY_BMSR_LINK))
488 brgphy_reset(struct mii_softc *sc)
492 switch (sc->mii_model) {
493 case MII_MODEL_xxBROADCOM_BCM5400:
494 brgphy_bcm5401_dspcode(sc);
496 case MII_MODEL_xxBROADCOM_BCM5401:
497 if (sc->mii_rev == 1 || sc->mii_rev == 3)
498 brgphy_bcm5401_dspcode(sc);
500 case MII_MODEL_xxBROADCOM_BCM5411:
501 brgphy_bcm5411_dspcode(sc);
503 case MII_MODEL_xxBROADCOM_BCM5421:
504 brgphy_bcm5421_dspcode(sc);
506 case MII_MODEL_xxBROADCOM_BCM54K2:
507 brgphy_bcm54k2_dspcode(sc);
511 if (sc->mii_privtag != MII_PRIVTAG_BRGPHY)
514 if (sc->mii_priv & BRGPHY_FLAG_ADC_BUG)
516 if (sc->mii_priv & BRGPHY_FLAG_5704_A0)
517 brgphy_5704_a0_bug(sc);
518 if (sc->mii_priv & BRGPHY_FLAG_BER_BUG) {
520 } else if (sc->mii_priv & BRGPHY_FLAG_JITTER_BUG) {
521 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0c00);
522 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a);
524 if (sc->mii_priv & BRGPHY_FLAG_ADJUST_TRIM) {
525 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 0x110b);
526 PHY_WRITE(sc, BRGPHY_TEST1,
527 BRGPHY_TEST1_TRIM_EN | 0x4);
529 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, 0x010b);
532 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0400);
534 if (sc->mii_priv & BRGPHY_FLAG_CRC_BUG)
536 if (sc->mii_priv & BRGPHY_FLAG_NO_EARLYDAC)
537 brgphy_disable_early_dac(sc);
539 /* Set Jumbo frame settings in the PHY. */
540 brgphy_jumbo_settings(sc, sc->mii_pdata->mii_ifp->if_mtu);
542 /* Adjust output voltage */
543 if (sc->mii_priv & BRGPHY_FLAG_5906)
544 PHY_WRITE(sc, BRGPHY_MII_EPHY_PTEST, 0x12);
546 /* Enable Ethernet@Wirespeed */
547 if (sc->mii_priv & BRGPHY_FLAG_WIRESPEED)
548 brgphy_eth_wirespeed(sc);
550 /* Enable Link LED on Dell boxes */
551 if (sc->mii_priv & BRGPHY_FLAG_NO_3LED) {
552 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
553 PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL) &
554 ~BRGPHY_PHY_EXTCTL_3_LED);
558 /* Turn off tap power management on 5401. */
560 brgphy_bcm5401_dspcode(struct mii_softc *sc)
562 static const struct {
566 { BRGPHY_MII_AUXCTL, 0x0c20 },
567 { BRGPHY_MII_DSP_ADDR_REG, 0x0012 },
568 { BRGPHY_MII_DSP_RW_PORT, 0x1804 },
569 { BRGPHY_MII_DSP_ADDR_REG, 0x0013 },
570 { BRGPHY_MII_DSP_RW_PORT, 0x1204 },
571 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
572 { BRGPHY_MII_DSP_RW_PORT, 0x0132 },
573 { BRGPHY_MII_DSP_ADDR_REG, 0x8006 },
574 { BRGPHY_MII_DSP_RW_PORT, 0x0232 },
575 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
576 { BRGPHY_MII_DSP_RW_PORT, 0x0a20 },
581 for (i = 0; dspcode[i].reg != 0; i++)
582 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
586 /* Setting some undocumented voltage */
588 brgphy_bcm5411_dspcode(struct mii_softc *sc)
590 static const struct {
601 for (i = 0; dspcode[i].reg != 0; i++)
602 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
606 brgphy_bcm5421_dspcode(struct mii_softc *sc)
610 /* Set Class A mode */
611 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x1007);
612 data = PHY_READ(sc, BRGPHY_MII_AUXCTL);
613 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0400);
615 /* Set FFE gamma override to -0.125 */
616 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x0007);
617 data = PHY_READ(sc, BRGPHY_MII_AUXCTL);
618 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, data | 0x0800);
619 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x000a);
620 data = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT);
621 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, data | 0x0200);
625 brgphy_bcm54k2_dspcode(struct mii_softc *sc)
627 static const struct {
637 for (i = 0; dspcode[i].reg != 0; i++)
638 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
642 brgphy_adc_bug(struct mii_softc *sc)
644 static const struct {
648 { BRGPHY_MII_AUXCTL, 0x0c00 },
649 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
650 { BRGPHY_MII_DSP_RW_PORT, 0x2aaa },
651 { BRGPHY_MII_DSP_ADDR_REG, 0x000a },
652 { BRGPHY_MII_DSP_RW_PORT, 0x0323 },
653 { BRGPHY_MII_AUXCTL, 0x0400 },
658 for (i = 0; dspcode[i].reg != 0; i++)
659 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
663 brgphy_5704_a0_bug(struct mii_softc *sc)
665 static const struct {
675 for (i = 0; dspcode[i].reg != 0; i++)
676 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
680 brgphy_ber_bug(struct mii_softc *sc)
682 static const struct {
686 { BRGPHY_MII_AUXCTL, 0x0c00 },
687 { BRGPHY_MII_DSP_ADDR_REG, 0x000a },
688 { BRGPHY_MII_DSP_RW_PORT, 0x310b },
689 { BRGPHY_MII_DSP_ADDR_REG, 0x201f },
690 { BRGPHY_MII_DSP_RW_PORT, 0x9506 },
691 { BRGPHY_MII_DSP_ADDR_REG, 0x401f },
692 { BRGPHY_MII_DSP_RW_PORT, 0x14e2 },
693 { BRGPHY_MII_AUXCTL, 0x0400 },
698 for (i = 0; dspcode[i].reg != 0; i++)
699 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
703 brgphy_crc_bug(struct mii_softc *sc)
705 static const struct {
709 { BRGPHY_MII_DSP_ADDR_REG, 0x0a75 },
717 for (i = 0; dspcode[i].reg != 0; i++)
718 PHY_WRITE(sc, dspcode[i].reg, dspcode[i].val);
722 brgphy_jumbo_settings(struct mii_softc *sc, u_long mtu)
726 /* Set or clear jumbo frame settings in the PHY. */
727 if (mtu > ETHER_MAX_LEN) {
728 if (sc->mii_model == MII_MODEL_xxBROADCOM_BCM5401) {
729 /* BCM5401 PHY cannot read-modify-write. */
730 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x4c20);
732 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
733 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
734 PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
735 val | BRGPHY_AUXCTL_LONG_PKT);
738 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
739 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
740 val | BRGPHY_PHY_EXTCTL_HIGH_LA);
742 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7);
743 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
744 PHY_WRITE(sc, BRGPHY_MII_AUXCTL,
745 val & ~(BRGPHY_AUXCTL_LONG_PKT | 0x7));
747 val = PHY_READ(sc, BRGPHY_MII_PHY_EXTCTL);
748 PHY_WRITE(sc, BRGPHY_MII_PHY_EXTCTL,
749 val & ~BRGPHY_PHY_EXTCTL_HIGH_LA);
754 brgphy_eth_wirespeed(struct mii_softc *sc)
758 /* Enable Ethernet@Wirespeed */
759 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, 0x7007);
760 val = PHY_READ(sc, BRGPHY_MII_AUXCTL);
761 PHY_WRITE(sc, BRGPHY_MII_AUXCTL, (val | (1 << 15) | (1 << 4)));
765 brgphy_disable_early_dac(struct mii_softc *sc)
769 PHY_WRITE(sc, BRGPHY_MII_DSP_ADDR_REG, 0x0f08);
770 val = PHY_READ(sc, BRGPHY_MII_DSP_RW_PORT);
772 PHY_WRITE(sc, BRGPHY_MII_DSP_RW_PORT, val);