2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mpapic.c,v 1.37.2.7 2003/01/25 02:31:47 peter Exp $
26 * $DragonFly: src/sys/platform/pc32/apic/mpapic.c,v 1.22 2008/04/20 13:44:26 swildner Exp $
29 #include <sys/param.h>
30 #include <sys/systm.h>
31 #include <machine/globaldata.h>
32 #include <machine/smp.h>
33 #include <machine_base/apic/mpapic.h>
34 #include <machine/segments.h>
35 #include <sys/thread2.h>
37 #include <machine_base/isa/intr_machdep.h> /* Xspuriousint() */
39 /* EISA Edge/Level trigger control registers */
40 #define ELCR0 0x4d0 /* eisa irq 0-7 */
41 #define ELCR1 0x4d1 /* eisa irq 8-15 */
43 static void lapic_timer_calibrate(void);
46 * pointers to pmapped apic hardware.
49 volatile ioapic_t **ioapic;
52 * Enable APIC, configure interrupts.
55 apic_initialize(boolean_t bsp)
60 * setup LVT1 as ExtINT on the BSP. This is theoretically an
61 * aggregate interrupt input from the 8259. The INTA cycle
62 * will be routed to the external controller (the 8259) which
63 * is expected to supply the vector.
65 * Must be setup edge triggered, active high.
67 * Disable LVT1 on the APs. It doesn't matter what delivery
68 * mode we use because we leave it masked.
70 temp = lapic.lvt_lint0;
71 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
72 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
73 if (mycpu->gd_cpuid == 0)
74 temp |= APIC_LVT_DM_EXTINT;
76 temp |= APIC_LVT_DM_FIXED | APIC_LVT_MASKED;
77 lapic.lvt_lint0 = temp;
80 * setup LVT2 as NMI, masked till later. Edge trigger, active high.
82 temp = lapic.lvt_lint1;
83 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
84 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
85 temp |= APIC_LVT_MASKED | APIC_LVT_DM_NMI;
86 lapic.lvt_lint1 = temp;
89 * Mask the apic error interrupt, apic performance counter
90 * interrupt, and the apic timer interrupt.
92 lapic.lvt_error = lapic.lvt_error | APIC_LVT_MASKED;
93 lapic.lvt_pcint = lapic.lvt_pcint | APIC_LVT_MASKED;
94 lapic.lvt_timer = lapic.lvt_timer | APIC_LVT_MASKED;
97 * Set the Task Priority Register as needed. At the moment allow
98 * interrupts on all cpus (the APs will remain CLId until they are
99 * ready to deal). We could disable all but IPIs by setting
100 * temp |= TPR_IPI_ONLY for cpu != 0.
103 temp &= ~APIC_TPR_PRIO; /* clear priority field */
106 * If we are NOT running the IO APICs, the LAPIC will only be used
107 * for IPIs. Set the TPR to prevent any unintentional interrupts.
109 temp |= TPR_IPI_ONLY;
115 * enable the local APIC
118 temp |= APIC_SVR_ENABLE; /* enable the APIC */
119 temp &= ~APIC_SVR_FOCUS_DISABLE; /* enable lopri focus processor */
122 * Set the spurious interrupt vector. The low 4 bits of the vector
125 if ((XSPURIOUSINT_OFFSET & 0x0F) != 0x0F)
126 panic("bad XSPURIOUSINT_OFFSET: 0x%08x", XSPURIOUSINT_OFFSET);
127 temp &= ~APIC_SVR_VECTOR;
128 temp |= XSPURIOUSINT_OFFSET;
133 * Pump out a few EOIs to clean out interrupts that got through
134 * before we were able to set the TPR.
141 lapic_timer_calibrate();
144 apic_dump("apic_initialize()");
148 static int lapic_timer_divisor_idx = -1;
149 static const uint32_t lapic_timer_divisors[] = {
150 APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
151 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128, APIC_TDCR_1
153 #define APIC_TIMER_NDIVISORS \
154 (int)(sizeof(lapic_timer_divisors) / sizeof(lapic_timer_divisors[0]))
157 lapic_timer_set_divisor(int divisor_idx)
159 KKASSERT(divisor_idx >= 0 && divisor_idx < APIC_TIMER_NDIVISORS);
160 lapic.dcr_timer = lapic_timer_divisors[divisor_idx];
164 lapic_timer_oneshot(u_int count)
168 value = lapic.lvt_timer;
169 value &= ~APIC_LVTT_PERIODIC;
170 lapic.lvt_timer = value;
171 lapic.icr_timer = count;
175 lapic_timer_calibrate(void)
179 /* Try to calibrate the local APIC timer. */
180 for (lapic_timer_divisor_idx = 0;
181 lapic_timer_divisor_idx < APIC_TIMER_NDIVISORS;
182 lapic_timer_divisor_idx++) {
183 lapic_timer_set_divisor(lapic_timer_divisor_idx);
184 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT);
186 value = APIC_TIMER_MAX_COUNT - lapic.ccr_timer;
187 if (value != APIC_TIMER_MAX_COUNT)
190 if (lapic_timer_divisor_idx >= APIC_TIMER_NDIVISORS)
191 panic("lapic: no proper timer divisor?!\n");
194 kprintf("lapic: divisor index %d, frequency %lu hz\n",
195 lapic_timer_divisor_idx, value);
200 * dump contents of local APIC registers
205 kprintf("SMP: CPU%d %s:\n", mycpu->gd_cpuid, str);
206 kprintf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
207 lapic.lvt_lint0, lapic.lvt_lint1, lapic.tpr, lapic.svr);
217 #define IOAPIC_ISA_INTS 16
218 #define REDIRCNT_IOAPIC(A) \
219 ((int)((io_apic_versions[(A)] & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1)
221 static int trigger (int apic, int pin, u_int32_t * flags);
222 static void polarity (int apic, int pin, u_int32_t * flags, int level);
224 #define DEFAULT_FLAGS \
230 #define DEFAULT_ISA_FLAGS \
239 io_apic_set_id(int apic, int id)
243 ux = io_apic_read(apic, IOAPIC_ID); /* get current contents */
244 if (((ux & APIC_ID_MASK) >> 24) != id) {
245 kprintf("Changing APIC ID for IO APIC #%d"
246 " from %d to %d on chip\n",
247 apic, ((ux & APIC_ID_MASK) >> 24), id);
248 ux &= ~APIC_ID_MASK; /* clear the ID field */
250 io_apic_write(apic, IOAPIC_ID, ux); /* write new value */
251 ux = io_apic_read(apic, IOAPIC_ID); /* re-read && test */
252 if (((ux & APIC_ID_MASK) >> 24) != id)
253 panic("can't control IO APIC #%d ID, reg: 0x%08x",
260 io_apic_get_id(int apic)
262 return (io_apic_read(apic, IOAPIC_ID) & APIC_ID_MASK) >> 24;
271 extern int apic_pin_trigger; /* 'opaque' */
274 io_apic_setup_intpin(int apic, int pin)
276 int bus, bustype, irq;
277 u_char select; /* the select register is 8 bits */
278 u_int32_t flags; /* the window register is 32 bits */
279 u_int32_t target; /* the window register is 32 bits */
280 u_int32_t vector; /* the window register is 32 bits */
283 select = pin * 2 + IOAPIC_REDTBL0; /* register */
286 * Always clear an IO APIC pin before [re]programming it. This is
287 * particularly important if the pin is set up for a level interrupt
288 * as the IOART_REM_IRR bit might be set. When we reprogram the
289 * vector any EOI from pending ints on this pin could be lost and
290 * IRR might never get reset.
292 * To fix this problem, clear the vector and make sure it is
293 * programmed as an edge interrupt. This should theoretically
294 * clear IRR so we can later, safely program it as a level
299 flags = io_apic_read(apic, select) & IOART_RESV;
300 flags |= IOART_INTMSET | IOART_TRGREDG | IOART_INTAHI;
301 flags |= IOART_DESTPHY | IOART_DELFIXED;
303 target = io_apic_read(apic, select + 1) & IOART_HI_DEST_RESV;
304 target |= 0; /* fixed mode cpu mask of 0 - don't deliver anywhere */
308 io_apic_write(apic, select, flags | vector);
309 io_apic_write(apic, select + 1, target);
314 * We only deal with vectored interrupts here. ? documentation is
315 * lacking, I'm guessing an interrupt type of 0 is the 'INT' type,
318 * This test also catches unconfigured pins.
320 if (apic_int_type(apic, pin) != 0)
324 * Leave the pin unprogrammed if it does not correspond to
327 irq = apic_irq(apic, pin);
331 /* determine the bus type for this pin */
332 bus = apic_src_bus_id(apic, pin);
335 bustype = apic_bus_type(bus);
337 if ((bustype == ISA) &&
338 (pin < IOAPIC_ISA_INTS) &&
340 (apic_polarity(apic, pin) == 0x1) &&
341 (apic_trigger(apic, pin) == 0x3)) {
343 * A broken BIOS might describe some ISA
344 * interrupts as active-high level-triggered.
345 * Use default ISA flags for those interrupts.
347 flags = DEFAULT_ISA_FLAGS;
350 * Program polarity and trigger mode according to
353 flags = DEFAULT_FLAGS;
354 level = trigger(apic, pin, &flags);
356 apic_pin_trigger |= (1 << irq);
357 polarity(apic, pin, &flags, level);
361 kprintf("IOAPIC #%d intpin %d -> irq %d\n",
366 * Program the appropriate registers. This routing may be
367 * overridden when an interrupt handler for a device is
368 * actually added (see register_int(), which calls through
369 * the MACHINTR ABI to set up an interrupt handler/vector).
371 * The order in which we must program the two registers for
372 * safety is unclear! XXX
376 vector = IDT_OFFSET + irq; /* IDT vec */
377 target = io_apic_read(apic, select + 1) & IOART_HI_DEST_RESV;
378 target |= IOART_HI_DEST_BROADCAST;
379 flags |= io_apic_read(apic, select) & IOART_RESV;
380 io_apic_write(apic, select, flags | vector);
381 io_apic_write(apic, select + 1, target);
387 io_apic_setup(int apic)
393 apic_pin_trigger = 0; /* default to edge-triggered */
395 maxpin = REDIRCNT_IOAPIC(apic); /* pins in APIC */
396 kprintf("Programming %d pins in IOAPIC #%d\n", maxpin, apic);
398 for (pin = 0; pin < maxpin; ++pin) {
399 io_apic_setup_intpin(apic, pin);
402 if (apic_int_type(apic, pin) >= 0) {
403 kprintf("Warning: IOAPIC #%d pin %d does not exist,"
404 " cannot program!\n", apic, pin);
409 /* return GOOD status */
412 #undef DEFAULT_ISA_FLAGS
416 #define DEFAULT_EXTINT_FLAGS \
425 * Setup the source of External INTerrupts.
428 ext_int_setup(int apic, int intr)
430 u_char select; /* the select register is 8 bits */
431 u_int32_t flags; /* the window register is 32 bits */
432 u_int32_t target; /* the window register is 32 bits */
433 u_int32_t vector; /* the window register is 32 bits */
435 if (apic_int_type(apic, intr) != 3)
438 target = IOART_HI_DEST_BROADCAST;
439 select = IOAPIC_REDTBL0 + (2 * intr);
440 vector = IDT_OFFSET + intr;
441 flags = DEFAULT_EXTINT_FLAGS;
443 io_apic_write(apic, select, flags | vector);
444 io_apic_write(apic, select + 1, target);
448 #undef DEFAULT_EXTINT_FLAGS
452 * Set the trigger level for an IO APIC pin.
455 trigger(int apic, int pin, u_int32_t * flags)
460 static int intcontrol = -1;
462 switch (apic_trigger(apic, pin)) {
468 *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG */
472 *flags |= IOART_TRGRLVL;
480 if ((id = apic_src_bus_id(apic, pin)) == -1)
483 switch (apic_bus_type(id)) {
485 *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG; */
489 eirq = apic_src_bus_irq(apic, pin);
491 if (eirq < 0 || eirq > 15) {
492 kprintf("EISA IRQ %d?!?!\n", eirq);
496 if (intcontrol == -1) {
497 intcontrol = inb(ELCR1) << 8;
498 intcontrol |= inb(ELCR0);
499 kprintf("EISA INTCONTROL = %08x\n", intcontrol);
502 /* Use ELCR settings to determine level or edge mode */
503 level = (intcontrol >> eirq) & 1;
506 * Note that on older Neptune chipset based systems, any
507 * pci interrupts often show up here and in the ELCR as well
508 * as level sensitive interrupts attributed to the EISA bus.
512 *flags |= IOART_TRGRLVL;
514 *flags &= ~IOART_TRGRLVL;
519 *flags |= IOART_TRGRLVL;
528 panic("bad APIC IO INT flags");
533 * Set the polarity value for an IO APIC pin.
536 polarity(int apic, int pin, u_int32_t * flags, int level)
540 switch (apic_polarity(apic, pin)) {
546 *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
550 *flags |= IOART_INTALO;
558 if ((id = apic_src_bus_id(apic, pin)) == -1)
561 switch (apic_bus_type(id)) {
563 *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
567 /* polarity converter always gives active high */
568 *flags &= ~IOART_INTALO;
572 *flags |= IOART_INTALO;
581 panic("bad APIC IO INT flags");
586 * Print contents of apic_imen.
588 extern u_int apic_imen; /* keep apic_imen 'opaque' */
594 kprintf("SMP: enabled INTs: ");
595 for (x = 0; x < 24; ++x)
596 if ((apic_imen & (1 << x)) == 0)
598 kprintf("apic_imen: 0x%08x\n", apic_imen);
603 * Inter Processor Interrupt functions.
609 * Send APIC IPI 'vector' to 'destType' via 'deliveryMode'.
611 * destType is 1 of: APIC_DEST_SELF, APIC_DEST_ALLISELF, APIC_DEST_ALLESELF
612 * vector is any valid SYSTEM INT vector
613 * delivery_mode is 1 of: APIC_DELMODE_FIXED, APIC_DELMODE_LOWPRIO
615 * A backlog of requests can create a deadlock between cpus. To avoid this
616 * we have to be able to accept IPIs at the same time we are trying to send
617 * them. The critical section prevents us from attempting to send additional
618 * IPIs reentrantly, but also prevents IPIQ processing so we have to call
619 * lwkt_process_ipiq() manually. It's rather messy and expensive for this
620 * to occur but fortunately it does not happen too often.
623 apic_ipi(int dest_type, int vector, int delivery_mode)
628 if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
629 unsigned int eflags = read_eflags();
631 while ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
634 write_eflags(eflags);
637 icr_lo = (lapic.icr_lo & APIC_ICRLO_RESV_MASK) | dest_type |
638 delivery_mode | vector;
639 lapic.icr_lo = icr_lo;
645 single_apic_ipi(int cpu, int vector, int delivery_mode)
651 if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
652 unsigned int eflags = read_eflags();
654 while ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
657 write_eflags(eflags);
659 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
660 icr_hi |= (CPU_TO_ID(cpu) << 24);
661 lapic.icr_hi = icr_hi;
664 icr_lo = (lapic.icr_lo & APIC_ICRLO_RESV_MASK)
665 | APIC_DEST_DESTFLD | delivery_mode | vector;
668 lapic.icr_lo = icr_lo;
675 * Returns 0 if the apic is busy, 1 if we were able to queue the request.
677 * NOT WORKING YET! The code as-is may end up not queueing an IPI at all
678 * to the target, and the scheduler does not 'poll' for IPI messages.
681 single_apic_ipi_passive(int cpu, int vector, int delivery_mode)
687 if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
691 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
692 icr_hi |= (CPU_TO_ID(cpu) << 24);
693 lapic.icr_hi = icr_hi;
696 icr_lo = (lapic.icr_lo & APIC_RESV2_MASK)
697 | APIC_DEST_DESTFLD | delivery_mode | vector;
700 lapic.icr_lo = icr_lo;
708 * Send APIC IPI 'vector' to 'target's via 'delivery_mode'.
710 * target is a bitmask of destination cpus. Vector is any
711 * valid system INT vector. Delivery mode may be either
712 * APIC_DELMODE_FIXED or APIC_DELMODE_LOWPRIO.
715 selected_apic_ipi(u_int target, int vector, int delivery_mode)
719 int n = bsfl(target);
721 single_apic_ipi(n, vector, delivery_mode);
727 * Timer code, in development...
728 * - suggested by rgrimes@gndrsh.aac.dev.com
731 /** XXX FIXME: temp hack till we can determin bus clock */
733 #define BUS_CLOCK 66000000
734 #define bus_clock() 66000000
738 int acquire_apic_timer (void);
739 int release_apic_timer (void);
742 * Acquire the APIC timer for exclusive use.
745 acquire_apic_timer(void)
750 /** XXX FIXME: make this really do something */
751 panic("APIC timer in use when attempting to acquire");
757 * Return the APIC timer.
760 release_apic_timer(void)
765 /** XXX FIXME: make this really do something */
766 panic("APIC timer was already released");
773 * Load a 'downcount time' in uSeconds.
776 set_apic_timer(int value)
779 long ticks_per_microsec;
782 * Calculate divisor and count from value:
784 * timeBase == CPU bus clock divisor == [1,2,4,8,16,32,64,128]
785 * value == time in uS
787 lapic.dcr_timer = APIC_TDCR_1;
788 ticks_per_microsec = bus_clock() / 1000000;
790 /* configure timer as one-shot */
791 lvtt = lapic.lvt_timer;
792 lvtt &= ~(APIC_LVTT_VECTOR | APIC_LVTT_DS);
793 lvtt &= ~(APIC_LVTT_PERIODIC);
794 lvtt |= APIC_LVTT_MASKED; /* no INT, one-shot */
795 lapic.lvt_timer = lvtt;
798 lapic.icr_timer = value * ticks_per_microsec;
803 * Read remaining time in timer.
806 read_apic_timer(void)
809 /** XXX FIXME: we need to return the actual remaining time,
810 * for now we just return the remaining count.
813 return lapic.ccr_timer;
819 * Spin-style delay, set delay time in uS, spin till it drains.
824 set_apic_timer(count);
825 while (read_apic_timer())