1 /* $FreeBSD: src/sys/dev/hifn/hifn7751.c,v 1.5.2.5 2003/06/04 17:56:59 sam Exp $ */
2 /* $OpenBSD: hifn7751.c,v 1.120 2002/05/17 00:33:34 deraadt Exp $ */
5 * Invertex AEON / Hifn 7751 driver
6 * Copyright (c) 1999 Invertex Inc. All rights reserved.
7 * Copyright (c) 1999 Theo de Raadt
8 * Copyright (c) 2000-2001 Network Security Technologies, Inc.
9 * http://www.netsec.net
10 * Copyright (c) 2003 Hifn Inc.
12 * This driver is based on a previous driver by Invertex, for which they
13 * requested: Please send any comments, feedback, bug-fixes, or feature
14 * requests to software@invertex.com.
16 * Redistribution and use in source and binary forms, with or without
17 * modification, are permitted provided that the following conditions
20 * 1. Redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer.
22 * 2. Redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution.
25 * 3. The name of the author may not be used to endorse or promote products
26 * derived from this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
29 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
30 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
31 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
32 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
33 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
37 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 * Effort sponsored in part by the Defense Advanced Research Projects
40 * Agency (DARPA) and Air Force Research Laboratory, Air Force
41 * Materiel Command, USAF, under agreement number F30602-01-2-0537.
46 * Driver for various Hifn encryption processors.
50 #include <sys/param.h>
51 #include <sys/systm.h>
53 #include <sys/errno.h>
54 #include <sys/malloc.h>
55 #include <sys/kernel.h>
57 #include <sys/sysctl.h>
60 #include <sys/random.h>
61 #include <sys/thread2.h>
67 #include <machine/clock.h>
68 #include <opencrypto/cryptodev.h>
70 #include "cryptodev_if.h"
72 #include <bus/pci/pcivar.h>
73 #include <bus/pci/pcireg.h>
76 #include "../rndtest/rndtest.h"
78 #include "hifn7751reg.h"
79 #include "hifn7751var.h"
82 * Prototypes and count for the pci_device structure
84 static int hifn_probe(device_t);
85 static int hifn_attach(device_t);
86 static int hifn_detach(device_t);
87 static int hifn_suspend(device_t);
88 static int hifn_resume(device_t);
89 static void hifn_shutdown(device_t);
91 static void hifn_reset_board(struct hifn_softc *, int);
92 static void hifn_reset_puc(struct hifn_softc *);
93 static void hifn_puc_wait(struct hifn_softc *);
94 static int hifn_enable_crypto(struct hifn_softc *);
95 static void hifn_set_retry(struct hifn_softc *sc);
96 static void hifn_init_dma(struct hifn_softc *);
97 static void hifn_init_pci_registers(struct hifn_softc *);
98 static int hifn_sramsize(struct hifn_softc *);
99 static int hifn_dramsize(struct hifn_softc *);
100 static int hifn_ramtype(struct hifn_softc *);
101 static void hifn_sessions(struct hifn_softc *);
102 static void hifn_intr(void *);
103 static u_int hifn_write_command(struct hifn_command *, u_int8_t *);
104 static u_int32_t hifn_next_signature(u_int32_t a, u_int cnt);
105 static int hifn_newsession(device_t, u_int32_t *, struct cryptoini *);
106 static int hifn_freesession(device_t, u_int64_t);
107 static int hifn_process(device_t, struct cryptop *, int);
108 static void hifn_callback(struct hifn_softc *, struct hifn_command *, u_int8_t *);
109 static int hifn_crypto(struct hifn_softc *, struct hifn_command *, struct cryptop *, int);
110 static int hifn_readramaddr(struct hifn_softc *, int, u_int8_t *);
111 static int hifn_writeramaddr(struct hifn_softc *, int, u_int8_t *);
112 static int hifn_dmamap_load_src(struct hifn_softc *, struct hifn_command *);
113 static int hifn_dmamap_load_dst(struct hifn_softc *, struct hifn_command *);
114 static int hifn_init_pubrng(struct hifn_softc *);
116 static void hifn_rng(void *);
118 static void hifn_tick(void *);
119 static void hifn_abort(struct hifn_softc *);
120 static void hifn_alloc_slot(struct hifn_softc *, int *, int *, int *, int *);
122 static void hifn_write_reg_0(struct hifn_softc *, bus_size_t, u_int32_t);
123 static void hifn_write_reg_1(struct hifn_softc *, bus_size_t, u_int32_t);
126 static device_method_t hifn_methods[] = {
127 /* Device interface */
128 DEVMETHOD(device_probe, hifn_probe),
129 DEVMETHOD(device_attach, hifn_attach),
130 DEVMETHOD(device_detach, hifn_detach),
131 DEVMETHOD(device_suspend, hifn_suspend),
132 DEVMETHOD(device_resume, hifn_resume),
133 DEVMETHOD(device_shutdown, hifn_shutdown),
136 DEVMETHOD(bus_print_child, bus_generic_print_child),
137 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
139 /* crypto device methods */
140 DEVMETHOD(cryptodev_newsession, hifn_newsession),
141 DEVMETHOD(cryptodev_freesession,hifn_freesession),
142 DEVMETHOD(cryptodev_process, hifn_process),
146 static driver_t hifn_driver = {
149 sizeof (struct hifn_softc)
151 static devclass_t hifn_devclass;
153 DECLARE_DUMMY_MODULE(hifn);
154 DRIVER_MODULE(hifn, pci, hifn_driver, hifn_devclass, NULL, NULL);
155 MODULE_DEPEND(hifn, crypto, 1, 1, 1);
157 MODULE_DEPEND(hifn, rndtest, 1, 1, 1);
160 static __inline__ u_int32_t
161 READ_REG_0(struct hifn_softc *sc, bus_size_t reg)
163 u_int32_t v = bus_space_read_4(sc->sc_st0, sc->sc_sh0, reg);
164 sc->sc_bar0_lastreg = (bus_size_t) -1;
167 #define WRITE_REG_0(sc, reg, val) hifn_write_reg_0(sc, reg, val)
169 static __inline__ u_int32_t
170 READ_REG_1(struct hifn_softc *sc, bus_size_t reg)
172 u_int32_t v = bus_space_read_4(sc->sc_st1, sc->sc_sh1, reg);
173 sc->sc_bar1_lastreg = (bus_size_t) -1;
176 #define WRITE_REG_1(sc, reg, val) hifn_write_reg_1(sc, reg, val)
178 SYSCTL_NODE(_hw, OID_AUTO, hifn, CTLFLAG_RD, 0, "Hifn driver parameters");
181 static int hifn_debug = 0;
182 SYSCTL_INT(_hw_hifn, OID_AUTO, debug, CTLFLAG_RW, &hifn_debug,
183 0, "control debugging msgs");
186 static struct hifn_stats hifnstats;
187 SYSCTL_STRUCT(_hw_hifn, OID_AUTO, stats, CTLFLAG_RD, &hifnstats,
188 hifn_stats, "driver statistics");
189 static int hifn_maxbatch = 1;
190 SYSCTL_INT(_hw_hifn, OID_AUTO, maxbatch, CTLFLAG_RW, &hifn_maxbatch,
191 0, "max ops to batch w/o interrupt");
194 * Probe for a supported device. The PCI vendor and device
195 * IDs are used to detect devices we know how to handle.
198 hifn_probe(device_t dev)
200 if (pci_get_vendor(dev) == PCI_VENDOR_INVERTEX &&
201 pci_get_device(dev) == PCI_PRODUCT_INVERTEX_AEON)
203 if (pci_get_vendor(dev) == PCI_VENDOR_HIFN &&
204 (pci_get_device(dev) == PCI_PRODUCT_HIFN_7751 ||
205 pci_get_device(dev) == PCI_PRODUCT_HIFN_7951 ||
206 pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 ||
207 pci_get_device(dev) == PCI_PRODUCT_HIFN_7956 ||
208 pci_get_device(dev) == PCI_PRODUCT_HIFN_7811))
210 if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC &&
211 pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751)
213 if (pci_get_vendor(dev) == PCI_VENDOR_HIFN) {
214 device_printf(dev,"device id = 0x%x\n", pci_get_device(dev) );
221 hifn_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
223 bus_addr_t *paddr = (bus_addr_t*) arg;
224 *paddr = segs->ds_addr;
228 hifn_partname(struct hifn_softc *sc)
230 /* XXX sprintf numbers when not decoded */
231 switch (pci_get_vendor(sc->sc_dev)) {
232 case PCI_VENDOR_HIFN:
233 switch (pci_get_device(sc->sc_dev)) {
234 case PCI_PRODUCT_HIFN_6500: return "Hifn 6500";
235 case PCI_PRODUCT_HIFN_7751: return "Hifn 7751";
236 case PCI_PRODUCT_HIFN_7811: return "Hifn 7811";
237 case PCI_PRODUCT_HIFN_7951: return "Hifn 7951";
238 case PCI_PRODUCT_HIFN_7955: return "Hifn 7955";
239 case PCI_PRODUCT_HIFN_7956: return "Hifn 7956";
241 return "Hifn unknown-part";
242 case PCI_VENDOR_INVERTEX:
243 switch (pci_get_device(sc->sc_dev)) {
244 case PCI_PRODUCT_INVERTEX_AEON: return "Invertex AEON";
246 return "Invertex unknown-part";
247 case PCI_VENDOR_NETSEC:
248 switch (pci_get_device(sc->sc_dev)) {
249 case PCI_PRODUCT_NETSEC_7751: return "NetSec 7751";
251 return "NetSec unknown-part";
253 return "Unknown-vendor unknown-part";
257 default_harvest(struct rndtest_state *rsp, void *buf, u_int count)
259 add_buffer_randomness_src(buf, count, RAND_SRC_HIFN);
263 checkmaxmin(device_t dev, const char *what, u_int v, u_int min, u_int max)
266 device_printf(dev, "Warning, %s %u out of range, "
267 "using max %u\n", what, v, max);
269 } else if (v < min) {
270 device_printf(dev, "Warning, %s %u out of range, "
271 "using min %u\n", what, v, min);
278 * Select PLL configuration for 795x parts. This is complicated in
279 * that we cannot determine the optimal parameters without user input.
280 * The reference clock is derived from an external clock through a
281 * multiplier. The external clock is either the host bus (i.e. PCI)
282 * or an external clock generator. When using the PCI bus we assume
283 * the clock is either 33 or 66 MHz; for an external source we cannot
286 * PLL configuration is done with a string: "pci" for PCI bus, or "ext"
287 * for an external source, followed by the frequency. We calculate
288 * the appropriate multiplier and PLL register contents accordingly.
289 * When no configuration is given we default to "pci66" since that
290 * always will allow the card to work. If a card is using the PCI
291 * bus clock and in a 33MHz slot then it will be operating at half
292 * speed until the correct information is provided.
294 * We use a default setting of "ext66" because according to Mike Ham
295 * of HiFn, almost every board in existence has an external crystal
296 * populated at 66Mhz. Using PCI can be a problem on modern motherboards,
297 * because PCI33 can have clocks from 0 to 33Mhz, and some have
298 * non-PCI-compliant spread-spectrum clocks, which can confuse the pll.
301 hifn_getpllconfig(device_t dev, u_int *pll)
304 u_int freq, mul, fl, fh;
308 if (resource_string_value("hifn", device_get_unit(dev),
309 "pllconfig", &pllspec))
313 if (strncmp(pllspec, "ext", 3) == 0) {
315 pllconfig |= HIFN_PLL_REF_SEL;
316 switch (pci_get_device(dev)) {
317 case PCI_PRODUCT_HIFN_7955:
318 case PCI_PRODUCT_HIFN_7956:
322 case PCI_PRODUCT_HIFN_7954:
327 } else if (strncmp(pllspec, "pci", 3) == 0)
329 freq = strtoul(pllspec, &nxt, 10);
333 freq = checkmaxmin(dev, "frequency", freq, fl, fh);
335 * Calculate multiplier. We target a Fck of 266 MHz,
336 * allowing only even values, possibly rounded down.
337 * Multipliers > 8 must set the charge pump current.
339 mul = checkmaxmin(dev, "PLL divisor", (266 / freq) &~ 1, 2, 12);
340 pllconfig |= (mul / 2 - 1) << HIFN_PLL_ND_SHIFT;
342 pllconfig |= HIFN_PLL_IS;
347 * Attach an interface that successfully probed.
350 hifn_attach(device_t dev)
352 struct hifn_softc *sc = device_get_softc(dev);
359 KASSERT(sc != NULL, ("hifn_attach: null software carrier!"));
360 bzero(sc, sizeof (*sc));
363 lockinit(&sc->sc_lock, __DECONST(char *, device_get_nameunit(dev)),
366 /* XXX handle power management */
369 * The 7951 and 795x have a random number generator and
370 * public key support; note this.
372 if (pci_get_vendor(dev) == PCI_VENDOR_HIFN &&
373 (pci_get_device(dev) == PCI_PRODUCT_HIFN_7951 ||
374 pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 ||
375 pci_get_device(dev) == PCI_PRODUCT_HIFN_7956))
376 sc->sc_flags = HIFN_HAS_RNG | HIFN_HAS_PUBLIC;
378 * The 7811 has a random number generator and
379 * we also note it's identity 'cuz of some quirks.
381 if (pci_get_vendor(dev) == PCI_VENDOR_HIFN &&
382 pci_get_device(dev) == PCI_PRODUCT_HIFN_7811)
383 sc->sc_flags |= HIFN_IS_7811 | HIFN_HAS_RNG;
386 * The 795x parts support AES.
388 if (pci_get_vendor(dev) == PCI_VENDOR_HIFN &&
389 (pci_get_device(dev) == PCI_PRODUCT_HIFN_7955 ||
390 pci_get_device(dev) == PCI_PRODUCT_HIFN_7956)) {
391 sc->sc_flags |= HIFN_IS_7956 | HIFN_HAS_AES;
393 * Select PLL configuration. This depends on the
394 * bus and board design and must be manually configured
395 * if the default setting is unacceptable.
397 hifn_getpllconfig(dev, &sc->sc_pllconfig);
401 * Configure support for memory-mapped access to
402 * registers and for DMA operations.
404 #define PCIM_ENA (PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN)
405 cmd = pci_read_config(dev, PCIR_COMMAND, 4);
407 pci_write_config(dev, PCIR_COMMAND, cmd, 4);
408 cmd = pci_read_config(dev, PCIR_COMMAND, 4);
409 if ((cmd & PCIM_ENA) != PCIM_ENA) {
410 device_printf(dev, "failed to enable %s\n",
411 (cmd & PCIM_ENA) == 0 ?
412 "memory mapping & bus mastering" :
413 (cmd & PCIM_CMD_MEMEN) == 0 ?
414 "memory mapping" : "bus mastering");
420 * Setup PCI resources. Note that we record the bus
421 * tag and handle for each register mapping, this is
422 * used by the READ_REG_0, WRITE_REG_0, READ_REG_1,
423 * and WRITE_REG_1 macros throughout the driver.
426 sc->sc_bar0res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
427 0, ~0, 1, RF_ACTIVE);
428 if (sc->sc_bar0res == NULL) {
429 device_printf(dev, "cannot map bar%d register space\n", 0);
432 sc->sc_st0 = rman_get_bustag(sc->sc_bar0res);
433 sc->sc_sh0 = rman_get_bushandle(sc->sc_bar0res);
434 sc->sc_bar0_lastreg = (bus_size_t) -1;
437 sc->sc_bar1res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid,
438 0, ~0, 1, RF_ACTIVE);
439 if (sc->sc_bar1res == NULL) {
440 device_printf(dev, "cannot map bar%d register space\n", 1);
443 sc->sc_st1 = rman_get_bustag(sc->sc_bar1res);
444 sc->sc_sh1 = rman_get_bushandle(sc->sc_bar1res);
445 sc->sc_bar1_lastreg = (bus_size_t) -1;
450 * Setup the area where the Hifn DMA's descriptors
451 * and associated data structures.
453 if (bus_dma_tag_create(NULL, /* parent */
454 1, 0, /* alignment,boundary */
455 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */
456 BUS_SPACE_MAXADDR, /* highaddr */
457 NULL, NULL, /* filter, filterarg */
458 HIFN_MAX_DMALEN, /* maxsize */
459 MAX_SCATTER, /* nsegments */
460 HIFN_MAX_SEGLEN, /* maxsegsize */
461 BUS_DMA_ALLOCNOW, /* flags */
463 device_printf(dev, "cannot allocate DMA tag\n");
466 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &sc->sc_dmamap)) {
467 device_printf(dev, "cannot create dma map\n");
468 bus_dma_tag_destroy(sc->sc_dmat);
471 if (bus_dmamem_alloc(sc->sc_dmat, (void**) &kva, BUS_DMA_NOWAIT, &sc->sc_dmamap)) {
472 device_printf(dev, "cannot alloc dma buffer\n");
473 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap);
474 bus_dma_tag_destroy(sc->sc_dmat);
477 if (bus_dmamap_load(sc->sc_dmat, sc->sc_dmamap, kva,
478 sizeof (*sc->sc_dma),
479 hifn_dmamap_cb, &sc->sc_dma_physaddr,
481 device_printf(dev, "cannot load dma map\n");
482 bus_dmamem_free(sc->sc_dmat, kva, sc->sc_dmamap);
483 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap);
484 bus_dma_tag_destroy(sc->sc_dmat);
487 sc->sc_dma = (struct hifn_dma *)kva;
488 bzero(sc->sc_dma, sizeof(*sc->sc_dma));
490 KASSERT(sc->sc_st0 != 0, ("hifn_attach: null bar0 tag!"));
491 KASSERT(sc->sc_sh0 != 0, ("hifn_attach: null bar0 handle!"));
492 KASSERT(sc->sc_st1 != 0, ("hifn_attach: null bar1 tag!"));
493 KASSERT(sc->sc_sh1 != 0, ("hifn_attach: null bar1 handle!"));
496 * Reset the board and do the ``secret handshake''
497 * to enable the crypto support. Then complete the
498 * initialization procedure by setting up the interrupt
499 * and hooking in to the system crypto support so we'll
500 * get used for system services like the crypto device,
501 * IPsec, RNG device, etc.
503 hifn_reset_board(sc, 0);
505 if (hifn_enable_crypto(sc) != 0) {
506 device_printf(dev, "crypto enabling failed\n");
512 hifn_init_pci_registers(sc);
514 /* XXX can't dynamically determine ram type for 795x; force dram */
515 if (sc->sc_flags & HIFN_IS_7956)
516 sc->sc_drammodel = 1;
517 else if (hifn_ramtype(sc))
520 if (sc->sc_drammodel == 0)
526 * Workaround for NetSec 7751 rev A: half ram size because two
527 * of the address lines were left floating
529 if (pci_get_vendor(dev) == PCI_VENDOR_NETSEC &&
530 pci_get_device(dev) == PCI_PRODUCT_NETSEC_7751 &&
531 pci_get_revid(dev) == 0x61) /*XXX???*/
532 sc->sc_ramsize >>= 1;
535 * Arrange the interrupt line.
538 sc->sc_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid,
539 0, ~0, 1, RF_SHAREABLE|RF_ACTIVE);
540 if (sc->sc_irq == NULL) {
541 device_printf(dev, "could not map interrupt\n");
545 * NB: Network code assumes we are blocked with splimp()
546 * so make sure the IRQ is marked appropriately.
548 if (bus_setup_intr(dev, sc->sc_irq, INTR_MPSAFE,
550 &sc->sc_intrhand, NULL)) {
551 device_printf(dev, "could not setup interrupt\n");
558 * NB: Keep only the low 16 bits; this masks the chip id
561 rev = READ_REG_1(sc, HIFN_1_REVID) & 0xffff;
563 rseg = sc->sc_ramsize / 1024;
565 if (sc->sc_ramsize >= (1024 * 1024)) {
569 device_printf(sc->sc_dev, "%s, rev %u, %d%cB %cram, %u sessions\n",
570 hifn_partname(sc), rev,
571 rseg, rbase, sc->sc_drammodel ? 'd' : 's',
574 if (sc->sc_flags & HIFN_IS_7956)
575 kprintf(", pll=0x%x<%s clk, %ux mult>",
577 sc->sc_pllconfig & HIFN_PLL_REF_SEL ? "ext" : "pci",
578 2 + 2*((sc->sc_pllconfig & HIFN_PLL_ND) >> 11));
581 sc->sc_cid = crypto_get_driverid(dev, CRYPTOCAP_F_HARDWARE);
582 if (sc->sc_cid < 0) {
583 device_printf(dev, "could not get crypto driver id\n");
587 WRITE_REG_0(sc, HIFN_0_PUCNFG,
588 READ_REG_0(sc, HIFN_0_PUCNFG) | HIFN_PUCNFG_CHIPID);
589 ena = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA;
592 case HIFN_PUSTAT_ENA_2:
593 crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0);
594 crypto_register(sc->sc_cid, CRYPTO_ARC4, 0, 0);
595 if (sc->sc_flags & HIFN_HAS_AES)
596 crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0);
598 case HIFN_PUSTAT_ENA_1:
599 crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0);
600 crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0);
601 crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0);
602 crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0);
603 crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0);
607 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
608 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
610 if (sc->sc_flags & (HIFN_HAS_PUBLIC | HIFN_HAS_RNG))
611 hifn_init_pubrng(sc);
613 /* NB: 1 means the callout runs w/o Giant locked */
614 callout_init_mp(&sc->sc_tickto);
615 callout_reset(&sc->sc_tickto, hz, hifn_tick, sc);
620 bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand);
622 /* XXX don't store rid */
623 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
625 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap);
626 bus_dmamem_free(sc->sc_dmat, sc->sc_dma, sc->sc_dmamap);
627 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap);
628 bus_dma_tag_destroy(sc->sc_dmat);
630 /* Turn off DMA polling */
631 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
632 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
634 bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR1, sc->sc_bar1res);
636 bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR0, sc->sc_bar0res);
638 lockuninit(&sc->sc_lock);
643 * Detach an interface that successfully probed.
646 hifn_detach(device_t dev)
648 struct hifn_softc *sc = device_get_softc(dev);
650 KASSERT(sc != NULL, ("hifn_detach: null software carrier!"));
652 /* disable interrupts */
653 WRITE_REG_1(sc, HIFN_1_DMA_IER, 0);
655 /*XXX other resources */
656 callout_stop(&sc->sc_tickto);
657 callout_stop(&sc->sc_rngto);
660 rndtest_detach(sc->sc_rndtest);
663 /* Turn off DMA polling */
664 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
665 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
667 crypto_unregister_all(sc->sc_cid);
669 bus_generic_detach(dev); /*XXX should be no children, right? */
671 bus_teardown_intr(dev, sc->sc_irq, sc->sc_intrhand);
672 /* XXX don't store rid */
673 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq);
675 bus_dmamap_unload(sc->sc_dmat, sc->sc_dmamap);
676 bus_dmamem_free(sc->sc_dmat, sc->sc_dma, sc->sc_dmamap);
677 bus_dmamap_destroy(sc->sc_dmat, sc->sc_dmamap);
678 bus_dma_tag_destroy(sc->sc_dmat);
680 bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR1, sc->sc_bar1res);
681 bus_release_resource(dev, SYS_RES_MEMORY, HIFN_BAR0, sc->sc_bar0res);
683 lockuninit(&sc->sc_lock);
689 * Stop all chip I/O so that the kernel's probe routines don't
690 * get confused by errant DMAs when rebooting.
693 hifn_shutdown(device_t dev)
696 hifn_stop(device_get_softc(dev));
701 * Device suspend routine. Stop the interface and save some PCI
702 * settings in case the BIOS doesn't restore them properly on
706 hifn_suspend(device_t dev)
708 struct hifn_softc *sc = device_get_softc(dev);
713 for (i = 0; i < 5; i++)
714 sc->saved_maps[i] = pci_read_config(dev, PCIR_MAPS + i * 4, 4);
715 sc->saved_biosaddr = pci_read_config(dev, PCIR_BIOS, 4);
716 sc->saved_intline = pci_read_config(dev, PCIR_INTLINE, 1);
717 sc->saved_cachelnsz = pci_read_config(dev, PCIR_CACHELNSZ, 1);
718 sc->saved_lattimer = pci_read_config(dev, PCIR_LATTIMER, 1);
720 sc->sc_suspended = 1;
726 * Device resume routine. Restore some PCI settings in case the BIOS
727 * doesn't, re-enable busmastering, and restart the interface if
731 hifn_resume(device_t dev)
733 struct hifn_softc *sc = device_get_softc(dev);
737 /* better way to do this? */
738 for (i = 0; i < 5; i++)
739 pci_write_config(dev, PCIR_MAPS + i * 4, sc->saved_maps[i], 4);
740 pci_write_config(dev, PCIR_BIOS, sc->saved_biosaddr, 4);
741 pci_write_config(dev, PCIR_INTLINE, sc->saved_intline, 1);
742 pci_write_config(dev, PCIR_CACHELNSZ, sc->saved_cachelnsz, 1);
743 pci_write_config(dev, PCIR_LATTIMER, sc->saved_lattimer, 1);
745 /* reenable busmastering */
746 pci_enable_busmaster(dev);
747 pci_enable_io(dev, HIFN_RES);
749 /* reinitialize interface if necessary */
750 if (ifp->if_flags & IFF_UP)
753 sc->sc_suspended = 0;
759 hifn_init_pubrng(struct hifn_softc *sc)
765 sc->sc_rndtest = rndtest_attach(sc->sc_dev);
767 sc->sc_harvest = rndtest_harvest;
769 sc->sc_harvest = default_harvest;
771 sc->sc_harvest = default_harvest;
773 if ((sc->sc_flags & HIFN_IS_7811) == 0) {
774 /* Reset 7951 public key/rng engine */
775 WRITE_REG_1(sc, HIFN_1_PUB_RESET,
776 READ_REG_1(sc, HIFN_1_PUB_RESET) | HIFN_PUBRST_RESET);
778 for (i = 0; i < 100; i++) {
780 if ((READ_REG_1(sc, HIFN_1_PUB_RESET) &
781 HIFN_PUBRST_RESET) == 0)
786 device_printf(sc->sc_dev, "public key init failed\n");
792 /* Enable the rng, if available */
793 if (sc->sc_flags & HIFN_HAS_RNG) {
794 if (sc->sc_flags & HIFN_IS_7811) {
795 r = READ_REG_1(sc, HIFN_1_7811_RNGENA);
796 if (r & HIFN_7811_RNGENA_ENA) {
797 r &= ~HIFN_7811_RNGENA_ENA;
798 WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r);
800 WRITE_REG_1(sc, HIFN_1_7811_RNGCFG,
801 HIFN_7811_RNGCFG_DEFL);
802 r |= HIFN_7811_RNGENA_ENA;
803 WRITE_REG_1(sc, HIFN_1_7811_RNGENA, r);
805 WRITE_REG_1(sc, HIFN_1_RNG_CONFIG,
806 READ_REG_1(sc, HIFN_1_RNG_CONFIG) |
811 sc->sc_rnghz = hz / 100;
814 /* NB: 1 means the callout runs w/o Giant locked */
815 callout_init_mp(&sc->sc_rngto);
816 callout_reset(&sc->sc_rngto, sc->sc_rnghz, hifn_rng, sc);
820 /* Enable public key engine, if available */
821 if (sc->sc_flags & HIFN_HAS_PUBLIC) {
822 WRITE_REG_1(sc, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE);
823 sc->sc_dmaier |= HIFN_DMAIER_PUBDONE;
824 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier);
834 #define RANDOM_BITS(n) (n)*sizeof (u_int32_t), (n)*sizeof (u_int32_t)*NBBY, 0
835 struct hifn_softc *sc = vsc;
836 u_int32_t sts, num[2];
839 if (sc->sc_flags & HIFN_IS_7811) {
840 for (i = 0; i < 5; i++) {
841 sts = READ_REG_1(sc, HIFN_1_7811_RNGSTS);
842 if (sts & HIFN_7811_RNGSTS_UFL) {
843 device_printf(sc->sc_dev,
844 "RNG underflow: disabling\n");
847 if ((sts & HIFN_7811_RNGSTS_RDY) == 0)
851 * There are at least two words in the RNG FIFO
854 num[0] = READ_REG_1(sc, HIFN_1_7811_RNGDAT);
855 num[1] = READ_REG_1(sc, HIFN_1_7811_RNGDAT);
856 /* NB: discard first data read */
860 (*sc->sc_harvest)(sc->sc_rndtest,
864 num[0] = READ_REG_1(sc, HIFN_1_RNG_DATA);
866 /* NB: discard first data read */
870 (*sc->sc_harvest)(sc->sc_rndtest,
871 num, sizeof (num[0]));
874 callout_reset(&sc->sc_rngto, sc->sc_rnghz, hifn_rng, sc);
880 hifn_puc_wait(struct hifn_softc *sc)
883 int reg = HIFN_0_PUCTRL;
885 if (sc->sc_flags & HIFN_IS_7956) {
886 reg = HIFN_0_PUCTRL2;
889 for (i = 5000; i > 0; i--) {
891 if (!(READ_REG_0(sc, reg) & HIFN_PUCTRL_RESET))
895 device_printf(sc->sc_dev, "proc unit did not reset\n");
899 * Reset the processing unit.
902 hifn_reset_puc(struct hifn_softc *sc)
904 int reg = HIFN_0_PUCTRL;
906 if (sc->sc_flags & HIFN_IS_7956) {
907 reg = HIFN_0_PUCTRL2;
910 /* Reset processing unit */
911 WRITE_REG_0(sc, reg, HIFN_PUCTRL_DMAENA);
916 * Set the Retry and TRDY registers; note that we set them to
917 * zero because the 7811 locks up when forced to retry (section
918 * 3.6 of "Specification Update SU-0014-04". Not clear if we
919 * should do this for all Hifn parts, but it doesn't seem to hurt.
922 hifn_set_retry(struct hifn_softc *sc)
924 /* NB: RETRY only responds to 8-bit reads/writes */
925 pci_write_config(sc->sc_dev, HIFN_RETRY_TIMEOUT, 0, 1);
926 pci_write_config(sc->sc_dev, HIFN_TRDY_TIMEOUT, 0, 4);
930 * Resets the board. Values in the regesters are left as is
931 * from the reset (i.e. initial values are assigned elsewhere).
934 hifn_reset_board(struct hifn_softc *sc, int full)
939 * Set polling in the DMA configuration register to zero. 0x7 avoids
940 * resetting the board and zeros out the other fields.
942 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
943 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
946 * Now that polling has been disabled, we have to wait 1 ms
947 * before resetting the board.
951 /* Reset the DMA unit */
953 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE);
956 WRITE_REG_1(sc, HIFN_1_DMA_CNFG,
957 HIFN_DMACNFG_MODE | HIFN_DMACNFG_MSTRESET);
961 KASSERT(sc->sc_dma != NULL, ("hifn_reset_board: null DMA tag!"));
962 bzero(sc->sc_dma, sizeof(*sc->sc_dma));
964 /* Bring dma unit out of reset */
965 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
966 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
971 if (sc->sc_flags & HIFN_IS_7811) {
972 for (reg = 0; reg < 1000; reg++) {
973 if (READ_REG_1(sc, HIFN_1_7811_MIPSRST) &
974 HIFN_MIPSRST_CRAMINIT)
979 kprintf(": cram init timeout\n");
981 /* set up DMA configuration register #2 */
982 /* turn off all PK and BAR0 swaps */
983 WRITE_REG_1(sc, HIFN_1_DMA_CNFG2,
984 (3 << HIFN_DMACNFG2_INIT_WRITE_BURST_SHIFT)|
985 (3 << HIFN_DMACNFG2_INIT_READ_BURST_SHIFT)|
986 (2 << HIFN_DMACNFG2_TGT_WRITE_BURST_SHIFT)|
987 (2 << HIFN_DMACNFG2_TGT_READ_BURST_SHIFT));
992 hifn_next_signature(u_int32_t a, u_int cnt)
997 for (i = 0; i < cnt; i++) {
1007 a = (v & 1) ^ (a << 1);
1018 static struct pci2id pci2id[] = {
1021 PCI_PRODUCT_HIFN_7951,
1022 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1023 0x00, 0x00, 0x00, 0x00, 0x00 }
1026 PCI_PRODUCT_HIFN_7955,
1027 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1028 0x00, 0x00, 0x00, 0x00, 0x00 }
1031 PCI_PRODUCT_HIFN_7956,
1032 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1033 0x00, 0x00, 0x00, 0x00, 0x00 }
1036 PCI_PRODUCT_NETSEC_7751,
1037 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1038 0x00, 0x00, 0x00, 0x00, 0x00 }
1040 PCI_VENDOR_INVERTEX,
1041 PCI_PRODUCT_INVERTEX_AEON,
1042 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1043 0x00, 0x00, 0x00, 0x00, 0x00 }
1046 PCI_PRODUCT_HIFN_7811,
1047 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1048 0x00, 0x00, 0x00, 0x00, 0x00 }
1051 * Other vendors share this PCI ID as well, such as
1052 * http://www.powercrypt.com, and obviously they also
1056 PCI_PRODUCT_HIFN_7751,
1057 { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
1058 0x00, 0x00, 0x00, 0x00, 0x00 }
1063 * Checks to see if crypto is already enabled. If crypto isn't enable,
1064 * "hifn_enable_crypto" is called to enable it. The check is important,
1065 * as enabling crypto twice will lock the board.
1068 hifn_enable_crypto(struct hifn_softc *sc)
1070 u_int32_t dmacfg, ramcfg, encl, addr, i;
1071 char *offtbl = NULL;
1073 for (i = 0; i < NELEM(pci2id); i++) {
1074 if (pci2id[i].pci_vendor == pci_get_vendor(sc->sc_dev) &&
1075 pci2id[i].pci_prod == pci_get_device(sc->sc_dev)) {
1076 offtbl = pci2id[i].card_id;
1080 if (offtbl == NULL) {
1081 device_printf(sc->sc_dev, "Unknown card!\n");
1085 ramcfg = READ_REG_0(sc, HIFN_0_PUCNFG);
1086 dmacfg = READ_REG_1(sc, HIFN_1_DMA_CNFG);
1089 * The RAM config register's encrypt level bit needs to be set before
1090 * every read performed on the encryption level register.
1092 WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID);
1094 encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA;
1097 * Make sure we don't re-unlock. Two unlocks kills chip until the
1100 if (encl == HIFN_PUSTAT_ENA_1 || encl == HIFN_PUSTAT_ENA_2) {
1103 device_printf(sc->sc_dev,
1104 "Strong crypto already enabled!\n");
1109 if (encl != 0 && encl != HIFN_PUSTAT_ENA_0) {
1112 device_printf(sc->sc_dev,
1113 "Unknown encryption level 0x%x\n", encl);
1118 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_UNLOCK |
1119 HIFN_DMACNFG_MSTRESET | HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
1121 addr = READ_REG_1(sc, HIFN_UNLOCK_SECRET1);
1123 WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, 0);
1126 for (i = 0; i <= 12; i++) {
1127 addr = hifn_next_signature(addr, offtbl[i] + 0x101);
1128 WRITE_REG_1(sc, HIFN_UNLOCK_SECRET2, addr);
1133 WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg | HIFN_PUCNFG_CHIPID);
1134 encl = READ_REG_0(sc, HIFN_0_PUSTAT) & HIFN_PUSTAT_CHIPENA;
1138 if (encl != HIFN_PUSTAT_ENA_1 && encl != HIFN_PUSTAT_ENA_2)
1139 device_printf(sc->sc_dev, "Engine is permanently "
1140 "locked until next system reset!\n");
1142 device_printf(sc->sc_dev, "Engine enabled "
1148 WRITE_REG_0(sc, HIFN_0_PUCNFG, ramcfg);
1149 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, dmacfg);
1152 case HIFN_PUSTAT_ENA_1:
1153 case HIFN_PUSTAT_ENA_2:
1155 case HIFN_PUSTAT_ENA_0:
1157 device_printf(sc->sc_dev, "disabled");
1165 * Give initial values to the registers listed in the "Register Space"
1166 * section of the HIFN Software Development reference manual.
1169 hifn_init_pci_registers(struct hifn_softc *sc)
1171 /* write fixed values needed by the Initialization registers */
1172 WRITE_REG_0(sc, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA);
1173 WRITE_REG_0(sc, HIFN_0_FIFOCNFG, HIFN_FIFOCNFG_THRESHOLD);
1174 WRITE_REG_0(sc, HIFN_0_PUIER, HIFN_PUIER_DSTOVER);
1176 /* write all 4 ring address registers */
1177 WRITE_REG_1(sc, HIFN_1_DMA_CRAR, sc->sc_dma_physaddr +
1178 offsetof(struct hifn_dma, cmdr[0]));
1179 WRITE_REG_1(sc, HIFN_1_DMA_SRAR, sc->sc_dma_physaddr +
1180 offsetof(struct hifn_dma, srcr[0]));
1181 WRITE_REG_1(sc, HIFN_1_DMA_DRAR, sc->sc_dma_physaddr +
1182 offsetof(struct hifn_dma, dstr[0]));
1183 WRITE_REG_1(sc, HIFN_1_DMA_RRAR, sc->sc_dma_physaddr +
1184 offsetof(struct hifn_dma, resr[0]));
1188 /* write status register */
1189 WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1190 HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS |
1191 HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS |
1192 HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST |
1193 HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER |
1194 HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST |
1195 HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER |
1196 HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST |
1197 HIFN_DMACSR_S_WAIT |
1198 HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST |
1199 HIFN_DMACSR_C_WAIT |
1200 HIFN_DMACSR_ENGINE |
1201 ((sc->sc_flags & HIFN_HAS_PUBLIC) ?
1202 HIFN_DMACSR_PUBDONE : 0) |
1203 ((sc->sc_flags & HIFN_IS_7811) ?
1204 HIFN_DMACSR_ILLW | HIFN_DMACSR_ILLR : 0));
1206 sc->sc_d_busy = sc->sc_r_busy = sc->sc_s_busy = sc->sc_c_busy = 0;
1207 sc->sc_dmaier |= HIFN_DMAIER_R_DONE | HIFN_DMAIER_C_ABORT |
1208 HIFN_DMAIER_D_OVER | HIFN_DMAIER_R_OVER |
1209 HIFN_DMAIER_S_ABORT | HIFN_DMAIER_D_ABORT | HIFN_DMAIER_R_ABORT |
1210 ((sc->sc_flags & HIFN_IS_7811) ?
1211 HIFN_DMAIER_ILLW | HIFN_DMAIER_ILLR : 0);
1212 sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT;
1213 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier);
1215 if (sc->sc_flags & HIFN_IS_7956) {
1218 WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING |
1219 HIFN_PUCNFG_TCALLPHASES |
1220 HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32);
1222 /* turn off the clocks and insure bypass is set */
1223 pll = READ_REG_1(sc, HIFN_1_PLL);
1224 pll = (pll &~ (HIFN_PLL_PK_CLK_SEL | HIFN_PLL_PE_CLK_SEL))
1225 | HIFN_PLL_BP | HIFN_PLL_MBSET;
1226 WRITE_REG_1(sc, HIFN_1_PLL, pll);
1227 DELAY(10*1000); /* 10ms */
1228 /* change configuration */
1229 pll = (pll &~ HIFN_PLL_CONFIG) | sc->sc_pllconfig;
1230 WRITE_REG_1(sc, HIFN_1_PLL, pll);
1231 DELAY(10*1000); /* 10ms */
1232 /* disable bypass */
1233 pll &= ~HIFN_PLL_BP;
1234 WRITE_REG_1(sc, HIFN_1_PLL, pll);
1235 /* enable clocks with new configuration */
1236 pll |= HIFN_PLL_PK_CLK_SEL | HIFN_PLL_PE_CLK_SEL;
1237 WRITE_REG_1(sc, HIFN_1_PLL, pll);
1239 WRITE_REG_0(sc, HIFN_0_PUCNFG, HIFN_PUCNFG_COMPSING |
1240 HIFN_PUCNFG_DRFR_128 | HIFN_PUCNFG_TCALLPHASES |
1241 HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32 |
1242 (sc->sc_drammodel ? HIFN_PUCNFG_DRAM : HIFN_PUCNFG_SRAM));
1245 WRITE_REG_0(sc, HIFN_0_PUISR, HIFN_PUISR_DSTOVER);
1246 WRITE_REG_1(sc, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
1247 HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE | HIFN_DMACNFG_LAST |
1248 ((HIFN_POLL_FREQUENCY << 16 ) & HIFN_DMACNFG_POLLFREQ) |
1249 ((HIFN_POLL_SCALAR << 8) & HIFN_DMACNFG_POLLINVAL));
1253 * The maximum number of sessions supported by the card
1254 * is dependent on the amount of context ram, which
1255 * encryption algorithms are enabled, and how compression
1256 * is configured. This should be configured before this
1257 * routine is called.
1260 hifn_sessions(struct hifn_softc *sc)
1265 pucnfg = READ_REG_0(sc, HIFN_0_PUCNFG);
1267 if (pucnfg & HIFN_PUCNFG_COMPSING) {
1268 if (pucnfg & HIFN_PUCNFG_ENCCNFG)
1273 * 7955/7956 has internal context memory of 32K
1275 if (sc->sc_flags & HIFN_IS_7956)
1276 sc->sc_maxses = 32768 / ctxsize;
1279 ((sc->sc_ramsize - 32768) / ctxsize);
1281 sc->sc_maxses = sc->sc_ramsize / 16384;
1283 if (sc->sc_maxses > 2048)
1284 sc->sc_maxses = 2048;
1288 * Determine ram type (sram or dram). Board should be just out of a reset
1289 * state when this is called.
1292 hifn_ramtype(struct hifn_softc *sc)
1294 u_int8_t data[8], dataexpect[8];
1297 for (i = 0; i < sizeof(data); i++)
1298 data[i] = dataexpect[i] = 0x55;
1299 if (hifn_writeramaddr(sc, 0, data))
1301 if (hifn_readramaddr(sc, 0, data))
1303 if (bcmp(data, dataexpect, sizeof(data)) != 0) {
1304 sc->sc_drammodel = 1;
1308 for (i = 0; i < sizeof(data); i++)
1309 data[i] = dataexpect[i] = 0xaa;
1310 if (hifn_writeramaddr(sc, 0, data))
1312 if (hifn_readramaddr(sc, 0, data))
1314 if (bcmp(data, dataexpect, sizeof(data)) != 0) {
1315 sc->sc_drammodel = 1;
1322 #define HIFN_SRAM_MAX (32 << 20)
1323 #define HIFN_SRAM_STEP_SIZE 16384
1324 #define HIFN_SRAM_GRANULARITY (HIFN_SRAM_MAX / HIFN_SRAM_STEP_SIZE)
1327 hifn_sramsize(struct hifn_softc *sc)
1331 u_int8_t dataexpect[sizeof(data)];
1334 for (i = 0; i < sizeof(data); i++)
1335 data[i] = dataexpect[i] = i ^ 0x5a;
1337 for (i = HIFN_SRAM_GRANULARITY - 1; i >= 0; i--) {
1338 a = i * HIFN_SRAM_STEP_SIZE;
1339 bcopy(&i, data, sizeof(i));
1340 hifn_writeramaddr(sc, a, data);
1343 for (i = 0; i < HIFN_SRAM_GRANULARITY; i++) {
1344 a = i * HIFN_SRAM_STEP_SIZE;
1345 bcopy(&i, dataexpect, sizeof(i));
1346 if (hifn_readramaddr(sc, a, data) < 0)
1348 if (bcmp(data, dataexpect, sizeof(data)) != 0)
1350 sc->sc_ramsize = a + HIFN_SRAM_STEP_SIZE;
1357 * XXX For dram boards, one should really try all of the
1358 * HIFN_PUCNFG_DSZ_*'s. This just assumes that PUCNFG
1359 * is already set up correctly.
1362 hifn_dramsize(struct hifn_softc *sc)
1366 if (sc->sc_flags & HIFN_IS_7956) {
1368 * 7955/7956 have a fixed internal ram of only 32K.
1370 sc->sc_ramsize = 32768;
1372 cnfg = READ_REG_0(sc, HIFN_0_PUCNFG) &
1373 HIFN_PUCNFG_DRAMMASK;
1374 sc->sc_ramsize = 1 << ((cnfg >> 13) + 18);
1380 hifn_alloc_slot(struct hifn_softc *sc, int *cmdp, int *srcp, int *dstp, int *resp)
1382 struct hifn_dma *dma = sc->sc_dma;
1384 if (dma->cmdi == HIFN_D_CMD_RSIZE) {
1386 dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_VALID |
1387 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1388 HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE,
1389 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1391 *cmdp = dma->cmdi++;
1392 dma->cmdk = dma->cmdi;
1394 if (dma->srci == HIFN_D_SRC_RSIZE) {
1396 dma->srcr[HIFN_D_SRC_RSIZE].l = htole32(HIFN_D_VALID |
1397 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1398 HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE,
1399 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1401 *srcp = dma->srci++;
1402 dma->srck = dma->srci;
1404 if (dma->dsti == HIFN_D_DST_RSIZE) {
1406 dma->dstr[HIFN_D_DST_RSIZE].l = htole32(HIFN_D_VALID |
1407 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1408 HIFN_DSTR_SYNC(sc, HIFN_D_DST_RSIZE,
1409 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1411 *dstp = dma->dsti++;
1412 dma->dstk = dma->dsti;
1414 if (dma->resi == HIFN_D_RES_RSIZE) {
1416 dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_VALID |
1417 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1418 HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE,
1419 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1421 *resp = dma->resi++;
1422 dma->resk = dma->resi;
1426 hifn_writeramaddr(struct hifn_softc *sc, int addr, u_int8_t *data)
1428 struct hifn_dma *dma = sc->sc_dma;
1429 hifn_base_command_t wc;
1430 const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ;
1431 int r, cmdi, resi, srci, dsti;
1433 wc.masks = htole16(3 << 13);
1434 wc.session_num = htole16(addr >> 14);
1435 wc.total_source_count = htole16(8);
1436 wc.total_dest_count = htole16(addr & 0x3fff);
1438 hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi);
1440 WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1441 HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA |
1442 HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA);
1444 /* build write command */
1445 bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND);
1446 *(hifn_base_command_t *)dma->command_bufs[cmdi] = wc;
1447 bcopy(data, &dma->test_src, sizeof(dma->test_src));
1449 dma->srcr[srci].p = htole32(sc->sc_dma_physaddr
1450 + offsetof(struct hifn_dma, test_src));
1451 dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr
1452 + offsetof(struct hifn_dma, test_dst));
1454 dma->cmdr[cmdi].l = htole32(16 | masks);
1455 dma->srcr[srci].l = htole32(8 | masks);
1456 dma->dstr[dsti].l = htole32(4 | masks);
1457 dma->resr[resi].l = htole32(4 | masks);
1459 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1460 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1462 for (r = 10000; r >= 0; r--) {
1464 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1465 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1466 if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0)
1468 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1469 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1472 device_printf(sc->sc_dev, "writeramaddr -- "
1473 "result[%d](addr %d) still valid\n", resi, addr);
1479 WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1480 HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS |
1481 HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS);
1487 hifn_readramaddr(struct hifn_softc *sc, int addr, u_int8_t *data)
1489 struct hifn_dma *dma = sc->sc_dma;
1490 hifn_base_command_t rc;
1491 const u_int32_t masks = HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ;
1492 int r, cmdi, srci, dsti, resi;
1494 rc.masks = htole16(2 << 13);
1495 rc.session_num = htole16(addr >> 14);
1496 rc.total_source_count = htole16(addr & 0x3fff);
1497 rc.total_dest_count = htole16(8);
1499 hifn_alloc_slot(sc, &cmdi, &srci, &dsti, &resi);
1501 WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1502 HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA |
1503 HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA);
1505 bzero(dma->command_bufs[cmdi], HIFN_MAX_COMMAND);
1506 *(hifn_base_command_t *)dma->command_bufs[cmdi] = rc;
1508 dma->srcr[srci].p = htole32(sc->sc_dma_physaddr +
1509 offsetof(struct hifn_dma, test_src));
1511 dma->dstr[dsti].p = htole32(sc->sc_dma_physaddr +
1512 offsetof(struct hifn_dma, test_dst));
1514 dma->cmdr[cmdi].l = htole32(8 | masks);
1515 dma->srcr[srci].l = htole32(8 | masks);
1516 dma->dstr[dsti].l = htole32(8 | masks);
1517 dma->resr[resi].l = htole32(HIFN_MAX_RESULT | masks);
1519 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1520 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1522 for (r = 10000; r >= 0; r--) {
1524 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1525 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1526 if ((dma->resr[resi].l & htole32(HIFN_D_VALID)) == 0)
1528 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
1529 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1532 device_printf(sc->sc_dev, "readramaddr -- "
1533 "result[%d](addr %d) still valid\n", resi, addr);
1537 bcopy(&dma->test_dst, data, sizeof(dma->test_dst));
1540 WRITE_REG_1(sc, HIFN_1_DMA_CSR,
1541 HIFN_DMACSR_C_CTRL_DIS | HIFN_DMACSR_S_CTRL_DIS |
1542 HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS);
1548 * Initialize the descriptor rings.
1551 hifn_init_dma(struct hifn_softc *sc)
1553 struct hifn_dma *dma = sc->sc_dma;
1558 /* initialize static pointer values */
1559 for (i = 0; i < HIFN_D_CMD_RSIZE; i++)
1560 dma->cmdr[i].p = htole32(sc->sc_dma_physaddr +
1561 offsetof(struct hifn_dma, command_bufs[i][0]));
1562 for (i = 0; i < HIFN_D_RES_RSIZE; i++)
1563 dma->resr[i].p = htole32(sc->sc_dma_physaddr +
1564 offsetof(struct hifn_dma, result_bufs[i][0]));
1566 dma->cmdr[HIFN_D_CMD_RSIZE].p =
1567 htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, cmdr[0]));
1568 dma->srcr[HIFN_D_SRC_RSIZE].p =
1569 htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, srcr[0]));
1570 dma->dstr[HIFN_D_DST_RSIZE].p =
1571 htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, dstr[0]));
1572 dma->resr[HIFN_D_RES_RSIZE].p =
1573 htole32(sc->sc_dma_physaddr + offsetof(struct hifn_dma, resr[0]));
1575 dma->cmdu = dma->srcu = dma->dstu = dma->resu = 0;
1576 dma->cmdi = dma->srci = dma->dsti = dma->resi = 0;
1577 dma->cmdk = dma->srck = dma->dstk = dma->resk = 0;
1581 * Writes out the raw command buffer space. Returns the
1582 * command buffer size.
1585 hifn_write_command(struct hifn_command *cmd, u_int8_t *buf)
1588 hifn_base_command_t *base_cmd;
1589 hifn_mac_command_t *mac_cmd;
1590 hifn_crypt_command_t *cry_cmd;
1591 int using_mac, using_crypt, len, ivlen;
1592 u_int32_t dlen, slen;
1595 using_mac = cmd->base_masks & HIFN_BASE_CMD_MAC;
1596 using_crypt = cmd->base_masks & HIFN_BASE_CMD_CRYPT;
1598 base_cmd = (hifn_base_command_t *)buf_pos;
1599 base_cmd->masks = htole16(cmd->base_masks);
1600 slen = cmd->src_mapsize;
1602 dlen = cmd->dst_mapsize - cmd->sloplen + sizeof(u_int32_t);
1604 dlen = cmd->dst_mapsize;
1605 base_cmd->total_source_count = htole16(slen & HIFN_BASE_CMD_LENMASK_LO);
1606 base_cmd->total_dest_count = htole16(dlen & HIFN_BASE_CMD_LENMASK_LO);
1610 base_cmd->session_num = htole16(
1611 ((slen << HIFN_BASE_CMD_SRCLEN_S) & HIFN_BASE_CMD_SRCLEN_M) |
1612 ((dlen << HIFN_BASE_CMD_DSTLEN_S) & HIFN_BASE_CMD_DSTLEN_M));
1613 buf_pos += sizeof(hifn_base_command_t);
1616 mac_cmd = (hifn_mac_command_t *)buf_pos;
1617 dlen = cmd->maccrd->crd_len;
1618 mac_cmd->source_count = htole16(dlen & 0xffff);
1620 mac_cmd->masks = htole16(cmd->mac_masks |
1621 ((dlen << HIFN_MAC_CMD_SRCLEN_S) & HIFN_MAC_CMD_SRCLEN_M));
1622 mac_cmd->header_skip = htole16(cmd->maccrd->crd_skip);
1623 mac_cmd->reserved = 0;
1624 buf_pos += sizeof(hifn_mac_command_t);
1628 cry_cmd = (hifn_crypt_command_t *)buf_pos;
1629 dlen = cmd->enccrd->crd_len;
1630 cry_cmd->source_count = htole16(dlen & 0xffff);
1632 cry_cmd->masks = htole16(cmd->cry_masks |
1633 ((dlen << HIFN_CRYPT_CMD_SRCLEN_S) & HIFN_CRYPT_CMD_SRCLEN_M));
1634 cry_cmd->header_skip = htole16(cmd->enccrd->crd_skip);
1635 cry_cmd->reserved = 0;
1636 buf_pos += sizeof(hifn_crypt_command_t);
1639 if (using_mac && cmd->mac_masks & HIFN_MAC_CMD_NEW_KEY) {
1640 bcopy(cmd->mac, buf_pos, HIFN_MAC_KEY_LENGTH);
1641 buf_pos += HIFN_MAC_KEY_LENGTH;
1644 if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_KEY) {
1645 switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) {
1646 case HIFN_CRYPT_CMD_ALG_3DES:
1647 bcopy(cmd->ck, buf_pos, HIFN_3DES_KEY_LENGTH);
1648 buf_pos += HIFN_3DES_KEY_LENGTH;
1650 case HIFN_CRYPT_CMD_ALG_DES:
1651 bcopy(cmd->ck, buf_pos, HIFN_DES_KEY_LENGTH);
1652 buf_pos += HIFN_DES_KEY_LENGTH;
1654 case HIFN_CRYPT_CMD_ALG_RC4:
1659 clen = MIN(cmd->cklen, len);
1660 bcopy(cmd->ck, buf_pos, clen);
1667 case HIFN_CRYPT_CMD_ALG_AES:
1669 * AES keys are variable 128, 192 and
1670 * 256 bits (16, 24 and 32 bytes).
1672 bcopy(cmd->ck, buf_pos, cmd->cklen);
1673 buf_pos += cmd->cklen;
1678 if (using_crypt && cmd->cry_masks & HIFN_CRYPT_CMD_NEW_IV) {
1679 switch (cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) {
1680 case HIFN_CRYPT_CMD_ALG_AES:
1681 ivlen = HIFN_AES_IV_LENGTH;
1684 ivlen = HIFN_IV_LENGTH;
1687 bcopy(cmd->iv, buf_pos, ivlen);
1691 if ((cmd->base_masks & (HIFN_BASE_CMD_MAC|HIFN_BASE_CMD_CRYPT)) == 0) {
1696 return (buf_pos - buf);
1701 hifn_dmamap_aligned(struct hifn_operand *op)
1705 for (i = 0; i < op->nsegs; i++) {
1706 if (op->segs[i].ds_addr & 3)
1708 if ((i != (op->nsegs - 1)) && (op->segs[i].ds_len & 3))
1715 hifn_dmamap_dstwrap(struct hifn_softc *sc, int idx)
1717 struct hifn_dma *dma = sc->sc_dma;
1719 if (++idx == HIFN_D_DST_RSIZE) {
1720 dma->dstr[idx].l = htole32(HIFN_D_VALID | HIFN_D_JUMP |
1721 HIFN_D_MASKDONEIRQ);
1722 HIFN_DSTR_SYNC(sc, idx,
1723 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1730 hifn_dmamap_load_dst(struct hifn_softc *sc, struct hifn_command *cmd)
1732 struct hifn_dma *dma = sc->sc_dma;
1733 struct hifn_operand *dst = &cmd->dst;
1735 int idx, used = 0, i;
1738 for (i = 0; i < dst->nsegs - 1; i++) {
1739 dma->dstr[idx].p = htole32(dst->segs[i].ds_addr);
1740 dma->dstr[idx].l = htole32(HIFN_D_VALID |
1741 HIFN_D_MASKDONEIRQ | dst->segs[i].ds_len);
1742 HIFN_DSTR_SYNC(sc, idx,
1743 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1746 idx = hifn_dmamap_dstwrap(sc, idx);
1749 if (cmd->sloplen == 0) {
1750 p = dst->segs[i].ds_addr;
1751 l = HIFN_D_VALID | HIFN_D_MASKDONEIRQ | HIFN_D_LAST |
1752 dst->segs[i].ds_len;
1754 p = sc->sc_dma_physaddr +
1755 offsetof(struct hifn_dma, slop[cmd->slopidx]);
1756 l = HIFN_D_VALID | HIFN_D_MASKDONEIRQ | HIFN_D_LAST |
1759 if ((dst->segs[i].ds_len - cmd->sloplen) != 0) {
1760 dma->dstr[idx].p = htole32(dst->segs[i].ds_addr);
1761 dma->dstr[idx].l = htole32(HIFN_D_VALID |
1762 HIFN_D_MASKDONEIRQ |
1763 (dst->segs[i].ds_len - cmd->sloplen));
1764 HIFN_DSTR_SYNC(sc, idx,
1765 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1768 idx = hifn_dmamap_dstwrap(sc, idx);
1771 dma->dstr[idx].p = htole32(p);
1772 dma->dstr[idx].l = htole32(l);
1773 HIFN_DSTR_SYNC(sc, idx, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1776 idx = hifn_dmamap_dstwrap(sc, idx);
1784 hifn_dmamap_srcwrap(struct hifn_softc *sc, int idx)
1786 struct hifn_dma *dma = sc->sc_dma;
1788 if (++idx == HIFN_D_SRC_RSIZE) {
1789 dma->srcr[idx].l = htole32(HIFN_D_VALID |
1790 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
1791 HIFN_SRCR_SYNC(sc, HIFN_D_SRC_RSIZE,
1792 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1799 hifn_dmamap_load_src(struct hifn_softc *sc, struct hifn_command *cmd)
1801 struct hifn_dma *dma = sc->sc_dma;
1802 struct hifn_operand *src = &cmd->src;
1807 for (i = 0; i < src->nsegs; i++) {
1808 if (i == src->nsegs - 1)
1811 dma->srcr[idx].p = htole32(src->segs[i].ds_addr);
1812 dma->srcr[idx].l = htole32(src->segs[i].ds_len |
1813 HIFN_D_VALID | HIFN_D_MASKDONEIRQ | last);
1814 HIFN_SRCR_SYNC(sc, idx,
1815 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
1817 idx = hifn_dmamap_srcwrap(sc, idx);
1820 dma->srcu += src->nsegs;
1825 hifn_op_cb(void* arg, bus_dma_segment_t *seg, int nsegs, bus_size_t mapsize, int error)
1827 struct hifn_operand *op = arg;
1829 KASSERT(nsegs <= MAX_SCATTER,
1830 ("hifn_op_cb: too many DMA segments (%u > %u) "
1831 "returned when mapping operand", nsegs, MAX_SCATTER));
1832 op->mapsize = mapsize;
1834 bcopy(seg, op->segs, nsegs * sizeof (seg[0]));
1839 struct hifn_softc *sc,
1840 struct hifn_command *cmd,
1841 struct cryptop *crp,
1844 struct hifn_dma *dma = sc->sc_dma;
1845 u_int32_t cmdlen, csr;
1846 int cmdi, resi, err = 0;
1849 * need 1 cmd, and 1 res
1851 * NB: check this first since it's easy.
1854 if ((dma->cmdu + 1) > HIFN_D_CMD_RSIZE ||
1855 (dma->resu + 1) > HIFN_D_RES_RSIZE) {
1858 device_printf(sc->sc_dev,
1859 "cmd/result exhaustion, cmdu %u resu %u\n",
1860 dma->cmdu, dma->resu);
1863 hifnstats.hst_nomem_cr++;
1868 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &cmd->src_map)) {
1869 hifnstats.hst_nomem_map++;
1874 if (crp->crp_flags & CRYPTO_F_IMBUF) {
1875 if (bus_dmamap_load_mbuf(sc->sc_dmat, cmd->src_map,
1876 cmd->src_m, hifn_op_cb, &cmd->src, BUS_DMA_NOWAIT)) {
1877 hifnstats.hst_nomem_load++;
1881 } else if (crp->crp_flags & CRYPTO_F_IOV) {
1883 cmd->src_io->uio_segflg = UIO_USERSPACE;
1885 if (bus_dmamap_load_uio(sc->sc_dmat, cmd->src_map,
1886 cmd->src_io, hifn_op_cb, &cmd->src, BUS_DMA_NOWAIT)) {
1887 hifnstats.hst_nomem_load++;
1896 if (hifn_dmamap_aligned(&cmd->src)) {
1897 cmd->sloplen = cmd->src_mapsize & 3;
1898 cmd->dst = cmd->src;
1900 if (crp->crp_flags & CRYPTO_F_IOV) {
1903 } else if (crp->crp_flags & CRYPTO_F_IMBUF) {
1905 struct mbuf *m, *m0, *mlast;
1907 KASSERT(cmd->dst_m == cmd->src_m,
1908 ("hifn_crypto: dst_m initialized improperly"));
1909 hifnstats.hst_unaligned++;
1911 * Source is not aligned on a longword boundary.
1912 * Copy the data to insure alignment. If we fail
1913 * to allocate mbufs or clusters while doing this
1914 * we return ERESTART so the operation is requeued
1915 * at the crypto later, but only if there are
1916 * ops already posted to the hardware; otherwise we
1917 * have no guarantee that we'll be re-entered.
1919 totlen = cmd->src_mapsize;
1920 if (cmd->src_m->m_flags & M_PKTHDR) {
1922 MGETHDR(m0, M_NOWAIT, MT_DATA);
1923 if (m0 && !m_dup_pkthdr(m0, cmd->src_m, M_NOWAIT)) {
1929 MGET(m0, M_NOWAIT, MT_DATA);
1932 hifnstats.hst_nomem_mbuf++;
1933 err = dma->cmdu ? ERESTART : ENOMEM;
1936 if (totlen >= MINCLSIZE) {
1937 MCLGET(m0, M_NOWAIT);
1938 if ((m0->m_flags & M_EXT) == 0) {
1939 hifnstats.hst_nomem_mcl++;
1940 err = dma->cmdu ? ERESTART : ENOMEM;
1947 m0->m_pkthdr.len = m0->m_len = len;
1950 while (totlen > 0) {
1951 MGET(m, M_NOWAIT, MT_DATA);
1953 hifnstats.hst_nomem_mbuf++;
1954 err = dma->cmdu ? ERESTART : ENOMEM;
1959 if (totlen >= MINCLSIZE) {
1960 MCLGET(m, M_NOWAIT);
1961 if ((m->m_flags & M_EXT) == 0) {
1962 hifnstats.hst_nomem_mcl++;
1963 err = dma->cmdu ? ERESTART : ENOMEM;
1972 m0->m_pkthdr.len += len;
1982 if (cmd->dst_map == NULL) {
1983 if (bus_dmamap_create(sc->sc_dmat, BUS_DMA_NOWAIT, &cmd->dst_map)) {
1984 hifnstats.hst_nomem_map++;
1988 if (crp->crp_flags & CRYPTO_F_IMBUF) {
1989 if (bus_dmamap_load_mbuf(sc->sc_dmat, cmd->dst_map,
1990 cmd->dst_m, hifn_op_cb, &cmd->dst, BUS_DMA_NOWAIT)) {
1991 hifnstats.hst_nomem_map++;
1995 } else if (crp->crp_flags & CRYPTO_F_IOV) {
1997 cmd->dst_io->uio_segflg |= UIO_USERSPACE;
1999 if (bus_dmamap_load_uio(sc->sc_dmat, cmd->dst_map,
2000 cmd->dst_io, hifn_op_cb, &cmd->dst, BUS_DMA_NOWAIT)) {
2001 hifnstats.hst_nomem_load++;
2010 device_printf(sc->sc_dev,
2011 "Entering cmd: stat %8x ien %8x u %d/%d/%d/%d n %d/%d\n",
2012 READ_REG_1(sc, HIFN_1_DMA_CSR),
2013 READ_REG_1(sc, HIFN_1_DMA_IER),
2014 dma->cmdu, dma->srcu, dma->dstu, dma->resu,
2015 cmd->src_nsegs, cmd->dst_nsegs);
2019 if (cmd->src_map == cmd->dst_map) {
2020 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
2021 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD);
2023 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
2024 BUS_DMASYNC_PREWRITE);
2025 bus_dmamap_sync(sc->sc_dmat, cmd->dst_map,
2026 BUS_DMASYNC_PREREAD);
2030 * need N src, and N dst
2032 if ((dma->srcu + cmd->src_nsegs) > HIFN_D_SRC_RSIZE ||
2033 (dma->dstu + cmd->dst_nsegs + 1) > HIFN_D_DST_RSIZE) {
2036 device_printf(sc->sc_dev,
2037 "src/dst exhaustion, srcu %u+%u dstu %u+%u\n",
2038 dma->srcu, cmd->src_nsegs,
2039 dma->dstu, cmd->dst_nsegs);
2042 hifnstats.hst_nomem_sd++;
2047 if (dma->cmdi == HIFN_D_CMD_RSIZE) {
2049 dma->cmdr[HIFN_D_CMD_RSIZE].l = htole32(HIFN_D_VALID |
2050 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
2051 HIFN_CMDR_SYNC(sc, HIFN_D_CMD_RSIZE,
2052 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2055 cmdlen = hifn_write_command(cmd, dma->command_bufs[cmdi]);
2056 HIFN_CMD_SYNC(sc, cmdi, BUS_DMASYNC_PREWRITE);
2058 /* .p for command/result already set */
2059 dma->cmdr[cmdi].l = htole32(cmdlen | HIFN_D_VALID | HIFN_D_LAST |
2060 HIFN_D_MASKDONEIRQ);
2061 HIFN_CMDR_SYNC(sc, cmdi,
2062 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD);
2066 * We don't worry about missing an interrupt (which a "command wait"
2067 * interrupt salvages us from), unless there is more than one command
2070 if (dma->cmdu > 1) {
2071 sc->sc_dmaier |= HIFN_DMAIER_C_WAIT;
2072 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier);
2075 hifnstats.hst_ipackets++;
2076 hifnstats.hst_ibytes += cmd->src_mapsize;
2078 hifn_dmamap_load_src(sc, cmd);
2081 * Unlike other descriptors, we don't mask done interrupt from
2082 * result descriptor.
2086 kprintf("load res\n");
2088 if (dma->resi == HIFN_D_RES_RSIZE) {
2090 dma->resr[HIFN_D_RES_RSIZE].l = htole32(HIFN_D_VALID |
2091 HIFN_D_JUMP | HIFN_D_MASKDONEIRQ);
2092 HIFN_RESR_SYNC(sc, HIFN_D_RES_RSIZE,
2093 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2096 KASSERT(dma->hifn_commands[resi] == NULL,
2097 ("hifn_crypto: command slot %u busy", resi));
2098 dma->hifn_commands[resi] = cmd;
2099 HIFN_RES_SYNC(sc, resi, BUS_DMASYNC_PREREAD);
2100 if ((hint & CRYPTO_HINT_MORE) && sc->sc_curbatch < hifn_maxbatch) {
2101 dma->resr[resi].l = htole32(HIFN_MAX_RESULT |
2102 HIFN_D_VALID | HIFN_D_LAST | HIFN_D_MASKDONEIRQ);
2104 if (sc->sc_curbatch > hifnstats.hst_maxbatch)
2105 hifnstats.hst_maxbatch = sc->sc_curbatch;
2106 hifnstats.hst_totbatch++;
2108 dma->resr[resi].l = htole32(HIFN_MAX_RESULT |
2109 HIFN_D_VALID | HIFN_D_LAST);
2110 sc->sc_curbatch = 0;
2112 HIFN_RESR_SYNC(sc, resi,
2113 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2117 cmd->slopidx = resi;
2119 hifn_dmamap_load_dst(sc, cmd);
2122 if (sc->sc_c_busy == 0) {
2123 csr |= HIFN_DMACSR_C_CTRL_ENA;
2126 if (sc->sc_s_busy == 0) {
2127 csr |= HIFN_DMACSR_S_CTRL_ENA;
2130 if (sc->sc_r_busy == 0) {
2131 csr |= HIFN_DMACSR_R_CTRL_ENA;
2134 if (sc->sc_d_busy == 0) {
2135 csr |= HIFN_DMACSR_D_CTRL_ENA;
2139 WRITE_REG_1(sc, HIFN_1_DMA_CSR, csr);
2143 device_printf(sc->sc_dev, "command: stat %8x ier %8x\n",
2144 READ_REG_1(sc, HIFN_1_DMA_CSR),
2145 READ_REG_1(sc, HIFN_1_DMA_IER));
2151 KASSERT(err == 0, ("hifn_crypto: success with error %u", err));
2152 return (err); /* success */
2155 if (cmd->src_map != cmd->dst_map)
2156 bus_dmamap_unload(sc->sc_dmat, cmd->dst_map);
2158 if (cmd->src_map != cmd->dst_map)
2159 bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map);
2161 if (crp->crp_flags & CRYPTO_F_IMBUF) {
2162 if (cmd->src_m != cmd->dst_m)
2163 m_freem(cmd->dst_m);
2165 bus_dmamap_unload(sc->sc_dmat, cmd->src_map);
2167 bus_dmamap_destroy(sc->sc_dmat, cmd->src_map);
2173 hifn_tick(void* vsc)
2175 struct hifn_softc *sc = vsc;
2178 if (sc->sc_active == 0) {
2179 struct hifn_dma *dma = sc->sc_dma;
2182 if (dma->cmdu == 0 && sc->sc_c_busy) {
2184 r |= HIFN_DMACSR_C_CTRL_DIS;
2186 if (dma->srcu == 0 && sc->sc_s_busy) {
2188 r |= HIFN_DMACSR_S_CTRL_DIS;
2190 if (dma->dstu == 0 && sc->sc_d_busy) {
2192 r |= HIFN_DMACSR_D_CTRL_DIS;
2194 if (dma->resu == 0 && sc->sc_r_busy) {
2196 r |= HIFN_DMACSR_R_CTRL_DIS;
2199 WRITE_REG_1(sc, HIFN_1_DMA_CSR, r);
2203 callout_reset(&sc->sc_tickto, hz, hifn_tick, sc);
2207 hifn_intr(void *arg)
2209 struct hifn_softc *sc = arg;
2210 struct hifn_dma *dma;
2211 u_int32_t dmacsr, restart;
2214 dmacsr = READ_REG_1(sc, HIFN_1_DMA_CSR);
2216 /* Nothing in the DMA unit interrupted */
2217 if ((dmacsr & sc->sc_dmaier) == 0) {
2218 hifnstats.hst_noirq++;
2228 device_printf(sc->sc_dev,
2229 "irq: stat %08x ien %08x damier %08x i %d/%d/%d/%d k %d/%d/%d/%d u %d/%d/%d/%d\n",
2230 dmacsr, READ_REG_1(sc, HIFN_1_DMA_IER), sc->sc_dmaier,
2231 dma->cmdi, dma->srci, dma->dsti, dma->resi,
2232 dma->cmdk, dma->srck, dma->dstk, dma->resk,
2233 dma->cmdu, dma->srcu, dma->dstu, dma->resu);
2237 WRITE_REG_1(sc, HIFN_1_DMA_CSR, dmacsr & sc->sc_dmaier);
2239 if ((sc->sc_flags & HIFN_HAS_PUBLIC) &&
2240 (dmacsr & HIFN_DMACSR_PUBDONE))
2241 WRITE_REG_1(sc, HIFN_1_PUB_STATUS,
2242 READ_REG_1(sc, HIFN_1_PUB_STATUS) | HIFN_PUBSTS_DONE);
2244 restart = dmacsr & (HIFN_DMACSR_D_OVER | HIFN_DMACSR_R_OVER);
2246 device_printf(sc->sc_dev, "overrun %x\n", dmacsr);
2248 if (sc->sc_flags & HIFN_IS_7811) {
2249 if (dmacsr & HIFN_DMACSR_ILLR)
2250 device_printf(sc->sc_dev, "illegal read\n");
2251 if (dmacsr & HIFN_DMACSR_ILLW)
2252 device_printf(sc->sc_dev, "illegal write\n");
2255 restart = dmacsr & (HIFN_DMACSR_C_ABORT | HIFN_DMACSR_S_ABORT |
2256 HIFN_DMACSR_D_ABORT | HIFN_DMACSR_R_ABORT);
2258 device_printf(sc->sc_dev, "abort, resetting.\n");
2259 hifnstats.hst_abort++;
2265 if ((dmacsr & HIFN_DMACSR_C_WAIT) && (dma->cmdu == 0)) {
2267 * If no slots to process and we receive a "waiting on
2268 * command" interrupt, we disable the "waiting on command"
2271 sc->sc_dmaier &= ~HIFN_DMAIER_C_WAIT;
2272 WRITE_REG_1(sc, HIFN_1_DMA_IER, sc->sc_dmaier);
2275 /* clear the rings */
2276 i = dma->resk; u = dma->resu;
2278 HIFN_RESR_SYNC(sc, i,
2279 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2280 if (dma->resr[i].l & htole32(HIFN_D_VALID)) {
2281 HIFN_RESR_SYNC(sc, i,
2282 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2286 if (i != HIFN_D_RES_RSIZE) {
2287 struct hifn_command *cmd;
2288 u_int8_t *macbuf = NULL;
2290 HIFN_RES_SYNC(sc, i, BUS_DMASYNC_POSTREAD);
2291 cmd = dma->hifn_commands[i];
2292 KASSERT(cmd != NULL,
2293 ("hifn_intr: null command slot %u", i));
2294 dma->hifn_commands[i] = NULL;
2296 if (cmd->base_masks & HIFN_BASE_CMD_MAC) {
2297 macbuf = dma->result_bufs[i];
2301 hifn_callback(sc, cmd, macbuf);
2302 hifnstats.hst_opackets++;
2306 if (++i == (HIFN_D_RES_RSIZE + 1))
2309 dma->resk = i; dma->resu = u;
2311 i = dma->srck; u = dma->srcu;
2313 if (i == HIFN_D_SRC_RSIZE)
2315 HIFN_SRCR_SYNC(sc, i,
2316 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2317 if (dma->srcr[i].l & htole32(HIFN_D_VALID)) {
2318 HIFN_SRCR_SYNC(sc, i,
2319 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2324 dma->srck = i; dma->srcu = u;
2326 i = dma->cmdk; u = dma->cmdu;
2328 HIFN_CMDR_SYNC(sc, i,
2329 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2330 if (dma->cmdr[i].l & htole32(HIFN_D_VALID)) {
2331 HIFN_CMDR_SYNC(sc, i,
2332 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2335 if (i != HIFN_D_CMD_RSIZE) {
2337 HIFN_CMD_SYNC(sc, i, BUS_DMASYNC_POSTWRITE);
2339 if (++i == (HIFN_D_CMD_RSIZE + 1))
2342 dma->cmdk = i; dma->cmdu = u;
2346 if (sc->sc_needwakeup) { /* XXX check high watermark */
2347 int wakeup = sc->sc_needwakeup & (CRYPTO_SYMQ|CRYPTO_ASYMQ);
2350 device_printf(sc->sc_dev,
2351 "wakeup crypto (%x) u %d/%d/%d/%d\n",
2353 dma->cmdu, dma->srcu, dma->dstu, dma->resu);
2355 sc->sc_needwakeup &= ~wakeup;
2356 crypto_unblock(sc->sc_cid, wakeup);
2361 * Allocate a new 'session' and return an encoded session id. 'sidp'
2362 * contains our registration id, and should contain an encoded session
2363 * id on successful allocation.
2366 hifn_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri)
2368 struct cryptoini *c;
2369 struct hifn_softc *sc = device_get_softc(dev);
2370 int mac = 0, cry = 0, sesn;
2371 struct hifn_session *ses = NULL;
2373 KASSERT(sc != NULL, ("hifn_newsession: null softc"));
2374 if (sidp == NULL || cri == NULL || sc == NULL)
2378 if (sc->sc_sessions == NULL) {
2379 ses = sc->sc_sessions = (struct hifn_session *)kmalloc(
2380 sizeof(*ses), M_DEVBUF, M_NOWAIT);
2386 sc->sc_nsessions = 1;
2388 for (sesn = 0; sesn < sc->sc_nsessions; sesn++) {
2389 if (!sc->sc_sessions[sesn].hs_used) {
2390 ses = &sc->sc_sessions[sesn];
2396 sesn = sc->sc_nsessions;
2397 ses = (struct hifn_session *)kmalloc((sesn + 1) *
2398 sizeof(*ses), M_DEVBUF, M_NOWAIT);
2403 bcopy(sc->sc_sessions, ses, sesn * sizeof(*ses));
2404 bzero(sc->sc_sessions, sesn * sizeof(*ses));
2405 kfree(sc->sc_sessions, M_DEVBUF);
2406 sc->sc_sessions = ses;
2407 ses = &sc->sc_sessions[sesn];
2413 bzero(ses, sizeof(*ses));
2416 for (c = cri; c != NULL; c = c->cri_next) {
2417 switch (c->cri_alg) {
2420 case CRYPTO_MD5_HMAC:
2421 case CRYPTO_SHA1_HMAC:
2425 ses->hs_mlen = c->cri_mlen;
2426 if (ses->hs_mlen == 0) {
2427 switch (c->cri_alg) {
2429 case CRYPTO_MD5_HMAC:
2433 case CRYPTO_SHA1_HMAC:
2439 case CRYPTO_DES_CBC:
2440 case CRYPTO_3DES_CBC:
2441 case CRYPTO_AES_CBC:
2442 /* XXX this may read fewer, does it matter? */
2443 read_random(ses->hs_iv,
2444 c->cri_alg == CRYPTO_AES_CBC ?
2445 HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH);
2456 if (mac == 0 && cry == 0)
2459 *sidp = HIFN_SID(device_get_unit(sc->sc_dev), sesn);
2465 * Deallocate a session.
2466 * XXX this routine should run a zero'd mac/encrypt key into context ram.
2467 * XXX to blow away any keys already stored there.
2469 #define CRYPTO_SESID2LID(_sid) (((u_int32_t) (_sid)) & 0xffffffff)
2472 hifn_freesession(device_t dev, u_int64_t tid)
2474 struct hifn_softc *sc = device_get_softc(dev);
2476 u_int32_t sid = CRYPTO_SESID2LID(tid);
2478 KASSERT(sc != NULL, ("hifn_freesession: null softc"));
2483 session = HIFN_SESSION(sid);
2484 if (session < sc->sc_nsessions) {
2485 bzero(&sc->sc_sessions[session], sizeof(struct hifn_session));
2495 hifn_process(device_t dev, struct cryptop *crp, int hint)
2497 struct hifn_softc *sc = device_get_softc(dev);
2498 struct hifn_command *cmd = NULL;
2499 int session, err, ivlen;
2500 struct cryptodesc *crd1, *crd2, *maccrd, *enccrd;
2502 if (crp == NULL || crp->crp_callback == NULL) {
2503 hifnstats.hst_invalid++;
2506 session = HIFN_SESSION(crp->crp_sid);
2508 if (sc == NULL || session >= sc->sc_nsessions) {
2513 cmd = kmalloc(sizeof(struct hifn_command), M_DEVBUF, M_INTWAIT | M_ZERO);
2515 if (crp->crp_flags & CRYPTO_F_IMBUF) {
2516 cmd->src_m = (struct mbuf *)crp->crp_buf;
2517 cmd->dst_m = (struct mbuf *)crp->crp_buf;
2518 } else if (crp->crp_flags & CRYPTO_F_IOV) {
2519 cmd->src_io = (struct uio *)crp->crp_buf;
2520 cmd->dst_io = (struct uio *)crp->crp_buf;
2523 goto errout; /* XXX we don't handle contiguous buffers! */
2526 crd1 = crp->crp_desc;
2531 crd2 = crd1->crd_next;
2534 if (crd1->crd_alg == CRYPTO_MD5_HMAC ||
2535 crd1->crd_alg == CRYPTO_SHA1_HMAC ||
2536 crd1->crd_alg == CRYPTO_SHA1 ||
2537 crd1->crd_alg == CRYPTO_MD5) {
2540 } else if (crd1->crd_alg == CRYPTO_DES_CBC ||
2541 crd1->crd_alg == CRYPTO_3DES_CBC ||
2542 crd1->crd_alg == CRYPTO_AES_CBC ||
2543 crd1->crd_alg == CRYPTO_ARC4) {
2544 if ((crd1->crd_flags & CRD_F_ENCRYPT) == 0)
2545 cmd->base_masks |= HIFN_BASE_CMD_DECODE;
2553 if ((crd1->crd_alg == CRYPTO_MD5_HMAC ||
2554 crd1->crd_alg == CRYPTO_SHA1_HMAC ||
2555 crd1->crd_alg == CRYPTO_MD5 ||
2556 crd1->crd_alg == CRYPTO_SHA1) &&
2557 (crd2->crd_alg == CRYPTO_DES_CBC ||
2558 crd2->crd_alg == CRYPTO_3DES_CBC ||
2559 crd2->crd_alg == CRYPTO_AES_CBC ||
2560 crd2->crd_alg == CRYPTO_ARC4) &&
2561 ((crd2->crd_flags & CRD_F_ENCRYPT) == 0)) {
2562 cmd->base_masks = HIFN_BASE_CMD_DECODE;
2565 } else if ((crd1->crd_alg == CRYPTO_DES_CBC ||
2566 crd1->crd_alg == CRYPTO_ARC4 ||
2567 crd1->crd_alg == CRYPTO_3DES_CBC ||
2568 crd1->crd_alg == CRYPTO_AES_CBC) &&
2569 (crd2->crd_alg == CRYPTO_MD5_HMAC ||
2570 crd2->crd_alg == CRYPTO_SHA1_HMAC ||
2571 crd2->crd_alg == CRYPTO_MD5 ||
2572 crd2->crd_alg == CRYPTO_SHA1) &&
2573 (crd1->crd_flags & CRD_F_ENCRYPT)) {
2578 * We cannot order the 7751 as requested
2586 cmd->enccrd = enccrd;
2587 cmd->base_masks |= HIFN_BASE_CMD_CRYPT;
2588 switch (enccrd->crd_alg) {
2590 cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_RC4;
2592 case CRYPTO_DES_CBC:
2593 cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_DES |
2594 HIFN_CRYPT_CMD_MODE_CBC |
2595 HIFN_CRYPT_CMD_NEW_IV;
2597 case CRYPTO_3DES_CBC:
2598 cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_3DES |
2599 HIFN_CRYPT_CMD_MODE_CBC |
2600 HIFN_CRYPT_CMD_NEW_IV;
2602 case CRYPTO_AES_CBC:
2603 cmd->cry_masks |= HIFN_CRYPT_CMD_ALG_AES |
2604 HIFN_CRYPT_CMD_MODE_CBC |
2605 HIFN_CRYPT_CMD_NEW_IV;
2611 if (enccrd->crd_alg != CRYPTO_ARC4) {
2612 ivlen = ((enccrd->crd_alg == CRYPTO_AES_CBC) ?
2613 HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH);
2614 if (enccrd->crd_flags & CRD_F_ENCRYPT) {
2615 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
2616 bcopy(enccrd->crd_iv, cmd->iv, ivlen);
2618 bcopy(sc->sc_sessions[session].hs_iv,
2621 if ((enccrd->crd_flags & CRD_F_IV_PRESENT)
2623 crypto_copyback(crp->crp_flags,
2624 crp->crp_buf, enccrd->crd_inject,
2628 if (enccrd->crd_flags & CRD_F_IV_EXPLICIT)
2629 bcopy(enccrd->crd_iv, cmd->iv, ivlen);
2631 crypto_copydata(crp->crp_flags,
2632 crp->crp_buf, enccrd->crd_inject,
2638 if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT)
2639 cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY;
2640 cmd->ck = enccrd->crd_key;
2641 cmd->cklen = enccrd->crd_klen >> 3;
2642 cmd->cry_masks |= HIFN_CRYPT_CMD_NEW_KEY;
2645 * Need to specify the size for the AES key in the masks.
2647 if ((cmd->cry_masks & HIFN_CRYPT_CMD_ALG_MASK) ==
2648 HIFN_CRYPT_CMD_ALG_AES) {
2649 switch (cmd->cklen) {
2651 cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_128;
2654 cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_192;
2657 cmd->cry_masks |= HIFN_CRYPT_CMD_KSZ_256;
2667 cmd->maccrd = maccrd;
2668 cmd->base_masks |= HIFN_BASE_CMD_MAC;
2670 switch (maccrd->crd_alg) {
2672 cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 |
2673 HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH |
2674 HIFN_MAC_CMD_POS_IPSEC;
2676 case CRYPTO_MD5_HMAC:
2677 cmd->mac_masks |= HIFN_MAC_CMD_ALG_MD5 |
2678 HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC |
2679 HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC;
2682 cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 |
2683 HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HASH |
2684 HIFN_MAC_CMD_POS_IPSEC;
2686 case CRYPTO_SHA1_HMAC:
2687 cmd->mac_masks |= HIFN_MAC_CMD_ALG_SHA1 |
2688 HIFN_MAC_CMD_RESULT | HIFN_MAC_CMD_MODE_HMAC |
2689 HIFN_MAC_CMD_POS_IPSEC | HIFN_MAC_CMD_TRUNC;
2693 if (maccrd->crd_alg == CRYPTO_SHA1_HMAC ||
2694 maccrd->crd_alg == CRYPTO_MD5_HMAC) {
2695 cmd->mac_masks |= HIFN_MAC_CMD_NEW_KEY;
2696 bcopy(maccrd->crd_key, cmd->mac, maccrd->crd_klen >> 3);
2697 bzero(cmd->mac + (maccrd->crd_klen >> 3),
2698 HIFN_MAC_KEY_LENGTH - (maccrd->crd_klen >> 3));
2703 cmd->session_num = session;
2706 err = hifn_crypto(sc, cmd, crp, hint);
2709 } else if (err == ERESTART) {
2711 * There weren't enough resources to dispatch the request
2712 * to the part. Notify the caller so they'll requeue this
2713 * request and resubmit it again soon.
2717 device_printf(sc->sc_dev, "requeue request\n");
2719 kfree(cmd, M_DEVBUF);
2720 sc->sc_needwakeup |= CRYPTO_SYMQ;
2726 kfree(cmd, M_DEVBUF);
2728 hifnstats.hst_invalid++;
2730 hifnstats.hst_nomem++;
2731 crp->crp_etype = err;
2737 hifn_abort(struct hifn_softc *sc)
2739 struct hifn_dma *dma = sc->sc_dma;
2740 struct hifn_command *cmd;
2741 struct cryptop *crp;
2744 i = dma->resk; u = dma->resu;
2746 cmd = dma->hifn_commands[i];
2747 KASSERT(cmd != NULL, ("hifn_abort: null command slot %u", i));
2748 dma->hifn_commands[i] = NULL;
2751 if ((dma->resr[i].l & htole32(HIFN_D_VALID)) == 0) {
2752 /* Salvage what we can. */
2755 if (cmd->base_masks & HIFN_BASE_CMD_MAC) {
2756 macbuf = dma->result_bufs[i];
2760 hifnstats.hst_opackets++;
2761 hifn_callback(sc, cmd, macbuf);
2763 if (cmd->src_map == cmd->dst_map) {
2764 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
2765 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
2767 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
2768 BUS_DMASYNC_POSTWRITE);
2769 bus_dmamap_sync(sc->sc_dmat, cmd->dst_map,
2770 BUS_DMASYNC_POSTREAD);
2773 if (cmd->src_m != cmd->dst_m) {
2774 m_freem(cmd->src_m);
2775 crp->crp_buf = (caddr_t)cmd->dst_m;
2778 /* non-shared buffers cannot be restarted */
2779 if (cmd->src_map != cmd->dst_map) {
2781 * XXX should be EAGAIN, delayed until
2784 crp->crp_etype = ENOMEM;
2785 bus_dmamap_unload(sc->sc_dmat, cmd->dst_map);
2786 bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map);
2788 crp->crp_etype = ENOMEM;
2790 bus_dmamap_unload(sc->sc_dmat, cmd->src_map);
2791 bus_dmamap_destroy(sc->sc_dmat, cmd->src_map);
2793 kfree(cmd, M_DEVBUF);
2794 if (crp->crp_etype != EAGAIN)
2798 if (++i == HIFN_D_RES_RSIZE)
2802 dma->resk = i; dma->resu = u;
2804 hifn_reset_board(sc, 1);
2806 hifn_init_pci_registers(sc);
2810 hifn_callback(struct hifn_softc *sc, struct hifn_command *cmd, u_int8_t *macbuf)
2812 struct hifn_dma *dma = sc->sc_dma;
2813 struct cryptop *crp = cmd->crp;
2814 struct cryptodesc *crd;
2816 int totlen, i, u, ivlen;
2818 if (cmd->src_map == cmd->dst_map) {
2819 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
2820 BUS_DMASYNC_POSTWRITE | BUS_DMASYNC_POSTREAD);
2822 bus_dmamap_sync(sc->sc_dmat, cmd->src_map,
2823 BUS_DMASYNC_POSTWRITE);
2824 bus_dmamap_sync(sc->sc_dmat, cmd->dst_map,
2825 BUS_DMASYNC_POSTREAD);
2828 if (crp->crp_flags & CRYPTO_F_IMBUF) {
2829 if (cmd->src_m != cmd->dst_m) {
2830 crp->crp_buf = (caddr_t)cmd->dst_m;
2831 totlen = cmd->src_mapsize;
2832 for (m = cmd->dst_m; m != NULL; m = m->m_next) {
2833 if (totlen < m->m_len) {
2839 cmd->dst_m->m_pkthdr.len = cmd->src_m->m_pkthdr.len;
2840 m_freem(cmd->src_m);
2844 if (cmd->sloplen != 0) {
2845 crypto_copyback(crp->crp_flags, crp->crp_buf,
2846 cmd->src_mapsize - cmd->sloplen, cmd->sloplen,
2847 (caddr_t)&dma->slop[cmd->slopidx]);
2850 i = dma->dstk; u = dma->dstu;
2852 if (i == HIFN_D_DST_RSIZE)
2854 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
2855 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2856 if (dma->dstr[i].l & htole32(HIFN_D_VALID)) {
2857 bus_dmamap_sync(sc->sc_dmat, sc->sc_dmamap,
2858 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2863 dma->dstk = i; dma->dstu = u;
2865 hifnstats.hst_obytes += cmd->dst_mapsize;
2867 if ((cmd->base_masks & (HIFN_BASE_CMD_CRYPT | HIFN_BASE_CMD_DECODE)) ==
2868 HIFN_BASE_CMD_CRYPT) {
2869 for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
2870 if (crd->crd_alg != CRYPTO_DES_CBC &&
2871 crd->crd_alg != CRYPTO_3DES_CBC &&
2872 crd->crd_alg != CRYPTO_AES_CBC)
2874 ivlen = ((crd->crd_alg == CRYPTO_AES_CBC) ?
2875 HIFN_AES_IV_LENGTH : HIFN_IV_LENGTH);
2876 crypto_copydata(crp->crp_flags, crp->crp_buf,
2877 crd->crd_skip + crd->crd_len - ivlen, ivlen,
2878 cmd->softc->sc_sessions[cmd->session_num].hs_iv);
2883 if (macbuf != NULL) {
2884 for (crd = crp->crp_desc; crd; crd = crd->crd_next) {
2887 if (crd->crd_alg != CRYPTO_MD5 &&
2888 crd->crd_alg != CRYPTO_SHA1 &&
2889 crd->crd_alg != CRYPTO_MD5_HMAC &&
2890 crd->crd_alg != CRYPTO_SHA1_HMAC) {
2893 len = cmd->softc->sc_sessions[cmd->session_num].hs_mlen;
2894 crypto_copyback(crp->crp_flags, crp->crp_buf,
2895 crd->crd_inject, len, macbuf);
2900 if (cmd->src_map != cmd->dst_map) {
2901 bus_dmamap_unload(sc->sc_dmat, cmd->dst_map);
2902 bus_dmamap_destroy(sc->sc_dmat, cmd->dst_map);
2904 bus_dmamap_unload(sc->sc_dmat, cmd->src_map);
2905 bus_dmamap_destroy(sc->sc_dmat, cmd->src_map);
2906 kfree(cmd, M_DEVBUF);
2911 * 7811 PB3 rev/2 parts lock-up on burst writes to Group 0
2912 * and Group 1 registers; avoid conditions that could create
2913 * burst writes by doing a read in between the writes.
2915 * NB: The read we interpose is always to the same register;
2916 * we do this because reading from an arbitrary (e.g. last)
2917 * register may not always work.
2920 hifn_write_reg_0(struct hifn_softc *sc, bus_size_t reg, u_int32_t val)
2922 if (sc->sc_flags & HIFN_IS_7811) {
2923 if (sc->sc_bar0_lastreg == reg - 4)
2924 bus_space_read_4(sc->sc_st0, sc->sc_sh0, HIFN_0_PUCNFG);
2925 sc->sc_bar0_lastreg = reg;
2927 bus_space_write_4(sc->sc_st0, sc->sc_sh0, reg, val);
2931 hifn_write_reg_1(struct hifn_softc *sc, bus_size_t reg, u_int32_t val)
2933 if (sc->sc_flags & HIFN_IS_7811) {
2934 if (sc->sc_bar1_lastreg == reg - 4)
2935 bus_space_read_4(sc->sc_st1, sc->sc_sh1, HIFN_1_REVID);
2936 sc->sc_bar1_lastreg = reg;
2938 bus_space_write_4(sc->sc_st1, sc->sc_sh1, reg, val);