2 * Copyright (c) 2004 Joerg Sonnenberger <joerg@bec.de>. All rights reserved.
4 * Copyright (c) 2001-2008, Intel Corporation
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * 3. Neither the name of the Intel Corporation nor the names of its
18 * contributors may be used to endorse or promote products derived from
19 * this software without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
34 * Copyright (c) 2005 The DragonFly Project. All rights reserved.
36 * This code is derived from software contributed to The DragonFly Project
37 * by Matthew Dillon <dillon@backplane.com>
39 * Redistribution and use in source and binary forms, with or without
40 * modification, are permitted provided that the following conditions
43 * 1. Redistributions of source code must retain the above copyright
44 * notice, this list of conditions and the following disclaimer.
45 * 2. Redistributions in binary form must reproduce the above copyright
46 * notice, this list of conditions and the following disclaimer in
47 * the documentation and/or other materials provided with the
49 * 3. Neither the name of The DragonFly Project nor the names of its
50 * contributors may be used to endorse or promote products derived
51 * from this software without specific, prior written permission.
53 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
54 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
55 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
56 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
57 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
58 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
59 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
60 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
61 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
62 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
63 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
67 #include "opt_ifpoll.h"
70 #include <sys/param.h>
72 #include <sys/endian.h>
73 #include <sys/interrupt.h>
74 #include <sys/kernel.h>
76 #include <sys/malloc.h>
80 #include <sys/serialize.h>
81 #include <sys/serialize2.h>
82 #include <sys/socket.h>
83 #include <sys/sockio.h>
84 #include <sys/sysctl.h>
85 #include <sys/systm.h>
88 #include <net/ethernet.h>
90 #include <net/if_arp.h>
91 #include <net/if_dl.h>
92 #include <net/if_media.h>
93 #include <net/ifq_var.h>
94 #include <net/toeplitz.h>
95 #include <net/toeplitz2.h>
96 #include <net/vlan/if_vlan_var.h>
97 #include <net/vlan/if_vlan_ether.h>
98 #include <net/if_poll.h>
100 #include <netinet/in_systm.h>
101 #include <netinet/in.h>
102 #include <netinet/ip.h>
103 #include <netinet/tcp.h>
104 #include <netinet/udp.h>
106 #include <bus/pci/pcivar.h>
107 #include <bus/pci/pcireg.h>
109 #include <dev/netif/ig_hal/e1000_api.h>
110 #include <dev/netif/ig_hal/e1000_82571.h>
111 #include <dev/netif/emx/if_emx.h>
116 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) \
118 if (sc->rss_debug >= lvl) \
119 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
121 #else /* !EMX_RSS_DEBUG */
122 #define EMX_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
123 #endif /* EMX_RSS_DEBUG */
125 #define EMX_NAME "Intel(R) PRO/1000 "
127 #define EMX_DEVICE(id) \
128 { EMX_VENDOR_ID, E1000_DEV_ID_##id, EMX_NAME #id }
129 #define EMX_DEVICE_NULL { 0, 0, NULL }
131 static const struct emx_device {
136 EMX_DEVICE(82571EB_COPPER),
137 EMX_DEVICE(82571EB_FIBER),
138 EMX_DEVICE(82571EB_SERDES),
139 EMX_DEVICE(82571EB_SERDES_DUAL),
140 EMX_DEVICE(82571EB_SERDES_QUAD),
141 EMX_DEVICE(82571EB_QUAD_COPPER),
142 EMX_DEVICE(82571EB_QUAD_COPPER_BP),
143 EMX_DEVICE(82571EB_QUAD_COPPER_LP),
144 EMX_DEVICE(82571EB_QUAD_FIBER),
145 EMX_DEVICE(82571PT_QUAD_COPPER),
147 EMX_DEVICE(82572EI_COPPER),
148 EMX_DEVICE(82572EI_FIBER),
149 EMX_DEVICE(82572EI_SERDES),
153 EMX_DEVICE(82573E_IAMT),
156 EMX_DEVICE(80003ES2LAN_COPPER_SPT),
157 EMX_DEVICE(80003ES2LAN_SERDES_SPT),
158 EMX_DEVICE(80003ES2LAN_COPPER_DPT),
159 EMX_DEVICE(80003ES2LAN_SERDES_DPT),
164 EMX_DEVICE(PCH_LPT_I217_LM),
165 EMX_DEVICE(PCH_LPT_I217_V),
166 EMX_DEVICE(PCH_LPTLP_I218_LM),
167 EMX_DEVICE(PCH_LPTLP_I218_V),
168 EMX_DEVICE(PCH_I218_LM2),
169 EMX_DEVICE(PCH_I218_V2),
170 EMX_DEVICE(PCH_I218_LM3),
171 EMX_DEVICE(PCH_I218_V3),
173 /* required last entry */
177 static int emx_probe(device_t);
178 static int emx_attach(device_t);
179 static int emx_detach(device_t);
180 static int emx_shutdown(device_t);
181 static int emx_suspend(device_t);
182 static int emx_resume(device_t);
184 static void emx_init(void *);
185 static void emx_stop(struct emx_softc *);
186 static int emx_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
187 static void emx_start(struct ifnet *, struct ifaltq_subque *);
189 static void emx_npoll(struct ifnet *, struct ifpoll_info *);
190 static void emx_npoll_status(struct ifnet *);
191 static void emx_npoll_tx(struct ifnet *, void *, int);
192 static void emx_npoll_rx(struct ifnet *, void *, int);
194 static void emx_watchdog(struct ifaltq_subque *);
195 static void emx_media_status(struct ifnet *, struct ifmediareq *);
196 static int emx_media_change(struct ifnet *);
197 static void emx_timer(void *);
198 static void emx_serialize(struct ifnet *, enum ifnet_serialize);
199 static void emx_deserialize(struct ifnet *, enum ifnet_serialize);
200 static int emx_tryserialize(struct ifnet *, enum ifnet_serialize);
202 static void emx_serialize_assert(struct ifnet *, enum ifnet_serialize,
206 static void emx_intr(void *);
207 static void emx_intr_mask(void *);
208 static void emx_intr_body(struct emx_softc *, boolean_t);
209 static void emx_rxeof(struct emx_rxdata *, int);
210 static void emx_txeof(struct emx_txdata *);
211 static void emx_tx_collect(struct emx_txdata *);
212 static void emx_tx_purge(struct emx_softc *);
213 static void emx_enable_intr(struct emx_softc *);
214 static void emx_disable_intr(struct emx_softc *);
216 static int emx_dma_alloc(struct emx_softc *);
217 static void emx_dma_free(struct emx_softc *);
218 static void emx_init_tx_ring(struct emx_txdata *);
219 static int emx_init_rx_ring(struct emx_rxdata *);
220 static void emx_free_tx_ring(struct emx_txdata *);
221 static void emx_free_rx_ring(struct emx_rxdata *);
222 static int emx_create_tx_ring(struct emx_txdata *);
223 static int emx_create_rx_ring(struct emx_rxdata *);
224 static void emx_destroy_tx_ring(struct emx_txdata *, int);
225 static void emx_destroy_rx_ring(struct emx_rxdata *, int);
226 static int emx_newbuf(struct emx_rxdata *, int, int);
227 static int emx_encap(struct emx_txdata *, struct mbuf **, int *, int *);
228 static int emx_txcsum(struct emx_txdata *, struct mbuf *,
229 uint32_t *, uint32_t *);
230 static int emx_tso_pullup(struct emx_txdata *, struct mbuf **);
231 static int emx_tso_setup(struct emx_txdata *, struct mbuf *,
232 uint32_t *, uint32_t *);
233 static int emx_get_txring_inuse(const struct emx_softc *, boolean_t);
235 static int emx_is_valid_eaddr(const uint8_t *);
236 static int emx_reset(struct emx_softc *);
237 static void emx_setup_ifp(struct emx_softc *);
238 static void emx_init_tx_unit(struct emx_softc *);
239 static void emx_init_rx_unit(struct emx_softc *);
240 static void emx_update_stats(struct emx_softc *);
241 static void emx_set_promisc(struct emx_softc *);
242 static void emx_disable_promisc(struct emx_softc *);
243 static void emx_set_multi(struct emx_softc *);
244 static void emx_update_link_status(struct emx_softc *);
245 static void emx_smartspeed(struct emx_softc *);
246 static void emx_set_itr(struct emx_softc *, uint32_t);
247 static void emx_disable_aspm(struct emx_softc *);
249 static void emx_print_debug_info(struct emx_softc *);
250 static void emx_print_nvm_info(struct emx_softc *);
251 static void emx_print_hw_stats(struct emx_softc *);
253 static int emx_sysctl_stats(SYSCTL_HANDLER_ARGS);
254 static int emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS);
255 static int emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS);
256 static int emx_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS);
257 static int emx_sysctl_tx_wreg_nsegs(SYSCTL_HANDLER_ARGS);
259 static int emx_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS);
260 static int emx_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS);
262 static void emx_add_sysctl(struct emx_softc *);
264 static void emx_serialize_skipmain(struct emx_softc *);
265 static void emx_deserialize_skipmain(struct emx_softc *);
267 /* Management and WOL Support */
268 static void emx_get_mgmt(struct emx_softc *);
269 static void emx_rel_mgmt(struct emx_softc *);
270 static void emx_get_hw_control(struct emx_softc *);
271 static void emx_rel_hw_control(struct emx_softc *);
272 static void emx_enable_wol(device_t);
274 static device_method_t emx_methods[] = {
275 /* Device interface */
276 DEVMETHOD(device_probe, emx_probe),
277 DEVMETHOD(device_attach, emx_attach),
278 DEVMETHOD(device_detach, emx_detach),
279 DEVMETHOD(device_shutdown, emx_shutdown),
280 DEVMETHOD(device_suspend, emx_suspend),
281 DEVMETHOD(device_resume, emx_resume),
285 static driver_t emx_driver = {
288 sizeof(struct emx_softc),
291 static devclass_t emx_devclass;
293 DECLARE_DUMMY_MODULE(if_emx);
294 MODULE_DEPEND(emx, ig_hal, 1, 1, 1);
295 DRIVER_MODULE(if_emx, pci, emx_driver, emx_devclass, NULL, NULL);
300 static int emx_int_throttle_ceil = EMX_DEFAULT_ITR;
301 static int emx_rxd = EMX_DEFAULT_RXD;
302 static int emx_txd = EMX_DEFAULT_TXD;
303 static int emx_smart_pwr_down = 0;
304 static int emx_rxr = 0;
305 static int emx_txr = 1;
307 /* Controls whether promiscuous also shows bad packets */
308 static int emx_debug_sbp = 0;
310 static int emx_82573_workaround = 1;
311 static int emx_msi_enable = 1;
313 TUNABLE_INT("hw.emx.int_throttle_ceil", &emx_int_throttle_ceil);
314 TUNABLE_INT("hw.emx.rxd", &emx_rxd);
315 TUNABLE_INT("hw.emx.rxr", &emx_rxr);
316 TUNABLE_INT("hw.emx.txd", &emx_txd);
317 TUNABLE_INT("hw.emx.txr", &emx_txr);
318 TUNABLE_INT("hw.emx.smart_pwr_down", &emx_smart_pwr_down);
319 TUNABLE_INT("hw.emx.sbp", &emx_debug_sbp);
320 TUNABLE_INT("hw.emx.82573_workaround", &emx_82573_workaround);
321 TUNABLE_INT("hw.emx.msi.enable", &emx_msi_enable);
323 /* Global used in WOL setup with multiport cards */
324 static int emx_global_quad_port_a = 0;
326 /* Set this to one to display debug statistics */
327 static int emx_display_debug_stats = 0;
329 #if !defined(KTR_IF_EMX)
330 #define KTR_IF_EMX KTR_ALL
332 KTR_INFO_MASTER(if_emx);
333 KTR_INFO(KTR_IF_EMX, if_emx, intr_beg, 0, "intr begin");
334 KTR_INFO(KTR_IF_EMX, if_emx, intr_end, 1, "intr end");
335 KTR_INFO(KTR_IF_EMX, if_emx, pkt_receive, 4, "rx packet");
336 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txqueue, 5, "tx packet");
337 KTR_INFO(KTR_IF_EMX, if_emx, pkt_txclean, 6, "tx clean");
338 #define logif(name) KTR_LOG(if_emx_ ## name)
341 emx_setup_rxdesc(emx_rxdesc_t *rxd, const struct emx_rxbuf *rxbuf)
343 rxd->rxd_bufaddr = htole64(rxbuf->paddr);
344 /* DD bit must be cleared */
345 rxd->rxd_staterr = 0;
349 emx_rxcsum(uint32_t staterr, struct mbuf *mp)
351 /* Ignore Checksum bit is set */
352 if (staterr & E1000_RXD_STAT_IXSM)
355 if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
357 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
359 if ((staterr & (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
360 E1000_RXD_STAT_TCPCS) {
361 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
363 CSUM_FRAG_NOT_CHECKED;
364 mp->m_pkthdr.csum_data = htons(0xffff);
368 static __inline struct pktinfo *
369 emx_rssinfo(struct mbuf *m, struct pktinfo *pi,
370 uint32_t mrq, uint32_t hash, uint32_t staterr)
372 switch (mrq & EMX_RXDMRQ_RSSTYPE_MASK) {
373 case EMX_RXDMRQ_IPV4_TCP:
374 pi->pi_netisr = NETISR_IP;
376 pi->pi_l3proto = IPPROTO_TCP;
379 case EMX_RXDMRQ_IPV6_TCP:
380 pi->pi_netisr = NETISR_IPV6;
382 pi->pi_l3proto = IPPROTO_TCP;
385 case EMX_RXDMRQ_IPV4:
386 if (staterr & E1000_RXD_STAT_IXSM)
390 (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
391 E1000_RXD_STAT_TCPCS) {
392 pi->pi_netisr = NETISR_IP;
394 pi->pi_l3proto = IPPROTO_UDP;
402 m->m_flags |= M_HASH;
403 m->m_pkthdr.hash = toeplitz_hash(hash);
408 emx_probe(device_t dev)
410 const struct emx_device *d;
413 vid = pci_get_vendor(dev);
414 did = pci_get_device(dev);
416 for (d = emx_devices; d->desc != NULL; ++d) {
417 if (vid == d->vid && did == d->did) {
418 device_set_desc(dev, d->desc);
419 device_set_async_attach(dev, TRUE);
427 emx_attach(device_t dev)
429 struct emx_softc *sc = device_get_softc(dev);
430 int error = 0, i, throttle, msi_enable, tx_ring_max;
432 uint16_t eeprom_data, device_id, apme_mask;
433 driver_intr_t *intr_func;
435 int offset, offset_def;
441 for (i = 0; i < EMX_NRX_RING; ++i) {
442 sc->rx_data[i].sc = sc;
443 sc->rx_data[i].idx = i;
449 for (i = 0; i < EMX_NTX_RING; ++i) {
450 sc->tx_data[i].sc = sc;
451 sc->tx_data[i].idx = i;
455 * Initialize serializers
457 lwkt_serialize_init(&sc->main_serialize);
458 for (i = 0; i < EMX_NTX_RING; ++i)
459 lwkt_serialize_init(&sc->tx_data[i].tx_serialize);
460 for (i = 0; i < EMX_NRX_RING; ++i)
461 lwkt_serialize_init(&sc->rx_data[i].rx_serialize);
464 * Initialize serializer array
468 KKASSERT(i < EMX_NSERIALIZE);
469 sc->serializes[i++] = &sc->main_serialize;
471 KKASSERT(i < EMX_NSERIALIZE);
472 sc->serializes[i++] = &sc->tx_data[0].tx_serialize;
473 KKASSERT(i < EMX_NSERIALIZE);
474 sc->serializes[i++] = &sc->tx_data[1].tx_serialize;
476 KKASSERT(i < EMX_NSERIALIZE);
477 sc->serializes[i++] = &sc->rx_data[0].rx_serialize;
478 KKASSERT(i < EMX_NSERIALIZE);
479 sc->serializes[i++] = &sc->rx_data[1].rx_serialize;
481 KKASSERT(i == EMX_NSERIALIZE);
483 ifmedia_init(&sc->media, IFM_IMASK, emx_media_change, emx_media_status);
484 callout_init_mp(&sc->timer);
486 sc->dev = sc->osdep.dev = dev;
489 * Determine hardware and mac type
491 sc->hw.vendor_id = pci_get_vendor(dev);
492 sc->hw.device_id = pci_get_device(dev);
493 sc->hw.revision_id = pci_get_revid(dev);
494 sc->hw.subsystem_vendor_id = pci_get_subvendor(dev);
495 sc->hw.subsystem_device_id = pci_get_subdevice(dev);
497 if (e1000_set_mac_type(&sc->hw))
500 /* Enable bus mastering */
501 pci_enable_busmaster(dev);
506 sc->memory_rid = EMX_BAR_MEM;
507 sc->memory = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
508 &sc->memory_rid, RF_ACTIVE);
509 if (sc->memory == NULL) {
510 device_printf(dev, "Unable to allocate bus resource: memory\n");
514 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->memory);
515 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->memory);
517 /* XXX This is quite goofy, it is not actually used */
518 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
521 * Don't enable MSI-X on 82574, see:
522 * 82574 specification update errata #15
524 * Don't enable MSI on 82571/82572, see:
525 * 82571/82572 specification update errata #63
527 msi_enable = emx_msi_enable;
529 (sc->hw.mac.type == e1000_82571 ||
530 sc->hw.mac.type == e1000_82572))
536 sc->intr_type = pci_alloc_1intr(dev, msi_enable,
537 &sc->intr_rid, &intr_flags);
539 if (sc->intr_type == PCI_INTR_TYPE_LEGACY) {
542 unshared = device_getenv_int(dev, "irq.unshared", 0);
544 sc->flags |= EMX_FLAG_SHARED_INTR;
546 device_printf(dev, "IRQ shared\n");
548 intr_flags &= ~RF_SHAREABLE;
550 device_printf(dev, "IRQ unshared\n");
554 sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid,
556 if (sc->intr_res == NULL) {
557 device_printf(dev, "Unable to allocate bus resource: "
563 /* Save PCI command register for Shared Code */
564 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
565 sc->hw.back = &sc->osdep;
568 * For I217/I218, we need to map the flash memory and this
569 * must happen after the MAC is identified.
571 if (sc->hw.mac.type == e1000_pch_lpt) {
572 sc->flash_rid = EMX_BAR_FLASH;
574 sc->flash = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
575 &sc->flash_rid, RF_ACTIVE);
576 if (sc->flash == NULL) {
577 device_printf(dev, "Mapping of Flash failed\n");
581 sc->osdep.flash_bus_space_tag = rman_get_bustag(sc->flash);
582 sc->osdep.flash_bus_space_handle =
583 rman_get_bushandle(sc->flash);
586 * This is used in the shared code
587 * XXX this goof is actually not used.
589 sc->hw.flash_address = (uint8_t *)sc->flash;
592 /* Do Shared Code initialization */
593 if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
594 device_printf(dev, "Setup of Shared code failed\n");
598 e1000_get_bus_info(&sc->hw);
600 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
601 sc->hw.phy.autoneg_wait_to_complete = FALSE;
602 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
605 * Interrupt throttle rate
607 throttle = device_getenv_int(dev, "int_throttle_ceil",
608 emx_int_throttle_ceil);
610 sc->int_throttle_ceil = 0;
613 throttle = EMX_DEFAULT_ITR;
615 /* Recalculate the tunable value to get the exact frequency. */
616 throttle = 1000000000 / 256 / throttle;
618 /* Upper 16bits of ITR is reserved and should be zero */
619 if (throttle & 0xffff0000)
620 throttle = 1000000000 / 256 / EMX_DEFAULT_ITR;
622 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
625 e1000_init_script_state_82541(&sc->hw, TRUE);
626 e1000_set_tbi_compatibility_82543(&sc->hw, TRUE);
629 if (sc->hw.phy.media_type == e1000_media_type_copper) {
630 sc->hw.phy.mdix = EMX_AUTO_ALL_MODES;
631 sc->hw.phy.disable_polarity_correction = FALSE;
632 sc->hw.phy.ms_type = EMX_MASTER_SLAVE;
635 /* Set the frame limits assuming standard ethernet sized frames. */
636 sc->hw.mac.max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
638 /* This controls when hardware reports transmit completion status. */
639 sc->hw.mac.report_tx_early = 1;
641 /* Calculate # of RX rings */
642 sc->rx_ring_cnt = device_getenv_int(dev, "rxr", emx_rxr);
643 sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, EMX_NRX_RING);
646 * Calculate # of TX rings
649 * I217/I218 claims to have 2 TX queues
652 * Don't enable multiple TX queues on 82574; it always gives
653 * watchdog timeout on TX queue0, when multiple TCP streams are
654 * received. It was originally suspected that the hardware TX
655 * checksum offloading caused this watchdog timeout, since only
656 * TCP ACKs are sent during TCP receiving tests. However, even
657 * if the hardware TX checksum offloading is disable, TX queue0
658 * still will give watchdog.
661 if (sc->hw.mac.type == e1000_82571 ||
662 sc->hw.mac.type == e1000_82572 ||
663 sc->hw.mac.type == e1000_80003es2lan ||
664 sc->hw.mac.type == e1000_pch_lpt)
665 tx_ring_max = EMX_NTX_RING;
666 sc->tx_ring_cnt = device_getenv_int(dev, "txr", emx_txr);
667 sc->tx_ring_cnt = if_ring_count2(sc->tx_ring_cnt, tx_ring_max);
669 /* Allocate RX/TX rings' busdma(9) stuffs */
670 error = emx_dma_alloc(sc);
674 /* Allocate multicast array memory. */
675 sc->mta = kmalloc(ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX,
678 /* Indicate SOL/IDER usage */
679 if (e1000_check_reset_block(&sc->hw)) {
681 "PHY reset is blocked due to SOL/IDER session.\n");
684 /* Disable EEE on I217/I218 */
685 sc->hw.dev_spec.ich8lan.eee_disable = 1;
688 * Start from a known state, this is important in reading the
689 * nvm and mac from that.
691 e1000_reset_hw(&sc->hw);
693 /* Make sure we have a good EEPROM before we read from it */
694 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
696 * Some PCI-E parts fail the first check due to
697 * the link being in sleep state, call it again,
698 * if it fails a second time its a real issue.
700 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
702 "The EEPROM Checksum Is Not Valid\n");
708 /* Copy the permanent MAC address out of the EEPROM */
709 if (e1000_read_mac_addr(&sc->hw) < 0) {
710 device_printf(dev, "EEPROM read error while reading MAC"
715 if (!emx_is_valid_eaddr(sc->hw.mac.addr)) {
716 device_printf(dev, "Invalid MAC address\n");
721 /* Disable ULP support */
722 e1000_disable_ulp_lpt_lp(&sc->hw, TRUE);
724 /* Determine if we have to control management hardware */
725 if (e1000_enable_mng_pass_thru(&sc->hw))
726 sc->flags |= EMX_FLAG_HAS_MGMT;
731 apme_mask = EMX_EEPROM_APME;
733 switch (sc->hw.mac.type) {
735 sc->flags |= EMX_FLAG_HAS_AMT;
740 case e1000_80003es2lan:
741 if (sc->hw.bus.func == 1) {
742 e1000_read_nvm(&sc->hw,
743 NVM_INIT_CONTROL3_PORT_B, 1, &eeprom_data);
745 e1000_read_nvm(&sc->hw,
746 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
751 e1000_read_nvm(&sc->hw,
752 NVM_INIT_CONTROL3_PORT_A, 1, &eeprom_data);
755 if (eeprom_data & apme_mask)
756 sc->wol = E1000_WUFC_MAG | E1000_WUFC_MC;
759 * We have the eeprom settings, now apply the special cases
760 * where the eeprom may be wrong or the board won't support
761 * wake on lan on a particular port
763 device_id = pci_get_device(dev);
765 case E1000_DEV_ID_82571EB_FIBER:
767 * Wake events only supported on port A for dual fiber
768 * regardless of eeprom setting
770 if (E1000_READ_REG(&sc->hw, E1000_STATUS) &
775 case E1000_DEV_ID_82571EB_QUAD_COPPER:
776 case E1000_DEV_ID_82571EB_QUAD_FIBER:
777 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
778 /* if quad port sc, disable WoL on all but port A */
779 if (emx_global_quad_port_a != 0)
781 /* Reset for multiple quad port adapters */
782 if (++emx_global_quad_port_a == 4)
783 emx_global_quad_port_a = 0;
787 /* XXX disable wol */
792 * NPOLLING RX CPU offset
794 if (sc->rx_ring_cnt == ncpus2) {
797 offset_def = (sc->rx_ring_cnt * device_get_unit(dev)) % ncpus2;
798 offset = device_getenv_int(dev, "npoll.rxoff", offset_def);
799 if (offset >= ncpus2 ||
800 offset % sc->rx_ring_cnt != 0) {
801 device_printf(dev, "invalid npoll.rxoff %d, use %d\n",
806 sc->rx_npoll_off = offset;
809 * NPOLLING TX CPU offset
811 if (sc->tx_ring_cnt == ncpus2) {
814 offset_def = (sc->tx_ring_cnt * device_get_unit(dev)) % ncpus2;
815 offset = device_getenv_int(dev, "npoll.txoff", offset_def);
816 if (offset >= ncpus2 ||
817 offset % sc->tx_ring_cnt != 0) {
818 device_printf(dev, "invalid npoll.txoff %d, use %d\n",
823 sc->tx_npoll_off = offset;
825 sc->tx_ring_inuse = emx_get_txring_inuse(sc, FALSE);
827 /* Setup OS specific network interface */
830 /* Add sysctl tree, must after em_setup_ifp() */
833 /* Reset the hardware */
834 error = emx_reset(sc);
837 * Some 82573 parts fail the first reset, call it again,
838 * if it fails a second time its a real issue.
840 error = emx_reset(sc);
842 device_printf(dev, "Unable to reset the hardware\n");
843 ether_ifdetach(&sc->arpcom.ac_if);
848 /* Initialize statistics */
849 emx_update_stats(sc);
851 sc->hw.mac.get_link_status = 1;
852 emx_update_link_status(sc);
854 /* Non-AMT based hardware can now take control from firmware */
855 if ((sc->flags & (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT)) ==
857 emx_get_hw_control(sc);
860 * Missing Interrupt Following ICR read:
862 * 82571/82572 specification update errata #76
863 * 82573 specification update errata #31
864 * 82574 specification update errata #12
866 intr_func = emx_intr;
867 if ((sc->flags & EMX_FLAG_SHARED_INTR) &&
868 (sc->hw.mac.type == e1000_82571 ||
869 sc->hw.mac.type == e1000_82572 ||
870 sc->hw.mac.type == e1000_82573 ||
871 sc->hw.mac.type == e1000_82574))
872 intr_func = emx_intr_mask;
874 error = bus_setup_intr(dev, sc->intr_res, INTR_MPSAFE, intr_func, sc,
875 &sc->intr_tag, &sc->main_serialize);
877 device_printf(dev, "Failed to register interrupt handler");
878 ether_ifdetach(&sc->arpcom.ac_if);
888 emx_detach(device_t dev)
890 struct emx_softc *sc = device_get_softc(dev);
892 if (device_is_attached(dev)) {
893 struct ifnet *ifp = &sc->arpcom.ac_if;
895 ifnet_serialize_all(ifp);
899 e1000_phy_hw_reset(&sc->hw);
902 emx_rel_hw_control(sc);
905 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
906 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
910 bus_teardown_intr(dev, sc->intr_res, sc->intr_tag);
912 ifnet_deserialize_all(ifp);
915 } else if (sc->memory != NULL) {
916 emx_rel_hw_control(sc);
919 ifmedia_removeall(&sc->media);
920 bus_generic_detach(dev);
922 if (sc->intr_res != NULL) {
923 bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid,
927 if (sc->intr_type == PCI_INTR_TYPE_MSI)
928 pci_release_msi(dev);
930 if (sc->memory != NULL) {
931 bus_release_resource(dev, SYS_RES_MEMORY, sc->memory_rid,
935 if (sc->flash != NULL) {
936 bus_release_resource(dev, SYS_RES_MEMORY, sc->flash_rid,
943 kfree(sc->mta, M_DEVBUF);
949 emx_shutdown(device_t dev)
951 return emx_suspend(dev);
955 emx_suspend(device_t dev)
957 struct emx_softc *sc = device_get_softc(dev);
958 struct ifnet *ifp = &sc->arpcom.ac_if;
960 ifnet_serialize_all(ifp);
965 emx_rel_hw_control(sc);
968 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
969 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
973 ifnet_deserialize_all(ifp);
975 return bus_generic_suspend(dev);
979 emx_resume(device_t dev)
981 struct emx_softc *sc = device_get_softc(dev);
982 struct ifnet *ifp = &sc->arpcom.ac_if;
985 ifnet_serialize_all(ifp);
989 for (i = 0; i < sc->tx_ring_inuse; ++i)
990 ifsq_devstart_sched(sc->tx_data[i].ifsq);
992 ifnet_deserialize_all(ifp);
994 return bus_generic_resume(dev);
998 emx_start(struct ifnet *ifp, struct ifaltq_subque *ifsq)
1000 struct emx_softc *sc = ifp->if_softc;
1001 struct emx_txdata *tdata = ifsq_get_priv(ifsq);
1002 struct mbuf *m_head;
1003 int idx = -1, nsegs = 0;
1005 KKASSERT(tdata->ifsq == ifsq);
1006 ASSERT_SERIALIZED(&tdata->tx_serialize);
1008 if ((ifp->if_flags & IFF_RUNNING) == 0 || ifsq_is_oactive(ifsq))
1011 if (!sc->link_active || (tdata->tx_flags & EMX_TXFLAG_ENABLED) == 0) {
1016 while (!ifsq_is_empty(ifsq)) {
1017 /* Now do we at least have a minimal? */
1018 if (EMX_IS_OACTIVE(tdata)) {
1019 emx_tx_collect(tdata);
1020 if (EMX_IS_OACTIVE(tdata)) {
1021 ifsq_set_oactive(ifsq);
1027 m_head = ifsq_dequeue(ifsq);
1031 if (emx_encap(tdata, &m_head, &nsegs, &idx)) {
1032 IFNET_STAT_INC(ifp, oerrors, 1);
1033 emx_tx_collect(tdata);
1037 if (nsegs >= tdata->tx_wreg_nsegs) {
1038 E1000_WRITE_REG(&sc->hw, E1000_TDT(tdata->idx), idx);
1043 /* Send a copy of the frame to the BPF listener */
1044 ETHER_BPF_MTAP(ifp, m_head);
1046 /* Set timeout in case hardware has problems transmitting. */
1047 tdata->tx_watchdog.wd_timer = EMX_TX_TIMEOUT;
1050 E1000_WRITE_REG(&sc->hw, E1000_TDT(tdata->idx), idx);
1054 emx_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
1056 struct emx_softc *sc = ifp->if_softc;
1057 struct ifreq *ifr = (struct ifreq *)data;
1058 uint16_t eeprom_data = 0;
1059 int max_frame_size, mask, reinit;
1062 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1066 switch (sc->hw.mac.type) {
1069 * 82573 only supports jumbo frames
1070 * if ASPM is disabled.
1072 e1000_read_nvm(&sc->hw, NVM_INIT_3GIO_3, 1,
1074 if (eeprom_data & NVM_WORD1A_ASPM_MASK) {
1075 max_frame_size = ETHER_MAX_LEN;
1080 /* Limit Jumbo Frame size */
1085 case e1000_80003es2lan:
1086 max_frame_size = 9234;
1090 max_frame_size = MAX_JUMBO_FRAME_SIZE;
1093 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
1099 ifp->if_mtu = ifr->ifr_mtu;
1100 sc->hw.mac.max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
1103 if (ifp->if_flags & IFF_RUNNING)
1108 if (ifp->if_flags & IFF_UP) {
1109 if ((ifp->if_flags & IFF_RUNNING)) {
1110 if ((ifp->if_flags ^ sc->if_flags) &
1111 (IFF_PROMISC | IFF_ALLMULTI)) {
1112 emx_disable_promisc(sc);
1113 emx_set_promisc(sc);
1118 } else if (ifp->if_flags & IFF_RUNNING) {
1121 sc->if_flags = ifp->if_flags;
1126 if (ifp->if_flags & IFF_RUNNING) {
1127 emx_disable_intr(sc);
1129 #ifdef IFPOLL_ENABLE
1130 if (!(ifp->if_flags & IFF_NPOLLING))
1132 emx_enable_intr(sc);
1137 /* Check SOL/IDER usage */
1138 if (e1000_check_reset_block(&sc->hw)) {
1139 device_printf(sc->dev, "Media change is"
1140 " blocked due to SOL/IDER session.\n");
1146 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
1151 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1152 if (mask & IFCAP_RXCSUM) {
1153 ifp->if_capenable ^= IFCAP_RXCSUM;
1156 if (mask & IFCAP_VLAN_HWTAGGING) {
1157 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1160 if (mask & IFCAP_TXCSUM) {
1161 ifp->if_capenable ^= IFCAP_TXCSUM;
1162 if (ifp->if_capenable & IFCAP_TXCSUM)
1163 ifp->if_hwassist |= EMX_CSUM_FEATURES;
1165 ifp->if_hwassist &= ~EMX_CSUM_FEATURES;
1167 if (mask & IFCAP_TSO) {
1168 ifp->if_capenable ^= IFCAP_TSO;
1169 if (ifp->if_capenable & IFCAP_TSO)
1170 ifp->if_hwassist |= CSUM_TSO;
1172 ifp->if_hwassist &= ~CSUM_TSO;
1174 if (mask & IFCAP_RSS)
1175 ifp->if_capenable ^= IFCAP_RSS;
1176 if (reinit && (ifp->if_flags & IFF_RUNNING))
1181 error = ether_ioctl(ifp, command, data);
1188 emx_watchdog(struct ifaltq_subque *ifsq)
1190 struct emx_txdata *tdata = ifsq_get_priv(ifsq);
1191 struct ifnet *ifp = ifsq_get_ifp(ifsq);
1192 struct emx_softc *sc = ifp->if_softc;
1195 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1198 * The timer is set to 5 every time start queues a packet.
1199 * Then txeof keeps resetting it as long as it cleans at
1200 * least one descriptor.
1201 * Finally, anytime all descriptors are clean the timer is
1205 if (E1000_READ_REG(&sc->hw, E1000_TDT(tdata->idx)) ==
1206 E1000_READ_REG(&sc->hw, E1000_TDH(tdata->idx))) {
1208 * If we reach here, all TX jobs are completed and
1209 * the TX engine should have been idled for some time.
1210 * We don't need to call ifsq_devstart_sched() here.
1212 ifsq_clr_oactive(ifsq);
1213 tdata->tx_watchdog.wd_timer = 0;
1218 * If we are in this routine because of pause frames, then
1219 * don't reset the hardware.
1221 if (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_TXOFF) {
1222 tdata->tx_watchdog.wd_timer = EMX_TX_TIMEOUT;
1226 if_printf(ifp, "TX %d watchdog timeout -- resetting\n", tdata->idx);
1228 IFNET_STAT_INC(ifp, oerrors, 1);
1231 for (i = 0; i < sc->tx_ring_inuse; ++i)
1232 ifsq_devstart_sched(sc->tx_data[i].ifsq);
1238 struct emx_softc *sc = xsc;
1239 struct ifnet *ifp = &sc->arpcom.ac_if;
1240 device_t dev = sc->dev;
1244 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1248 /* Get the latest mac address, User can use a LAA */
1249 bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
1251 /* Put the address into the Receive Address Array */
1252 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1255 * With the 82571 sc, RAR[0] may be overwritten
1256 * when the other port is reset, we make a duplicate
1257 * in RAR[14] for that eventuality, this assures
1258 * the interface continues to function.
1260 if (sc->hw.mac.type == e1000_82571) {
1261 e1000_set_laa_state_82571(&sc->hw, TRUE);
1262 e1000_rar_set(&sc->hw, sc->hw.mac.addr,
1263 E1000_RAR_ENTRIES - 1);
1266 /* Initialize the hardware */
1267 if (emx_reset(sc)) {
1268 device_printf(dev, "Unable to reset the hardware\n");
1269 /* XXX emx_stop()? */
1272 emx_update_link_status(sc);
1274 /* Setup VLAN support, basic and offload if available */
1275 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1277 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) {
1280 ctrl = E1000_READ_REG(&sc->hw, E1000_CTRL);
1281 ctrl |= E1000_CTRL_VME;
1282 E1000_WRITE_REG(&sc->hw, E1000_CTRL, ctrl);
1285 /* Configure for OS presence */
1289 #ifdef IFPOLL_ENABLE
1290 if (ifp->if_flags & IFF_NPOLLING)
1293 sc->tx_ring_inuse = emx_get_txring_inuse(sc, polling);
1294 ifq_set_subq_mask(&ifp->if_snd, sc->tx_ring_inuse - 1);
1296 /* Prepare transmit descriptors and buffers */
1297 for (i = 0; i < sc->tx_ring_inuse; ++i)
1298 emx_init_tx_ring(&sc->tx_data[i]);
1299 emx_init_tx_unit(sc);
1301 /* Setup Multicast table */
1304 /* Prepare receive descriptors and buffers */
1305 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1306 if (emx_init_rx_ring(&sc->rx_data[i])) {
1308 "Could not setup receive structures\n");
1313 emx_init_rx_unit(sc);
1315 /* Don't lose promiscuous settings */
1316 emx_set_promisc(sc);
1318 ifp->if_flags |= IFF_RUNNING;
1319 for (i = 0; i < sc->tx_ring_inuse; ++i) {
1320 ifsq_clr_oactive(sc->tx_data[i].ifsq);
1321 ifsq_watchdog_start(&sc->tx_data[i].tx_watchdog);
1324 callout_reset(&sc->timer, hz, emx_timer, sc);
1325 e1000_clear_hw_cntrs_base_generic(&sc->hw);
1327 /* MSI/X configuration for 82574 */
1328 if (sc->hw.mac.type == e1000_82574) {
1331 tmp = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
1332 tmp |= E1000_CTRL_EXT_PBA_CLR;
1333 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT, tmp);
1336 * Set the IVAR - interrupt vector routing.
1337 * Each nibble represents a vector, high bit
1338 * is enable, other 3 bits are the MSIX table
1339 * entry, we map RXQ0 to 0, TXQ0 to 1, and
1340 * Link (other) to 2, hence the magic number.
1342 E1000_WRITE_REG(&sc->hw, E1000_IVAR, 0x800A0908);
1346 * Only enable interrupts if we are not polling, make sure
1347 * they are off otherwise.
1350 emx_disable_intr(sc);
1352 emx_enable_intr(sc);
1354 /* AMT based hardware can now take control from firmware */
1355 if ((sc->flags & (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT)) ==
1356 (EMX_FLAG_HAS_MGMT | EMX_FLAG_HAS_AMT))
1357 emx_get_hw_control(sc);
1363 emx_intr_body(xsc, TRUE);
1367 emx_intr_body(struct emx_softc *sc, boolean_t chk_asserted)
1369 struct ifnet *ifp = &sc->arpcom.ac_if;
1373 ASSERT_SERIALIZED(&sc->main_serialize);
1375 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
1377 if (chk_asserted && (reg_icr & E1000_ICR_INT_ASSERTED) == 0) {
1383 * XXX: some laptops trigger several spurious interrupts
1384 * on emx(4) when in the resume cycle. The ICR register
1385 * reports all-ones value in this case. Processing such
1386 * interrupts would lead to a freeze. I don't know why.
1388 if (reg_icr == 0xffffffff) {
1393 if (ifp->if_flags & IFF_RUNNING) {
1395 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
1398 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1399 lwkt_serialize_enter(
1400 &sc->rx_data[i].rx_serialize);
1401 emx_rxeof(&sc->rx_data[i], -1);
1402 lwkt_serialize_exit(
1403 &sc->rx_data[i].rx_serialize);
1406 if (reg_icr & E1000_ICR_TXDW) {
1407 struct emx_txdata *tdata = &sc->tx_data[0];
1409 lwkt_serialize_enter(&tdata->tx_serialize);
1411 if (!ifsq_is_empty(tdata->ifsq))
1412 ifsq_devstart(tdata->ifsq);
1413 lwkt_serialize_exit(&tdata->tx_serialize);
1417 /* Link status change */
1418 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
1419 emx_serialize_skipmain(sc);
1421 callout_stop(&sc->timer);
1422 sc->hw.mac.get_link_status = 1;
1423 emx_update_link_status(sc);
1425 /* Deal with TX cruft when link lost */
1428 callout_reset(&sc->timer, hz, emx_timer, sc);
1430 emx_deserialize_skipmain(sc);
1433 if (reg_icr & E1000_ICR_RXO)
1440 emx_intr_mask(void *xsc)
1442 struct emx_softc *sc = xsc;
1444 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
1447 * ICR.INT_ASSERTED bit will never be set if IMS is 0,
1448 * so don't check it.
1450 emx_intr_body(sc, FALSE);
1451 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
1455 emx_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1457 struct emx_softc *sc = ifp->if_softc;
1459 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1461 emx_update_link_status(sc);
1463 ifmr->ifm_status = IFM_AVALID;
1464 ifmr->ifm_active = IFM_ETHER;
1466 if (!sc->link_active)
1469 ifmr->ifm_status |= IFM_ACTIVE;
1471 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1472 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1473 ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
1475 switch (sc->link_speed) {
1477 ifmr->ifm_active |= IFM_10_T;
1480 ifmr->ifm_active |= IFM_100_TX;
1484 ifmr->ifm_active |= IFM_1000_T;
1487 if (sc->link_duplex == FULL_DUPLEX)
1488 ifmr->ifm_active |= IFM_FDX;
1490 ifmr->ifm_active |= IFM_HDX;
1495 emx_media_change(struct ifnet *ifp)
1497 struct emx_softc *sc = ifp->if_softc;
1498 struct ifmedia *ifm = &sc->media;
1500 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1502 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1505 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1507 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1508 sc->hw.phy.autoneg_advertised = EMX_AUTONEG_ADV_DEFAULT;
1514 sc->hw.mac.autoneg = EMX_DO_AUTO_NEG;
1515 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1519 sc->hw.mac.autoneg = FALSE;
1520 sc->hw.phy.autoneg_advertised = 0;
1521 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1522 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1524 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1528 sc->hw.mac.autoneg = FALSE;
1529 sc->hw.phy.autoneg_advertised = 0;
1530 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1531 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1533 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1537 if_printf(ifp, "Unsupported media type\n");
1547 emx_encap(struct emx_txdata *tdata, struct mbuf **m_headp,
1548 int *segs_used, int *idx)
1550 bus_dma_segment_t segs[EMX_MAX_SCATTER];
1552 struct emx_txbuf *tx_buffer, *tx_buffer_mapped;
1553 struct e1000_tx_desc *ctxd = NULL;
1554 struct mbuf *m_head = *m_headp;
1555 uint32_t txd_upper, txd_lower, cmd = 0;
1556 int maxsegs, nsegs, i, j, first, last = 0, error;
1558 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
1559 error = emx_tso_pullup(tdata, m_headp);
1565 txd_upper = txd_lower = 0;
1568 * Capture the first descriptor index, this descriptor
1569 * will have the index of the EOP which is the only one
1570 * that now gets a DONE bit writeback.
1572 first = tdata->next_avail_tx_desc;
1573 tx_buffer = &tdata->tx_buf[first];
1574 tx_buffer_mapped = tx_buffer;
1575 map = tx_buffer->map;
1577 maxsegs = tdata->num_tx_desc_avail - EMX_TX_RESERVED;
1578 KASSERT(maxsegs >= tdata->spare_tx_desc, ("not enough spare TX desc"));
1579 if (maxsegs > EMX_MAX_SCATTER)
1580 maxsegs = EMX_MAX_SCATTER;
1582 error = bus_dmamap_load_mbuf_defrag(tdata->txtag, map, m_headp,
1583 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
1589 bus_dmamap_sync(tdata->txtag, map, BUS_DMASYNC_PREWRITE);
1592 tdata->tx_nsegs += nsegs;
1593 *segs_used += nsegs;
1595 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
1596 /* TSO will consume one TX desc */
1597 i = emx_tso_setup(tdata, m_head, &txd_upper, &txd_lower);
1598 tdata->tx_nsegs += i;
1600 } else if (m_head->m_pkthdr.csum_flags & EMX_CSUM_FEATURES) {
1601 /* TX csum offloading will consume one TX desc */
1602 i = emx_txcsum(tdata, m_head, &txd_upper, &txd_lower);
1603 tdata->tx_nsegs += i;
1607 /* Handle VLAN tag */
1608 if (m_head->m_flags & M_VLANTAG) {
1609 /* Set the vlan id. */
1610 txd_upper |= (htole16(m_head->m_pkthdr.ether_vlantag) << 16);
1611 /* Tell hardware to add tag */
1612 txd_lower |= htole32(E1000_TXD_CMD_VLE);
1615 i = tdata->next_avail_tx_desc;
1617 /* Set up our transmit descriptors */
1618 for (j = 0; j < nsegs; j++) {
1619 tx_buffer = &tdata->tx_buf[i];
1620 ctxd = &tdata->tx_desc_base[i];
1622 ctxd->buffer_addr = htole64(segs[j].ds_addr);
1623 ctxd->lower.data = htole32(E1000_TXD_CMD_IFCS |
1624 txd_lower | segs[j].ds_len);
1625 ctxd->upper.data = htole32(txd_upper);
1628 if (++i == tdata->num_tx_desc)
1632 tdata->next_avail_tx_desc = i;
1634 KKASSERT(tdata->num_tx_desc_avail > nsegs);
1635 tdata->num_tx_desc_avail -= nsegs;
1637 tx_buffer->m_head = m_head;
1638 tx_buffer_mapped->map = tx_buffer->map;
1639 tx_buffer->map = map;
1641 if (tdata->tx_nsegs >= tdata->tx_intr_nsegs) {
1642 tdata->tx_nsegs = 0;
1645 * Report Status (RS) is turned on
1646 * every tx_intr_nsegs descriptors.
1648 cmd = E1000_TXD_CMD_RS;
1651 * Keep track of the descriptor, which will
1652 * be written back by hardware.
1654 tdata->tx_dd[tdata->tx_dd_tail] = last;
1655 EMX_INC_TXDD_IDX(tdata->tx_dd_tail);
1656 KKASSERT(tdata->tx_dd_tail != tdata->tx_dd_head);
1660 * Last Descriptor of Packet needs End Of Packet (EOP)
1662 ctxd->lower.data |= htole32(E1000_TXD_CMD_EOP | cmd);
1665 * Defer TDT updating, until enough descriptors are setup
1669 #ifdef EMX_TSS_DEBUG
1677 emx_set_promisc(struct emx_softc *sc)
1679 struct ifnet *ifp = &sc->arpcom.ac_if;
1682 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1684 if (ifp->if_flags & IFF_PROMISC) {
1685 reg_rctl |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1686 /* Turn this on if you want to see bad packets */
1688 reg_rctl |= E1000_RCTL_SBP;
1689 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1690 } else if (ifp->if_flags & IFF_ALLMULTI) {
1691 reg_rctl |= E1000_RCTL_MPE;
1692 reg_rctl &= ~E1000_RCTL_UPE;
1693 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1698 emx_disable_promisc(struct emx_softc *sc)
1702 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1704 reg_rctl &= ~E1000_RCTL_UPE;
1705 reg_rctl &= ~E1000_RCTL_MPE;
1706 reg_rctl &= ~E1000_RCTL_SBP;
1707 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1711 emx_set_multi(struct emx_softc *sc)
1713 struct ifnet *ifp = &sc->arpcom.ac_if;
1714 struct ifmultiaddr *ifma;
1715 uint32_t reg_rctl = 0;
1720 bzero(mta, ETH_ADDR_LEN * EMX_MCAST_ADDR_MAX);
1722 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1723 if (ifma->ifma_addr->sa_family != AF_LINK)
1726 if (mcnt == EMX_MCAST_ADDR_MAX)
1729 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1730 &mta[mcnt * ETHER_ADDR_LEN], ETHER_ADDR_LEN);
1734 if (mcnt >= EMX_MCAST_ADDR_MAX) {
1735 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1736 reg_rctl |= E1000_RCTL_MPE;
1737 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1739 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1744 * This routine checks for link status and updates statistics.
1747 emx_timer(void *xsc)
1749 struct emx_softc *sc = xsc;
1750 struct ifnet *ifp = &sc->arpcom.ac_if;
1752 lwkt_serialize_enter(&sc->main_serialize);
1754 emx_update_link_status(sc);
1755 emx_update_stats(sc);
1757 /* Reset LAA into RAR[0] on 82571 */
1758 if (e1000_get_laa_state_82571(&sc->hw) == TRUE)
1759 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
1761 if (emx_display_debug_stats && (ifp->if_flags & IFF_RUNNING))
1762 emx_print_hw_stats(sc);
1766 callout_reset(&sc->timer, hz, emx_timer, sc);
1768 lwkt_serialize_exit(&sc->main_serialize);
1772 emx_update_link_status(struct emx_softc *sc)
1774 struct e1000_hw *hw = &sc->hw;
1775 struct ifnet *ifp = &sc->arpcom.ac_if;
1776 device_t dev = sc->dev;
1777 uint32_t link_check = 0;
1779 /* Get the cached link value or read phy for real */
1780 switch (hw->phy.media_type) {
1781 case e1000_media_type_copper:
1782 if (hw->mac.get_link_status) {
1783 /* Do the work to read phy */
1784 e1000_check_for_link(hw);
1785 link_check = !hw->mac.get_link_status;
1786 if (link_check) /* ESB2 fix */
1787 e1000_cfg_on_link_up(hw);
1793 case e1000_media_type_fiber:
1794 e1000_check_for_link(hw);
1795 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1798 case e1000_media_type_internal_serdes:
1799 e1000_check_for_link(hw);
1800 link_check = sc->hw.mac.serdes_has_link;
1803 case e1000_media_type_unknown:
1808 /* Now check for a transition */
1809 if (link_check && sc->link_active == 0) {
1810 e1000_get_speed_and_duplex(hw, &sc->link_speed,
1814 * Check if we should enable/disable SPEED_MODE bit on
1817 if (sc->link_speed != SPEED_1000 &&
1818 (hw->mac.type == e1000_82571 ||
1819 hw->mac.type == e1000_82572)) {
1822 tarc0 = E1000_READ_REG(hw, E1000_TARC(0));
1823 tarc0 &= ~EMX_TARC_SPEED_MODE;
1824 E1000_WRITE_REG(hw, E1000_TARC(0), tarc0);
1827 device_printf(dev, "Link is up %d Mbps %s\n",
1829 ((sc->link_duplex == FULL_DUPLEX) ?
1830 "Full Duplex" : "Half Duplex"));
1832 sc->link_active = 1;
1834 ifp->if_baudrate = sc->link_speed * 1000000;
1835 ifp->if_link_state = LINK_STATE_UP;
1836 if_link_state_change(ifp);
1837 } else if (!link_check && sc->link_active == 1) {
1838 ifp->if_baudrate = sc->link_speed = 0;
1839 sc->link_duplex = 0;
1841 device_printf(dev, "Link is Down\n");
1842 sc->link_active = 0;
1843 ifp->if_link_state = LINK_STATE_DOWN;
1844 if_link_state_change(ifp);
1849 emx_stop(struct emx_softc *sc)
1851 struct ifnet *ifp = &sc->arpcom.ac_if;
1854 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1856 emx_disable_intr(sc);
1858 callout_stop(&sc->timer);
1860 ifp->if_flags &= ~IFF_RUNNING;
1861 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1862 struct emx_txdata *tdata = &sc->tx_data[i];
1864 ifsq_clr_oactive(tdata->ifsq);
1865 ifsq_watchdog_stop(&tdata->tx_watchdog);
1866 tdata->tx_flags &= ~EMX_TXFLAG_ENABLED;
1870 * Disable multiple receive queues.
1873 * We should disable multiple receive queues before
1874 * resetting the hardware.
1876 E1000_WRITE_REG(&sc->hw, E1000_MRQC, 0);
1878 e1000_reset_hw(&sc->hw);
1879 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1881 for (i = 0; i < sc->tx_ring_cnt; ++i)
1882 emx_free_tx_ring(&sc->tx_data[i]);
1883 for (i = 0; i < sc->rx_ring_cnt; ++i)
1884 emx_free_rx_ring(&sc->rx_data[i]);
1888 emx_reset(struct emx_softc *sc)
1890 device_t dev = sc->dev;
1891 uint16_t rx_buffer_size;
1894 /* Set up smart power down as default off on newer adapters. */
1895 if (!emx_smart_pwr_down &&
1896 (sc->hw.mac.type == e1000_82571 ||
1897 sc->hw.mac.type == e1000_82572)) {
1898 uint16_t phy_tmp = 0;
1900 /* Speed up time to link by disabling smart power down. */
1901 e1000_read_phy_reg(&sc->hw,
1902 IGP02E1000_PHY_POWER_MGMT, &phy_tmp);
1903 phy_tmp &= ~IGP02E1000_PM_SPD;
1904 e1000_write_phy_reg(&sc->hw,
1905 IGP02E1000_PHY_POWER_MGMT, phy_tmp);
1909 * Packet Buffer Allocation (PBA)
1910 * Writing PBA sets the receive portion of the buffer
1911 * the remainder is used for the transmit buffer.
1913 switch (sc->hw.mac.type) {
1914 /* Total Packet Buffer on these is 48K */
1917 case e1000_80003es2lan:
1918 pba = E1000_PBA_32K; /* 32K for Rx, 16K for Tx */
1921 case e1000_82573: /* 82573: Total Packet Buffer is 32K */
1922 pba = E1000_PBA_12K; /* 12K for Rx, 20K for Tx */
1926 pba = E1000_PBA_20K; /* 20K for Rx, 20K for Tx */
1930 pba = E1000_PBA_26K;
1934 /* Devices before 82547 had a Packet Buffer of 64K. */
1935 if (sc->hw.mac.max_frame_size > 8192)
1936 pba = E1000_PBA_40K; /* 40K for Rx, 24K for Tx */
1938 pba = E1000_PBA_48K; /* 48K for Rx, 16K for Tx */
1940 E1000_WRITE_REG(&sc->hw, E1000_PBA, pba);
1943 * These parameters control the automatic generation (Tx) and
1944 * response (Rx) to Ethernet PAUSE frames.
1945 * - High water mark should allow for at least two frames to be
1946 * received after sending an XOFF.
1947 * - Low water mark works best when it is very near the high water mark.
1948 * This allows the receiver to restart by sending XON when it has
1949 * drained a bit. Here we use an arbitary value of 1500 which will
1950 * restart after one full frame is pulled from the buffer. There
1951 * could be several smaller frames in the buffer and if so they will
1952 * not trigger the XON until their total number reduces the buffer
1954 * - The pause time is fairly large at 1000 x 512ns = 512 usec.
1956 rx_buffer_size = (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) << 10;
1958 sc->hw.fc.high_water = rx_buffer_size -
1959 roundup2(sc->hw.mac.max_frame_size, 1024);
1960 sc->hw.fc.low_water = sc->hw.fc.high_water - 1500;
1962 sc->hw.fc.pause_time = EMX_FC_PAUSE_TIME;
1963 sc->hw.fc.send_xon = TRUE;
1964 sc->hw.fc.requested_mode = e1000_fc_full;
1967 * Device specific overrides/settings
1969 if (sc->hw.mac.type == e1000_pch_lpt) {
1970 sc->hw.fc.high_water = 0x5C20;
1971 sc->hw.fc.low_water = 0x5048;
1972 sc->hw.fc.pause_time = 0x0650;
1973 sc->hw.fc.refresh_time = 0x0400;
1974 /* Jumbos need adjusted PBA */
1975 if (sc->arpcom.ac_if.if_mtu > ETHERMTU)
1976 E1000_WRITE_REG(&sc->hw, E1000_PBA, 12);
1978 E1000_WRITE_REG(&sc->hw, E1000_PBA, 26);
1979 } else if (sc->hw.mac.type == e1000_80003es2lan) {
1980 sc->hw.fc.pause_time = 0xFFFF;
1983 /* Issue a global reset */
1984 e1000_reset_hw(&sc->hw);
1985 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1986 emx_disable_aspm(sc);
1988 if (e1000_init_hw(&sc->hw) < 0) {
1989 device_printf(dev, "Hardware Initialization Failed\n");
1993 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1994 e1000_get_phy_info(&sc->hw);
1995 e1000_check_for_link(&sc->hw);
2001 emx_setup_ifp(struct emx_softc *sc)
2003 struct ifnet *ifp = &sc->arpcom.ac_if;
2006 if_initname(ifp, device_get_name(sc->dev),
2007 device_get_unit(sc->dev));
2009 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
2010 ifp->if_init = emx_init;
2011 ifp->if_ioctl = emx_ioctl;
2012 ifp->if_start = emx_start;
2013 #ifdef IFPOLL_ENABLE
2014 ifp->if_npoll = emx_npoll;
2016 ifp->if_serialize = emx_serialize;
2017 ifp->if_deserialize = emx_deserialize;
2018 ifp->if_tryserialize = emx_tryserialize;
2020 ifp->if_serialize_assert = emx_serialize_assert;
2023 ifq_set_maxlen(&ifp->if_snd, sc->tx_data[0].num_tx_desc - 1);
2024 ifq_set_ready(&ifp->if_snd);
2025 ifq_set_subq_cnt(&ifp->if_snd, sc->tx_ring_cnt);
2027 ifp->if_mapsubq = ifq_mapsubq_mask;
2028 ifq_set_subq_mask(&ifp->if_snd, 0);
2030 ether_ifattach(ifp, sc->hw.mac.addr, NULL);
2032 ifp->if_capabilities = IFCAP_HWCSUM |
2033 IFCAP_VLAN_HWTAGGING |
2036 if (sc->rx_ring_cnt > 1)
2037 ifp->if_capabilities |= IFCAP_RSS;
2038 ifp->if_capenable = ifp->if_capabilities;
2039 ifp->if_hwassist = EMX_CSUM_FEATURES | CSUM_TSO;
2042 * Tell the upper layer(s) we support long frames.
2044 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
2046 for (i = 0; i < sc->tx_ring_cnt; ++i) {
2047 struct ifaltq_subque *ifsq = ifq_get_subq(&ifp->if_snd, i);
2048 struct emx_txdata *tdata = &sc->tx_data[i];
2050 ifsq_set_cpuid(ifsq, rman_get_cpuid(sc->intr_res));
2051 ifsq_set_priv(ifsq, tdata);
2052 ifsq_set_hw_serialize(ifsq, &tdata->tx_serialize);
2055 ifsq_watchdog_init(&tdata->tx_watchdog, ifsq, emx_watchdog);
2059 * Specify the media types supported by this sc and register
2060 * callbacks to update media and link information
2062 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
2063 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
2064 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
2066 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
2068 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
2069 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
2071 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
2072 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
2074 if (sc->hw.phy.type != e1000_phy_ife) {
2075 ifmedia_add(&sc->media,
2076 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
2077 ifmedia_add(&sc->media,
2078 IFM_ETHER | IFM_1000_T, 0, NULL);
2081 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
2082 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
2086 * Workaround for SmartSpeed on 82541 and 82547 controllers
2089 emx_smartspeed(struct emx_softc *sc)
2093 if (sc->link_active || sc->hw.phy.type != e1000_phy_igp ||
2094 sc->hw.mac.autoneg == 0 ||
2095 (sc->hw.phy.autoneg_advertised & ADVERTISE_1000_FULL) == 0)
2098 if (sc->smartspeed == 0) {
2100 * If Master/Slave config fault is asserted twice,
2101 * we assume back-to-back
2103 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
2104 if (!(phy_tmp & SR_1000T_MS_CONFIG_FAULT))
2106 e1000_read_phy_reg(&sc->hw, PHY_1000T_STATUS, &phy_tmp);
2107 if (phy_tmp & SR_1000T_MS_CONFIG_FAULT) {
2108 e1000_read_phy_reg(&sc->hw,
2109 PHY_1000T_CTRL, &phy_tmp);
2110 if (phy_tmp & CR_1000T_MS_ENABLE) {
2111 phy_tmp &= ~CR_1000T_MS_ENABLE;
2112 e1000_write_phy_reg(&sc->hw,
2113 PHY_1000T_CTRL, phy_tmp);
2115 if (sc->hw.mac.autoneg &&
2116 !e1000_phy_setup_autoneg(&sc->hw) &&
2117 !e1000_read_phy_reg(&sc->hw,
2118 PHY_CONTROL, &phy_tmp)) {
2119 phy_tmp |= MII_CR_AUTO_NEG_EN |
2120 MII_CR_RESTART_AUTO_NEG;
2121 e1000_write_phy_reg(&sc->hw,
2122 PHY_CONTROL, phy_tmp);
2127 } else if (sc->smartspeed == EMX_SMARTSPEED_DOWNSHIFT) {
2128 /* If still no link, perhaps using 2/3 pair cable */
2129 e1000_read_phy_reg(&sc->hw, PHY_1000T_CTRL, &phy_tmp);
2130 phy_tmp |= CR_1000T_MS_ENABLE;
2131 e1000_write_phy_reg(&sc->hw, PHY_1000T_CTRL, phy_tmp);
2132 if (sc->hw.mac.autoneg &&
2133 !e1000_phy_setup_autoneg(&sc->hw) &&
2134 !e1000_read_phy_reg(&sc->hw, PHY_CONTROL, &phy_tmp)) {
2135 phy_tmp |= MII_CR_AUTO_NEG_EN | MII_CR_RESTART_AUTO_NEG;
2136 e1000_write_phy_reg(&sc->hw, PHY_CONTROL, phy_tmp);
2140 /* Restart process after EMX_SMARTSPEED_MAX iterations */
2141 if (sc->smartspeed++ == EMX_SMARTSPEED_MAX)
2146 emx_create_tx_ring(struct emx_txdata *tdata)
2148 device_t dev = tdata->sc->dev;
2149 struct emx_txbuf *tx_buffer;
2150 int error, i, tsize, ntxd;
2153 * Validate number of transmit descriptors. It must not exceed
2154 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
2156 ntxd = device_getenv_int(dev, "txd", emx_txd);
2157 if ((ntxd * sizeof(struct e1000_tx_desc)) % EMX_DBA_ALIGN != 0 ||
2158 ntxd > EMX_MAX_TXD || ntxd < EMX_MIN_TXD) {
2159 device_printf(dev, "Using %d TX descriptors instead of %d!\n",
2160 EMX_DEFAULT_TXD, ntxd);
2161 tdata->num_tx_desc = EMX_DEFAULT_TXD;
2163 tdata->num_tx_desc = ntxd;
2167 * Allocate Transmit Descriptor ring
2169 tsize = roundup2(tdata->num_tx_desc * sizeof(struct e1000_tx_desc),
2171 tdata->tx_desc_base = bus_dmamem_coherent_any(tdata->sc->parent_dtag,
2172 EMX_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
2173 &tdata->tx_desc_dtag, &tdata->tx_desc_dmap,
2174 &tdata->tx_desc_paddr);
2175 if (tdata->tx_desc_base == NULL) {
2176 device_printf(dev, "Unable to allocate tx_desc memory\n");
2180 tsize = __VM_CACHELINE_ALIGN(
2181 sizeof(struct emx_txbuf) * tdata->num_tx_desc);
2182 tdata->tx_buf = kmalloc_cachealign(tsize, M_DEVBUF, M_WAITOK | M_ZERO);
2185 * Create DMA tags for tx buffers
2187 error = bus_dma_tag_create(tdata->sc->parent_dtag, /* parent */
2188 1, 0, /* alignment, bounds */
2189 BUS_SPACE_MAXADDR, /* lowaddr */
2190 BUS_SPACE_MAXADDR, /* highaddr */
2191 NULL, NULL, /* filter, filterarg */
2192 EMX_TSO_SIZE, /* maxsize */
2193 EMX_MAX_SCATTER, /* nsegments */
2194 EMX_MAX_SEGSIZE, /* maxsegsize */
2195 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
2196 BUS_DMA_ONEBPAGE, /* flags */
2199 device_printf(dev, "Unable to allocate TX DMA tag\n");
2200 kfree(tdata->tx_buf, M_DEVBUF);
2201 tdata->tx_buf = NULL;
2206 * Create DMA maps for tx buffers
2208 for (i = 0; i < tdata->num_tx_desc; i++) {
2209 tx_buffer = &tdata->tx_buf[i];
2211 error = bus_dmamap_create(tdata->txtag,
2212 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE,
2215 device_printf(dev, "Unable to create TX DMA map\n");
2216 emx_destroy_tx_ring(tdata, i);
2222 * Setup TX parameters
2224 tdata->spare_tx_desc = EMX_TX_SPARE;
2225 tdata->tx_wreg_nsegs = EMX_DEFAULT_TXWREG;
2228 * Keep following relationship between spare_tx_desc, oact_tx_desc
2229 * and tx_intr_nsegs:
2230 * (spare_tx_desc + EMX_TX_RESERVED) <=
2231 * oact_tx_desc <= EMX_TX_OACTIVE_MAX <= tx_intr_nsegs
2233 tdata->oact_tx_desc = tdata->num_tx_desc / 8;
2234 if (tdata->oact_tx_desc > EMX_TX_OACTIVE_MAX)
2235 tdata->oact_tx_desc = EMX_TX_OACTIVE_MAX;
2236 if (tdata->oact_tx_desc < tdata->spare_tx_desc + EMX_TX_RESERVED)
2237 tdata->oact_tx_desc = tdata->spare_tx_desc + EMX_TX_RESERVED;
2239 tdata->tx_intr_nsegs = tdata->num_tx_desc / 16;
2240 if (tdata->tx_intr_nsegs < tdata->oact_tx_desc)
2241 tdata->tx_intr_nsegs = tdata->oact_tx_desc;
2244 * Pullup extra 4bytes into the first data segment for TSO, see:
2245 * 82571/82572 specification update errata #7
2247 * Same applies to I217 (and maybe I218).
2250 * 4bytes instead of 2bytes, which are mentioned in the errata,
2251 * are pulled; mainly to keep rest of the data properly aligned.
2253 if (tdata->sc->hw.mac.type == e1000_82571 ||
2254 tdata->sc->hw.mac.type == e1000_82572 ||
2255 tdata->sc->hw.mac.type == e1000_pch_lpt)
2256 tdata->tx_flags |= EMX_TXFLAG_TSO_PULLEX;
2262 emx_init_tx_ring(struct emx_txdata *tdata)
2264 /* Clear the old ring contents */
2265 bzero(tdata->tx_desc_base,
2266 sizeof(struct e1000_tx_desc) * tdata->num_tx_desc);
2269 tdata->next_avail_tx_desc = 0;
2270 tdata->next_tx_to_clean = 0;
2271 tdata->num_tx_desc_avail = tdata->num_tx_desc;
2273 tdata->tx_flags |= EMX_TXFLAG_ENABLED;
2274 if (tdata->sc->tx_ring_inuse > 1) {
2275 tdata->tx_flags |= EMX_TXFLAG_FORCECTX;
2277 if_printf(&tdata->sc->arpcom.ac_if,
2278 "TX %d force ctx setup\n", tdata->idx);
2284 emx_init_tx_unit(struct emx_softc *sc)
2286 uint32_t tctl, tarc, tipg = 0;
2289 for (i = 0; i < sc->tx_ring_inuse; ++i) {
2290 struct emx_txdata *tdata = &sc->tx_data[i];
2293 /* Setup the Base and Length of the Tx Descriptor Ring */
2294 bus_addr = tdata->tx_desc_paddr;
2295 E1000_WRITE_REG(&sc->hw, E1000_TDLEN(i),
2296 tdata->num_tx_desc * sizeof(struct e1000_tx_desc));
2297 E1000_WRITE_REG(&sc->hw, E1000_TDBAH(i),
2298 (uint32_t)(bus_addr >> 32));
2299 E1000_WRITE_REG(&sc->hw, E1000_TDBAL(i),
2300 (uint32_t)bus_addr);
2301 /* Setup the HW Tx Head and Tail descriptor pointers */
2302 E1000_WRITE_REG(&sc->hw, E1000_TDT(i), 0);
2303 E1000_WRITE_REG(&sc->hw, E1000_TDH(i), 0);
2306 /* Set the default values for the Tx Inter Packet Gap timer */
2307 switch (sc->hw.mac.type) {
2308 case e1000_80003es2lan:
2309 tipg = DEFAULT_82543_TIPG_IPGR1;
2310 tipg |= DEFAULT_80003ES2LAN_TIPG_IPGR2 <<
2311 E1000_TIPG_IPGR2_SHIFT;
2315 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
2316 sc->hw.phy.media_type == e1000_media_type_internal_serdes)
2317 tipg = DEFAULT_82543_TIPG_IPGT_FIBER;
2319 tipg = DEFAULT_82543_TIPG_IPGT_COPPER;
2320 tipg |= DEFAULT_82543_TIPG_IPGR1 << E1000_TIPG_IPGR1_SHIFT;
2321 tipg |= DEFAULT_82543_TIPG_IPGR2 << E1000_TIPG_IPGR2_SHIFT;
2325 E1000_WRITE_REG(&sc->hw, E1000_TIPG, tipg);
2327 /* NOTE: 0 is not allowed for TIDV */
2328 E1000_WRITE_REG(&sc->hw, E1000_TIDV, 1);
2329 E1000_WRITE_REG(&sc->hw, E1000_TADV, 0);
2331 if (sc->hw.mac.type == e1000_82571 ||
2332 sc->hw.mac.type == e1000_82572) {
2333 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2334 tarc |= EMX_TARC_SPEED_MODE;
2335 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2336 } else if (sc->hw.mac.type == e1000_80003es2lan) {
2337 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2339 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2340 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1));
2342 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc);
2345 /* Program the Transmit Control Register */
2346 tctl = E1000_READ_REG(&sc->hw, E1000_TCTL);
2347 tctl &= ~E1000_TCTL_CT;
2348 tctl |= E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
2349 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT);
2350 tctl |= E1000_TCTL_MULR;
2352 /* This write will effectively turn on the transmit unit. */
2353 E1000_WRITE_REG(&sc->hw, E1000_TCTL, tctl);
2355 if (sc->hw.mac.type == e1000_82571 ||
2356 sc->hw.mac.type == e1000_82572 ||
2357 sc->hw.mac.type == e1000_80003es2lan) {
2358 /* Bit 28 of TARC1 must be cleared when MULR is enabled */
2359 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1));
2361 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc);
2364 if (sc->tx_ring_inuse > 1) {
2365 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(0));
2366 tarc &= ~EMX_TARC_COUNT_MASK;
2368 E1000_WRITE_REG(&sc->hw, E1000_TARC(0), tarc);
2370 tarc = E1000_READ_REG(&sc->hw, E1000_TARC(1));
2371 tarc &= ~EMX_TARC_COUNT_MASK;
2373 E1000_WRITE_REG(&sc->hw, E1000_TARC(1), tarc);
2378 emx_destroy_tx_ring(struct emx_txdata *tdata, int ndesc)
2380 struct emx_txbuf *tx_buffer;
2383 /* Free Transmit Descriptor ring */
2384 if (tdata->tx_desc_base) {
2385 bus_dmamap_unload(tdata->tx_desc_dtag, tdata->tx_desc_dmap);
2386 bus_dmamem_free(tdata->tx_desc_dtag, tdata->tx_desc_base,
2387 tdata->tx_desc_dmap);
2388 bus_dma_tag_destroy(tdata->tx_desc_dtag);
2390 tdata->tx_desc_base = NULL;
2393 if (tdata->tx_buf == NULL)
2396 for (i = 0; i < ndesc; i++) {
2397 tx_buffer = &tdata->tx_buf[i];
2399 KKASSERT(tx_buffer->m_head == NULL);
2400 bus_dmamap_destroy(tdata->txtag, tx_buffer->map);
2402 bus_dma_tag_destroy(tdata->txtag);
2404 kfree(tdata->tx_buf, M_DEVBUF);
2405 tdata->tx_buf = NULL;
2409 * The offload context needs to be set when we transfer the first
2410 * packet of a particular protocol (TCP/UDP). This routine has been
2411 * enhanced to deal with inserted VLAN headers.
2413 * If the new packet's ether header length, ip header length and
2414 * csum offloading type are same as the previous packet, we should
2415 * avoid allocating a new csum context descriptor; mainly to take
2416 * advantage of the pipeline effect of the TX data read request.
2418 * This function returns number of TX descrptors allocated for
2422 emx_txcsum(struct emx_txdata *tdata, struct mbuf *mp,
2423 uint32_t *txd_upper, uint32_t *txd_lower)
2425 struct e1000_context_desc *TXD;
2426 int curr_txd, ehdrlen, csum_flags;
2427 uint32_t cmd, hdr_len, ip_hlen;
2429 csum_flags = mp->m_pkthdr.csum_flags & EMX_CSUM_FEATURES;
2430 ip_hlen = mp->m_pkthdr.csum_iphlen;
2431 ehdrlen = mp->m_pkthdr.csum_lhlen;
2433 if ((tdata->tx_flags & EMX_TXFLAG_FORCECTX) == 0 &&
2434 tdata->csum_lhlen == ehdrlen && tdata->csum_iphlen == ip_hlen &&
2435 tdata->csum_flags == csum_flags) {
2437 * Same csum offload context as the previous packets;
2440 *txd_upper = tdata->csum_txd_upper;
2441 *txd_lower = tdata->csum_txd_lower;
2446 * Setup a new csum offload context.
2449 curr_txd = tdata->next_avail_tx_desc;
2450 TXD = (struct e1000_context_desc *)&tdata->tx_desc_base[curr_txd];
2454 /* Setup of IP header checksum. */
2455 if (csum_flags & CSUM_IP) {
2457 * Start offset for header checksum calculation.
2458 * End offset for header checksum calculation.
2459 * Offset of place to put the checksum.
2461 TXD->lower_setup.ip_fields.ipcss = ehdrlen;
2462 TXD->lower_setup.ip_fields.ipcse =
2463 htole16(ehdrlen + ip_hlen - 1);
2464 TXD->lower_setup.ip_fields.ipcso =
2465 ehdrlen + offsetof(struct ip, ip_sum);
2466 cmd |= E1000_TXD_CMD_IP;
2467 *txd_upper |= E1000_TXD_POPTS_IXSM << 8;
2469 hdr_len = ehdrlen + ip_hlen;
2471 if (csum_flags & CSUM_TCP) {
2473 * Start offset for payload checksum calculation.
2474 * End offset for payload checksum calculation.
2475 * Offset of place to put the checksum.
2477 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2478 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2479 TXD->upper_setup.tcp_fields.tucso =
2480 hdr_len + offsetof(struct tcphdr, th_sum);
2481 cmd |= E1000_TXD_CMD_TCP;
2482 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2483 } else if (csum_flags & CSUM_UDP) {
2485 * Start offset for header checksum calculation.
2486 * End offset for header checksum calculation.
2487 * Offset of place to put the checksum.
2489 TXD->upper_setup.tcp_fields.tucss = hdr_len;
2490 TXD->upper_setup.tcp_fields.tucse = htole16(0);
2491 TXD->upper_setup.tcp_fields.tucso =
2492 hdr_len + offsetof(struct udphdr, uh_sum);
2493 *txd_upper |= E1000_TXD_POPTS_TXSM << 8;
2496 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
2497 E1000_TXD_DTYP_D; /* Data descr */
2499 /* Save the information for this csum offloading context */
2500 tdata->csum_lhlen = ehdrlen;
2501 tdata->csum_iphlen = ip_hlen;
2502 tdata->csum_flags = csum_flags;
2503 tdata->csum_txd_upper = *txd_upper;
2504 tdata->csum_txd_lower = *txd_lower;
2506 TXD->tcp_seg_setup.data = htole32(0);
2507 TXD->cmd_and_length =
2508 htole32(E1000_TXD_CMD_IFCS | E1000_TXD_CMD_DEXT | cmd);
2510 if (++curr_txd == tdata->num_tx_desc)
2513 KKASSERT(tdata->num_tx_desc_avail > 0);
2514 tdata->num_tx_desc_avail--;
2516 tdata->next_avail_tx_desc = curr_txd;
2521 emx_txeof(struct emx_txdata *tdata)
2523 struct ifnet *ifp = &tdata->sc->arpcom.ac_if;
2524 struct emx_txbuf *tx_buffer;
2525 int first, num_avail;
2527 if (tdata->tx_dd_head == tdata->tx_dd_tail)
2530 if (tdata->num_tx_desc_avail == tdata->num_tx_desc)
2533 num_avail = tdata->num_tx_desc_avail;
2534 first = tdata->next_tx_to_clean;
2536 while (tdata->tx_dd_head != tdata->tx_dd_tail) {
2537 int dd_idx = tdata->tx_dd[tdata->tx_dd_head];
2538 struct e1000_tx_desc *tx_desc;
2540 tx_desc = &tdata->tx_desc_base[dd_idx];
2541 if (tx_desc->upper.fields.status & E1000_TXD_STAT_DD) {
2542 EMX_INC_TXDD_IDX(tdata->tx_dd_head);
2544 if (++dd_idx == tdata->num_tx_desc)
2547 while (first != dd_idx) {
2552 tx_buffer = &tdata->tx_buf[first];
2553 if (tx_buffer->m_head) {
2554 IFNET_STAT_INC(ifp, opackets, 1);
2555 bus_dmamap_unload(tdata->txtag,
2557 m_freem(tx_buffer->m_head);
2558 tx_buffer->m_head = NULL;
2561 if (++first == tdata->num_tx_desc)
2568 tdata->next_tx_to_clean = first;
2569 tdata->num_tx_desc_avail = num_avail;
2571 if (tdata->tx_dd_head == tdata->tx_dd_tail) {
2572 tdata->tx_dd_head = 0;
2573 tdata->tx_dd_tail = 0;
2576 if (!EMX_IS_OACTIVE(tdata)) {
2577 ifsq_clr_oactive(tdata->ifsq);
2579 /* All clean, turn off the timer */
2580 if (tdata->num_tx_desc_avail == tdata->num_tx_desc)
2581 tdata->tx_watchdog.wd_timer = 0;
2586 emx_tx_collect(struct emx_txdata *tdata)
2588 struct ifnet *ifp = &tdata->sc->arpcom.ac_if;
2589 struct emx_txbuf *tx_buffer;
2590 int tdh, first, num_avail, dd_idx = -1;
2592 if (tdata->num_tx_desc_avail == tdata->num_tx_desc)
2595 tdh = E1000_READ_REG(&tdata->sc->hw, E1000_TDH(tdata->idx));
2596 if (tdh == tdata->next_tx_to_clean)
2599 if (tdata->tx_dd_head != tdata->tx_dd_tail)
2600 dd_idx = tdata->tx_dd[tdata->tx_dd_head];
2602 num_avail = tdata->num_tx_desc_avail;
2603 first = tdata->next_tx_to_clean;
2605 while (first != tdh) {
2610 tx_buffer = &tdata->tx_buf[first];
2611 if (tx_buffer->m_head) {
2612 IFNET_STAT_INC(ifp, opackets, 1);
2613 bus_dmamap_unload(tdata->txtag,
2615 m_freem(tx_buffer->m_head);
2616 tx_buffer->m_head = NULL;
2619 if (first == dd_idx) {
2620 EMX_INC_TXDD_IDX(tdata->tx_dd_head);
2621 if (tdata->tx_dd_head == tdata->tx_dd_tail) {
2622 tdata->tx_dd_head = 0;
2623 tdata->tx_dd_tail = 0;
2626 dd_idx = tdata->tx_dd[tdata->tx_dd_head];
2630 if (++first == tdata->num_tx_desc)
2633 tdata->next_tx_to_clean = first;
2634 tdata->num_tx_desc_avail = num_avail;
2636 if (!EMX_IS_OACTIVE(tdata)) {
2637 ifsq_clr_oactive(tdata->ifsq);
2639 /* All clean, turn off the timer */
2640 if (tdata->num_tx_desc_avail == tdata->num_tx_desc)
2641 tdata->tx_watchdog.wd_timer = 0;
2646 * When Link is lost sometimes there is work still in the TX ring
2647 * which will result in a watchdog, rather than allow that do an
2648 * attempted cleanup and then reinit here. Note that this has been
2649 * seens mostly with fiber adapters.
2652 emx_tx_purge(struct emx_softc *sc)
2656 if (sc->link_active)
2659 for (i = 0; i < sc->tx_ring_inuse; ++i) {
2660 struct emx_txdata *tdata = &sc->tx_data[i];
2662 if (tdata->tx_watchdog.wd_timer) {
2663 emx_tx_collect(tdata);
2664 if (tdata->tx_watchdog.wd_timer) {
2665 if_printf(&sc->arpcom.ac_if,
2666 "Link lost, TX pending, reinit\n");
2675 emx_newbuf(struct emx_rxdata *rdata, int i, int init)
2678 bus_dma_segment_t seg;
2680 struct emx_rxbuf *rx_buffer;
2683 m = m_getcl(init ? M_WAITOK : M_NOWAIT, MT_DATA, M_PKTHDR);
2686 if_printf(&rdata->sc->arpcom.ac_if,
2687 "Unable to allocate RX mbuf\n");
2691 m->m_len = m->m_pkthdr.len = MCLBYTES;
2693 if (rdata->sc->hw.mac.max_frame_size <= MCLBYTES - ETHER_ALIGN)
2694 m_adj(m, ETHER_ALIGN);
2696 error = bus_dmamap_load_mbuf_segment(rdata->rxtag,
2697 rdata->rx_sparemap, m,
2698 &seg, 1, &nseg, BUS_DMA_NOWAIT);
2702 if_printf(&rdata->sc->arpcom.ac_if,
2703 "Unable to load RX mbuf\n");
2708 rx_buffer = &rdata->rx_buf[i];
2709 if (rx_buffer->m_head != NULL)
2710 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
2712 map = rx_buffer->map;
2713 rx_buffer->map = rdata->rx_sparemap;
2714 rdata->rx_sparemap = map;
2716 rx_buffer->m_head = m;
2717 rx_buffer->paddr = seg.ds_addr;
2719 emx_setup_rxdesc(&rdata->rx_desc[i], rx_buffer);
2724 emx_create_rx_ring(struct emx_rxdata *rdata)
2726 device_t dev = rdata->sc->dev;
2727 struct emx_rxbuf *rx_buffer;
2728 int i, error, rsize, nrxd;
2731 * Validate number of receive descriptors. It must not exceed
2732 * hardware maximum, and must be multiple of E1000_DBA_ALIGN.
2734 nrxd = device_getenv_int(dev, "rxd", emx_rxd);
2735 if ((nrxd * sizeof(emx_rxdesc_t)) % EMX_DBA_ALIGN != 0 ||
2736 nrxd > EMX_MAX_RXD || nrxd < EMX_MIN_RXD) {
2737 device_printf(dev, "Using %d RX descriptors instead of %d!\n",
2738 EMX_DEFAULT_RXD, nrxd);
2739 rdata->num_rx_desc = EMX_DEFAULT_RXD;
2741 rdata->num_rx_desc = nrxd;
2745 * Allocate Receive Descriptor ring
2747 rsize = roundup2(rdata->num_rx_desc * sizeof(emx_rxdesc_t),
2749 rdata->rx_desc = bus_dmamem_coherent_any(rdata->sc->parent_dtag,
2750 EMX_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
2751 &rdata->rx_desc_dtag, &rdata->rx_desc_dmap,
2752 &rdata->rx_desc_paddr);
2753 if (rdata->rx_desc == NULL) {
2754 device_printf(dev, "Unable to allocate rx_desc memory\n");
2758 rsize = __VM_CACHELINE_ALIGN(
2759 sizeof(struct emx_rxbuf) * rdata->num_rx_desc);
2760 rdata->rx_buf = kmalloc_cachealign(rsize, M_DEVBUF, M_WAITOK | M_ZERO);
2763 * Create DMA tag for rx buffers
2765 error = bus_dma_tag_create(rdata->sc->parent_dtag, /* parent */
2766 1, 0, /* alignment, bounds */
2767 BUS_SPACE_MAXADDR, /* lowaddr */
2768 BUS_SPACE_MAXADDR, /* highaddr */
2769 NULL, NULL, /* filter, filterarg */
2770 MCLBYTES, /* maxsize */
2772 MCLBYTES, /* maxsegsize */
2773 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
2776 device_printf(dev, "Unable to allocate RX DMA tag\n");
2777 kfree(rdata->rx_buf, M_DEVBUF);
2778 rdata->rx_buf = NULL;
2783 * Create spare DMA map for rx buffers
2785 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
2786 &rdata->rx_sparemap);
2788 device_printf(dev, "Unable to create spare RX DMA map\n");
2789 bus_dma_tag_destroy(rdata->rxtag);
2790 kfree(rdata->rx_buf, M_DEVBUF);
2791 rdata->rx_buf = NULL;
2796 * Create DMA maps for rx buffers
2798 for (i = 0; i < rdata->num_rx_desc; i++) {
2799 rx_buffer = &rdata->rx_buf[i];
2801 error = bus_dmamap_create(rdata->rxtag, BUS_DMA_WAITOK,
2804 device_printf(dev, "Unable to create RX DMA map\n");
2805 emx_destroy_rx_ring(rdata, i);
2813 emx_free_rx_ring(struct emx_rxdata *rdata)
2817 for (i = 0; i < rdata->num_rx_desc; i++) {
2818 struct emx_rxbuf *rx_buffer = &rdata->rx_buf[i];
2820 if (rx_buffer->m_head != NULL) {
2821 bus_dmamap_unload(rdata->rxtag, rx_buffer->map);
2822 m_freem(rx_buffer->m_head);
2823 rx_buffer->m_head = NULL;
2827 if (rdata->fmp != NULL)
2828 m_freem(rdata->fmp);
2834 emx_free_tx_ring(struct emx_txdata *tdata)
2838 for (i = 0; i < tdata->num_tx_desc; i++) {
2839 struct emx_txbuf *tx_buffer = &tdata->tx_buf[i];
2841 if (tx_buffer->m_head != NULL) {
2842 bus_dmamap_unload(tdata->txtag, tx_buffer->map);
2843 m_freem(tx_buffer->m_head);
2844 tx_buffer->m_head = NULL;
2848 tdata->tx_flags &= ~EMX_TXFLAG_FORCECTX;
2850 tdata->csum_flags = 0;
2851 tdata->csum_lhlen = 0;
2852 tdata->csum_iphlen = 0;
2853 tdata->csum_thlen = 0;
2854 tdata->csum_mss = 0;
2855 tdata->csum_pktlen = 0;
2857 tdata->tx_dd_head = 0;
2858 tdata->tx_dd_tail = 0;
2859 tdata->tx_nsegs = 0;
2863 emx_init_rx_ring(struct emx_rxdata *rdata)
2867 /* Reset descriptor ring */
2868 bzero(rdata->rx_desc, sizeof(emx_rxdesc_t) * rdata->num_rx_desc);
2870 /* Allocate new ones. */
2871 for (i = 0; i < rdata->num_rx_desc; i++) {
2872 error = emx_newbuf(rdata, i, 1);
2877 /* Setup our descriptor pointers */
2878 rdata->next_rx_desc_to_check = 0;
2884 emx_init_rx_unit(struct emx_softc *sc)
2886 struct ifnet *ifp = &sc->arpcom.ac_if;
2888 uint32_t rctl, itr, rfctl;
2892 * Make sure receives are disabled while setting
2893 * up the descriptor ring
2895 rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
2896 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2899 * Set the interrupt throttling rate. Value is calculated
2900 * as ITR = 1 / (INT_THROTTLE_CEIL * 256ns)
2902 if (sc->int_throttle_ceil)
2903 itr = 1000000000 / 256 / sc->int_throttle_ceil;
2906 emx_set_itr(sc, itr);
2908 /* Use extended RX descriptor */
2909 rfctl = E1000_RFCTL_EXTEN;
2911 /* Disable accelerated ackknowledge */
2912 if (sc->hw.mac.type == e1000_82574)
2913 rfctl |= E1000_RFCTL_ACK_DIS;
2915 E1000_WRITE_REG(&sc->hw, E1000_RFCTL, rfctl);
2918 * Receive Checksum Offload for TCP and UDP
2920 * Checksum offloading is also enabled if multiple receive
2921 * queue is to be supported, since we need it to figure out
2924 if ((ifp->if_capenable & IFCAP_RXCSUM) ||
2925 sc->rx_ring_cnt > 1) {
2928 rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
2932 * PCSD must be enabled to enable multiple
2935 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2937 E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2941 * Configure multiple receive queue (RSS)
2943 if (sc->rx_ring_cnt > 1) {
2944 uint8_t key[EMX_NRSSRK * EMX_RSSRK_SIZE];
2947 KASSERT(sc->rx_ring_cnt == EMX_NRX_RING,
2948 ("invalid number of RX ring (%d)", sc->rx_ring_cnt));
2952 * When we reach here, RSS has already been disabled
2953 * in emx_stop(), so we could safely configure RSS key
2954 * and redirect table.
2960 toeplitz_get_key(key, sizeof(key));
2961 for (i = 0; i < EMX_NRSSRK; ++i) {
2964 rssrk = EMX_RSSRK_VAL(key, i);
2965 EMX_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2967 E1000_WRITE_REG(&sc->hw, E1000_RSSRK(i), rssrk);
2971 * Configure RSS redirect table in following fashion:
2972 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2975 for (i = 0; i < EMX_RETA_SIZE; ++i) {
2978 q = (i % sc->rx_ring_cnt) << EMX_RETA_RINGIDX_SHIFT;
2979 reta |= q << (8 * i);
2981 EMX_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2983 for (i = 0; i < EMX_NRETA; ++i)
2984 E1000_WRITE_REG(&sc->hw, E1000_RETA(i), reta);
2987 * Enable multiple receive queues.
2988 * Enable IPv4 RSS standard hash functions.
2989 * Disable RSS interrupt.
2991 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
2992 E1000_MRQC_ENABLE_RSS_2Q |
2993 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2994 E1000_MRQC_RSS_FIELD_IPV4);
2998 * XXX TEMPORARY WORKAROUND: on some systems with 82573
2999 * long latencies are observed, like Lenovo X60. This
3000 * change eliminates the problem, but since having positive
3001 * values in RDTR is a known source of problems on other
3002 * platforms another solution is being sought.
3004 if (emx_82573_workaround && sc->hw.mac.type == e1000_82573) {
3005 E1000_WRITE_REG(&sc->hw, E1000_RADV, EMX_RADV_82573);
3006 E1000_WRITE_REG(&sc->hw, E1000_RDTR, EMX_RDTR_82573);
3009 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3010 struct emx_rxdata *rdata = &sc->rx_data[i];
3013 * Setup the Base and Length of the Rx Descriptor Ring
3015 bus_addr = rdata->rx_desc_paddr;
3016 E1000_WRITE_REG(&sc->hw, E1000_RDLEN(i),
3017 rdata->num_rx_desc * sizeof(emx_rxdesc_t));
3018 E1000_WRITE_REG(&sc->hw, E1000_RDBAH(i),
3019 (uint32_t)(bus_addr >> 32));
3020 E1000_WRITE_REG(&sc->hw, E1000_RDBAL(i),
3021 (uint32_t)bus_addr);
3024 * Setup the HW Rx Head and Tail Descriptor Pointers
3026 E1000_WRITE_REG(&sc->hw, E1000_RDH(i), 0);
3027 E1000_WRITE_REG(&sc->hw, E1000_RDT(i),
3028 sc->rx_data[i].num_rx_desc - 1);
3031 if (sc->hw.mac.type >= e1000_pch2lan) {
3032 if (ifp->if_mtu > ETHERMTU)
3033 e1000_lv_jumbo_workaround_ich8lan(&sc->hw, TRUE);
3035 e1000_lv_jumbo_workaround_ich8lan(&sc->hw, FALSE);
3038 /* Setup the Receive Control Register */
3039 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
3040 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
3041 E1000_RCTL_RDMTS_HALF | E1000_RCTL_SECRC |
3042 (sc->hw.mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
3044 /* Make sure VLAN Filters are off */
3045 rctl &= ~E1000_RCTL_VFE;
3047 /* Don't store bad paket */
3048 rctl &= ~E1000_RCTL_SBP;
3051 rctl |= E1000_RCTL_SZ_2048;
3053 if (ifp->if_mtu > ETHERMTU)
3054 rctl |= E1000_RCTL_LPE;
3056 rctl &= ~E1000_RCTL_LPE;
3058 /* Enable Receives */
3059 E1000_WRITE_REG(&sc->hw, E1000_RCTL, rctl);
3063 emx_destroy_rx_ring(struct emx_rxdata *rdata, int ndesc)
3065 struct emx_rxbuf *rx_buffer;
3068 /* Free Receive Descriptor ring */
3069 if (rdata->rx_desc) {
3070 bus_dmamap_unload(rdata->rx_desc_dtag, rdata->rx_desc_dmap);
3071 bus_dmamem_free(rdata->rx_desc_dtag, rdata->rx_desc,
3072 rdata->rx_desc_dmap);
3073 bus_dma_tag_destroy(rdata->rx_desc_dtag);
3075 rdata->rx_desc = NULL;
3078 if (rdata->rx_buf == NULL)
3081 for (i = 0; i < ndesc; i++) {
3082 rx_buffer = &rdata->rx_buf[i];
3084 KKASSERT(rx_buffer->m_head == NULL);
3085 bus_dmamap_destroy(rdata->rxtag, rx_buffer->map);
3087 bus_dmamap_destroy(rdata->rxtag, rdata->rx_sparemap);
3088 bus_dma_tag_destroy(rdata->rxtag);
3090 kfree(rdata->rx_buf, M_DEVBUF);
3091 rdata->rx_buf = NULL;
3095 emx_rxeof(struct emx_rxdata *rdata, int count)
3097 struct ifnet *ifp = &rdata->sc->arpcom.ac_if;
3099 emx_rxdesc_t *current_desc;
3101 int i, cpuid = mycpuid;
3103 i = rdata->next_rx_desc_to_check;
3104 current_desc = &rdata->rx_desc[i];
3105 staterr = le32toh(current_desc->rxd_staterr);
3107 if (!(staterr & E1000_RXD_STAT_DD))
3110 while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
3111 struct pktinfo *pi = NULL, pi0;
3112 struct emx_rxbuf *rx_buf = &rdata->rx_buf[i];
3113 struct mbuf *m = NULL;
3118 mp = rx_buf->m_head;
3121 * Can't defer bus_dmamap_sync(9) because TBI_ACCEPT
3122 * needs to access the last received byte in the mbuf.
3124 bus_dmamap_sync(rdata->rxtag, rx_buf->map,
3125 BUS_DMASYNC_POSTREAD);
3127 len = le16toh(current_desc->rxd_length);
3128 if (staterr & E1000_RXD_STAT_EOP) {
3135 if (!(staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK)) {
3137 uint32_t mrq, rss_hash;
3140 * Save several necessary information,
3141 * before emx_newbuf() destroy it.
3143 if ((staterr & E1000_RXD_STAT_VP) && eop)
3144 vlan = le16toh(current_desc->rxd_vlan);
3146 mrq = le32toh(current_desc->rxd_mrq);
3147 rss_hash = le32toh(current_desc->rxd_rss);
3149 EMX_RSS_DPRINTF(rdata->sc, 10,
3150 "ring%d, mrq 0x%08x, rss_hash 0x%08x\n",
3151 rdata->idx, mrq, rss_hash);
3153 if (emx_newbuf(rdata, i, 0) != 0) {
3154 IFNET_STAT_INC(ifp, iqdrops, 1);
3158 /* Assign correct length to the current fragment */
3161 if (rdata->fmp == NULL) {
3162 mp->m_pkthdr.len = len;
3163 rdata->fmp = mp; /* Store the first mbuf */
3167 * Chain mbuf's together
3169 rdata->lmp->m_next = mp;
3170 rdata->lmp = rdata->lmp->m_next;
3171 rdata->fmp->m_pkthdr.len += len;
3175 rdata->fmp->m_pkthdr.rcvif = ifp;
3176 IFNET_STAT_INC(ifp, ipackets, 1);
3178 if (ifp->if_capenable & IFCAP_RXCSUM)
3179 emx_rxcsum(staterr, rdata->fmp);
3181 if (staterr & E1000_RXD_STAT_VP) {
3182 rdata->fmp->m_pkthdr.ether_vlantag =
3184 rdata->fmp->m_flags |= M_VLANTAG;
3190 if (ifp->if_capenable & IFCAP_RSS) {
3191 pi = emx_rssinfo(m, &pi0, mrq,
3194 #ifdef EMX_RSS_DEBUG
3199 IFNET_STAT_INC(ifp, ierrors, 1);
3201 emx_setup_rxdesc(current_desc, rx_buf);
3202 if (rdata->fmp != NULL) {
3203 m_freem(rdata->fmp);
3211 ifp->if_input(ifp, m, pi, cpuid);
3213 /* Advance our pointers to the next descriptor. */
3214 if (++i == rdata->num_rx_desc)
3217 current_desc = &rdata->rx_desc[i];
3218 staterr = le32toh(current_desc->rxd_staterr);
3220 rdata->next_rx_desc_to_check = i;
3222 /* Advance the E1000's Receive Queue "Tail Pointer". */
3224 i = rdata->num_rx_desc - 1;
3225 E1000_WRITE_REG(&rdata->sc->hw, E1000_RDT(rdata->idx), i);
3229 emx_enable_intr(struct emx_softc *sc)
3231 uint32_t ims_mask = IMS_ENABLE_MASK;
3233 lwkt_serialize_handler_enable(&sc->main_serialize);
3236 if (sc->hw.mac.type == e1000_82574) {
3237 E1000_WRITE_REG(hw, EMX_EIAC, EM_MSIX_MASK);
3238 ims_mask |= EM_MSIX_MASK;
3241 E1000_WRITE_REG(&sc->hw, E1000_IMS, ims_mask);
3245 emx_disable_intr(struct emx_softc *sc)
3247 if (sc->hw.mac.type == e1000_82574)
3248 E1000_WRITE_REG(&sc->hw, EMX_EIAC, 0);
3249 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
3251 lwkt_serialize_handler_disable(&sc->main_serialize);
3255 * Bit of a misnomer, what this really means is
3256 * to enable OS management of the system... aka
3257 * to disable special hardware management features
3260 emx_get_mgmt(struct emx_softc *sc)
3262 /* A shared code workaround */
3263 if (sc->flags & EMX_FLAG_HAS_MGMT) {
3264 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
3265 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3267 /* disable hardware interception of ARP */
3268 manc &= ~(E1000_MANC_ARP_EN);
3270 /* enable receiving management packets to the host */
3271 manc |= E1000_MANC_EN_MNG2HOST;
3272 #define E1000_MNG2HOST_PORT_623 (1 << 5)
3273 #define E1000_MNG2HOST_PORT_664 (1 << 6)
3274 manc2h |= E1000_MNG2HOST_PORT_623;
3275 manc2h |= E1000_MNG2HOST_PORT_664;
3276 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
3278 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3283 * Give control back to hardware management
3284 * controller if there is one.
3287 emx_rel_mgmt(struct emx_softc *sc)
3289 if (sc->flags & EMX_FLAG_HAS_MGMT) {
3290 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
3292 /* re-enable hardware interception of ARP */
3293 manc |= E1000_MANC_ARP_EN;
3294 manc &= ~E1000_MANC_EN_MNG2HOST;
3296 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
3301 * emx_get_hw_control() sets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3302 * For ASF and Pass Through versions of f/w this means that
3303 * the driver is loaded. For AMT version (only with 82573)
3304 * of the f/w this means that the network i/f is open.
3307 emx_get_hw_control(struct emx_softc *sc)
3309 /* Let firmware know the driver has taken over */
3310 if (sc->hw.mac.type == e1000_82573) {
3313 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3314 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3315 swsm | E1000_SWSM_DRV_LOAD);
3319 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3320 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3321 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
3323 sc->flags |= EMX_FLAG_HW_CTRL;
3327 * emx_rel_hw_control() resets {CTRL_EXT|FWSM}:DRV_LOAD bit.
3328 * For ASF and Pass Through versions of f/w this means that the
3329 * driver is no longer loaded. For AMT version (only with 82573)
3330 * of the f/w this means that the network i/f is closed.
3333 emx_rel_hw_control(struct emx_softc *sc)
3335 if ((sc->flags & EMX_FLAG_HW_CTRL) == 0)
3337 sc->flags &= ~EMX_FLAG_HW_CTRL;
3339 /* Let firmware taken over control of h/w */
3340 if (sc->hw.mac.type == e1000_82573) {
3343 swsm = E1000_READ_REG(&sc->hw, E1000_SWSM);
3344 E1000_WRITE_REG(&sc->hw, E1000_SWSM,
3345 swsm & ~E1000_SWSM_DRV_LOAD);
3349 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
3350 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
3351 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
3356 emx_is_valid_eaddr(const uint8_t *addr)
3358 char zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
3360 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
3367 * Enable PCI Wake On Lan capability
3370 emx_enable_wol(device_t dev)
3372 uint16_t cap, status;
3375 /* First find the capabilities pointer*/
3376 cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
3378 /* Read the PM Capabilities */
3379 id = pci_read_config(dev, cap, 1);
3380 if (id != PCIY_PMG) /* Something wrong */
3384 * OK, we have the power capabilities,
3385 * so now get the status register
3387 cap += PCIR_POWER_STATUS;
3388 status = pci_read_config(dev, cap, 2);
3389 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
3390 pci_write_config(dev, cap, status, 2);
3394 emx_update_stats(struct emx_softc *sc)
3396 struct ifnet *ifp = &sc->arpcom.ac_if;
3398 if (sc->hw.phy.media_type == e1000_media_type_copper ||
3399 (E1000_READ_REG(&sc->hw, E1000_STATUS) & E1000_STATUS_LU)) {
3400 sc->stats.symerrs += E1000_READ_REG(&sc->hw, E1000_SYMERRS);
3401 sc->stats.sec += E1000_READ_REG(&sc->hw, E1000_SEC);
3403 sc->stats.crcerrs += E1000_READ_REG(&sc->hw, E1000_CRCERRS);
3404 sc->stats.mpc += E1000_READ_REG(&sc->hw, E1000_MPC);
3405 sc->stats.scc += E1000_READ_REG(&sc->hw, E1000_SCC);
3406 sc->stats.ecol += E1000_READ_REG(&sc->hw, E1000_ECOL);
3408 sc->stats.mcc += E1000_READ_REG(&sc->hw, E1000_MCC);
3409 sc->stats.latecol += E1000_READ_REG(&sc->hw, E1000_LATECOL);
3410 sc->stats.colc += E1000_READ_REG(&sc->hw, E1000_COLC);
3411 sc->stats.dc += E1000_READ_REG(&sc->hw, E1000_DC);
3412 sc->stats.rlec += E1000_READ_REG(&sc->hw, E1000_RLEC);
3413 sc->stats.xonrxc += E1000_READ_REG(&sc->hw, E1000_XONRXC);
3414 sc->stats.xontxc += E1000_READ_REG(&sc->hw, E1000_XONTXC);
3415 sc->stats.xoffrxc += E1000_READ_REG(&sc->hw, E1000_XOFFRXC);
3416 sc->stats.xofftxc += E1000_READ_REG(&sc->hw, E1000_XOFFTXC);
3417 sc->stats.fcruc += E1000_READ_REG(&sc->hw, E1000_FCRUC);
3418 sc->stats.prc64 += E1000_READ_REG(&sc->hw, E1000_PRC64);
3419 sc->stats.prc127 += E1000_READ_REG(&sc->hw, E1000_PRC127);
3420 sc->stats.prc255 += E1000_READ_REG(&sc->hw, E1000_PRC255);
3421 sc->stats.prc511 += E1000_READ_REG(&sc->hw, E1000_PRC511);
3422 sc->stats.prc1023 += E1000_READ_REG(&sc->hw, E1000_PRC1023);
3423 sc->stats.prc1522 += E1000_READ_REG(&sc->hw, E1000_PRC1522);
3424 sc->stats.gprc += E1000_READ_REG(&sc->hw, E1000_GPRC);
3425 sc->stats.bprc += E1000_READ_REG(&sc->hw, E1000_BPRC);
3426 sc->stats.mprc += E1000_READ_REG(&sc->hw, E1000_MPRC);
3427 sc->stats.gptc += E1000_READ_REG(&sc->hw, E1000_GPTC);
3429 /* For the 64-bit byte counters the low dword must be read first. */
3430 /* Both registers clear on the read of the high dword */
3432 sc->stats.gorc += E1000_READ_REG(&sc->hw, E1000_GORCH);
3433 sc->stats.gotc += E1000_READ_REG(&sc->hw, E1000_GOTCH);
3435 sc->stats.rnbc += E1000_READ_REG(&sc->hw, E1000_RNBC);
3436 sc->stats.ruc += E1000_READ_REG(&sc->hw, E1000_RUC);
3437 sc->stats.rfc += E1000_READ_REG(&sc->hw, E1000_RFC);
3438 sc->stats.roc += E1000_READ_REG(&sc->hw, E1000_ROC);
3439 sc->stats.rjc += E1000_READ_REG(&sc->hw, E1000_RJC);
3441 sc->stats.tor += E1000_READ_REG(&sc->hw, E1000_TORH);
3442 sc->stats.tot += E1000_READ_REG(&sc->hw, E1000_TOTH);
3444 sc->stats.tpr += E1000_READ_REG(&sc->hw, E1000_TPR);
3445 sc->stats.tpt += E1000_READ_REG(&sc->hw, E1000_TPT);
3446 sc->stats.ptc64 += E1000_READ_REG(&sc->hw, E1000_PTC64);
3447 sc->stats.ptc127 += E1000_READ_REG(&sc->hw, E1000_PTC127);
3448 sc->stats.ptc255 += E1000_READ_REG(&sc->hw, E1000_PTC255);
3449 sc->stats.ptc511 += E1000_READ_REG(&sc->hw, E1000_PTC511);
3450 sc->stats.ptc1023 += E1000_READ_REG(&sc->hw, E1000_PTC1023);
3451 sc->stats.ptc1522 += E1000_READ_REG(&sc->hw, E1000_PTC1522);
3452 sc->stats.mptc += E1000_READ_REG(&sc->hw, E1000_MPTC);
3453 sc->stats.bptc += E1000_READ_REG(&sc->hw, E1000_BPTC);
3455 sc->stats.algnerrc += E1000_READ_REG(&sc->hw, E1000_ALGNERRC);
3456 sc->stats.rxerrc += E1000_READ_REG(&sc->hw, E1000_RXERRC);
3457 sc->stats.tncrs += E1000_READ_REG(&sc->hw, E1000_TNCRS);
3458 sc->stats.cexterr += E1000_READ_REG(&sc->hw, E1000_CEXTERR);
3459 sc->stats.tsctc += E1000_READ_REG(&sc->hw, E1000_TSCTC);
3460 sc->stats.tsctfc += E1000_READ_REG(&sc->hw, E1000_TSCTFC);
3462 IFNET_STAT_SET(ifp, collisions, sc->stats.colc);
3465 IFNET_STAT_SET(ifp, ierrors,
3466 sc->stats.rxerrc + sc->stats.crcerrs + sc->stats.algnerrc +
3467 sc->stats.ruc + sc->stats.roc + sc->stats.mpc + sc->stats.cexterr);
3470 IFNET_STAT_SET(ifp, oerrors, sc->stats.ecol + sc->stats.latecol);
3474 emx_print_debug_info(struct emx_softc *sc)
3476 device_t dev = sc->dev;
3477 uint8_t *hw_addr = sc->hw.hw_addr;
3480 device_printf(dev, "Adapter hardware address = %p \n", hw_addr);
3481 device_printf(dev, "CTRL = 0x%x RCTL = 0x%x \n",
3482 E1000_READ_REG(&sc->hw, E1000_CTRL),
3483 E1000_READ_REG(&sc->hw, E1000_RCTL));
3484 device_printf(dev, "Packet buffer = Tx=%dk Rx=%dk \n",
3485 ((E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff0000) >> 16),\
3486 (E1000_READ_REG(&sc->hw, E1000_PBA) & 0xffff) );
3487 device_printf(dev, "Flow control watermarks high = %d low = %d\n",
3488 sc->hw.fc.high_water, sc->hw.fc.low_water);
3489 device_printf(dev, "tx_int_delay = %d, tx_abs_int_delay = %d\n",
3490 E1000_READ_REG(&sc->hw, E1000_TIDV),
3491 E1000_READ_REG(&sc->hw, E1000_TADV));
3492 device_printf(dev, "rx_int_delay = %d, rx_abs_int_delay = %d\n",
3493 E1000_READ_REG(&sc->hw, E1000_RDTR),
3494 E1000_READ_REG(&sc->hw, E1000_RADV));
3496 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3497 device_printf(dev, "hw %d tdh = %d, hw tdt = %d\n", i,
3498 E1000_READ_REG(&sc->hw, E1000_TDH(i)),
3499 E1000_READ_REG(&sc->hw, E1000_TDT(i)));
3501 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3502 device_printf(dev, "hw %d rdh = %d, hw rdt = %d\n", i,
3503 E1000_READ_REG(&sc->hw, E1000_RDH(i)),
3504 E1000_READ_REG(&sc->hw, E1000_RDT(i)));
3507 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3508 device_printf(dev, "TX %d Tx descriptors avail = %d\n", i,
3509 sc->tx_data[i].num_tx_desc_avail);
3510 device_printf(dev, "TX %d TSO segments = %lu\n", i,
3511 sc->tx_data[i].tso_segments);
3512 device_printf(dev, "TX %d TSO ctx reused = %lu\n", i,
3513 sc->tx_data[i].tso_ctx_reused);
3518 emx_print_hw_stats(struct emx_softc *sc)
3520 device_t dev = sc->dev;
3522 device_printf(dev, "Excessive collisions = %lld\n",
3523 (long long)sc->stats.ecol);
3524 #if (DEBUG_HW > 0) /* Dont output these errors normally */
3525 device_printf(dev, "Symbol errors = %lld\n",
3526 (long long)sc->stats.symerrs);
3528 device_printf(dev, "Sequence errors = %lld\n",
3529 (long long)sc->stats.sec);
3530 device_printf(dev, "Defer count = %lld\n",
3531 (long long)sc->stats.dc);
3532 device_printf(dev, "Missed Packets = %lld\n",
3533 (long long)sc->stats.mpc);
3534 device_printf(dev, "Receive No Buffers = %lld\n",
3535 (long long)sc->stats.rnbc);
3536 /* RLEC is inaccurate on some hardware, calculate our own. */
3537 device_printf(dev, "Receive Length Errors = %lld\n",
3538 ((long long)sc->stats.roc + (long long)sc->stats.ruc));
3539 device_printf(dev, "Receive errors = %lld\n",
3540 (long long)sc->stats.rxerrc);
3541 device_printf(dev, "Crc errors = %lld\n",
3542 (long long)sc->stats.crcerrs);
3543 device_printf(dev, "Alignment errors = %lld\n",
3544 (long long)sc->stats.algnerrc);
3545 device_printf(dev, "Collision/Carrier extension errors = %lld\n",
3546 (long long)sc->stats.cexterr);
3547 device_printf(dev, "RX overruns = %ld\n", sc->rx_overruns);
3548 device_printf(dev, "XON Rcvd = %lld\n",
3549 (long long)sc->stats.xonrxc);
3550 device_printf(dev, "XON Xmtd = %lld\n",
3551 (long long)sc->stats.xontxc);
3552 device_printf(dev, "XOFF Rcvd = %lld\n",
3553 (long long)sc->stats.xoffrxc);
3554 device_printf(dev, "XOFF Xmtd = %lld\n",
3555 (long long)sc->stats.xofftxc);
3556 device_printf(dev, "Good Packets Rcvd = %lld\n",
3557 (long long)sc->stats.gprc);
3558 device_printf(dev, "Good Packets Xmtd = %lld\n",
3559 (long long)sc->stats.gptc);
3563 emx_print_nvm_info(struct emx_softc *sc)
3565 uint16_t eeprom_data;
3568 /* Its a bit crude, but it gets the job done */
3569 kprintf("\nInterface EEPROM Dump:\n");
3570 kprintf("Offset\n0x0000 ");
3571 for (i = 0, j = 0; i < 32; i++, j++) {
3572 if (j == 8) { /* Make the offset block */
3574 kprintf("\n0x00%x0 ",row);
3576 e1000_read_nvm(&sc->hw, i, 1, &eeprom_data);
3577 kprintf("%04x ", eeprom_data);
3583 emx_sysctl_debug_info(SYSCTL_HANDLER_ARGS)
3585 struct emx_softc *sc;
3590 error = sysctl_handle_int(oidp, &result, 0, req);
3591 if (error || !req->newptr)
3594 sc = (struct emx_softc *)arg1;
3595 ifp = &sc->arpcom.ac_if;
3597 ifnet_serialize_all(ifp);
3600 emx_print_debug_info(sc);
3603 * This value will cause a hex dump of the
3604 * first 32 16-bit words of the EEPROM to
3608 emx_print_nvm_info(sc);
3610 ifnet_deserialize_all(ifp);
3616 emx_sysctl_stats(SYSCTL_HANDLER_ARGS)
3621 error = sysctl_handle_int(oidp, &result, 0, req);
3622 if (error || !req->newptr)
3626 struct emx_softc *sc = (struct emx_softc *)arg1;
3627 struct ifnet *ifp = &sc->arpcom.ac_if;
3629 ifnet_serialize_all(ifp);
3630 emx_print_hw_stats(sc);
3631 ifnet_deserialize_all(ifp);
3637 emx_add_sysctl(struct emx_softc *sc)
3639 struct sysctl_ctx_list *ctx;
3640 struct sysctl_oid *tree;
3641 #if defined(EMX_RSS_DEBUG) || defined(EMX_TSS_DEBUG)
3646 ctx = device_get_sysctl_ctx(sc->dev);
3647 tree = device_get_sysctl_tree(sc->dev);
3648 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3649 OID_AUTO, "debug", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3650 emx_sysctl_debug_info, "I", "Debug Information");
3652 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3653 OID_AUTO, "stats", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3654 emx_sysctl_stats, "I", "Statistics");
3656 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
3657 OID_AUTO, "rxd", CTLFLAG_RD, &sc->rx_data[0].num_rx_desc, 0,
3659 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
3660 OID_AUTO, "txd", CTLFLAG_RD, &sc->tx_data[0].num_tx_desc, 0,
3663 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3664 OID_AUTO, "int_throttle_ceil", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3665 emx_sysctl_int_throttle, "I", "interrupt throttling rate");
3666 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3667 OID_AUTO, "tx_intr_nsegs", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3668 emx_sysctl_tx_intr_nsegs, "I", "# segments per TX interrupt");
3669 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3670 OID_AUTO, "tx_wreg_nsegs", CTLTYPE_INT|CTLFLAG_RW, sc, 0,
3671 emx_sysctl_tx_wreg_nsegs, "I",
3672 "# segments sent before write to hardware register");
3674 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
3675 OID_AUTO, "rx_ring_cnt", CTLFLAG_RD, &sc->rx_ring_cnt, 0,
3677 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
3678 OID_AUTO, "tx_ring_cnt", CTLFLAG_RD, &sc->tx_ring_cnt, 0,
3680 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
3681 OID_AUTO, "tx_ring_inuse", CTLFLAG_RD, &sc->tx_ring_inuse, 0,
3682 "# of TX rings used");
3684 #ifdef IFPOLL_ENABLE
3685 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3686 OID_AUTO, "npoll_rxoff", CTLTYPE_INT|CTLFLAG_RW,
3687 sc, 0, emx_sysctl_npoll_rxoff, "I",
3688 "NPOLLING RX cpu offset");
3689 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree),
3690 OID_AUTO, "npoll_txoff", CTLTYPE_INT|CTLFLAG_RW,
3691 sc, 0, emx_sysctl_npoll_txoff, "I",
3692 "NPOLLING TX cpu offset");
3695 #ifdef EMX_RSS_DEBUG
3696 SYSCTL_ADD_INT(ctx, SYSCTL_CHILDREN(tree),
3697 OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug,
3698 0, "RSS debug level");
3699 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3700 ksnprintf(pkt_desc, sizeof(pkt_desc), "rx%d_pkt", i);
3701 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
3702 pkt_desc, CTLFLAG_RW, &sc->rx_data[i].rx_pkts,
3706 #ifdef EMX_TSS_DEBUG
3707 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3708 ksnprintf(pkt_desc, sizeof(pkt_desc), "tx%d_pkt", i);
3709 SYSCTL_ADD_ULONG(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
3710 pkt_desc, CTLFLAG_RW, &sc->tx_data[i].tx_pkts,
3717 emx_sysctl_int_throttle(SYSCTL_HANDLER_ARGS)
3719 struct emx_softc *sc = (void *)arg1;
3720 struct ifnet *ifp = &sc->arpcom.ac_if;
3721 int error, throttle;
3723 throttle = sc->int_throttle_ceil;
3724 error = sysctl_handle_int(oidp, &throttle, 0, req);
3725 if (error || req->newptr == NULL)
3727 if (throttle < 0 || throttle > 1000000000 / 256)
3732 * Set the interrupt throttling rate in 256ns increments,
3733 * recalculate sysctl value assignment to get exact frequency.
3735 throttle = 1000000000 / 256 / throttle;
3737 /* Upper 16bits of ITR is reserved and should be zero */
3738 if (throttle & 0xffff0000)
3742 ifnet_serialize_all(ifp);
3745 sc->int_throttle_ceil = 1000000000 / 256 / throttle;
3747 sc->int_throttle_ceil = 0;
3749 if (ifp->if_flags & IFF_RUNNING)
3750 emx_set_itr(sc, throttle);
3752 ifnet_deserialize_all(ifp);
3755 if_printf(ifp, "Interrupt moderation set to %d/sec\n",
3756 sc->int_throttle_ceil);
3762 emx_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS)
3764 struct emx_softc *sc = (void *)arg1;
3765 struct ifnet *ifp = &sc->arpcom.ac_if;
3766 struct emx_txdata *tdata = &sc->tx_data[0];
3769 segs = tdata->tx_intr_nsegs;
3770 error = sysctl_handle_int(oidp, &segs, 0, req);
3771 if (error || req->newptr == NULL)
3776 ifnet_serialize_all(ifp);
3779 * Don't allow tx_intr_nsegs to become:
3780 * o Less the oact_tx_desc
3781 * o Too large that no TX desc will cause TX interrupt to
3782 * be generated (OACTIVE will never recover)
3783 * o Too small that will cause tx_dd[] overflow
3785 if (segs < tdata->oact_tx_desc ||
3786 segs >= tdata->num_tx_desc - tdata->oact_tx_desc ||
3787 segs < tdata->num_tx_desc / EMX_TXDD_SAFE) {
3793 for (i = 0; i < sc->tx_ring_cnt; ++i)
3794 sc->tx_data[i].tx_intr_nsegs = segs;
3797 ifnet_deserialize_all(ifp);
3803 emx_sysctl_tx_wreg_nsegs(SYSCTL_HANDLER_ARGS)
3805 struct emx_softc *sc = (void *)arg1;
3806 struct ifnet *ifp = &sc->arpcom.ac_if;
3807 int error, nsegs, i;
3809 nsegs = sc->tx_data[0].tx_wreg_nsegs;
3810 error = sysctl_handle_int(oidp, &nsegs, 0, req);
3811 if (error || req->newptr == NULL)
3814 ifnet_serialize_all(ifp);
3815 for (i = 0; i < sc->tx_ring_cnt; ++i)
3816 sc->tx_data[i].tx_wreg_nsegs =nsegs;
3817 ifnet_deserialize_all(ifp);
3822 #ifdef IFPOLL_ENABLE
3825 emx_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS)
3827 struct emx_softc *sc = (void *)arg1;
3828 struct ifnet *ifp = &sc->arpcom.ac_if;
3831 off = sc->rx_npoll_off;
3832 error = sysctl_handle_int(oidp, &off, 0, req);
3833 if (error || req->newptr == NULL)
3838 ifnet_serialize_all(ifp);
3839 if (off >= ncpus2 || off % sc->rx_ring_cnt != 0) {
3843 sc->rx_npoll_off = off;
3845 ifnet_deserialize_all(ifp);
3851 emx_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS)
3853 struct emx_softc *sc = (void *)arg1;
3854 struct ifnet *ifp = &sc->arpcom.ac_if;
3857 off = sc->tx_npoll_off;
3858 error = sysctl_handle_int(oidp, &off, 0, req);
3859 if (error || req->newptr == NULL)
3864 ifnet_serialize_all(ifp);
3865 if (off >= ncpus2 || off % sc->tx_ring_cnt != 0) {
3869 sc->tx_npoll_off = off;
3871 ifnet_deserialize_all(ifp);
3876 #endif /* IFPOLL_ENABLE */
3879 emx_dma_alloc(struct emx_softc *sc)
3884 * Create top level busdma tag
3886 error = bus_dma_tag_create(NULL, 1, 0,
3887 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR,
3889 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT,
3890 0, &sc->parent_dtag);
3892 device_printf(sc->dev, "could not create top level DMA tag\n");
3897 * Allocate transmit descriptors ring and buffers
3899 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3900 error = emx_create_tx_ring(&sc->tx_data[i]);
3902 device_printf(sc->dev,
3903 "Could not setup transmit structures\n");
3909 * Allocate receive descriptors ring and buffers
3911 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3912 error = emx_create_rx_ring(&sc->rx_data[i]);
3914 device_printf(sc->dev,
3915 "Could not setup receive structures\n");
3923 emx_dma_free(struct emx_softc *sc)
3927 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3928 emx_destroy_tx_ring(&sc->tx_data[i],
3929 sc->tx_data[i].num_tx_desc);
3932 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3933 emx_destroy_rx_ring(&sc->rx_data[i],
3934 sc->rx_data[i].num_rx_desc);
3937 /* Free top level busdma tag */
3938 if (sc->parent_dtag != NULL)
3939 bus_dma_tag_destroy(sc->parent_dtag);
3943 emx_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3945 struct emx_softc *sc = ifp->if_softc;
3947 ifnet_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, slz);
3951 emx_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3953 struct emx_softc *sc = ifp->if_softc;
3955 ifnet_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, slz);
3959 emx_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3961 struct emx_softc *sc = ifp->if_softc;
3963 return ifnet_serialize_array_try(sc->serializes, EMX_NSERIALIZE, slz);
3967 emx_serialize_skipmain(struct emx_softc *sc)
3969 lwkt_serialize_array_enter(sc->serializes, EMX_NSERIALIZE, 1);
3973 emx_deserialize_skipmain(struct emx_softc *sc)
3975 lwkt_serialize_array_exit(sc->serializes, EMX_NSERIALIZE, 1);
3981 emx_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3982 boolean_t serialized)
3984 struct emx_softc *sc = ifp->if_softc;
3986 ifnet_serialize_array_assert(sc->serializes, EMX_NSERIALIZE,
3990 #endif /* INVARIANTS */
3992 #ifdef IFPOLL_ENABLE
3995 emx_npoll_status(struct ifnet *ifp)
3997 struct emx_softc *sc = ifp->if_softc;
4000 ASSERT_SERIALIZED(&sc->main_serialize);
4002 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
4003 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
4004 callout_stop(&sc->timer);
4005 sc->hw.mac.get_link_status = 1;
4006 emx_update_link_status(sc);
4007 callout_reset(&sc->timer, hz, emx_timer, sc);
4012 emx_npoll_tx(struct ifnet *ifp, void *arg, int cycle __unused)
4014 struct emx_txdata *tdata = arg;
4016 ASSERT_SERIALIZED(&tdata->tx_serialize);
4019 if (!ifsq_is_empty(tdata->ifsq))
4020 ifsq_devstart(tdata->ifsq);
4024 emx_npoll_rx(struct ifnet *ifp __unused, void *arg, int cycle)
4026 struct emx_rxdata *rdata = arg;
4028 ASSERT_SERIALIZED(&rdata->rx_serialize);
4030 emx_rxeof(rdata, cycle);
4034 emx_npoll(struct ifnet *ifp, struct ifpoll_info *info)
4036 struct emx_softc *sc = ifp->if_softc;
4039 ASSERT_IFNET_SERIALIZED_ALL(ifp);
4044 info->ifpi_status.status_func = emx_npoll_status;
4045 info->ifpi_status.serializer = &sc->main_serialize;
4047 txr_cnt = emx_get_txring_inuse(sc, TRUE);
4048 off = sc->tx_npoll_off;
4049 for (i = 0; i < txr_cnt; ++i) {
4050 struct emx_txdata *tdata = &sc->tx_data[i];
4053 KKASSERT(idx < ncpus2);
4054 info->ifpi_tx[idx].poll_func = emx_npoll_tx;
4055 info->ifpi_tx[idx].arg = tdata;
4056 info->ifpi_tx[idx].serializer = &tdata->tx_serialize;
4057 ifsq_set_cpuid(tdata->ifsq, idx);
4060 off = sc->rx_npoll_off;
4061 for (i = 0; i < sc->rx_ring_cnt; ++i) {
4062 struct emx_rxdata *rdata = &sc->rx_data[i];
4065 KKASSERT(idx < ncpus2);
4066 info->ifpi_rx[idx].poll_func = emx_npoll_rx;
4067 info->ifpi_rx[idx].arg = rdata;
4068 info->ifpi_rx[idx].serializer = &rdata->rx_serialize;
4071 if (ifp->if_flags & IFF_RUNNING) {
4072 if (txr_cnt == sc->tx_ring_inuse)
4073 emx_disable_intr(sc);
4078 for (i = 0; i < sc->tx_ring_cnt; ++i) {
4079 struct emx_txdata *tdata = &sc->tx_data[i];
4081 ifsq_set_cpuid(tdata->ifsq,
4082 rman_get_cpuid(sc->intr_res));
4085 if (ifp->if_flags & IFF_RUNNING) {
4086 txr_cnt = emx_get_txring_inuse(sc, FALSE);
4087 if (txr_cnt == sc->tx_ring_inuse)
4088 emx_enable_intr(sc);
4095 #endif /* IFPOLL_ENABLE */
4098 emx_set_itr(struct emx_softc *sc, uint32_t itr)
4100 E1000_WRITE_REG(&sc->hw, E1000_ITR, itr);
4101 if (sc->hw.mac.type == e1000_82574) {
4105 * When using MSIX interrupts we need to
4106 * throttle using the EITR register
4108 for (i = 0; i < 4; ++i)
4109 E1000_WRITE_REG(&sc->hw, E1000_EITR_82574(i), itr);
4114 * Disable the L0s, 82574L Errata #20
4117 emx_disable_aspm(struct emx_softc *sc)
4119 uint16_t link_cap, link_ctrl, disable;
4120 uint8_t pcie_ptr, reg;
4121 device_t dev = sc->dev;
4123 switch (sc->hw.mac.type) {
4128 * 82573 specification update
4129 * errata #8 disable L0s
4130 * errata #41 disable L1
4132 * 82571/82572 specification update
4133 # errata #13 disable L1
4134 * errata #68 disable L0s
4136 disable = PCIEM_LNKCTL_ASPM_L0S | PCIEM_LNKCTL_ASPM_L1;
4141 * 82574 specification update errata #20
4143 * There is no need to disable L1
4145 disable = PCIEM_LNKCTL_ASPM_L0S;
4152 pcie_ptr = pci_get_pciecap_ptr(dev);
4156 link_cap = pci_read_config(dev, pcie_ptr + PCIER_LINKCAP, 2);
4157 if ((link_cap & PCIEM_LNKCAP_ASPM_MASK) == 0)
4161 if_printf(&sc->arpcom.ac_if, "disable ASPM %#02x\n", disable);
4163 reg = pcie_ptr + PCIER_LINKCTRL;
4164 link_ctrl = pci_read_config(dev, reg, 2);
4165 link_ctrl &= ~disable;
4166 pci_write_config(dev, reg, link_ctrl, 2);
4170 emx_tso_pullup(struct emx_txdata *tdata, struct mbuf **mp)
4172 int iphlen, hoff, thoff, ex = 0;
4177 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
4179 iphlen = m->m_pkthdr.csum_iphlen;
4180 thoff = m->m_pkthdr.csum_thlen;
4181 hoff = m->m_pkthdr.csum_lhlen;
4183 KASSERT(iphlen > 0, ("invalid ip hlen"));
4184 KASSERT(thoff > 0, ("invalid tcp hlen"));
4185 KASSERT(hoff > 0, ("invalid ether hlen"));
4187 if (tdata->tx_flags & EMX_TXFLAG_TSO_PULLEX)
4190 if (m->m_len < hoff + iphlen + thoff + ex) {
4191 m = m_pullup(m, hoff + iphlen + thoff + ex);
4198 ip = mtodoff(m, struct ip *, hoff);
4205 emx_tso_setup(struct emx_txdata *tdata, struct mbuf *mp,
4206 uint32_t *txd_upper, uint32_t *txd_lower)
4208 struct e1000_context_desc *TXD;
4209 int hoff, iphlen, thoff, hlen;
4210 int mss, pktlen, curr_txd;
4212 #ifdef EMX_TSO_DEBUG
4213 tdata->tso_segments++;
4216 iphlen = mp->m_pkthdr.csum_iphlen;
4217 thoff = mp->m_pkthdr.csum_thlen;
4218 hoff = mp->m_pkthdr.csum_lhlen;
4219 mss = mp->m_pkthdr.tso_segsz;
4220 pktlen = mp->m_pkthdr.len;
4222 if ((tdata->tx_flags & EMX_TXFLAG_FORCECTX) == 0 &&
4223 tdata->csum_flags == CSUM_TSO &&
4224 tdata->csum_iphlen == iphlen &&
4225 tdata->csum_lhlen == hoff &&
4226 tdata->csum_thlen == thoff &&
4227 tdata->csum_mss == mss &&
4228 tdata->csum_pktlen == pktlen) {
4229 *txd_upper = tdata->csum_txd_upper;
4230 *txd_lower = tdata->csum_txd_lower;
4231 #ifdef EMX_TSO_DEBUG
4232 tdata->tso_ctx_reused++;
4236 hlen = hoff + iphlen + thoff;
4239 * Setup a new TSO context.
4242 curr_txd = tdata->next_avail_tx_desc;
4243 TXD = (struct e1000_context_desc *)&tdata->tx_desc_base[curr_txd];
4245 *txd_lower = E1000_TXD_CMD_DEXT | /* Extended descr type */
4246 E1000_TXD_DTYP_D | /* Data descr type */
4247 E1000_TXD_CMD_TSE; /* Do TSE on this packet */
4249 /* IP and/or TCP header checksum calculation and insertion. */
4250 *txd_upper = (E1000_TXD_POPTS_IXSM | E1000_TXD_POPTS_TXSM) << 8;
4253 * Start offset for header checksum calculation.
4254 * End offset for header checksum calculation.
4255 * Offset of place put the checksum.
4257 TXD->lower_setup.ip_fields.ipcss = hoff;
4258 TXD->lower_setup.ip_fields.ipcse = htole16(hoff + iphlen - 1);
4259 TXD->lower_setup.ip_fields.ipcso = hoff + offsetof(struct ip, ip_sum);
4262 * Start offset for payload checksum calculation.
4263 * End offset for payload checksum calculation.
4264 * Offset of place to put the checksum.
4266 TXD->upper_setup.tcp_fields.tucss = hoff + iphlen;
4267 TXD->upper_setup.tcp_fields.tucse = 0;
4268 TXD->upper_setup.tcp_fields.tucso =
4269 hoff + iphlen + offsetof(struct tcphdr, th_sum);
4272 * Payload size per packet w/o any headers.
4273 * Length of all headers up to payload.
4275 TXD->tcp_seg_setup.fields.mss = htole16(mss);
4276 TXD->tcp_seg_setup.fields.hdr_len = hlen;
4277 TXD->cmd_and_length = htole32(E1000_TXD_CMD_IFCS |
4278 E1000_TXD_CMD_DEXT | /* Extended descr */
4279 E1000_TXD_CMD_TSE | /* TSE context */
4280 E1000_TXD_CMD_IP | /* Do IP csum */
4281 E1000_TXD_CMD_TCP | /* Do TCP checksum */
4282 (pktlen - hlen)); /* Total len */
4284 /* Save the information for this TSO context */
4285 tdata->csum_flags = CSUM_TSO;
4286 tdata->csum_lhlen = hoff;
4287 tdata->csum_iphlen = iphlen;
4288 tdata->csum_thlen = thoff;
4289 tdata->csum_mss = mss;
4290 tdata->csum_pktlen = pktlen;
4291 tdata->csum_txd_upper = *txd_upper;
4292 tdata->csum_txd_lower = *txd_lower;
4294 if (++curr_txd == tdata->num_tx_desc)
4297 KKASSERT(tdata->num_tx_desc_avail > 0);
4298 tdata->num_tx_desc_avail--;
4300 tdata->next_avail_tx_desc = curr_txd;
4305 emx_get_txring_inuse(const struct emx_softc *sc, boolean_t polling)
4308 return sc->tx_ring_cnt;