2 * Copyright (c) 2001-2011, Intel Corporation
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * 3. Neither the name of the Intel Corporation nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
32 #include "opt_ifpoll.h"
35 #include <sys/param.h>
37 #include <sys/endian.h>
38 #include <sys/interrupt.h>
39 #include <sys/kernel.h>
40 #include <sys/malloc.h>
44 #include <sys/serialize.h>
45 #include <sys/serialize2.h>
46 #include <sys/socket.h>
47 #include <sys/sockio.h>
48 #include <sys/sysctl.h>
49 #include <sys/systm.h>
52 #include <net/ethernet.h>
54 #include <net/if_arp.h>
55 #include <net/if_dl.h>
56 #include <net/if_media.h>
57 #include <net/ifq_var.h>
58 #include <net/toeplitz.h>
59 #include <net/toeplitz2.h>
60 #include <net/vlan/if_vlan_var.h>
61 #include <net/vlan/if_vlan_ether.h>
62 #include <net/if_poll.h>
64 #include <netinet/in_systm.h>
65 #include <netinet/in.h>
66 #include <netinet/ip.h>
67 #include <netinet/tcp.h>
68 #include <netinet/udp.h>
70 #include <bus/pci/pcivar.h>
71 #include <bus/pci/pcireg.h>
73 #include <dev/netif/ig_hal/e1000_api.h>
74 #include <dev/netif/ig_hal/e1000_82575.h>
75 #include <dev/netif/igb/if_igb.h>
78 #define IGB_RSS_DPRINTF(sc, lvl, fmt, ...) \
80 if (sc->rss_debug >= lvl) \
81 if_printf(&sc->arpcom.ac_if, fmt, __VA_ARGS__); \
83 #else /* !IGB_RSS_DEBUG */
84 #define IGB_RSS_DPRINTF(sc, lvl, fmt, ...) ((void)0)
85 #endif /* IGB_RSS_DEBUG */
87 #define IGB_NAME "Intel(R) PRO/1000 "
88 #define IGB_DEVICE(id) \
89 { IGB_VENDOR_ID, E1000_DEV_ID_##id, IGB_NAME #id }
90 #define IGB_DEVICE_NULL { 0, 0, NULL }
92 static struct igb_device {
97 IGB_DEVICE(82575EB_COPPER),
98 IGB_DEVICE(82575EB_FIBER_SERDES),
99 IGB_DEVICE(82575GB_QUAD_COPPER),
101 IGB_DEVICE(82576_NS),
102 IGB_DEVICE(82576_NS_SERDES),
103 IGB_DEVICE(82576_FIBER),
104 IGB_DEVICE(82576_SERDES),
105 IGB_DEVICE(82576_SERDES_QUAD),
106 IGB_DEVICE(82576_QUAD_COPPER),
107 IGB_DEVICE(82576_QUAD_COPPER_ET2),
108 IGB_DEVICE(82576_VF),
109 IGB_DEVICE(82580_COPPER),
110 IGB_DEVICE(82580_FIBER),
111 IGB_DEVICE(82580_SERDES),
112 IGB_DEVICE(82580_SGMII),
113 IGB_DEVICE(82580_COPPER_DUAL),
114 IGB_DEVICE(82580_QUAD_FIBER),
115 IGB_DEVICE(DH89XXCC_SERDES),
116 IGB_DEVICE(DH89XXCC_SGMII),
117 IGB_DEVICE(DH89XXCC_SFP),
118 IGB_DEVICE(DH89XXCC_BACKPLANE),
119 IGB_DEVICE(I350_COPPER),
120 IGB_DEVICE(I350_FIBER),
121 IGB_DEVICE(I350_SERDES),
122 IGB_DEVICE(I350_SGMII),
125 /* required last entry */
129 static int igb_probe(device_t);
130 static int igb_attach(device_t);
131 static int igb_detach(device_t);
132 static int igb_shutdown(device_t);
133 static int igb_suspend(device_t);
134 static int igb_resume(device_t);
136 static boolean_t igb_is_valid_ether_addr(const uint8_t *);
137 static void igb_setup_ifp(struct igb_softc *);
138 static boolean_t igb_txcsum_ctx(struct igb_tx_ring *, struct mbuf *);
139 static int igb_tso_pullup(struct igb_tx_ring *, struct mbuf **);
140 static void igb_tso_ctx(struct igb_tx_ring *, struct mbuf *, uint32_t *);
141 static void igb_add_sysctl(struct igb_softc *);
142 static int igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS);
143 static int igb_sysctl_msix_rate(SYSCTL_HANDLER_ARGS);
144 static int igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS);
145 static void igb_set_ring_inuse(struct igb_softc *, boolean_t);
147 static int igb_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS);
148 static int igb_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS);
151 static void igb_vf_init_stats(struct igb_softc *);
152 static void igb_reset(struct igb_softc *);
153 static void igb_update_stats_counters(struct igb_softc *);
154 static void igb_update_vf_stats_counters(struct igb_softc *);
155 static void igb_update_link_status(struct igb_softc *);
156 static void igb_init_tx_unit(struct igb_softc *);
157 static void igb_init_rx_unit(struct igb_softc *);
159 static void igb_set_vlan(struct igb_softc *);
160 static void igb_set_multi(struct igb_softc *);
161 static void igb_set_promisc(struct igb_softc *);
162 static void igb_disable_promisc(struct igb_softc *);
164 static int igb_alloc_rings(struct igb_softc *);
165 static void igb_free_rings(struct igb_softc *);
166 static int igb_create_tx_ring(struct igb_tx_ring *);
167 static int igb_create_rx_ring(struct igb_rx_ring *);
168 static void igb_free_tx_ring(struct igb_tx_ring *);
169 static void igb_free_rx_ring(struct igb_rx_ring *);
170 static void igb_destroy_tx_ring(struct igb_tx_ring *, int);
171 static void igb_destroy_rx_ring(struct igb_rx_ring *, int);
172 static void igb_init_tx_ring(struct igb_tx_ring *);
173 static int igb_init_rx_ring(struct igb_rx_ring *);
174 static int igb_newbuf(struct igb_rx_ring *, int, boolean_t);
175 static int igb_encap(struct igb_tx_ring *, struct mbuf **, int *, int *);
176 static void igb_rx_refresh(struct igb_rx_ring *, int);
178 static void igb_stop(struct igb_softc *);
179 static void igb_init(void *);
180 static int igb_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
181 static void igb_media_status(struct ifnet *, struct ifmediareq *);
182 static int igb_media_change(struct ifnet *);
183 static void igb_timer(void *);
184 static void igb_watchdog(struct ifnet *);
185 static void igb_start(struct ifnet *);
187 static void igb_npoll(struct ifnet *, struct ifpoll_info *);
188 static void igb_npoll_rx(struct ifnet *, void *, int);
189 static void igb_npoll_tx(struct ifnet *, void *, int);
190 static void igb_npoll_status(struct ifnet *);
192 static void igb_serialize(struct ifnet *, enum ifnet_serialize);
193 static void igb_deserialize(struct ifnet *, enum ifnet_serialize);
194 static int igb_tryserialize(struct ifnet *, enum ifnet_serialize);
196 static void igb_serialize_assert(struct ifnet *, enum ifnet_serialize,
200 static void igb_intr(void *);
201 static void igb_intr_shared(void *);
202 static void igb_rxeof(struct igb_rx_ring *, int);
203 static void igb_txeof(struct igb_tx_ring *);
204 static void igb_set_eitr(struct igb_softc *, int, int);
205 static void igb_enable_intr(struct igb_softc *);
206 static void igb_disable_intr(struct igb_softc *);
207 static void igb_init_unshared_intr(struct igb_softc *);
208 static void igb_init_intr(struct igb_softc *);
209 static int igb_setup_intr(struct igb_softc *);
210 static void igb_set_txintr_mask(struct igb_tx_ring *, int *, int);
211 static void igb_set_rxintr_mask(struct igb_rx_ring *, int *, int);
212 static void igb_set_intr_mask(struct igb_softc *);
213 static int igb_alloc_intr(struct igb_softc *);
214 static void igb_free_intr(struct igb_softc *);
215 static void igb_teardown_intr(struct igb_softc *);
216 static void igb_msix_try_alloc(struct igb_softc *);
217 static void igb_msix_free(struct igb_softc *, boolean_t);
218 static int igb_msix_setup(struct igb_softc *);
219 static void igb_msix_teardown(struct igb_softc *, int);
220 static void igb_msix_rx(void *);
221 static void igb_msix_tx(void *);
222 static void igb_msix_status(void *);
224 /* Management and WOL Support */
225 static void igb_get_mgmt(struct igb_softc *);
226 static void igb_rel_mgmt(struct igb_softc *);
227 static void igb_get_hw_control(struct igb_softc *);
228 static void igb_rel_hw_control(struct igb_softc *);
229 static void igb_enable_wol(device_t);
231 static device_method_t igb_methods[] = {
232 /* Device interface */
233 DEVMETHOD(device_probe, igb_probe),
234 DEVMETHOD(device_attach, igb_attach),
235 DEVMETHOD(device_detach, igb_detach),
236 DEVMETHOD(device_shutdown, igb_shutdown),
237 DEVMETHOD(device_suspend, igb_suspend),
238 DEVMETHOD(device_resume, igb_resume),
242 static driver_t igb_driver = {
245 sizeof(struct igb_softc),
248 static devclass_t igb_devclass;
250 DECLARE_DUMMY_MODULE(if_igb);
251 MODULE_DEPEND(igb, ig_hal, 1, 1, 1);
252 DRIVER_MODULE(if_igb, pci, igb_driver, igb_devclass, NULL, NULL);
254 static int igb_rxd = IGB_DEFAULT_RXD;
255 static int igb_txd = IGB_DEFAULT_TXD;
256 static int igb_rxr = 0;
257 static int igb_msi_enable = 1;
258 static int igb_msix_enable = 1;
259 static int igb_eee_disabled = 1; /* Energy Efficient Ethernet */
260 static int igb_fc_setting = e1000_fc_full;
263 * DMA Coalescing, only for i350 - default to off,
264 * this feature is for power savings
266 static int igb_dma_coalesce = 0;
268 TUNABLE_INT("hw.igb.rxd", &igb_rxd);
269 TUNABLE_INT("hw.igb.txd", &igb_txd);
270 TUNABLE_INT("hw.igb.rxr", &igb_rxr);
271 TUNABLE_INT("hw.igb.msi.enable", &igb_msi_enable);
272 TUNABLE_INT("hw.igb.msix.enable", &igb_msix_enable);
273 TUNABLE_INT("hw.igb.fc_setting", &igb_fc_setting);
276 TUNABLE_INT("hw.igb.eee_disabled", &igb_eee_disabled);
277 TUNABLE_INT("hw.igb.dma_coalesce", &igb_dma_coalesce);
280 igb_rxcsum(uint32_t staterr, struct mbuf *mp)
282 /* Ignore Checksum bit is set */
283 if (staterr & E1000_RXD_STAT_IXSM)
286 if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
288 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
290 if (staterr & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)) {
291 if ((staterr & E1000_RXDEXT_STATERR_TCPE) == 0) {
292 mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
293 CSUM_PSEUDO_HDR | CSUM_FRAG_NOT_CHECKED;
294 mp->m_pkthdr.csum_data = htons(0xffff);
299 static __inline struct pktinfo *
300 igb_rssinfo(struct mbuf *m, struct pktinfo *pi,
301 uint32_t hash, uint32_t hashtype, uint32_t staterr)
304 case E1000_RXDADV_RSSTYPE_IPV4_TCP:
305 pi->pi_netisr = NETISR_IP;
307 pi->pi_l3proto = IPPROTO_TCP;
310 case E1000_RXDADV_RSSTYPE_IPV4:
311 if (staterr & E1000_RXD_STAT_IXSM)
315 (E1000_RXD_STAT_TCPCS | E1000_RXDEXT_STATERR_TCPE)) ==
316 E1000_RXD_STAT_TCPCS) {
317 pi->pi_netisr = NETISR_IP;
319 pi->pi_l3proto = IPPROTO_UDP;
327 m->m_flags |= M_HASH;
328 m->m_pkthdr.hash = toeplitz_hash(hash);
333 igb_probe(device_t dev)
335 const struct igb_device *d;
338 vid = pci_get_vendor(dev);
339 did = pci_get_device(dev);
341 for (d = igb_devices; d->desc != NULL; ++d) {
342 if (vid == d->vid && did == d->did) {
343 device_set_desc(dev, d->desc);
351 igb_attach(device_t dev)
353 struct igb_softc *sc = device_get_softc(dev);
354 uint16_t eeprom_data;
355 int error = 0, i, j, ring_max;
357 int offset, offset_def;
362 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
363 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
364 OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
365 igb_sysctl_nvm_info, "I", "NVM Information");
366 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
367 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
368 OID_AUTO, "flow_control", CTLTYPE_INT|CTLFLAG_RW,
369 adapter, 0, igb_set_flowcntl, "I", "Flow Control");
372 callout_init_mp(&sc->timer);
373 lwkt_serialize_init(&sc->main_serialize);
375 if_initname(&sc->arpcom.ac_if, device_get_name(dev),
376 device_get_unit(dev));
377 sc->dev = sc->osdep.dev = dev;
380 * Determine hardware and mac type
382 sc->hw.vendor_id = pci_get_vendor(dev);
383 sc->hw.device_id = pci_get_device(dev);
384 sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
385 sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2);
386 sc->hw.subsystem_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
388 if (e1000_set_mac_type(&sc->hw))
391 /* Are we a VF device? */
392 if (sc->hw.mac.type == e1000_vfadapt ||
393 sc->hw.mac.type == e1000_vfadapt_i350)
399 * Configure total supported RX/TX ring count
401 switch (sc->hw.mac.type) {
403 ring_max = IGB_MAX_RING_82575;
406 ring_max = IGB_MAX_RING_82580;
409 ring_max = IGB_MAX_RING_I350;
412 ring_max = IGB_MAX_RING_82576;
415 ring_max = IGB_MIN_RING;
418 sc->rx_ring_cnt = device_getenv_int(dev, "rxr", igb_rxr);
419 sc->rx_ring_cnt = if_ring_count2(sc->rx_ring_cnt, ring_max);
421 sc->rx_ring_cnt = device_getenv_int(dev, "rxr_debug", sc->rx_ring_cnt);
423 sc->rx_ring_inuse = sc->rx_ring_cnt;
424 sc->tx_ring_cnt = 1; /* XXX */
426 if (sc->hw.mac.type == e1000_82575)
427 sc->flags |= IGB_FLAG_TSO_IPLEN0;
429 /* Enable bus mastering */
430 pci_enable_busmaster(dev);
435 sc->mem_rid = PCIR_BAR(0);
436 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
438 if (sc->mem_res == NULL) {
439 device_printf(dev, "Unable to allocate bus resource: memory\n");
443 sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->mem_res);
444 sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->mem_res);
446 sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
448 /* Save PCI command register for Shared Code */
449 sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
450 sc->hw.back = &sc->osdep;
452 /* Do Shared Code initialization */
453 if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
454 device_printf(dev, "Setup of Shared code failed\n");
459 e1000_get_bus_info(&sc->hw);
461 sc->hw.mac.autoneg = DO_AUTO_NEG;
462 sc->hw.phy.autoneg_wait_to_complete = FALSE;
463 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
466 if (sc->hw.phy.media_type == e1000_media_type_copper) {
467 sc->hw.phy.mdix = AUTO_ALL_MODES;
468 sc->hw.phy.disable_polarity_correction = FALSE;
469 sc->hw.phy.ms_type = IGB_MASTER_SLAVE;
472 /* Set the frame limits assuming standard ethernet sized frames. */
473 sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
475 /* Allocate RX/TX rings */
476 error = igb_alloc_rings(sc);
482 * NPOLLING RX CPU offset
484 if (sc->rx_ring_cnt == ncpus2) {
487 offset_def = (sc->rx_ring_cnt * device_get_unit(dev)) % ncpus2;
488 offset = device_getenv_int(dev, "npoll.rxoff", offset_def);
489 if (offset >= ncpus2 ||
490 offset % sc->rx_ring_cnt != 0) {
491 device_printf(dev, "invalid npoll.rxoff %d, use %d\n",
496 sc->rx_npoll_off = offset;
499 * NPOLLING TX CPU offset
501 offset_def = sc->rx_npoll_off;
502 offset = device_getenv_int(dev, "npoll.txoff", offset_def);
503 if (offset >= ncpus2) {
504 device_printf(dev, "invalid npoll.txoff %d, use %d\n",
508 sc->tx_npoll_off = offset;
511 /* Allocate interrupt */
512 error = igb_alloc_intr(sc);
520 sc->serializes[i++] = &sc->main_serialize;
522 sc->tx_serialize = i;
523 for (j = 0; j < sc->tx_ring_cnt; ++j)
524 sc->serializes[i++] = &sc->tx_rings[j].tx_serialize;
526 sc->rx_serialize = i;
527 for (j = 0; j < sc->rx_ring_cnt; ++j)
528 sc->serializes[i++] = &sc->rx_rings[j].rx_serialize;
530 sc->serialize_cnt = i;
531 KKASSERT(sc->serialize_cnt <= IGB_NSERIALIZE);
533 /* Allocate the appropriate stats memory */
535 sc->stats = kmalloc(sizeof(struct e1000_vf_stats), M_DEVBUF,
537 igb_vf_init_stats(sc);
539 sc->stats = kmalloc(sizeof(struct e1000_hw_stats), M_DEVBUF,
543 /* Allocate multicast array memory. */
544 sc->mta = kmalloc(ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES,
547 /* Some adapter-specific advanced features */
548 if (sc->hw.mac.type >= e1000_i350) {
550 igb_set_sysctl_value(adapter, "dma_coalesce",
551 "configure dma coalesce",
552 &adapter->dma_coalesce, igb_dma_coalesce);
553 igb_set_sysctl_value(adapter, "eee_disabled",
554 "enable Energy Efficient Ethernet",
555 &adapter->hw.dev_spec._82575.eee_disable,
558 sc->dma_coalesce = igb_dma_coalesce;
559 sc->hw.dev_spec._82575.eee_disable = igb_eee_disabled;
561 e1000_set_eee_i350(&sc->hw);
565 * Start from a known state, this is important in reading the nvm and
568 e1000_reset_hw(&sc->hw);
570 /* Make sure we have a good EEPROM before we read from it */
571 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
573 * Some PCI-E parts fail the first check due to
574 * the link being in sleep state, call it again,
575 * if it fails a second time its a real issue.
577 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
579 "The EEPROM Checksum Is Not Valid\n");
585 /* Copy the permanent MAC address out of the EEPROM */
586 if (e1000_read_mac_addr(&sc->hw) < 0) {
587 device_printf(dev, "EEPROM read error while reading MAC"
592 if (!igb_is_valid_ether_addr(sc->hw.mac.addr)) {
593 device_printf(dev, "Invalid MAC address\n");
598 /* Setup OS specific network interface */
601 /* Add sysctl tree, must after igb_setup_ifp() */
604 /* Now get a good starting state */
607 /* Initialize statistics */
608 igb_update_stats_counters(sc);
610 sc->hw.mac.get_link_status = 1;
611 igb_update_link_status(sc);
613 /* Indicate SOL/IDER usage */
614 if (e1000_check_reset_block(&sc->hw)) {
616 "PHY reset is blocked due to SOL/IDER session.\n");
619 /* Determine if we have to control management hardware */
620 if (e1000_enable_mng_pass_thru(&sc->hw))
621 sc->flags |= IGB_FLAG_HAS_MGMT;
626 /* APME bit in EEPROM is mapped to WUC.APME */
627 eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC) & E1000_WUC_APME;
629 sc->wol = E1000_WUFC_MAG;
630 /* XXX disable WOL */
634 /* Register for VLAN events */
635 adapter->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
636 igb_register_vlan, adapter, EVENTHANDLER_PRI_FIRST);
637 adapter->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
638 igb_unregister_vlan, adapter, EVENTHANDLER_PRI_FIRST);
642 igb_add_hw_stats(adapter);
645 error = igb_setup_intr(sc);
647 ether_ifdetach(&sc->arpcom.ac_if);
658 igb_detach(device_t dev)
660 struct igb_softc *sc = device_get_softc(dev);
662 if (device_is_attached(dev)) {
663 struct ifnet *ifp = &sc->arpcom.ac_if;
665 ifnet_serialize_all(ifp);
669 e1000_phy_hw_reset(&sc->hw);
671 /* Give control back to firmware */
673 igb_rel_hw_control(sc);
676 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
677 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
681 igb_teardown_intr(sc);
683 ifnet_deserialize_all(ifp);
686 } else if (sc->mem_res != NULL) {
687 igb_rel_hw_control(sc);
689 bus_generic_detach(dev);
691 if (sc->sysctl_tree != NULL)
692 sysctl_ctx_free(&sc->sysctl_ctx);
696 if (sc->msix_mem_res != NULL) {
697 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_mem_rid,
700 if (sc->mem_res != NULL) {
701 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid,
708 kfree(sc->mta, M_DEVBUF);
709 if (sc->stats != NULL)
710 kfree(sc->stats, M_DEVBUF);
716 igb_shutdown(device_t dev)
718 return igb_suspend(dev);
722 igb_suspend(device_t dev)
724 struct igb_softc *sc = device_get_softc(dev);
725 struct ifnet *ifp = &sc->arpcom.ac_if;
727 ifnet_serialize_all(ifp);
732 igb_rel_hw_control(sc);
735 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
736 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
740 ifnet_deserialize_all(ifp);
742 return bus_generic_suspend(dev);
746 igb_resume(device_t dev)
748 struct igb_softc *sc = device_get_softc(dev);
749 struct ifnet *ifp = &sc->arpcom.ac_if;
751 ifnet_serialize_all(ifp);
758 ifnet_deserialize_all(ifp);
760 return bus_generic_resume(dev);
764 igb_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
766 struct igb_softc *sc = ifp->if_softc;
767 struct ifreq *ifr = (struct ifreq *)data;
768 int max_frame_size, mask, reinit;
771 ASSERT_IFNET_SERIALIZED_ALL(ifp);
775 max_frame_size = 9234;
776 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
782 ifp->if_mtu = ifr->ifr_mtu;
783 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
786 if (ifp->if_flags & IFF_RUNNING)
791 if (ifp->if_flags & IFF_UP) {
792 if (ifp->if_flags & IFF_RUNNING) {
793 if ((ifp->if_flags ^ sc->if_flags) &
794 (IFF_PROMISC | IFF_ALLMULTI)) {
795 igb_disable_promisc(sc);
801 } else if (ifp->if_flags & IFF_RUNNING) {
804 sc->if_flags = ifp->if_flags;
809 if (ifp->if_flags & IFF_RUNNING) {
810 igb_disable_intr(sc);
813 if (!(ifp->if_flags & IFF_NPOLLING))
821 * As the speed/duplex settings are being
822 * changed, we need toreset the PHY.
824 sc->hw.phy.reset_disable = FALSE;
826 /* Check SOL/IDER usage */
827 if (e1000_check_reset_block(&sc->hw)) {
828 if_printf(ifp, "Media change is "
829 "blocked due to SOL/IDER session.\n");
835 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
840 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
841 if (mask & IFCAP_RXCSUM) {
842 ifp->if_capenable ^= IFCAP_RXCSUM;
845 if (mask & IFCAP_VLAN_HWTAGGING) {
846 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
849 if (mask & IFCAP_TXCSUM) {
850 ifp->if_capenable ^= IFCAP_TXCSUM;
851 if (ifp->if_capenable & IFCAP_TXCSUM)
852 ifp->if_hwassist |= IGB_CSUM_FEATURES;
854 ifp->if_hwassist &= ~IGB_CSUM_FEATURES;
856 if (mask & IFCAP_TSO) {
857 ifp->if_capenable ^= IFCAP_TSO;
858 if (ifp->if_capenable & IFCAP_TSO)
859 ifp->if_hwassist |= CSUM_TSO;
861 ifp->if_hwassist &= ~CSUM_TSO;
863 if (mask & IFCAP_RSS)
864 ifp->if_capenable ^= IFCAP_RSS;
865 if (reinit && (ifp->if_flags & IFF_RUNNING))
870 error = ether_ioctl(ifp, command, data);
879 struct igb_softc *sc = xsc;
880 struct ifnet *ifp = &sc->arpcom.ac_if;
884 ASSERT_IFNET_SERIALIZED_ALL(ifp);
888 /* Get the latest mac address, User can use a LAA */
889 bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
891 /* Put the address into the Receive Address Array */
892 e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
895 igb_update_link_status(sc);
897 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
899 /* Configure for OS presence */
904 if (ifp->if_flags & IFF_NPOLLING)
908 /* Configured used RX/TX rings */
909 igb_set_ring_inuse(sc, polling);
911 /* Initialize interrupt */
914 /* Prepare transmit descriptors and buffers */
915 for (i = 0; i < sc->tx_ring_cnt; ++i)
916 igb_init_tx_ring(&sc->tx_rings[i]);
917 igb_init_tx_unit(sc);
919 /* Setup Multicast table */
924 * Figure out the desired mbuf pool
925 * for doing jumbo/packetsplit
927 if (adapter->max_frame_size <= 2048)
928 adapter->rx_mbuf_sz = MCLBYTES;
929 else if (adapter->max_frame_size <= 4096)
930 adapter->rx_mbuf_sz = MJUMPAGESIZE;
932 adapter->rx_mbuf_sz = MJUM9BYTES;
935 /* Prepare receive descriptors and buffers */
936 for (i = 0; i < sc->rx_ring_inuse; ++i) {
939 error = igb_init_rx_ring(&sc->rx_rings[i]);
941 if_printf(ifp, "Could not setup receive structures\n");
946 igb_init_rx_unit(sc);
948 /* Enable VLAN support */
949 if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
952 /* Don't lose promiscuous settings */
955 ifp->if_flags |= IFF_RUNNING;
956 ifp->if_flags &= ~IFF_OACTIVE;
958 if (polling || sc->intr_type == PCI_INTR_TYPE_MSIX)
959 sc->timer_cpuid = 0; /* XXX fixed */
961 sc->timer_cpuid = rman_get_cpuid(sc->intr_res);
962 callout_reset_bycpu(&sc->timer, hz, igb_timer, sc, sc->timer_cpuid);
963 e1000_clear_hw_cntrs_base_generic(&sc->hw);
965 /* This clears any pending interrupts */
966 E1000_READ_REG(&sc->hw, E1000_ICR);
969 * Only enable interrupts if we are not polling, make sure
970 * they are off otherwise.
973 igb_disable_intr(sc);
976 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC);
979 /* Set Energy Efficient Ethernet */
980 e1000_set_eee_i350(&sc->hw);
982 /* Don't reset the phy next time init gets called */
983 sc->hw.phy.reset_disable = TRUE;
987 igb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
989 struct igb_softc *sc = ifp->if_softc;
990 u_char fiber_type = IFM_1000_SX;
992 ASSERT_IFNET_SERIALIZED_ALL(ifp);
994 igb_update_link_status(sc);
996 ifmr->ifm_status = IFM_AVALID;
997 ifmr->ifm_active = IFM_ETHER;
999 if (!sc->link_active)
1002 ifmr->ifm_status |= IFM_ACTIVE;
1004 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1005 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1006 ifmr->ifm_active |= fiber_type | IFM_FDX;
1008 switch (sc->link_speed) {
1010 ifmr->ifm_active |= IFM_10_T;
1014 ifmr->ifm_active |= IFM_100_TX;
1018 ifmr->ifm_active |= IFM_1000_T;
1021 if (sc->link_duplex == FULL_DUPLEX)
1022 ifmr->ifm_active |= IFM_FDX;
1024 ifmr->ifm_active |= IFM_HDX;
1029 igb_media_change(struct ifnet *ifp)
1031 struct igb_softc *sc = ifp->if_softc;
1032 struct ifmedia *ifm = &sc->media;
1034 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1036 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
1039 switch (IFM_SUBTYPE(ifm->ifm_media)) {
1041 sc->hw.mac.autoneg = DO_AUTO_NEG;
1042 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
1048 sc->hw.mac.autoneg = DO_AUTO_NEG;
1049 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
1053 sc->hw.mac.autoneg = FALSE;
1054 sc->hw.phy.autoneg_advertised = 0;
1055 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1056 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
1058 sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
1062 sc->hw.mac.autoneg = FALSE;
1063 sc->hw.phy.autoneg_advertised = 0;
1064 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
1065 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
1067 sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
1071 if_printf(ifp, "Unsupported media type\n");
1081 igb_set_promisc(struct igb_softc *sc)
1083 struct ifnet *ifp = &sc->arpcom.ac_if;
1084 struct e1000_hw *hw = &sc->hw;
1088 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
1092 reg = E1000_READ_REG(hw, E1000_RCTL);
1093 if (ifp->if_flags & IFF_PROMISC) {
1094 reg |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
1095 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1096 } else if (ifp->if_flags & IFF_ALLMULTI) {
1097 reg |= E1000_RCTL_MPE;
1098 reg &= ~E1000_RCTL_UPE;
1099 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1104 igb_disable_promisc(struct igb_softc *sc)
1106 struct e1000_hw *hw = &sc->hw;
1110 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
1113 reg = E1000_READ_REG(hw, E1000_RCTL);
1114 reg &= ~E1000_RCTL_UPE;
1115 reg &= ~E1000_RCTL_MPE;
1116 E1000_WRITE_REG(hw, E1000_RCTL, reg);
1120 igb_set_multi(struct igb_softc *sc)
1122 struct ifnet *ifp = &sc->arpcom.ac_if;
1123 struct ifmultiaddr *ifma;
1124 uint32_t reg_rctl = 0;
1129 bzero(mta, ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
1131 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1132 if (ifma->ifma_addr->sa_family != AF_LINK)
1135 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
1138 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
1139 &mta[mcnt * ETH_ADDR_LEN], ETH_ADDR_LEN);
1143 if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1144 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1145 reg_rctl |= E1000_RCTL_MPE;
1146 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1148 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1153 igb_timer(void *xsc)
1155 struct igb_softc *sc = xsc;
1157 lwkt_serialize_enter(&sc->main_serialize);
1159 igb_update_link_status(sc);
1160 igb_update_stats_counters(sc);
1162 callout_reset_bycpu(&sc->timer, hz, igb_timer, sc, sc->timer_cpuid);
1164 lwkt_serialize_exit(&sc->main_serialize);
1168 igb_update_link_status(struct igb_softc *sc)
1170 struct ifnet *ifp = &sc->arpcom.ac_if;
1171 struct e1000_hw *hw = &sc->hw;
1172 uint32_t link_check, thstat, ctrl;
1174 link_check = thstat = ctrl = 0;
1176 /* Get the cached link value or read for real */
1177 switch (hw->phy.media_type) {
1178 case e1000_media_type_copper:
1179 if (hw->mac.get_link_status) {
1180 /* Do the work to read phy */
1181 e1000_check_for_link(hw);
1182 link_check = !hw->mac.get_link_status;
1188 case e1000_media_type_fiber:
1189 e1000_check_for_link(hw);
1190 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1193 case e1000_media_type_internal_serdes:
1194 e1000_check_for_link(hw);
1195 link_check = hw->mac.serdes_has_link;
1198 /* VF device is type_unknown */
1199 case e1000_media_type_unknown:
1200 e1000_check_for_link(hw);
1201 link_check = !hw->mac.get_link_status;
1207 /* Check for thermal downshift or shutdown */
1208 if (hw->mac.type == e1000_i350) {
1209 thstat = E1000_READ_REG(hw, E1000_THSTAT);
1210 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1213 /* Now we check if a transition has happened */
1214 if (link_check && sc->link_active == 0) {
1215 e1000_get_speed_and_duplex(hw,
1216 &sc->link_speed, &sc->link_duplex);
1218 if_printf(ifp, "Link is up %d Mbps %s\n",
1220 sc->link_duplex == FULL_DUPLEX ?
1221 "Full Duplex" : "Half Duplex");
1223 sc->link_active = 1;
1225 ifp->if_baudrate = sc->link_speed * 1000000;
1226 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1227 (thstat & E1000_THSTAT_LINK_THROTTLE))
1228 if_printf(ifp, "Link: thermal downshift\n");
1229 /* This can sleep */
1230 ifp->if_link_state = LINK_STATE_UP;
1231 if_link_state_change(ifp);
1232 } else if (!link_check && sc->link_active == 1) {
1233 ifp->if_baudrate = sc->link_speed = 0;
1234 sc->link_duplex = 0;
1236 if_printf(ifp, "Link is Down\n");
1237 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1238 (thstat & E1000_THSTAT_PWR_DOWN))
1239 if_printf(ifp, "Link: thermal shutdown\n");
1240 sc->link_active = 0;
1241 /* This can sleep */
1242 ifp->if_link_state = LINK_STATE_DOWN;
1243 if_link_state_change(ifp);
1248 igb_stop(struct igb_softc *sc)
1250 struct ifnet *ifp = &sc->arpcom.ac_if;
1253 ASSERT_IFNET_SERIALIZED_ALL(ifp);
1255 igb_disable_intr(sc);
1257 callout_stop(&sc->timer);
1259 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1262 e1000_reset_hw(&sc->hw);
1263 E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1265 e1000_led_off(&sc->hw);
1266 e1000_cleanup_led(&sc->hw);
1268 for (i = 0; i < sc->tx_ring_cnt; ++i)
1269 igb_free_tx_ring(&sc->tx_rings[i]);
1270 for (i = 0; i < sc->rx_ring_cnt; ++i)
1271 igb_free_rx_ring(&sc->rx_rings[i]);
1275 igb_reset(struct igb_softc *sc)
1277 struct ifnet *ifp = &sc->arpcom.ac_if;
1278 struct e1000_hw *hw = &sc->hw;
1279 struct e1000_fc_info *fc = &hw->fc;
1283 /* Let the firmware know the OS is in control */
1284 igb_get_hw_control(sc);
1287 * Packet Buffer Allocation (PBA)
1288 * Writing PBA sets the receive portion of the buffer
1289 * the remainder is used for the transmit buffer.
1291 switch (hw->mac.type) {
1293 pba = E1000_PBA_32K;
1298 pba = E1000_READ_REG(hw, E1000_RXPBS);
1299 pba &= E1000_RXPBS_SIZE_MASK_82576;
1304 case e1000_vfadapt_i350:
1305 pba = E1000_READ_REG(hw, E1000_RXPBS);
1306 pba = e1000_rxpbs_adjust_82580(pba);
1308 /* XXX pba = E1000_PBA_35K; */
1314 /* Special needs in case of Jumbo frames */
1315 if (hw->mac.type == e1000_82575 && ifp->if_mtu > ETHERMTU) {
1316 uint32_t tx_space, min_tx, min_rx;
1318 pba = E1000_READ_REG(hw, E1000_PBA);
1319 tx_space = pba >> 16;
1322 min_tx = (sc->max_frame_size +
1323 sizeof(struct e1000_tx_desc) - ETHER_CRC_LEN) * 2;
1324 min_tx = roundup2(min_tx, 1024);
1326 min_rx = sc->max_frame_size;
1327 min_rx = roundup2(min_rx, 1024);
1329 if (tx_space < min_tx && (min_tx - tx_space) < pba) {
1330 pba = pba - (min_tx - tx_space);
1332 * if short on rx space, rx wins
1333 * and must trump tx adjustment
1338 E1000_WRITE_REG(hw, E1000_PBA, pba);
1342 * These parameters control the automatic generation (Tx) and
1343 * response (Rx) to Ethernet PAUSE frames.
1344 * - High water mark should allow for at least two frames to be
1345 * received after sending an XOFF.
1346 * - Low water mark works best when it is very near the high water mark.
1347 * This allows the receiver to restart by sending XON when it has
1350 hwm = min(((pba << 10) * 9 / 10),
1351 ((pba << 10) - 2 * sc->max_frame_size));
1353 if (hw->mac.type < e1000_82576) {
1354 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1355 fc->low_water = fc->high_water - 8;
1357 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1358 fc->low_water = fc->high_water - 16;
1360 fc->pause_time = IGB_FC_PAUSE_TIME;
1361 fc->send_xon = TRUE;
1363 /* Issue a global reset */
1365 E1000_WRITE_REG(hw, E1000_WUC, 0);
1367 if (e1000_init_hw(hw) < 0)
1368 if_printf(ifp, "Hardware Initialization Failed\n");
1370 /* Setup DMA Coalescing */
1371 if (hw->mac.type == e1000_i350 && sc->dma_coalesce) {
1374 hwm = (pba - 4) << 10;
1375 reg = ((pba - 6) << E1000_DMACR_DMACTHR_SHIFT)
1376 & E1000_DMACR_DMACTHR_MASK;
1378 /* transition to L0x or L1 if available..*/
1379 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
1381 /* timer = +-1000 usec in 32usec intervals */
1383 E1000_WRITE_REG(hw, E1000_DMACR, reg);
1385 /* No lower threshold */
1386 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
1388 /* set hwm to PBA - 2 * max frame size */
1389 E1000_WRITE_REG(hw, E1000_FCRTC, hwm);
1391 /* Set the interval before transition */
1392 reg = E1000_READ_REG(hw, E1000_DMCTLX);
1393 reg |= 0x800000FF; /* 255 usec */
1394 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
1396 /* free space in tx packet buffer to wake from DMA coal */
1397 E1000_WRITE_REG(hw, E1000_DMCTXTH,
1398 (20480 - (2 * sc->max_frame_size)) >> 6);
1400 /* make low power state decision controlled by DMA coal */
1401 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
1402 E1000_WRITE_REG(hw, E1000_PCIEMISC,
1403 reg | E1000_PCIEMISC_LX_DECISION);
1404 if_printf(ifp, "DMA Coalescing enabled\n");
1407 E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1408 e1000_get_phy_info(hw);
1409 e1000_check_for_link(hw);
1413 igb_setup_ifp(struct igb_softc *sc)
1415 struct ifnet *ifp = &sc->arpcom.ac_if;
1418 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1419 ifp->if_init = igb_init;
1420 ifp->if_ioctl = igb_ioctl;
1421 ifp->if_start = igb_start;
1422 ifp->if_serialize = igb_serialize;
1423 ifp->if_deserialize = igb_deserialize;
1424 ifp->if_tryserialize = igb_tryserialize;
1426 ifp->if_serialize_assert = igb_serialize_assert;
1428 #ifdef IFPOLL_ENABLE
1429 ifp->if_npoll = igb_npoll;
1431 ifp->if_watchdog = igb_watchdog;
1433 ifq_set_maxlen(&ifp->if_snd, sc->tx_rings[0].num_tx_desc - 1);
1434 ifq_set_ready(&ifp->if_snd);
1436 ether_ifattach(ifp, sc->hw.mac.addr, NULL);
1438 ifp->if_capabilities =
1439 IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_TSO;
1440 if (IGB_ENABLE_HWRSS(sc))
1441 ifp->if_capabilities |= IFCAP_RSS;
1442 ifp->if_capenable = ifp->if_capabilities;
1443 ifp->if_hwassist = IGB_CSUM_FEATURES | CSUM_TSO;
1446 * Tell the upper layer(s) we support long frames
1448 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1451 * Specify the media types supported by this adapter and register
1452 * callbacks to update media and link information
1454 ifmedia_init(&sc->media, IFM_IMASK, igb_media_change, igb_media_status);
1455 if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1456 sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1457 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1459 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1461 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1462 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1464 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1465 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1467 if (sc->hw.phy.type != e1000_phy_ife) {
1468 ifmedia_add(&sc->media,
1469 IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1470 ifmedia_add(&sc->media,
1471 IFM_ETHER | IFM_1000_T, 0, NULL);
1474 ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1475 ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1479 igb_add_sysctl(struct igb_softc *sc)
1484 sysctl_ctx_init(&sc->sysctl_ctx);
1485 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
1486 SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1487 device_get_nameunit(sc->dev), CTLFLAG_RD, 0, "");
1488 if (sc->sysctl_tree == NULL) {
1489 device_printf(sc->dev, "can't add sysctl node\n");
1493 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1494 OID_AUTO, "rxr", CTLFLAG_RD, &sc->rx_ring_cnt, 0, "# of RX rings");
1495 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1496 OID_AUTO, "rxr_inuse", CTLFLAG_RD, &sc->rx_ring_inuse, 0,
1497 "# of RX rings used");
1498 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1499 OID_AUTO, "rxd", CTLFLAG_RD, &sc->rx_rings[0].num_rx_desc, 0,
1501 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1502 OID_AUTO, "txd", CTLFLAG_RD, &sc->tx_rings[0].num_tx_desc, 0,
1505 if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
1506 SYSCTL_ADD_PROC(&sc->sysctl_ctx,
1507 SYSCTL_CHILDREN(sc->sysctl_tree),
1508 OID_AUTO, "intr_rate", CTLTYPE_INT | CTLFLAG_RW,
1509 sc, 0, igb_sysctl_intr_rate, "I", "interrupt rate");
1511 for (i = 0; i < sc->msix_cnt; ++i) {
1512 struct igb_msix_data *msix = &sc->msix_data[i];
1514 ksnprintf(node, sizeof(node), "msix%d_rate", i);
1515 SYSCTL_ADD_PROC(&sc->sysctl_ctx,
1516 SYSCTL_CHILDREN(sc->sysctl_tree),
1517 OID_AUTO, node, CTLTYPE_INT | CTLFLAG_RW,
1518 msix, 0, igb_sysctl_msix_rate, "I",
1519 msix->msix_rate_desc);
1523 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1524 OID_AUTO, "tx_intr_nsegs", CTLTYPE_INT | CTLFLAG_RW,
1525 sc, 0, igb_sysctl_tx_intr_nsegs, "I",
1526 "# of segments per TX interrupt");
1528 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1529 OID_AUTO, "tx_wreg_nsegs", CTLFLAG_RW,
1530 &sc->tx_rings[0].wreg_nsegs, 0,
1531 "# of segments before write to hardare register");
1533 #ifdef IFPOLL_ENABLE
1534 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1535 OID_AUTO, "npoll_rxoff", CTLTYPE_INT|CTLFLAG_RW,
1536 sc, 0, igb_sysctl_npoll_rxoff, "I", "NPOLLING RX cpu offset");
1537 SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1538 OID_AUTO, "npoll_txoff", CTLTYPE_INT|CTLFLAG_RW,
1539 sc, 0, igb_sysctl_npoll_txoff, "I", "NPOLLING TX cpu offset");
1542 #ifdef IGB_RSS_DEBUG
1543 SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1544 OID_AUTO, "rss_debug", CTLFLAG_RW, &sc->rss_debug, 0,
1547 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1548 #ifdef IGB_RSS_DEBUG
1549 ksnprintf(node, sizeof(node), "rx%d_pkt", i);
1550 SYSCTL_ADD_ULONG(&sc->sysctl_ctx,
1551 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, node,
1552 CTLFLAG_RW, &sc->rx_rings[i].rx_packets, "RXed packets");
1554 ksnprintf(node, sizeof(node), "rx%d_wreg", i);
1555 SYSCTL_ADD_INT(&sc->sysctl_ctx,
1556 SYSCTL_CHILDREN(sc->sysctl_tree), OID_AUTO, node,
1557 CTLFLAG_RW, &sc->rx_rings[i].rx_wreg, 0,
1558 "# of segments before write to hardare register");
1563 igb_alloc_rings(struct igb_softc *sc)
1568 * Create top level busdma tag
1570 error = bus_dma_tag_create(NULL, 1, 0,
1571 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1572 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
1575 device_printf(sc->dev, "could not create top level DMA tag\n");
1580 * Allocate TX descriptor rings and buffers
1582 sc->tx_rings = kmalloc_cachealign(
1583 sizeof(struct igb_tx_ring) * sc->tx_ring_cnt,
1584 M_DEVBUF, M_WAITOK | M_ZERO);
1585 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1586 struct igb_tx_ring *txr = &sc->tx_rings[i];
1588 /* Set up some basics */
1591 lwkt_serialize_init(&txr->tx_serialize);
1593 error = igb_create_tx_ring(txr);
1599 * Allocate RX descriptor rings and buffers
1601 sc->rx_rings = kmalloc_cachealign(
1602 sizeof(struct igb_rx_ring) * sc->rx_ring_cnt,
1603 M_DEVBUF, M_WAITOK | M_ZERO);
1604 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1605 struct igb_rx_ring *rxr = &sc->rx_rings[i];
1607 /* Set up some basics */
1610 lwkt_serialize_init(&rxr->rx_serialize);
1612 error = igb_create_rx_ring(rxr);
1621 igb_free_rings(struct igb_softc *sc)
1625 if (sc->tx_rings != NULL) {
1626 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1627 struct igb_tx_ring *txr = &sc->tx_rings[i];
1629 igb_destroy_tx_ring(txr, txr->num_tx_desc);
1631 kfree(sc->tx_rings, M_DEVBUF);
1634 if (sc->rx_rings != NULL) {
1635 for (i = 0; i < sc->rx_ring_cnt; ++i) {
1636 struct igb_rx_ring *rxr = &sc->rx_rings[i];
1638 igb_destroy_rx_ring(rxr, rxr->num_rx_desc);
1640 kfree(sc->rx_rings, M_DEVBUF);
1645 igb_create_tx_ring(struct igb_tx_ring *txr)
1647 int tsize, error, i, ntxd;
1650 * Validate number of transmit descriptors. It must not exceed
1651 * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
1653 ntxd = device_getenv_int(txr->sc->dev, "txd", igb_txd);
1654 if ((ntxd * sizeof(struct e1000_tx_desc)) % IGB_DBA_ALIGN != 0 ||
1655 ntxd > IGB_MAX_TXD || ntxd < IGB_MIN_TXD) {
1656 device_printf(txr->sc->dev,
1657 "Using %d TX descriptors instead of %d!\n",
1658 IGB_DEFAULT_TXD, ntxd);
1659 txr->num_tx_desc = IGB_DEFAULT_TXD;
1661 txr->num_tx_desc = ntxd;
1665 * Allocate TX descriptor ring
1667 tsize = roundup2(txr->num_tx_desc * sizeof(union e1000_adv_tx_desc),
1669 txr->txdma.dma_vaddr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1670 IGB_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
1671 &txr->txdma.dma_tag, &txr->txdma.dma_map, &txr->txdma.dma_paddr);
1672 if (txr->txdma.dma_vaddr == NULL) {
1673 device_printf(txr->sc->dev,
1674 "Unable to allocate TX Descriptor memory\n");
1677 txr->tx_base = txr->txdma.dma_vaddr;
1678 bzero(txr->tx_base, tsize);
1680 tsize = __VM_CACHELINE_ALIGN(
1681 sizeof(struct igb_tx_buf) * txr->num_tx_desc);
1682 txr->tx_buf = kmalloc_cachealign(tsize, M_DEVBUF, M_WAITOK | M_ZERO);
1685 * Allocate TX head write-back buffer
1687 txr->tx_hdr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1688 __VM_CACHELINE_SIZE, __VM_CACHELINE_SIZE, BUS_DMA_WAITOK,
1689 &txr->tx_hdr_dtag, &txr->tx_hdr_dmap, &txr->tx_hdr_paddr);
1690 if (txr->tx_hdr == NULL) {
1691 device_printf(txr->sc->dev,
1692 "Unable to allocate TX head write-back buffer\n");
1697 * Create DMA tag for TX buffers
1699 error = bus_dma_tag_create(txr->sc->parent_tag,
1700 1, 0, /* alignment, bounds */
1701 BUS_SPACE_MAXADDR, /* lowaddr */
1702 BUS_SPACE_MAXADDR, /* highaddr */
1703 NULL, NULL, /* filter, filterarg */
1704 IGB_TSO_SIZE, /* maxsize */
1705 IGB_MAX_SCATTER, /* nsegments */
1706 PAGE_SIZE, /* maxsegsize */
1707 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
1708 BUS_DMA_ONEBPAGE, /* flags */
1711 device_printf(txr->sc->dev, "Unable to allocate TX DMA tag\n");
1712 kfree(txr->tx_buf, M_DEVBUF);
1718 * Create DMA maps for TX buffers
1720 for (i = 0; i < txr->num_tx_desc; ++i) {
1721 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1723 error = bus_dmamap_create(txr->tx_tag,
1724 BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, &txbuf->map);
1726 device_printf(txr->sc->dev,
1727 "Unable to create TX DMA map\n");
1728 igb_destroy_tx_ring(txr, i);
1734 * Initialize various watermark
1736 txr->spare_desc = IGB_TX_SPARE;
1737 txr->intr_nsegs = txr->num_tx_desc / 16;
1738 txr->wreg_nsegs = 8;
1739 txr->oact_hi_desc = txr->num_tx_desc / 2;
1740 txr->oact_lo_desc = txr->num_tx_desc / 8;
1741 if (txr->oact_lo_desc > IGB_TX_OACTIVE_MAX)
1742 txr->oact_lo_desc = IGB_TX_OACTIVE_MAX;
1743 if (txr->oact_lo_desc < txr->spare_desc + IGB_TX_RESERVED)
1744 txr->oact_lo_desc = txr->spare_desc + IGB_TX_RESERVED;
1750 igb_free_tx_ring(struct igb_tx_ring *txr)
1754 for (i = 0; i < txr->num_tx_desc; ++i) {
1755 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1757 if (txbuf->m_head != NULL) {
1758 bus_dmamap_unload(txr->tx_tag, txbuf->map);
1759 m_freem(txbuf->m_head);
1760 txbuf->m_head = NULL;
1766 igb_destroy_tx_ring(struct igb_tx_ring *txr, int ndesc)
1770 if (txr->txdma.dma_vaddr != NULL) {
1771 bus_dmamap_unload(txr->txdma.dma_tag, txr->txdma.dma_map);
1772 bus_dmamem_free(txr->txdma.dma_tag, txr->txdma.dma_vaddr,
1773 txr->txdma.dma_map);
1774 bus_dma_tag_destroy(txr->txdma.dma_tag);
1775 txr->txdma.dma_vaddr = NULL;
1778 if (txr->tx_hdr != NULL) {
1779 bus_dmamap_unload(txr->tx_hdr_dtag, txr->tx_hdr_dmap);
1780 bus_dmamem_free(txr->tx_hdr_dtag, txr->tx_hdr,
1782 bus_dma_tag_destroy(txr->tx_hdr_dtag);
1786 if (txr->tx_buf == NULL)
1789 for (i = 0; i < ndesc; ++i) {
1790 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1792 KKASSERT(txbuf->m_head == NULL);
1793 bus_dmamap_destroy(txr->tx_tag, txbuf->map);
1795 bus_dma_tag_destroy(txr->tx_tag);
1797 kfree(txr->tx_buf, M_DEVBUF);
1802 igb_init_tx_ring(struct igb_tx_ring *txr)
1804 /* Clear the old descriptor contents */
1806 sizeof(union e1000_adv_tx_desc) * txr->num_tx_desc);
1808 /* Clear TX head write-back buffer */
1812 txr->next_avail_desc = 0;
1813 txr->next_to_clean = 0;
1816 /* Set number of descriptors available */
1817 txr->tx_avail = txr->num_tx_desc;
1821 igb_init_tx_unit(struct igb_softc *sc)
1823 struct e1000_hw *hw = &sc->hw;
1827 /* Setup the Tx Descriptor Rings */
1828 for (i = 0; i < sc->tx_ring_cnt; ++i) {
1829 struct igb_tx_ring *txr = &sc->tx_rings[i];
1830 uint64_t bus_addr = txr->txdma.dma_paddr;
1831 uint64_t hdr_paddr = txr->tx_hdr_paddr;
1832 uint32_t txdctl = 0;
1833 uint32_t dca_txctrl;
1835 E1000_WRITE_REG(hw, E1000_TDLEN(i),
1836 txr->num_tx_desc * sizeof(struct e1000_tx_desc));
1837 E1000_WRITE_REG(hw, E1000_TDBAH(i),
1838 (uint32_t)(bus_addr >> 32));
1839 E1000_WRITE_REG(hw, E1000_TDBAL(i),
1840 (uint32_t)bus_addr);
1842 /* Setup the HW Tx Head and Tail descriptor pointers */
1843 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
1844 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
1846 dca_txctrl = E1000_READ_REG(hw, E1000_DCA_TXCTRL(i));
1847 dca_txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1848 E1000_WRITE_REG(hw, E1000_DCA_TXCTRL(i), dca_txctrl);
1851 * Don't set WB_on_EITR:
1852 * - 82575 does not have it
1853 * - It almost has no effect on 82576, see:
1854 * 82576 specification update errata #26
1855 * - It causes unnecessary bus traffic
1857 E1000_WRITE_REG(hw, E1000_TDWBAH(i),
1858 (uint32_t)(hdr_paddr >> 32));
1859 E1000_WRITE_REG(hw, E1000_TDWBAL(i),
1860 ((uint32_t)hdr_paddr) | E1000_TX_HEAD_WB_ENABLE);
1863 * WTHRESH is ignored by the hardware, since header
1864 * write back mode is used.
1866 txdctl |= IGB_TX_PTHRESH;
1867 txdctl |= IGB_TX_HTHRESH << 8;
1868 txdctl |= IGB_TX_WTHRESH << 16;
1869 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1870 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
1876 e1000_config_collision_dist(hw);
1878 /* Program the Transmit Control Register */
1879 tctl = E1000_READ_REG(hw, E1000_TCTL);
1880 tctl &= ~E1000_TCTL_CT;
1881 tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
1882 (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
1884 /* This write will effectively turn on the transmit unit. */
1885 E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1889 igb_txcsum_ctx(struct igb_tx_ring *txr, struct mbuf *mp)
1891 struct e1000_adv_tx_context_desc *TXD;
1892 uint32_t vlan_macip_lens, type_tucmd_mlhl, mss_l4len_idx;
1893 int ehdrlen, ctxd, ip_hlen = 0;
1894 boolean_t offload = TRUE;
1896 if ((mp->m_pkthdr.csum_flags & IGB_CSUM_FEATURES) == 0)
1899 vlan_macip_lens = type_tucmd_mlhl = mss_l4len_idx = 0;
1901 ctxd = txr->next_avail_desc;
1902 TXD = (struct e1000_adv_tx_context_desc *)&txr->tx_base[ctxd];
1905 * In advanced descriptors the vlan tag must
1906 * be placed into the context descriptor, thus
1907 * we need to be here just for that setup.
1909 if (mp->m_flags & M_VLANTAG) {
1912 vlantag = htole16(mp->m_pkthdr.ether_vlantag);
1913 vlan_macip_lens |= (vlantag << E1000_ADVTXD_VLAN_SHIFT);
1914 } else if (!offload) {
1918 ehdrlen = mp->m_pkthdr.csum_lhlen;
1919 KASSERT(ehdrlen > 0, ("invalid ether hlen"));
1921 /* Set the ether header length */
1922 vlan_macip_lens |= ehdrlen << E1000_ADVTXD_MACLEN_SHIFT;
1923 if (mp->m_pkthdr.csum_flags & CSUM_IP) {
1924 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4;
1925 ip_hlen = mp->m_pkthdr.csum_iphlen;
1926 KASSERT(ip_hlen > 0, ("invalid ip hlen"));
1928 vlan_macip_lens |= ip_hlen;
1930 type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
1931 if (mp->m_pkthdr.csum_flags & CSUM_TCP)
1932 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP;
1933 else if (mp->m_pkthdr.csum_flags & CSUM_UDP)
1934 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_UDP;
1936 /* 82575 needs the queue index added */
1937 if (txr->sc->hw.mac.type == e1000_82575)
1938 mss_l4len_idx = txr->me << 4;
1940 /* Now copy bits into descriptor */
1941 TXD->vlan_macip_lens = htole32(vlan_macip_lens);
1942 TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
1943 TXD->seqnum_seed = htole32(0);
1944 TXD->mss_l4len_idx = htole32(mss_l4len_idx);
1946 /* We've consumed the first desc, adjust counters */
1947 if (++ctxd == txr->num_tx_desc)
1949 txr->next_avail_desc = ctxd;
1956 igb_txeof(struct igb_tx_ring *txr)
1958 struct ifnet *ifp = &txr->sc->arpcom.ac_if;
1959 int first, hdr, avail;
1961 if (txr->tx_avail == txr->num_tx_desc)
1964 first = txr->next_to_clean;
1965 hdr = *(txr->tx_hdr);
1970 avail = txr->tx_avail;
1971 while (first != hdr) {
1972 struct igb_tx_buf *txbuf = &txr->tx_buf[first];
1975 if (txbuf->m_head) {
1976 bus_dmamap_unload(txr->tx_tag, txbuf->map);
1977 m_freem(txbuf->m_head);
1978 txbuf->m_head = NULL;
1981 if (++first == txr->num_tx_desc)
1984 txr->next_to_clean = first;
1985 txr->tx_avail = avail;
1988 * If we have a minimum free, clear IFF_OACTIVE
1989 * to tell the stack that it is OK to send packets.
1991 if (IGB_IS_NOT_OACTIVE(txr)) {
1992 ifp->if_flags &= ~IFF_OACTIVE;
1995 * We have enough TX descriptors, turn off
1996 * the watchdog. We allow small amount of
1997 * packets (roughly intr_nsegs) pending on
1998 * the transmit ring.
2005 igb_create_rx_ring(struct igb_rx_ring *rxr)
2007 int rsize, i, error, nrxd;
2010 * Validate number of receive descriptors. It must not exceed
2011 * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
2013 nrxd = device_getenv_int(rxr->sc->dev, "rxd", igb_rxd);
2014 if ((nrxd * sizeof(struct e1000_rx_desc)) % IGB_DBA_ALIGN != 0 ||
2015 nrxd > IGB_MAX_RXD || nrxd < IGB_MIN_RXD) {
2016 device_printf(rxr->sc->dev,
2017 "Using %d RX descriptors instead of %d!\n",
2018 IGB_DEFAULT_RXD, nrxd);
2019 rxr->num_rx_desc = IGB_DEFAULT_RXD;
2021 rxr->num_rx_desc = nrxd;
2025 * Allocate RX descriptor ring
2027 rsize = roundup2(rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc),
2029 rxr->rxdma.dma_vaddr = bus_dmamem_coherent_any(rxr->sc->parent_tag,
2030 IGB_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
2031 &rxr->rxdma.dma_tag, &rxr->rxdma.dma_map,
2032 &rxr->rxdma.dma_paddr);
2033 if (rxr->rxdma.dma_vaddr == NULL) {
2034 device_printf(rxr->sc->dev,
2035 "Unable to allocate RxDescriptor memory\n");
2038 rxr->rx_base = rxr->rxdma.dma_vaddr;
2039 bzero(rxr->rx_base, rsize);
2041 rsize = __VM_CACHELINE_ALIGN(
2042 sizeof(struct igb_rx_buf) * rxr->num_rx_desc);
2043 rxr->rx_buf = kmalloc_cachealign(rsize, M_DEVBUF, M_WAITOK | M_ZERO);
2046 * Create DMA tag for RX buffers
2048 error = bus_dma_tag_create(rxr->sc->parent_tag,
2049 1, 0, /* alignment, bounds */
2050 BUS_SPACE_MAXADDR, /* lowaddr */
2051 BUS_SPACE_MAXADDR, /* highaddr */
2052 NULL, NULL, /* filter, filterarg */
2053 MCLBYTES, /* maxsize */
2055 MCLBYTES, /* maxsegsize */
2056 BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
2059 device_printf(rxr->sc->dev,
2060 "Unable to create RX payload DMA tag\n");
2061 kfree(rxr->rx_buf, M_DEVBUF);
2067 * Create spare DMA map for RX buffers
2069 error = bus_dmamap_create(rxr->rx_tag, BUS_DMA_WAITOK,
2072 device_printf(rxr->sc->dev,
2073 "Unable to create spare RX DMA maps\n");
2074 bus_dma_tag_destroy(rxr->rx_tag);
2075 kfree(rxr->rx_buf, M_DEVBUF);
2081 * Create DMA maps for RX buffers
2083 for (i = 0; i < rxr->num_rx_desc; i++) {
2084 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2086 error = bus_dmamap_create(rxr->rx_tag,
2087 BUS_DMA_WAITOK, &rxbuf->map);
2089 device_printf(rxr->sc->dev,
2090 "Unable to create RX DMA maps\n");
2091 igb_destroy_rx_ring(rxr, i);
2097 * Initialize various watermark
2105 igb_free_rx_ring(struct igb_rx_ring *rxr)
2109 for (i = 0; i < rxr->num_rx_desc; ++i) {
2110 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2112 if (rxbuf->m_head != NULL) {
2113 bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2114 m_freem(rxbuf->m_head);
2115 rxbuf->m_head = NULL;
2119 if (rxr->fmp != NULL)
2126 igb_destroy_rx_ring(struct igb_rx_ring *rxr, int ndesc)
2130 if (rxr->rxdma.dma_vaddr != NULL) {
2131 bus_dmamap_unload(rxr->rxdma.dma_tag, rxr->rxdma.dma_map);
2132 bus_dmamem_free(rxr->rxdma.dma_tag, rxr->rxdma.dma_vaddr,
2133 rxr->rxdma.dma_map);
2134 bus_dma_tag_destroy(rxr->rxdma.dma_tag);
2135 rxr->rxdma.dma_vaddr = NULL;
2138 if (rxr->rx_buf == NULL)
2141 for (i = 0; i < ndesc; ++i) {
2142 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2144 KKASSERT(rxbuf->m_head == NULL);
2145 bus_dmamap_destroy(rxr->rx_tag, rxbuf->map);
2147 bus_dmamap_destroy(rxr->rx_tag, rxr->rx_sparemap);
2148 bus_dma_tag_destroy(rxr->rx_tag);
2150 kfree(rxr->rx_buf, M_DEVBUF);
2155 igb_setup_rxdesc(union e1000_adv_rx_desc *rxd, const struct igb_rx_buf *rxbuf)
2157 rxd->read.pkt_addr = htole64(rxbuf->paddr);
2158 rxd->wb.upper.status_error = 0;
2162 igb_newbuf(struct igb_rx_ring *rxr, int i, boolean_t wait)
2165 bus_dma_segment_t seg;
2167 struct igb_rx_buf *rxbuf;
2170 m = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
2173 if_printf(&rxr->sc->arpcom.ac_if,
2174 "Unable to allocate RX mbuf\n");
2178 m->m_len = m->m_pkthdr.len = MCLBYTES;
2180 if (rxr->sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2181 m_adj(m, ETHER_ALIGN);
2183 error = bus_dmamap_load_mbuf_segment(rxr->rx_tag,
2184 rxr->rx_sparemap, m, &seg, 1, &nseg, BUS_DMA_NOWAIT);
2188 if_printf(&rxr->sc->arpcom.ac_if,
2189 "Unable to load RX mbuf\n");
2194 rxbuf = &rxr->rx_buf[i];
2195 if (rxbuf->m_head != NULL)
2196 bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2199 rxbuf->map = rxr->rx_sparemap;
2200 rxr->rx_sparemap = map;
2203 rxbuf->paddr = seg.ds_addr;
2205 igb_setup_rxdesc(&rxr->rx_base[i], rxbuf);
2210 igb_init_rx_ring(struct igb_rx_ring *rxr)
2214 /* Clear the ring contents */
2216 rxr->num_rx_desc * sizeof(union e1000_adv_rx_desc));
2218 /* Now replenish the ring mbufs */
2219 for (i = 0; i < rxr->num_rx_desc; ++i) {
2222 error = igb_newbuf(rxr, i, TRUE);
2227 /* Setup our descriptor indices */
2228 rxr->next_to_check = 0;
2232 rxr->discard = FALSE;
2238 igb_init_rx_unit(struct igb_softc *sc)
2240 struct ifnet *ifp = &sc->arpcom.ac_if;
2241 struct e1000_hw *hw = &sc->hw;
2242 uint32_t rctl, rxcsum, srrctl = 0;
2246 * Make sure receives are disabled while setting
2247 * up the descriptor ring
2249 rctl = E1000_READ_REG(hw, E1000_RCTL);
2250 E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2254 ** Set up for header split
2256 if (igb_header_split) {
2257 /* Use a standard mbuf for the header */
2258 srrctl |= IGB_HDR_BUF << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2259 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2262 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2265 ** Set up for jumbo frames
2267 if (ifp->if_mtu > ETHERMTU) {
2268 rctl |= E1000_RCTL_LPE;
2270 if (adapter->rx_mbuf_sz == MJUMPAGESIZE) {
2271 srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2272 rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
2273 } else if (adapter->rx_mbuf_sz > MJUMPAGESIZE) {
2274 srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2275 rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
2277 /* Set maximum packet len */
2278 psize = adapter->max_frame_size;
2279 /* are we on a vlan? */
2280 if (adapter->ifp->if_vlantrunk != NULL)
2281 psize += VLAN_TAG_SIZE;
2282 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize);
2284 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2285 rctl |= E1000_RCTL_SZ_2048;
2288 rctl &= ~E1000_RCTL_LPE;
2289 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2290 rctl |= E1000_RCTL_SZ_2048;
2293 /* Setup the Base and Length of the Rx Descriptor Rings */
2294 for (i = 0; i < sc->rx_ring_inuse; ++i) {
2295 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2296 uint64_t bus_addr = rxr->rxdma.dma_paddr;
2299 E1000_WRITE_REG(hw, E1000_RDLEN(i),
2300 rxr->num_rx_desc * sizeof(struct e1000_rx_desc));
2301 E1000_WRITE_REG(hw, E1000_RDBAH(i),
2302 (uint32_t)(bus_addr >> 32));
2303 E1000_WRITE_REG(hw, E1000_RDBAL(i),
2304 (uint32_t)bus_addr);
2305 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
2306 /* Enable this Queue */
2307 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
2308 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2309 rxdctl &= 0xFFF00000;
2310 rxdctl |= IGB_RX_PTHRESH;
2311 rxdctl |= IGB_RX_HTHRESH << 8;
2313 * Don't set WTHRESH to a value above 1 on 82576, see:
2314 * 82576 specification update errata #26
2316 rxdctl |= IGB_RX_WTHRESH << 16;
2317 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
2320 rxcsum = E1000_READ_REG(&sc->hw, E1000_RXCSUM);
2321 rxcsum &= ~(E1000_RXCSUM_PCSS_MASK | E1000_RXCSUM_IPPCSE);
2324 * Receive Checksum Offload for TCP and UDP
2326 * Checksum offloading is also enabled if multiple receive
2327 * queue is to be supported, since we need it to figure out
2330 if ((ifp->if_capenable & IFCAP_RXCSUM) || IGB_ENABLE_HWRSS(sc)) {
2333 * PCSD must be enabled to enable multiple
2336 rxcsum |= E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2339 rxcsum &= ~(E1000_RXCSUM_IPOFL | E1000_RXCSUM_TUOFL |
2342 E1000_WRITE_REG(&sc->hw, E1000_RXCSUM, rxcsum);
2344 if (IGB_ENABLE_HWRSS(sc)) {
2345 uint8_t key[IGB_NRSSRK * IGB_RSSRK_SIZE];
2346 uint32_t reta_shift;
2351 * When we reach here, RSS has already been disabled
2352 * in igb_stop(), so we could safely configure RSS key
2353 * and redirect table.
2359 toeplitz_get_key(key, sizeof(key));
2360 for (i = 0; i < IGB_NRSSRK; ++i) {
2363 rssrk = IGB_RSSRK_VAL(key, i);
2364 IGB_RSS_DPRINTF(sc, 1, "rssrk%d 0x%08x\n", i, rssrk);
2366 E1000_WRITE_REG(hw, E1000_RSSRK(i), rssrk);
2370 * Configure RSS redirect table in following fashion:
2371 * (hash & ring_cnt_mask) == rdr_table[(hash & rdr_table_mask)]
2373 reta_shift = IGB_RETA_SHIFT;
2374 if (hw->mac.type == e1000_82575)
2375 reta_shift = IGB_RETA_SHIFT_82575;
2378 for (j = 0; j < IGB_NRETA; ++j) {
2381 for (i = 0; i < IGB_RETA_SIZE; ++i) {
2384 q = (r % sc->rx_ring_inuse) << reta_shift;
2385 reta |= q << (8 * i);
2388 IGB_RSS_DPRINTF(sc, 1, "reta 0x%08x\n", reta);
2389 E1000_WRITE_REG(hw, E1000_RETA(j), reta);
2393 * Enable multiple receive queues.
2394 * Enable IPv4 RSS standard hash functions.
2395 * Disable RSS interrupt on 82575
2397 E1000_WRITE_REG(&sc->hw, E1000_MRQC,
2398 E1000_MRQC_ENABLE_RSS_4Q |
2399 E1000_MRQC_RSS_FIELD_IPV4_TCP |
2400 E1000_MRQC_RSS_FIELD_IPV4);
2403 /* Setup the Receive Control Register */
2404 rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2405 rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2406 E1000_RCTL_RDMTS_HALF |
2407 (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2408 /* Strip CRC bytes. */
2409 rctl |= E1000_RCTL_SECRC;
2410 /* Make sure VLAN Filters are off */
2411 rctl &= ~E1000_RCTL_VFE;
2412 /* Don't store bad packets */
2413 rctl &= ~E1000_RCTL_SBP;
2415 /* Enable Receives */
2416 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2419 * Setup the HW Rx Head and Tail Descriptor Pointers
2420 * - needs to be after enable
2422 for (i = 0; i < sc->rx_ring_inuse; ++i) {
2423 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2425 E1000_WRITE_REG(hw, E1000_RDH(i), rxr->next_to_check);
2426 E1000_WRITE_REG(hw, E1000_RDT(i), rxr->num_rx_desc - 1);
2431 igb_rx_refresh(struct igb_rx_ring *rxr, int i)
2434 i = rxr->num_rx_desc - 1;
2435 E1000_WRITE_REG(&rxr->sc->hw, E1000_RDT(rxr->me), i);
2439 igb_rxeof(struct igb_rx_ring *rxr, int count)
2441 struct ifnet *ifp = &rxr->sc->arpcom.ac_if;
2442 union e1000_adv_rx_desc *cur;
2446 i = rxr->next_to_check;
2447 cur = &rxr->rx_base[i];
2448 staterr = le32toh(cur->wb.upper.status_error);
2450 if ((staterr & E1000_RXD_STAT_DD) == 0)
2453 while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
2454 struct pktinfo *pi = NULL, pi0;
2455 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2456 struct mbuf *m = NULL;
2459 eop = (staterr & E1000_RXD_STAT_EOP) ? TRUE : FALSE;
2464 if ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) == 0 &&
2466 struct mbuf *mp = rxbuf->m_head;
2467 uint32_t hash, hashtype;
2471 len = le16toh(cur->wb.upper.length);
2472 if (rxr->sc->hw.mac.type == e1000_i350 &&
2473 (staterr & E1000_RXDEXT_STATERR_LB))
2474 vlan = be16toh(cur->wb.upper.vlan);
2476 vlan = le16toh(cur->wb.upper.vlan);
2478 hash = le32toh(cur->wb.lower.hi_dword.rss);
2479 hashtype = le32toh(cur->wb.lower.lo_dword.data) &
2480 E1000_RXDADV_RSSTYPE_MASK;
2482 IGB_RSS_DPRINTF(rxr->sc, 10,
2483 "ring%d, hash 0x%08x, hashtype %u\n",
2484 rxr->me, hash, hashtype);
2486 bus_dmamap_sync(rxr->rx_tag, rxbuf->map,
2487 BUS_DMASYNC_POSTREAD);
2489 if (igb_newbuf(rxr, i, FALSE) != 0) {
2495 if (rxr->fmp == NULL) {
2496 mp->m_pkthdr.len = len;
2500 rxr->lmp->m_next = mp;
2501 rxr->lmp = rxr->lmp->m_next;
2502 rxr->fmp->m_pkthdr.len += len;
2510 m->m_pkthdr.rcvif = ifp;
2513 if (ifp->if_capenable & IFCAP_RXCSUM)
2514 igb_rxcsum(staterr, m);
2516 if (staterr & E1000_RXD_STAT_VP) {
2517 m->m_pkthdr.ether_vlantag = vlan;
2518 m->m_flags |= M_VLANTAG;
2521 if (ifp->if_capenable & IFCAP_RSS) {
2522 pi = igb_rssinfo(m, &pi0,
2523 hash, hashtype, staterr);
2525 #ifdef IGB_RSS_DEBUG
2532 igb_setup_rxdesc(cur, rxbuf);
2534 rxr->discard = TRUE;
2536 rxr->discard = FALSE;
2537 if (rxr->fmp != NULL) {
2546 ether_input_pkt(ifp, m, pi);
2548 /* Advance our pointers to the next descriptor. */
2549 if (++i == rxr->num_rx_desc)
2552 if (ncoll > rxr->rx_wreg) {
2553 igb_rx_refresh(rxr, i);
2557 cur = &rxr->rx_base[i];
2558 staterr = le32toh(cur->wb.upper.status_error);
2560 rxr->next_to_check = i;
2563 igb_rx_refresh(rxr, i);
2568 igb_set_vlan(struct igb_softc *sc)
2570 struct e1000_hw *hw = &sc->hw;
2573 struct ifnet *ifp = sc->arpcom.ac_if;
2577 e1000_rlpml_set_vf(hw, sc->max_frame_size + VLAN_TAG_SIZE);
2581 reg = E1000_READ_REG(hw, E1000_CTRL);
2582 reg |= E1000_CTRL_VME;
2583 E1000_WRITE_REG(hw, E1000_CTRL, reg);
2586 /* Enable the Filter Table */
2587 if (ifp->if_capenable & IFCAP_VLAN_HWFILTER) {
2588 reg = E1000_READ_REG(hw, E1000_RCTL);
2589 reg &= ~E1000_RCTL_CFIEN;
2590 reg |= E1000_RCTL_VFE;
2591 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2595 /* Update the frame size */
2596 E1000_WRITE_REG(&sc->hw, E1000_RLPML,
2597 sc->max_frame_size + VLAN_TAG_SIZE);
2600 /* Don't bother with table if no vlans */
2601 if ((adapter->num_vlans == 0) ||
2602 ((ifp->if_capenable & IFCAP_VLAN_HWFILTER) == 0))
2605 ** A soft reset zero's out the VFTA, so
2606 ** we need to repopulate it now.
2608 for (int i = 0; i < IGB_VFTA_SIZE; i++)
2609 if (adapter->shadow_vfta[i] != 0) {
2610 if (adapter->vf_ifp)
2611 e1000_vfta_set_vf(hw,
2612 adapter->shadow_vfta[i], TRUE);
2614 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,
2615 i, adapter->shadow_vfta[i]);
2621 igb_enable_intr(struct igb_softc *sc)
2623 if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
2624 lwkt_serialize_handler_enable(&sc->main_serialize);
2628 for (i = 0; i < sc->msix_cnt; ++i) {
2629 lwkt_serialize_handler_enable(
2630 sc->msix_data[i].msix_serialize);
2634 if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
2635 if (sc->intr_type == PCI_INTR_TYPE_MSIX)
2636 E1000_WRITE_REG(&sc->hw, E1000_EIAC, sc->intr_mask);
2638 E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2639 E1000_WRITE_REG(&sc->hw, E1000_EIAM, sc->intr_mask);
2640 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
2641 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC);
2643 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
2645 E1000_WRITE_FLUSH(&sc->hw);
2649 igb_disable_intr(struct igb_softc *sc)
2651 if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0) {
2652 E1000_WRITE_REG(&sc->hw, E1000_EIMC, 0xffffffff);
2653 E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2655 E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
2656 E1000_WRITE_FLUSH(&sc->hw);
2658 if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
2659 lwkt_serialize_handler_disable(&sc->main_serialize);
2663 for (i = 0; i < sc->msix_cnt; ++i) {
2664 lwkt_serialize_handler_disable(
2665 sc->msix_data[i].msix_serialize);
2671 * Bit of a misnomer, what this really means is
2672 * to enable OS management of the system... aka
2673 * to disable special hardware management features
2676 igb_get_mgmt(struct igb_softc *sc)
2678 if (sc->flags & IGB_FLAG_HAS_MGMT) {
2679 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
2680 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2682 /* disable hardware interception of ARP */
2683 manc &= ~E1000_MANC_ARP_EN;
2685 /* enable receiving management packets to the host */
2686 manc |= E1000_MANC_EN_MNG2HOST;
2687 manc2h |= 1 << 5; /* Mng Port 623 */
2688 manc2h |= 1 << 6; /* Mng Port 664 */
2689 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
2690 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2695 * Give control back to hardware management controller
2699 igb_rel_mgmt(struct igb_softc *sc)
2701 if (sc->flags & IGB_FLAG_HAS_MGMT) {
2702 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2704 /* Re-enable hardware interception of ARP */
2705 manc |= E1000_MANC_ARP_EN;
2706 manc &= ~E1000_MANC_EN_MNG2HOST;
2708 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2713 * Sets CTRL_EXT:DRV_LOAD bit.
2715 * For ASF and Pass Through versions of f/w this means that
2716 * the driver is loaded.
2719 igb_get_hw_control(struct igb_softc *sc)
2726 /* Let firmware know the driver has taken over */
2727 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2728 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2729 ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2733 * Resets CTRL_EXT:DRV_LOAD bit.
2735 * For ASF and Pass Through versions of f/w this means that the
2736 * driver is no longer loaded.
2739 igb_rel_hw_control(struct igb_softc *sc)
2746 /* Let firmware taken over control of h/w */
2747 ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2748 E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2749 ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2753 igb_is_valid_ether_addr(const uint8_t *addr)
2755 uint8_t zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
2757 if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
2763 * Enable PCI Wake On Lan capability
2766 igb_enable_wol(device_t dev)
2768 uint16_t cap, status;
2771 /* First find the capabilities pointer*/
2772 cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
2774 /* Read the PM Capabilities */
2775 id = pci_read_config(dev, cap, 1);
2776 if (id != PCIY_PMG) /* Something wrong */
2780 * OK, we have the power capabilities,
2781 * so now get the status register
2783 cap += PCIR_POWER_STATUS;
2784 status = pci_read_config(dev, cap, 2);
2785 status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2786 pci_write_config(dev, cap, status, 2);
2790 igb_update_stats_counters(struct igb_softc *sc)
2792 struct e1000_hw *hw = &sc->hw;
2793 struct e1000_hw_stats *stats;
2794 struct ifnet *ifp = &sc->arpcom.ac_if;
2797 * The virtual function adapter has only a
2798 * small controlled set of stats, do only
2802 igb_update_vf_stats_counters(sc);
2807 if (sc->hw.phy.media_type == e1000_media_type_copper ||
2808 (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
2810 E1000_READ_REG(hw,E1000_SYMERRS);
2811 stats->sec += E1000_READ_REG(hw, E1000_SEC);
2814 stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
2815 stats->mpc += E1000_READ_REG(hw, E1000_MPC);
2816 stats->scc += E1000_READ_REG(hw, E1000_SCC);
2817 stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
2819 stats->mcc += E1000_READ_REG(hw, E1000_MCC);
2820 stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
2821 stats->colc += E1000_READ_REG(hw, E1000_COLC);
2822 stats->dc += E1000_READ_REG(hw, E1000_DC);
2823 stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
2824 stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
2825 stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
2828 * For watchdog management we need to know if we have been
2829 * paused during the last interval, so capture that here.
2831 sc->pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
2832 stats->xoffrxc += sc->pause_frames;
2833 stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
2834 stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
2835 stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
2836 stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
2837 stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
2838 stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
2839 stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
2840 stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
2841 stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
2842 stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
2843 stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
2844 stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
2846 /* For the 64-bit byte counters the low dword must be read first. */
2847 /* Both registers clear on the read of the high dword */
2849 stats->gorc += E1000_READ_REG(hw, E1000_GORCL) +
2850 ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
2851 stats->gotc += E1000_READ_REG(hw, E1000_GOTCL) +
2852 ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
2854 stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
2855 stats->ruc += E1000_READ_REG(hw, E1000_RUC);
2856 stats->rfc += E1000_READ_REG(hw, E1000_RFC);
2857 stats->roc += E1000_READ_REG(hw, E1000_ROC);
2858 stats->rjc += E1000_READ_REG(hw, E1000_RJC);
2860 stats->tor += E1000_READ_REG(hw, E1000_TORH);
2861 stats->tot += E1000_READ_REG(hw, E1000_TOTH);
2863 stats->tpr += E1000_READ_REG(hw, E1000_TPR);
2864 stats->tpt += E1000_READ_REG(hw, E1000_TPT);
2865 stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
2866 stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
2867 stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
2868 stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
2869 stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
2870 stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
2871 stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
2872 stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
2874 /* Interrupt Counts */
2876 stats->iac += E1000_READ_REG(hw, E1000_IAC);
2877 stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
2878 stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
2879 stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
2880 stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
2881 stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
2882 stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
2883 stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
2884 stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
2886 /* Host to Card Statistics */
2888 stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
2889 stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
2890 stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
2891 stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
2892 stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
2893 stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
2894 stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
2895 stats->hgorc += (E1000_READ_REG(hw, E1000_HGORCL) +
2896 ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32));
2897 stats->hgotc += (E1000_READ_REG(hw, E1000_HGOTCL) +
2898 ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32));
2899 stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
2900 stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
2901 stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
2903 stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
2904 stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
2905 stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
2906 stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
2907 stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
2908 stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
2910 ifp->if_collisions = stats->colc;
2913 ifp->if_ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
2914 stats->ruc + stats->roc + stats->mpc + stats->cexterr;
2917 ifp->if_oerrors = stats->ecol + stats->latecol + sc->watchdog_events;
2919 /* Driver specific counters */
2920 sc->device_control = E1000_READ_REG(hw, E1000_CTRL);
2921 sc->rx_control = E1000_READ_REG(hw, E1000_RCTL);
2922 sc->int_mask = E1000_READ_REG(hw, E1000_IMS);
2923 sc->eint_mask = E1000_READ_REG(hw, E1000_EIMS);
2924 sc->packet_buf_alloc_tx =
2925 ((E1000_READ_REG(hw, E1000_PBA) & 0xffff0000) >> 16);
2926 sc->packet_buf_alloc_rx =
2927 (E1000_READ_REG(hw, E1000_PBA) & 0xffff);
2931 igb_vf_init_stats(struct igb_softc *sc)
2933 struct e1000_hw *hw = &sc->hw;
2934 struct e1000_vf_stats *stats;
2937 stats->last_gprc = E1000_READ_REG(hw, E1000_VFGPRC);
2938 stats->last_gorc = E1000_READ_REG(hw, E1000_VFGORC);
2939 stats->last_gptc = E1000_READ_REG(hw, E1000_VFGPTC);
2940 stats->last_gotc = E1000_READ_REG(hw, E1000_VFGOTC);
2941 stats->last_mprc = E1000_READ_REG(hw, E1000_VFMPRC);
2945 igb_update_vf_stats_counters(struct igb_softc *sc)
2947 struct e1000_hw *hw = &sc->hw;
2948 struct e1000_vf_stats *stats;
2950 if (sc->link_speed == 0)
2954 UPDATE_VF_REG(E1000_VFGPRC, stats->last_gprc, stats->gprc);
2955 UPDATE_VF_REG(E1000_VFGORC, stats->last_gorc, stats->gorc);
2956 UPDATE_VF_REG(E1000_VFGPTC, stats->last_gptc, stats->gptc);
2957 UPDATE_VF_REG(E1000_VFGOTC, stats->last_gotc, stats->gotc);
2958 UPDATE_VF_REG(E1000_VFMPRC, stats->last_mprc, stats->mprc);
2961 #ifdef IFPOLL_ENABLE
2964 igb_npoll_status(struct ifnet *ifp)
2966 struct igb_softc *sc = ifp->if_softc;
2969 ASSERT_SERIALIZED(&sc->main_serialize);
2971 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
2972 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
2973 sc->hw.mac.get_link_status = 1;
2974 igb_update_link_status(sc);
2979 igb_npoll_tx(struct ifnet *ifp, void *arg, int cycle __unused)
2981 struct igb_tx_ring *txr = arg;
2983 ASSERT_SERIALIZED(&txr->tx_serialize);
2986 if (!ifq_is_empty(&ifp->if_snd))
2991 igb_npoll_rx(struct ifnet *ifp __unused, void *arg, int cycle)
2993 struct igb_rx_ring *rxr = arg;
2995 ASSERT_SERIALIZED(&rxr->rx_serialize);
2997 igb_rxeof(rxr, cycle);
3001 igb_npoll(struct ifnet *ifp, struct ifpoll_info *info)
3003 struct igb_softc *sc = ifp->if_softc;
3005 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3008 struct igb_tx_ring *txr;
3011 info->ifpi_status.status_func = igb_npoll_status;
3012 info->ifpi_status.serializer = &sc->main_serialize;
3014 off = sc->tx_npoll_off;
3015 KKASSERT(off < ncpus2);
3016 txr = &sc->tx_rings[0];
3017 info->ifpi_tx[off].poll_func = igb_npoll_tx;
3018 info->ifpi_tx[off].arg = txr;
3019 info->ifpi_tx[off].serializer = &txr->tx_serialize;
3021 off = sc->rx_npoll_off;
3022 for (i = 0; i < sc->rx_ring_cnt; ++i) {
3023 struct igb_rx_ring *rxr = &sc->rx_rings[i];
3026 KKASSERT(idx < ncpus2);
3027 info->ifpi_rx[idx].poll_func = igb_npoll_rx;
3028 info->ifpi_rx[idx].arg = rxr;
3029 info->ifpi_rx[idx].serializer = &rxr->rx_serialize;
3032 if (ifp->if_flags & IFF_RUNNING) {
3033 if (sc->rx_ring_inuse == sc->rx_ring_cnt)
3034 igb_disable_intr(sc);
3038 ifp->if_npoll_cpuid = sc->tx_npoll_off;
3040 if (ifp->if_flags & IFF_RUNNING) {
3041 if (sc->rx_ring_inuse == sc->rx_ring_cnt)
3042 igb_enable_intr(sc);
3046 ifp->if_npoll_cpuid = -1;
3050 #endif /* IFPOLL_ENABLE */
3055 struct igb_softc *sc = xsc;
3056 struct ifnet *ifp = &sc->arpcom.ac_if;
3059 ASSERT_SERIALIZED(&sc->main_serialize);
3061 eicr = E1000_READ_REG(&sc->hw, E1000_EICR);
3066 if (ifp->if_flags & IFF_RUNNING) {
3067 struct igb_tx_ring *txr;
3070 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3071 struct igb_rx_ring *rxr = &sc->rx_rings[i];
3073 if (eicr & rxr->rx_intr_mask) {
3074 lwkt_serialize_enter(&rxr->rx_serialize);
3076 lwkt_serialize_exit(&rxr->rx_serialize);
3080 txr = &sc->tx_rings[0];
3081 if (eicr & txr->tx_intr_mask) {
3082 lwkt_serialize_enter(&txr->tx_serialize);
3084 if (!ifq_is_empty(&ifp->if_snd))
3086 lwkt_serialize_exit(&txr->tx_serialize);
3090 if (eicr & E1000_EICR_OTHER) {
3091 uint32_t icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3093 /* Link status change */
3094 if (icr & E1000_ICR_LSC) {
3095 sc->hw.mac.get_link_status = 1;
3096 igb_update_link_status(sc);
3101 * Reading EICR has the side effect to clear interrupt mask,
3102 * so all interrupts need to be enabled here.
3104 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->intr_mask);
3108 igb_intr_shared(void *xsc)
3110 struct igb_softc *sc = xsc;
3111 struct ifnet *ifp = &sc->arpcom.ac_if;
3114 ASSERT_SERIALIZED(&sc->main_serialize);
3116 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
3119 if (reg_icr == 0xffffffff)
3122 /* Definitely not our interrupt. */
3126 if ((reg_icr & E1000_ICR_INT_ASSERTED) == 0)
3129 if (ifp->if_flags & IFF_RUNNING) {
3131 (E1000_ICR_RXT0 | E1000_ICR_RXDMT0 | E1000_ICR_RXO)) {
3134 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3135 struct igb_rx_ring *rxr = &sc->rx_rings[i];
3137 lwkt_serialize_enter(&rxr->rx_serialize);
3139 lwkt_serialize_exit(&rxr->rx_serialize);
3143 if (reg_icr & E1000_ICR_TXDW) {
3144 struct igb_tx_ring *txr = &sc->tx_rings[0];
3146 lwkt_serialize_enter(&txr->tx_serialize);
3148 if (!ifq_is_empty(&ifp->if_snd))
3150 lwkt_serialize_exit(&txr->tx_serialize);
3154 /* Link status change */
3155 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
3156 sc->hw.mac.get_link_status = 1;
3157 igb_update_link_status(sc);
3160 if (reg_icr & E1000_ICR_RXO)
3165 igb_encap(struct igb_tx_ring *txr, struct mbuf **m_headp,
3166 int *segs_used, int *idx)
3168 bus_dma_segment_t segs[IGB_MAX_SCATTER];
3170 struct igb_tx_buf *tx_buf, *tx_buf_mapped;
3171 union e1000_adv_tx_desc *txd = NULL;
3172 struct mbuf *m_head = *m_headp;
3173 uint32_t olinfo_status = 0, cmd_type_len = 0, cmd_rs = 0;
3174 int maxsegs, nsegs, i, j, error, last = 0;
3175 uint32_t hdrlen = 0;
3177 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3178 error = igb_tso_pullup(txr, m_headp);
3184 /* Set basic descriptor constants */
3185 cmd_type_len |= E1000_ADVTXD_DTYP_DATA;
3186 cmd_type_len |= E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT;
3187 if (m_head->m_flags & M_VLANTAG)
3188 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
3191 * Map the packet for DMA.
3193 tx_buf = &txr->tx_buf[txr->next_avail_desc];
3194 tx_buf_mapped = tx_buf;
3197 maxsegs = txr->tx_avail - IGB_TX_RESERVED;
3198 KASSERT(maxsegs >= txr->spare_desc, ("not enough spare TX desc\n"));
3199 if (maxsegs > IGB_MAX_SCATTER)
3200 maxsegs = IGB_MAX_SCATTER;
3202 error = bus_dmamap_load_mbuf_defrag(txr->tx_tag, map, m_headp,
3203 segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
3205 if (error == ENOBUFS)
3206 txr->sc->mbuf_defrag_failed++;
3208 txr->sc->no_tx_dma_setup++;
3214 bus_dmamap_sync(txr->tx_tag, map, BUS_DMASYNC_PREWRITE);
3219 * Set up the TX context descriptor, if any hardware offloading is
3220 * needed. This includes CSUM, VLAN, and TSO. It will consume one
3223 * Unlike these chips' predecessors (em/emx), TX context descriptor
3224 * will _not_ interfere TX data fetching pipelining.
3226 if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
3227 igb_tso_ctx(txr, m_head, &hdrlen);
3228 cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
3229 olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
3230 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
3233 } else if (igb_txcsum_ctx(txr, m_head)) {
3234 if (m_head->m_pkthdr.csum_flags & CSUM_IP)
3235 olinfo_status |= (E1000_TXD_POPTS_IXSM << 8);
3236 if (m_head->m_pkthdr.csum_flags & (CSUM_UDP | CSUM_TCP))
3237 olinfo_status |= (E1000_TXD_POPTS_TXSM << 8);
3242 *segs_used += nsegs;
3243 txr->tx_nsegs += nsegs;
3244 if (txr->tx_nsegs >= txr->intr_nsegs) {
3246 * Report Status (RS) is turned on every intr_nsegs
3247 * descriptors (roughly).
3250 cmd_rs = E1000_ADVTXD_DCMD_RS;
3253 /* Calculate payload length */
3254 olinfo_status |= ((m_head->m_pkthdr.len - hdrlen)
3255 << E1000_ADVTXD_PAYLEN_SHIFT);
3257 /* 82575 needs the queue index added */
3258 if (txr->sc->hw.mac.type == e1000_82575)
3259 olinfo_status |= txr->me << 4;
3261 /* Set up our transmit descriptors */
3262 i = txr->next_avail_desc;
3263 for (j = 0; j < nsegs; j++) {
3265 bus_addr_t seg_addr;
3267 tx_buf = &txr->tx_buf[i];
3268 txd = (union e1000_adv_tx_desc *)&txr->tx_base[i];
3269 seg_addr = segs[j].ds_addr;
3270 seg_len = segs[j].ds_len;
3272 txd->read.buffer_addr = htole64(seg_addr);
3273 txd->read.cmd_type_len = htole32(cmd_type_len | seg_len);
3274 txd->read.olinfo_status = htole32(olinfo_status);
3276 if (++i == txr->num_tx_desc)
3278 tx_buf->m_head = NULL;
3281 KASSERT(txr->tx_avail > nsegs, ("invalid avail TX desc\n"));
3282 txr->next_avail_desc = i;
3283 txr->tx_avail -= nsegs;
3285 tx_buf->m_head = m_head;
3286 tx_buf_mapped->map = tx_buf->map;
3290 * Last Descriptor of Packet needs End Of Packet (EOP)
3292 txd->read.cmd_type_len |= htole32(E1000_ADVTXD_DCMD_EOP | cmd_rs);
3295 * Advance the Transmit Descriptor Tail (TDT), this tells the E1000
3296 * that this frame is available to transmit.
3305 igb_start(struct ifnet *ifp)
3307 struct igb_softc *sc = ifp->if_softc;
3308 struct igb_tx_ring *txr = &sc->tx_rings[0];
3309 struct mbuf *m_head;
3310 int idx = -1, nsegs = 0;
3312 ASSERT_SERIALIZED(&txr->tx_serialize);
3314 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING)
3317 if (!sc->link_active) {
3318 ifq_purge(&ifp->if_snd);
3322 if (!IGB_IS_NOT_OACTIVE(txr))
3325 while (!ifq_is_empty(&ifp->if_snd)) {
3326 if (IGB_IS_OACTIVE(txr)) {
3327 ifp->if_flags |= IFF_OACTIVE;
3328 /* Set watchdog on */
3333 m_head = ifq_dequeue(&ifp->if_snd, NULL);
3337 if (igb_encap(txr, &m_head, &nsegs, &idx)) {
3342 if (nsegs >= txr->wreg_nsegs) {
3343 E1000_WRITE_REG(&txr->sc->hw, E1000_TDT(txr->me), idx);
3348 /* Send a copy of the frame to the BPF listener */
3349 ETHER_BPF_MTAP(ifp, m_head);
3352 E1000_WRITE_REG(&txr->sc->hw, E1000_TDT(txr->me), idx);
3356 igb_watchdog(struct ifnet *ifp)
3358 struct igb_softc *sc = ifp->if_softc;
3359 struct igb_tx_ring *txr = &sc->tx_rings[0];
3361 ASSERT_IFNET_SERIALIZED_ALL(ifp);
3364 * If flow control has paused us since last checking
3365 * it invalidates the watchdog timing, so dont run it.
3367 if (sc->pause_frames) {
3368 sc->pause_frames = 0;
3373 if_printf(ifp, "Watchdog timeout -- resetting\n");
3374 if_printf(ifp, "Queue(%d) tdh = %d, hw tdt = %d\n", txr->me,
3375 E1000_READ_REG(&sc->hw, E1000_TDH(txr->me)),
3376 E1000_READ_REG(&sc->hw, E1000_TDT(txr->me)));
3377 if_printf(ifp, "TX(%d) desc avail = %d, "
3378 "Next TX to Clean = %d\n",
3379 txr->me, txr->tx_avail, txr->next_to_clean);
3382 sc->watchdog_events++;
3385 if (!ifq_is_empty(&ifp->if_snd))
3390 igb_set_eitr(struct igb_softc *sc, int idx, int rate)
3395 if (sc->hw.mac.type == e1000_82575) {
3396 eitr = 1000000000 / 256 / rate;
3399 * Document is wrong on the 2 bits left shift
3402 eitr = 1000000 / rate;
3403 eitr <<= IGB_EITR_INTVL_SHIFT;
3407 /* Don't disable it */
3408 eitr = 1 << IGB_EITR_INTVL_SHIFT;
3409 } else if (eitr > IGB_EITR_INTVL_MASK) {
3410 /* Don't allow it to be too large */
3411 eitr = IGB_EITR_INTVL_MASK;
3414 if (sc->hw.mac.type == e1000_82575)
3417 eitr |= E1000_EITR_CNT_IGNR;
3418 E1000_WRITE_REG(&sc->hw, E1000_EITR(idx), eitr);
3422 igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS)
3424 struct igb_softc *sc = (void *)arg1;
3425 struct ifnet *ifp = &sc->arpcom.ac_if;
3426 int error, intr_rate;
3428 intr_rate = sc->intr_rate;
3429 error = sysctl_handle_int(oidp, &intr_rate, 0, req);
3430 if (error || req->newptr == NULL)
3435 ifnet_serialize_all(ifp);
3437 sc->intr_rate = intr_rate;
3438 if (ifp->if_flags & IFF_RUNNING)
3439 igb_set_eitr(sc, 0, sc->intr_rate);
3442 if_printf(ifp, "interrupt rate set to %d/sec\n", sc->intr_rate);
3444 ifnet_deserialize_all(ifp);
3450 igb_sysctl_msix_rate(SYSCTL_HANDLER_ARGS)
3452 struct igb_msix_data *msix = (void *)arg1;
3453 struct igb_softc *sc = msix->msix_sc;
3454 struct ifnet *ifp = &sc->arpcom.ac_if;
3455 int error, msix_rate;
3457 msix_rate = msix->msix_rate;
3458 error = sysctl_handle_int(oidp, &msix_rate, 0, req);
3459 if (error || req->newptr == NULL)
3464 lwkt_serialize_enter(msix->msix_serialize);
3466 msix->msix_rate = msix_rate;
3467 if (ifp->if_flags & IFF_RUNNING)
3468 igb_set_eitr(sc, msix->msix_vector, msix->msix_rate);
3471 if_printf(ifp, "%s set to %d/sec\n", msix->msix_rate_desc,
3475 lwkt_serialize_exit(msix->msix_serialize);
3481 igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS)
3483 struct igb_softc *sc = (void *)arg1;
3484 struct ifnet *ifp = &sc->arpcom.ac_if;
3485 struct igb_tx_ring *txr = &sc->tx_rings[0];
3488 nsegs = txr->intr_nsegs;
3489 error = sysctl_handle_int(oidp, &nsegs, 0, req);
3490 if (error || req->newptr == NULL)
3495 ifnet_serialize_all(ifp);
3497 if (nsegs >= txr->num_tx_desc - txr->oact_lo_desc ||
3498 nsegs >= txr->oact_hi_desc - IGB_MAX_SCATTER) {
3502 txr->intr_nsegs = nsegs;
3505 ifnet_deserialize_all(ifp);
3510 #ifdef IFPOLL_ENABLE
3513 igb_sysctl_npoll_rxoff(SYSCTL_HANDLER_ARGS)
3515 struct igb_softc *sc = (void *)arg1;
3516 struct ifnet *ifp = &sc->arpcom.ac_if;
3519 off = sc->rx_npoll_off;
3520 error = sysctl_handle_int(oidp, &off, 0, req);
3521 if (error || req->newptr == NULL)
3526 ifnet_serialize_all(ifp);
3527 if (off >= ncpus2 || off % sc->rx_ring_cnt != 0) {
3531 sc->rx_npoll_off = off;
3533 ifnet_deserialize_all(ifp);
3539 igb_sysctl_npoll_txoff(SYSCTL_HANDLER_ARGS)
3541 struct igb_softc *sc = (void *)arg1;
3542 struct ifnet *ifp = &sc->arpcom.ac_if;
3545 off = sc->tx_npoll_off;
3546 error = sysctl_handle_int(oidp, &off, 0, req);
3547 if (error || req->newptr == NULL)
3552 ifnet_serialize_all(ifp);
3553 if (off >= ncpus2) {
3557 sc->tx_npoll_off = off;
3559 ifnet_deserialize_all(ifp);
3564 #endif /* IFPOLL_ENABLE */
3567 igb_init_intr(struct igb_softc *sc)
3569 igb_set_intr_mask(sc);
3571 if ((sc->flags & IGB_FLAG_SHARED_INTR) == 0)
3572 igb_init_unshared_intr(sc);
3574 if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
3575 igb_set_eitr(sc, 0, sc->intr_rate);
3579 for (i = 0; i < sc->msix_cnt; ++i)
3580 igb_set_eitr(sc, i, sc->msix_data[i].msix_rate);
3585 igb_init_unshared_intr(struct igb_softc *sc)
3587 struct e1000_hw *hw = &sc->hw;
3588 const struct igb_rx_ring *rxr;
3589 const struct igb_tx_ring *txr;
3590 uint32_t ivar, index;
3594 * Enable extended mode
3596 if (sc->hw.mac.type != e1000_82575) {
3600 gpie = E1000_GPIE_NSICR;
3601 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3602 gpie |= E1000_GPIE_MSIX_MODE |
3606 E1000_WRITE_REG(hw, E1000_GPIE, gpie);
3611 switch (sc->hw.mac.type) {
3613 ivar_max = IGB_MAX_IVAR_82580;
3617 ivar_max = IGB_MAX_IVAR_I350;
3621 case e1000_vfadapt_i350:
3622 ivar_max = IGB_MAX_IVAR_VF;
3626 ivar_max = IGB_MAX_IVAR_82576;
3630 panic("unknown mac type %d\n", sc->hw.mac.type);
3632 for (i = 0; i < ivar_max; ++i)
3633 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, i, 0);
3634 E1000_WRITE_REG(hw, E1000_IVAR_MISC, 0);
3638 KASSERT(sc->intr_type != PCI_INTR_TYPE_MSIX,
3639 ("82575 w/ MSI-X"));
3640 tmp = E1000_READ_REG(hw, E1000_CTRL_EXT);
3641 tmp |= E1000_CTRL_EXT_IRCA;
3642 E1000_WRITE_REG(hw, E1000_CTRL_EXT, tmp);
3646 * Map TX/RX interrupts to EICR
3648 switch (sc->hw.mac.type) {
3652 case e1000_vfadapt_i350:
3654 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3655 rxr = &sc->rx_rings[i];
3658 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3663 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3667 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3669 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3672 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3673 txr = &sc->tx_rings[i];
3676 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3681 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3685 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3687 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3689 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3690 ivar = (sc->sts_intr_bit | E1000_IVAR_VALID) << 8;
3691 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
3697 for (i = 0; i < sc->rx_ring_inuse; ++i) {
3698 rxr = &sc->rx_rings[i];
3700 index = i & 0x7; /* Each IVAR has two entries */
3701 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3706 (rxr->rx_intr_bit | E1000_IVAR_VALID);
3710 (rxr->rx_intr_bit | E1000_IVAR_VALID) << 16;
3712 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3715 for (i = 0; i < sc->tx_ring_cnt; ++i) {
3716 txr = &sc->tx_rings[i];
3718 index = i & 0x7; /* Each IVAR has two entries */
3719 ivar = E1000_READ_REG_ARRAY(hw, E1000_IVAR0, index);
3724 (txr->tx_intr_bit | E1000_IVAR_VALID) << 8;
3728 (txr->tx_intr_bit | E1000_IVAR_VALID) << 24;
3730 E1000_WRITE_REG_ARRAY(hw, E1000_IVAR0, index, ivar);
3732 if (sc->intr_type == PCI_INTR_TYPE_MSIX) {
3733 ivar = (sc->sts_intr_bit | E1000_IVAR_VALID) << 8;
3734 E1000_WRITE_REG(hw, E1000_IVAR_MISC, ivar);
3740 * Enable necessary interrupt bits.
3742 * The name of the register is confusing; in addition to
3743 * configuring the first vector of MSI-X, it also configures
3744 * which bits of EICR could be set by the hardware even when
3745 * MSI or line interrupt is used; it thus controls interrupt
3746 * generation. It MUST be configured explicitly; the default
3747 * value mentioned in the datasheet is wrong: RX queue0 and
3748 * TX queue0 are NOT enabled by default.
3750 E1000_WRITE_REG(&sc->hw, E1000_MSIXBM(0), sc->intr_mask);
3754 panic("unknown mac type %d\n", sc->hw.mac.type);
3759 igb_setup_intr(struct igb_softc *sc)
3761 struct ifnet *ifp = &sc->arpcom.ac_if;
3764 if (sc->intr_type == PCI_INTR_TYPE_MSIX)
3765 return igb_msix_setup(sc);
3767 error = bus_setup_intr(sc->dev, sc->intr_res, INTR_MPSAFE,
3768 (sc->flags & IGB_FLAG_SHARED_INTR) ? igb_intr_shared : igb_intr,
3769 sc, &sc->intr_tag, &sc->main_serialize);
3771 device_printf(sc->dev, "Failed to register interrupt handler");
3775 ifp->if_cpuid = rman_get_cpuid(sc->intr_res);
3776 KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
3782 igb_set_txintr_mask(struct igb_tx_ring *txr, int *intr_bit0, int intr_bitmax)
3784 if (txr->sc->hw.mac.type == e1000_82575) {
3785 txr->tx_intr_bit = 0; /* unused */
3788 txr->tx_intr_mask = E1000_EICR_TX_QUEUE0;
3791 txr->tx_intr_mask = E1000_EICR_TX_QUEUE1;
3794 txr->tx_intr_mask = E1000_EICR_TX_QUEUE2;
3797 txr->tx_intr_mask = E1000_EICR_TX_QUEUE3;
3800 panic("unsupported # of TX ring, %d\n", txr->me);
3803 int intr_bit = *intr_bit0;
3805 txr->tx_intr_bit = intr_bit % intr_bitmax;
3806 txr->tx_intr_mask = 1 << txr->tx_intr_bit;
3808 *intr_bit0 = intr_bit + 1;
3813 igb_set_rxintr_mask(struct igb_rx_ring *rxr, int *intr_bit0, int intr_bitmax)
3815 if (rxr->sc->hw.mac.type == e1000_82575) {
3816 rxr->rx_intr_bit = 0; /* unused */
3819 rxr->rx_intr_mask = E1000_EICR_RX_QUEUE0;
3822 rxr->rx_intr_mask = E1000_EICR_RX_QUEUE1;
3825 rxr->rx_intr_mask = E1000_EICR_RX_QUEUE2;
3828 rxr->rx_intr_mask = E1000_EICR_RX_QUEUE3;
3831 panic("unsupported # of RX ring, %d\n", rxr->me);
3834 int intr_bit = *intr_bit0;
3836 rxr->rx_intr_bit = intr_bit % intr_bitmax;
3837 rxr->rx_intr_mask = 1 << rxr->rx_intr_bit;
3839 *intr_bit0 = intr_bit + 1;
3844 igb_serialize(struct ifnet *ifp, enum ifnet_serialize slz)
3846 struct igb_softc *sc = ifp->if_softc;
3848 ifnet_serialize_array_enter(sc->serializes, sc->serialize_cnt,
3849 sc->tx_serialize, sc->rx_serialize, slz);
3853 igb_deserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3855 struct igb_softc *sc = ifp->if_softc;
3857 ifnet_serialize_array_exit(sc->serializes, sc->serialize_cnt,
3858 sc->tx_serialize, sc->rx_serialize, slz);
3862 igb_tryserialize(struct ifnet *ifp, enum ifnet_serialize slz)
3864 struct igb_softc *sc = ifp->if_softc;
3866 return ifnet_serialize_array_try(sc->serializes, sc->serialize_cnt,
3867 sc->tx_serialize, sc->rx_serialize, slz);
3873 igb_serialize_assert(struct ifnet *ifp, enum ifnet_serialize slz,
3874 boolean_t serialized)
3876 struct igb_softc *sc = ifp->if_softc;
3878 ifnet_serialize_array_assert(sc->serializes, sc->serialize_cnt,
3879 sc->tx_serialize, sc->rx_serialize, slz, serialized);
3882 #endif /* INVARIANTS */
3885 igb_set_intr_mask(struct igb_softc *sc)
3889 sc->intr_mask = sc->sts_intr_mask;
3890 for (i = 0; i < sc->rx_ring_inuse; ++i)
3891 sc->intr_mask |= sc->rx_rings[i].rx_intr_mask;
3892 for (i = 0; i < sc->tx_ring_cnt; ++i)
3893 sc->intr_mask |= sc->tx_rings[i].tx_intr_mask;
3895 if_printf(&sc->arpcom.ac_if, "intr mask 0x%08x\n",
3901 igb_alloc_intr(struct igb_softc *sc)
3903 int i, intr_bit, intr_bitmax;
3906 igb_msix_try_alloc(sc);
3907 if (sc->intr_type == PCI_INTR_TYPE_MSIX)
3911 * Allocate MSI/legacy interrupt resource
3913 sc->intr_type = pci_alloc_1intr(sc->dev, igb_msi_enable,
3914 &sc->intr_rid, &intr_flags);
3916 if (sc->intr_type == PCI_INTR_TYPE_LEGACY) {
3919 unshared = device_getenv_int(sc->dev, "irq.unshared", 0);
3921 sc->flags |= IGB_FLAG_SHARED_INTR;
3923 device_printf(sc->dev, "IRQ shared\n");
3925 intr_flags &= ~RF_SHAREABLE;
3927 device_printf(sc->dev, "IRQ unshared\n");
3931 sc->intr_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
3932 &sc->intr_rid, intr_flags);
3933 if (sc->intr_res == NULL) {
3934 device_printf(sc->dev, "Unable to allocate bus resource: "
3940 * Setup MSI/legacy interrupt mask
3942 switch (sc->hw.mac.type) {
3944 intr_bitmax = IGB_MAX_TXRXINT_82575;
3947 intr_bitmax = IGB_MAX_TXRXINT_82580;
3950 intr_bitmax = IGB_MAX_TXRXINT_I350;
3953 intr_bitmax = IGB_MAX_TXRXINT_82576;
3956 intr_bitmax = IGB_MIN_TXRXINT;
3960 for (i = 0; i < sc->tx_ring_cnt; ++i)
3961 igb_set_txintr_mask(&sc->tx_rings[i], &intr_bit, intr_bitmax);
3962 for (i = 0; i < sc->rx_ring_cnt; ++i)
3963 igb_set_rxintr_mask(&sc->rx_rings[i], &intr_bit, intr_bitmax);
3964 sc->sts_intr_bit = 0;
3965 sc->sts_intr_mask = E1000_EICR_OTHER;
3967 /* Initialize interrupt rate */
3968 sc->intr_rate = IGB_INTR_RATE;
3970 igb_set_ring_inuse(sc, FALSE);
3971 igb_set_intr_mask(sc);
3976 igb_free_intr(struct igb_softc *sc)
3978 if (sc->intr_type != PCI_INTR_TYPE_MSIX) {
3979 if (sc->intr_res != NULL) {
3980 bus_release_resource(sc->dev, SYS_RES_IRQ, sc->intr_rid,
3983 if (sc->intr_type == PCI_INTR_TYPE_MSI)
3984 pci_release_msi(sc->dev);
3986 igb_msix_free(sc, TRUE);
3991 igb_teardown_intr(struct igb_softc *sc)
3993 if (sc->intr_type != PCI_INTR_TYPE_MSIX)
3994 bus_teardown_intr(sc->dev, sc->intr_res, sc->intr_tag);
3996 igb_msix_teardown(sc, sc->msix_cnt);
4000 igb_msix_try_alloc(struct igb_softc *sc)
4002 int msix_enable, msix_cnt, msix_cnt2, alloc_cnt;
4004 struct igb_msix_data *msix;
4005 boolean_t aggregate, setup = FALSE;
4008 * Don't enable MSI-X on 82575, see:
4009 * 82575 specification update errata #25
4011 if (sc->hw.mac.type == e1000_82575)
4014 /* Don't enable MSI-X on VF */
4018 msix_enable = device_getenv_int(sc->dev, "msix.enable",
4023 msix_cnt = pci_msix_count(sc->dev);
4024 #ifdef IGB_MSIX_DEBUG
4025 msix_cnt = device_getenv_int(sc->dev, "msix.count", msix_cnt);
4027 if (msix_cnt <= 1) {
4028 /* One MSI-X model does not make sense */
4033 while ((1 << (i + 1)) <= msix_cnt)
4038 device_printf(sc->dev, "MSI-X count %d/%d\n",
4039 msix_cnt2, msix_cnt);
4042 KKASSERT(msix_cnt2 <= msix_cnt);
4043 if (msix_cnt == msix_cnt2) {
4044 /* We need at least one MSI-X for link status */
4046 if (msix_cnt2 <= 1) {
4047 /* One MSI-X for RX/TX does not make sense */
4048 device_printf(sc->dev, "not enough MSI-X for TX/RX, "
4049 "MSI-X count %d/%d\n", msix_cnt2, msix_cnt);
4052 KKASSERT(msix_cnt > msix_cnt2);
4055 device_printf(sc->dev, "MSI-X count fixup %d/%d\n",
4056 msix_cnt2, msix_cnt);
4060 sc->rx_ring_msix = sc->rx_ring_cnt;
4061 if (sc->rx_ring_msix > msix_cnt2)
4062 sc->rx_ring_msix = msix_cnt2;
4064 if (msix_cnt >= sc->tx_ring_cnt + sc->rx_ring_msix + 1) {
4066 * Independent TX/RX MSI-X
4070 device_printf(sc->dev, "independent TX/RX MSI-X\n");
4071 alloc_cnt = sc->tx_ring_cnt + sc->rx_ring_msix;
4074 * Aggregate TX/RX MSI-X
4078 device_printf(sc->dev, "aggregate TX/RX MSI-X\n");
4079 alloc_cnt = msix_cnt2;
4080 if (alloc_cnt > ncpus2)
4082 if (sc->rx_ring_msix > alloc_cnt)
4083 sc->rx_ring_msix = alloc_cnt;
4085 ++alloc_cnt; /* For link status */
4088 device_printf(sc->dev, "MSI-X alloc %d, RX ring %d\n",
4089 alloc_cnt, sc->rx_ring_msix);
4092 sc->msix_mem_rid = PCIR_BAR(IGB_MSIX_BAR);
4093 sc->msix_mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
4094 &sc->msix_mem_rid, RF_ACTIVE);
4095 if (sc->msix_mem_res == NULL) {
4096 device_printf(sc->dev, "Unable to map MSI-X table\n");
4100 sc->msix_cnt = alloc_cnt;
4101 sc->msix_data = kmalloc_cachealign(
4102 sizeof(struct igb_msix_data) * sc->msix_cnt,
4103 M_DEVBUF, M_WAITOK | M_ZERO);
4104 for (x = 0; x < sc->msix_cnt; ++x) {
4105 msix = &sc->msix_data[x];
4107 lwkt_serialize_init(&msix->msix_serialize0);
4109 msix->msix_rid = -1;
4110 msix->msix_vector = x;
4111 msix->msix_mask = 1 << msix->msix_vector;
4112 msix->msix_rate = IGB_INTR_RATE;
4117 int offset, offset_def;
4119 if (sc->rx_ring_msix == ncpus2) {
4122 offset_def = (sc->rx_ring_msix *
4123 device_get_unit(sc->dev)) % ncpus2;
4125 offset = device_getenv_int(sc->dev,
4126 "msix.rxoff", offset_def);
4127 if (offset >= ncpus2 ||
4128 offset % sc->rx_ring_msix != 0) {
4129 device_printf(sc->dev,
4130 "invalid msix.rxoff %d, use %d\n",
4131 offset, offset_def);
4132 offset = offset_def;
4137 for (i = 0; i < sc->rx_ring_msix; ++i) {
4138 struct igb_rx_ring *rxr = &sc->rx_rings[i];
4140 KKASSERT(x < sc->msix_cnt);
4141 msix = &sc->msix_data[x++];
4142 rxr->rx_intr_bit = msix->msix_vector;
4143 rxr->rx_intr_mask = msix->msix_mask;
4145 msix->msix_serialize = &rxr->rx_serialize;
4146 msix->msix_func = igb_msix_rx;
4147 msix->msix_arg = rxr;
4148 msix->msix_cpuid = i + offset;
4149 KKASSERT(msix->msix_cpuid < ncpus2);
4150 ksnprintf(msix->msix_desc, sizeof(msix->msix_desc),
4151 "%s rx%d", device_get_nameunit(sc->dev), i);
4152 msix->msix_rate = IGB_MSIX_RX_RATE;
4153 ksnprintf(msix->msix_rate_desc,
4154 sizeof(msix->msix_rate_desc),
4155 "RX%d interrupt rate", i);
4158 offset_def = device_get_unit(sc->dev) % ncpus2;
4159 offset = device_getenv_int(sc->dev, "msix.txoff", offset_def);
4160 if (offset >= ncpus2) {
4161 device_printf(sc->dev, "invalid msix.txoff %d, "
4162 "use %d\n", offset, offset_def);
4163 offset = offset_def;
4167 for (i = 0; i < sc->tx_ring_cnt; ++i) {
4168 struct igb_tx_ring *txr = &sc->tx_rings[i];
4170 KKASSERT(x < sc->msix_cnt);
4171 msix = &sc->msix_data[x++];
4172 txr->tx_intr_bit = msix->msix_vector;
4173 txr->tx_intr_mask = msix->msix_mask;
4175 msix->msix_serialize = &txr->tx_serialize;
4176 msix->msix_func = igb_msix_tx;
4177 msix->msix_arg = txr;
4178 msix->msix_cpuid = i + offset;
4179 sc->msix_tx_cpuid = msix->msix_cpuid; /* XXX */
4180 KKASSERT(msix->msix_cpuid < ncpus2);
4181 ksnprintf(msix->msix_desc, sizeof(msix->msix_desc),
4182 "%s tx%d", device_get_nameunit(sc->dev), i);
4183 msix->msix_rate = IGB_MSIX_TX_RATE;
4184 ksnprintf(msix->msix_rate_desc,
4185 sizeof(msix->msix_rate_desc),
4186 "TX%d interrupt rate", i);
4197 KKASSERT(x < sc->msix_cnt);
4198 msix = &sc->msix_data[x++];
4199 sc->sts_intr_bit = msix->msix_vector;
4200 sc->sts_intr_mask = msix->msix_mask;
4202 msix->msix_serialize = &sc->main_serialize;
4203 msix->msix_func = igb_msix_status;
4204 msix->msix_arg = sc;
4205 msix->msix_cpuid = 0; /* TODO tunable */
4206 ksnprintf(msix->msix_desc, sizeof(msix->msix_desc), "%s sts",
4207 device_get_nameunit(sc->dev));
4208 ksnprintf(msix->msix_rate_desc, sizeof(msix->msix_rate_desc),
4209 "status interrupt rate");
4211 KKASSERT(x == sc->msix_cnt);
4213 error = pci_setup_msix(sc->dev);
4215 device_printf(sc->dev, "Setup MSI-X failed\n");
4220 for (i = 0; i < sc->msix_cnt; ++i) {
4221 msix = &sc->msix_data[i];
4223 error = pci_alloc_msix_vector(sc->dev, msix->msix_vector,
4224 &msix->msix_rid, msix->msix_cpuid);
4226 device_printf(sc->dev,
4227 "Unable to allocate MSI-X %d on cpu%d\n",
4228 msix->msix_vector, msix->msix_cpuid);
4232 msix->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
4233 &msix->msix_rid, RF_ACTIVE);
4234 if (msix->msix_res == NULL) {
4235 device_printf(sc->dev,
4236 "Unable to allocate MSI-X %d resource\n",
4243 pci_enable_msix(sc->dev);
4244 sc->intr_type = PCI_INTR_TYPE_MSIX;
4247 igb_msix_free(sc, setup);
4251 igb_msix_free(struct igb_softc *sc, boolean_t setup)
4255 KKASSERT(sc->msix_cnt > 1);
4257 for (i = 0; i < sc->msix_cnt; ++i) {
4258 struct igb_msix_data *msix = &sc->msix_data[i];
4260 if (msix->msix_res != NULL) {
4261 bus_release_resource(sc->dev, SYS_RES_IRQ,
4262 msix->msix_rid, msix->msix_res);
4264 if (msix->msix_rid >= 0)
4265 pci_release_msix_vector(sc->dev, msix->msix_rid);
4268 pci_teardown_msix(sc->dev);
4271 kfree(sc->msix_data, M_DEVBUF);
4272 sc->msix_data = NULL;
4276 igb_msix_setup(struct igb_softc *sc)
4278 struct ifnet *ifp = &sc->arpcom.ac_if;
4281 for (i = 0; i < sc->msix_cnt; ++i) {
4282 struct igb_msix_data *msix = &sc->msix_data[i];
4285 error = bus_setup_intr_descr(sc->dev, msix->msix_res,
4286 INTR_MPSAFE, msix->msix_func, msix->msix_arg,
4287 &msix->msix_handle, msix->msix_serialize, msix->msix_desc);
4289 device_printf(sc->dev, "could not set up %s "
4290 "interrupt handler.\n", msix->msix_desc);
4291 igb_msix_teardown(sc, i);
4295 ifp->if_cpuid = sc->msix_tx_cpuid;
4301 igb_msix_teardown(struct igb_softc *sc, int msix_cnt)
4305 for (i = 0; i < msix_cnt; ++i) {
4306 struct igb_msix_data *msix = &sc->msix_data[i];
4308 bus_teardown_intr(sc->dev, msix->msix_res, msix->msix_handle);
4313 igb_msix_rx(void *arg)
4315 struct igb_rx_ring *rxr = arg;
4317 ASSERT_SERIALIZED(&rxr->rx_serialize);
4320 E1000_WRITE_REG(&rxr->sc->hw, E1000_EIMS, rxr->rx_intr_mask);
4324 igb_msix_tx(void *arg)
4326 struct igb_tx_ring *txr = arg;
4327 struct ifnet *ifp = &txr->sc->arpcom.ac_if;
4329 ASSERT_SERIALIZED(&txr->tx_serialize);
4332 if (!ifq_is_empty(&ifp->if_snd))
4335 E1000_WRITE_REG(&txr->sc->hw, E1000_EIMS, txr->tx_intr_mask);
4339 igb_msix_status(void *arg)
4341 struct igb_softc *sc = arg;
4344 ASSERT_SERIALIZED(&sc->main_serialize);
4346 icr = E1000_READ_REG(&sc->hw, E1000_ICR);
4347 if (icr & E1000_ICR_LSC) {
4348 sc->hw.mac.get_link_status = 1;
4349 igb_update_link_status(sc);
4352 E1000_WRITE_REG(&sc->hw, E1000_EIMS, sc->sts_intr_mask);
4356 igb_set_ring_inuse(struct igb_softc *sc, boolean_t polling)
4358 if (!IGB_ENABLE_HWRSS(sc))
4362 sc->rx_ring_inuse = sc->rx_ring_cnt;
4363 else if (sc->intr_type != PCI_INTR_TYPE_MSIX)
4364 sc->rx_ring_inuse = IGB_MIN_RING_RSS;
4366 sc->rx_ring_inuse = sc->rx_ring_msix;
4368 if_printf(&sc->arpcom.ac_if, "RX rings %d/%d\n",
4369 sc->rx_ring_inuse, sc->rx_ring_cnt);
4374 igb_tso_pullup(struct igb_tx_ring *txr, struct mbuf **mp)
4376 int hoff, iphlen, thoff;
4380 KASSERT(M_WRITABLE(m), ("TSO mbuf not writable"));
4382 iphlen = m->m_pkthdr.csum_iphlen;
4383 thoff = m->m_pkthdr.csum_thlen;
4384 hoff = m->m_pkthdr.csum_lhlen;
4386 KASSERT(iphlen > 0, ("invalid ip hlen"));
4387 KASSERT(thoff > 0, ("invalid tcp hlen"));
4388 KASSERT(hoff > 0, ("invalid ether hlen"));
4390 if (__predict_false(m->m_len < hoff + iphlen + thoff)) {
4391 m = m_pullup(m, hoff + iphlen + thoff);
4398 if (txr->sc->flags & IGB_FLAG_TSO_IPLEN0) {
4401 ip = mtodoff(m, struct ip *, hoff);
4409 igb_tso_ctx(struct igb_tx_ring *txr, struct mbuf *m, uint32_t *hlen)
4411 struct e1000_adv_tx_context_desc *TXD;
4412 uint32_t vlan_macip_lens, type_tucmd_mlhl, mss_l4len_idx;
4413 int hoff, ctxd, iphlen, thoff;
4415 iphlen = m->m_pkthdr.csum_iphlen;
4416 thoff = m->m_pkthdr.csum_thlen;
4417 hoff = m->m_pkthdr.csum_lhlen;
4419 vlan_macip_lens = type_tucmd_mlhl = mss_l4len_idx = 0;
4421 ctxd = txr->next_avail_desc;
4422 TXD = (struct e1000_adv_tx_context_desc *)&txr->tx_base[ctxd];
4424 if (m->m_flags & M_VLANTAG) {
4427 vlantag = htole16(m->m_pkthdr.ether_vlantag);
4428 vlan_macip_lens |= (vlantag << E1000_ADVTXD_VLAN_SHIFT);
4431 vlan_macip_lens |= (hoff << E1000_ADVTXD_MACLEN_SHIFT);
4432 vlan_macip_lens |= iphlen;
4434 type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
4435 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP;
4436 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4;
4438 mss_l4len_idx |= (m->m_pkthdr.tso_segsz << E1000_ADVTXD_MSS_SHIFT);
4439 mss_l4len_idx |= (thoff << E1000_ADVTXD_L4LEN_SHIFT);
4440 /* 82575 needs the queue index added */
4441 if (txr->sc->hw.mac.type == e1000_82575)
4442 mss_l4len_idx |= txr->me << 4;
4444 TXD->vlan_macip_lens = htole32(vlan_macip_lens);
4445 TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
4446 TXD->seqnum_seed = htole32(0);
4447 TXD->mss_l4len_idx = htole32(mss_l4len_idx);
4449 /* We've consumed the first desc, adjust counters */
4450 if (++ctxd == txr->num_tx_desc)
4452 txr->next_avail_desc = ctxd;
4455 *hlen = hoff + iphlen + thoff;