igb: Optimize TX path
[dragonfly.git] / sys / dev / netif / igb / if_igb.c
1 /*
2  * Copyright (c) 2001-2011, Intel Corporation 
3  * All rights reserved.
4  * 
5  * Redistribution and use in source and binary forms, with or without 
6  * modification, are permitted provided that the following conditions are met:
7  * 
8  *  1. Redistributions of source code must retain the above copyright notice, 
9  *     this list of conditions and the following disclaimer.
10  * 
11  *  2. Redistributions in binary form must reproduce the above copyright 
12  *     notice, this list of conditions and the following disclaimer in the 
13  *     documentation and/or other materials provided with the distribution.
14  * 
15  *  3. Neither the name of the Intel Corporation nor the names of its 
16  *     contributors may be used to endorse or promote products derived from 
17  *     this software without specific prior written permission.
18  * 
19  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 
21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 
22  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 
23  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 
24  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 
25  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 
26  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 
27  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
28  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  * POSSIBILITY OF SUCH DAMAGE.
30  */
31
32 #include "opt_polling.h"
33
34 #include <sys/param.h>
35 #include <sys/bus.h>
36 #include <sys/endian.h>
37 #include <sys/interrupt.h>
38 #include <sys/kernel.h>
39 #include <sys/malloc.h>
40 #include <sys/mbuf.h>
41 #include <sys/proc.h>
42 #include <sys/rman.h>
43 #include <sys/serialize.h>
44 #include <sys/serialize2.h>
45 #include <sys/socket.h>
46 #include <sys/sockio.h>
47 #include <sys/sysctl.h>
48 #include <sys/systm.h>
49
50 #include <net/bpf.h>
51 #include <net/ethernet.h>
52 #include <net/if.h>
53 #include <net/if_arp.h>
54 #include <net/if_dl.h>
55 #include <net/if_media.h>
56 #include <net/ifq_var.h>
57 #include <net/toeplitz.h>
58 #include <net/toeplitz2.h>
59 #include <net/vlan/if_vlan_var.h>
60 #include <net/vlan/if_vlan_ether.h>
61 #include <net/if_poll.h>
62
63 #include <netinet/in_systm.h>
64 #include <netinet/in.h>
65 #include <netinet/ip.h>
66 #include <netinet/tcp.h>
67 #include <netinet/udp.h>
68
69 #include <bus/pci/pcivar.h>
70 #include <bus/pci/pcireg.h>
71
72 #include <dev/netif/ig_hal/e1000_api.h>
73 #include <dev/netif/ig_hal/e1000_82575.h>
74 #include <dev/netif/igb/if_igb.h>
75
76 #define IGB_NAME        "Intel(R) PRO/1000 "
77 #define IGB_DEVICE(id)  \
78         { IGB_VENDOR_ID, E1000_DEV_ID_##id, IGB_NAME #id }
79 #define IGB_DEVICE_NULL { 0, 0, NULL }
80
81 static struct igb_device {
82         uint16_t        vid;
83         uint16_t        did;
84         const char      *desc;
85 } igb_devices[] = {
86         IGB_DEVICE(82575EB_COPPER),
87         IGB_DEVICE(82575EB_FIBER_SERDES),
88         IGB_DEVICE(82575GB_QUAD_COPPER),
89         IGB_DEVICE(82576),
90         IGB_DEVICE(82576_NS),
91         IGB_DEVICE(82576_NS_SERDES),
92         IGB_DEVICE(82576_FIBER),
93         IGB_DEVICE(82576_SERDES),
94         IGB_DEVICE(82576_SERDES_QUAD),
95         IGB_DEVICE(82576_QUAD_COPPER),
96         IGB_DEVICE(82576_QUAD_COPPER_ET2),
97         IGB_DEVICE(82576_VF),
98         IGB_DEVICE(82580_COPPER),
99         IGB_DEVICE(82580_FIBER),
100         IGB_DEVICE(82580_SERDES),
101         IGB_DEVICE(82580_SGMII),
102         IGB_DEVICE(82580_COPPER_DUAL),
103         IGB_DEVICE(82580_QUAD_FIBER),
104         IGB_DEVICE(DH89XXCC_SERDES),
105         IGB_DEVICE(DH89XXCC_SGMII),
106         IGB_DEVICE(DH89XXCC_SFP),
107         IGB_DEVICE(DH89XXCC_BACKPLANE),
108         IGB_DEVICE(I350_COPPER),
109         IGB_DEVICE(I350_FIBER),
110         IGB_DEVICE(I350_SERDES),
111         IGB_DEVICE(I350_SGMII),
112         IGB_DEVICE(I350_VF),
113
114         /* required last entry */
115         IGB_DEVICE_NULL
116 };
117
118 static int      igb_probe(device_t);
119 static int      igb_attach(device_t);
120 static int      igb_detach(device_t);
121 static int      igb_shutdown(device_t);
122 static int      igb_suspend(device_t);
123 static int      igb_resume(device_t);
124
125 static boolean_t igb_is_valid_ether_addr(const uint8_t *);
126 static void     igb_setup_ifp(struct igb_softc *);
127 static int      igb_txctx_pullup(struct igb_tx_ring *, struct mbuf **);
128 static boolean_t igb_txctx(struct igb_tx_ring *, struct mbuf *);
129 static void     igb_add_sysctl(struct igb_softc *);
130 static int      igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS);
131 static int      igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS);
132
133 static void     igb_vf_init_stats(struct igb_softc *);
134 static void     igb_reset(struct igb_softc *);
135 static void     igb_update_stats_counters(struct igb_softc *);
136 static void     igb_update_vf_stats_counters(struct igb_softc *);
137 static void     igb_update_link_status(struct igb_softc *);
138 static void     igb_init_tx_unit(struct igb_softc *);
139 static void     igb_init_rx_unit(struct igb_softc *);
140
141 static void     igb_set_vlan(struct igb_softc *);
142 static void     igb_set_multi(struct igb_softc *);
143 static void     igb_set_promisc(struct igb_softc *);
144 static void     igb_disable_promisc(struct igb_softc *);
145
146 static int      igb_dma_alloc(struct igb_softc *);
147 static void     igb_dma_free(struct igb_softc *);
148 static int      igb_create_tx_ring(struct igb_tx_ring *);
149 static int      igb_create_rx_ring(struct igb_rx_ring *);
150 static void     igb_free_tx_ring(struct igb_tx_ring *);
151 static void     igb_free_rx_ring(struct igb_rx_ring *);
152 static void     igb_destroy_tx_ring(struct igb_tx_ring *, int);
153 static void     igb_destroy_rx_ring(struct igb_rx_ring *, int);
154 static void     igb_init_tx_ring(struct igb_tx_ring *);
155 static int      igb_init_rx_ring(struct igb_rx_ring *);
156 static int      igb_newbuf(struct igb_rx_ring *, int, boolean_t);
157 static int      igb_encap(struct igb_tx_ring *, struct mbuf **);
158
159 static void     igb_stop(struct igb_softc *);
160 static void     igb_init(void *);
161 static int      igb_ioctl(struct ifnet *, u_long, caddr_t, struct ucred *);
162 static void     igb_media_status(struct ifnet *, struct ifmediareq *);
163 static int      igb_media_change(struct ifnet *);
164 static void     igb_timer(void *);
165 static void     igb_watchdog(struct ifnet *);
166 static void     igb_start(struct ifnet *);
167 #ifdef DEVICE_POLLING
168 static void     igb_poll(struct ifnet *, enum poll_cmd, int);
169 #endif
170
171 static void     igb_intr(void *);
172 static void     igb_rxeof(struct igb_rx_ring *, int);
173 static void     igb_txeof(struct igb_tx_ring *);
174 static void     igb_set_itr(struct igb_softc *);
175 static void     igb_enable_intr(struct igb_softc *);
176 static void     igb_disable_intr(struct igb_softc *);
177
178 /* Management and WOL Support */
179 static void     igb_get_mgmt(struct igb_softc *);
180 static void     igb_rel_mgmt(struct igb_softc *);
181 static void     igb_get_hw_control(struct igb_softc *);
182 static void     igb_rel_hw_control(struct igb_softc *);
183 static void     igb_enable_wol(device_t);
184
185 static device_method_t igb_methods[] = {
186         /* Device interface */
187         DEVMETHOD(device_probe,         igb_probe),
188         DEVMETHOD(device_attach,        igb_attach),
189         DEVMETHOD(device_detach,        igb_detach),
190         DEVMETHOD(device_shutdown,      igb_shutdown),
191         DEVMETHOD(device_suspend,       igb_suspend),
192         DEVMETHOD(device_resume,        igb_resume),
193         { 0, 0 }
194 };
195
196 static driver_t igb_driver = {
197         "igb",
198         igb_methods,
199         sizeof(struct igb_softc),
200 };
201
202 static devclass_t igb_devclass;
203
204 DECLARE_DUMMY_MODULE(if_igb);
205 MODULE_DEPEND(igb, ig_hal, 1, 1, 1);
206 DRIVER_MODULE(if_igb, pci, igb_driver, igb_devclass, NULL, NULL);
207
208 static int      igb_rxd = IGB_DEFAULT_RXD;
209 static int      igb_txd = IGB_DEFAULT_TXD;
210 static int      igb_msi_enable = 1;
211 static int      igb_msix_enable = 1;
212 static int      igb_eee_disabled = 1;   /* Energy Efficient Ethernet */
213 static int      igb_fc_setting = e1000_fc_full;
214
215 /*
216  * DMA Coalescing, only for i350 - default to off,
217  * this feature is for power savings
218  */
219 static int      igb_dma_coalesce = 0;
220
221 TUNABLE_INT("hw.igb.rxd", &igb_rxd);
222 TUNABLE_INT("hw.igb.txd", &igb_txd);
223 TUNABLE_INT("hw.igb.msi.enable", &igb_msi_enable);
224 TUNABLE_INT("hw.igb.msix.enable", &igb_msix_enable);
225 TUNABLE_INT("hw.igb.fc_setting", &igb_fc_setting);
226
227 /* i350 specific */
228 TUNABLE_INT("hw.igb.eee_disabled", &igb_eee_disabled);
229 TUNABLE_INT("hw.igb.dma_coalesce", &igb_dma_coalesce);
230
231 static __inline void
232 igb_rxcsum(uint32_t staterr, struct mbuf *mp)
233 {
234         /* Ignore Checksum bit is set */
235         if (staterr & E1000_RXD_STAT_IXSM)
236                 return;
237
238         if ((staterr & (E1000_RXD_STAT_IPCS | E1000_RXDEXT_STATERR_IPE)) ==
239             E1000_RXD_STAT_IPCS)
240                 mp->m_pkthdr.csum_flags |= CSUM_IP_CHECKED | CSUM_IP_VALID;
241
242         if (staterr & (E1000_RXD_STAT_TCPCS | E1000_RXD_STAT_UDPCS)) {
243                 if ((staterr & E1000_RXDEXT_STATERR_TCPE) == 0) {
244                         mp->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
245                             CSUM_PSEUDO_HDR | CSUM_FRAG_NOT_CHECKED;
246                         mp->m_pkthdr.csum_data = htons(0xffff);
247                 }
248         }
249 }
250
251 static int
252 igb_probe(device_t dev)
253 {
254         const struct igb_device *d;
255         uint16_t vid, did;
256
257         vid = pci_get_vendor(dev);
258         did = pci_get_device(dev);
259
260         for (d = igb_devices; d->desc != NULL; ++d) {
261                 if (vid == d->vid && did == d->did) {
262                         device_set_desc(dev, d->desc);
263                         return 0;
264                 }
265         }
266         return ENXIO;
267 }
268
269 static int
270 igb_attach(device_t dev)
271 {
272         struct igb_softc *sc = device_get_softc(dev);
273         struct ifnet *ifp = &sc->arpcom.ac_if;
274         uint16_t eeprom_data;
275         u_int intr_flags;
276         int error = 0;
277
278 #ifdef notyet
279         /* SYSCTL stuff */
280         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
281             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
282             OID_AUTO, "nvm", CTLTYPE_INT|CTLFLAG_RW, adapter, 0,
283             igb_sysctl_nvm_info, "I", "NVM Information");
284
285         SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
286             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
287             OID_AUTO, "enable_aim", CTLTYPE_INT|CTLFLAG_RW,
288             &igb_enable_aim, 1, "Interrupt Moderation");
289
290         SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
291             SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
292             OID_AUTO, "flow_control", CTLTYPE_INT|CTLFLAG_RW,
293             adapter, 0, igb_set_flowcntl, "I", "Flow Control");
294 #endif
295
296         callout_init_mp(&sc->timer);
297
298         sc->dev = sc->osdep.dev = dev;
299
300         /*
301          * Determine hardware and mac type
302          */
303         sc->hw.vendor_id = pci_get_vendor(dev);
304         sc->hw.device_id = pci_get_device(dev);
305         sc->hw.revision_id = pci_read_config(dev, PCIR_REVID, 1);
306         sc->hw.subsystem_vendor_id = pci_read_config(dev, PCIR_SUBVEND_0, 2);
307         sc->hw.subsystem_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2);
308
309         if (e1000_set_mac_type(&sc->hw))
310                 return ENXIO;
311
312         /* Are we a VF device? */
313         if (sc->hw.mac.type == e1000_vfadapt ||
314             sc->hw.mac.type == e1000_vfadapt_i350)
315                 sc->vf_ifp = 1;
316         else
317                 sc->vf_ifp = 0;
318
319         /* Enable bus mastering */
320         pci_enable_busmaster(dev);
321
322         /*
323          * Allocate IO memory
324          */
325         sc->mem_rid = PCIR_BAR(0);
326         sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->mem_rid,
327             RF_ACTIVE);
328         if (sc->mem_res == NULL) {
329                 device_printf(dev, "Unable to allocate bus resource: memory\n");
330                 error = ENXIO;
331                 goto failed;
332         }
333         sc->osdep.mem_bus_space_tag = rman_get_bustag(sc->mem_res);
334         sc->osdep.mem_bus_space_handle = rman_get_bushandle(sc->mem_res);
335
336         sc->hw.hw_addr = (uint8_t *)&sc->osdep.mem_bus_space_handle;
337
338         /*
339          * Allocate interrupt
340          */
341         sc->intr_type = pci_alloc_1intr(dev, igb_msi_enable,
342             &sc->intr_rid, &intr_flags);
343
344         sc->intr_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->intr_rid,
345             intr_flags);
346         if (sc->intr_res == NULL) {
347                 device_printf(dev, "Unable to allocate bus resource: "
348                     "interrupt\n");
349                 error = ENXIO;
350                 goto failed;
351         }
352
353         /* Save PCI command register for Shared Code */
354         sc->hw.bus.pci_cmd_word = pci_read_config(dev, PCIR_COMMAND, 2);
355         sc->hw.back = &sc->osdep;
356
357         sc->num_queues = 1; /* Defaults for Legacy or MSI */
358         sc->intr_rate = IGB_INTR_RATE;
359
360         /* Do Shared Code initialization */
361         if (e1000_setup_init_funcs(&sc->hw, TRUE)) {
362                 device_printf(dev, "Setup of Shared code failed\n");
363                 error = ENXIO;
364                 goto failed;
365         }
366
367         e1000_get_bus_info(&sc->hw);
368
369         sc->hw.mac.autoneg = DO_AUTO_NEG;
370         sc->hw.phy.autoneg_wait_to_complete = FALSE;
371         sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
372
373         /* Copper options */
374         if (sc->hw.phy.media_type == e1000_media_type_copper) {
375                 sc->hw.phy.mdix = AUTO_ALL_MODES;
376                 sc->hw.phy.disable_polarity_correction = FALSE;
377                 sc->hw.phy.ms_type = IGB_MASTER_SLAVE;
378         }
379
380         /* Set the frame limits assuming  standard ethernet sized frames. */
381         sc->max_frame_size = ETHERMTU + ETHER_HDR_LEN + ETHER_CRC_LEN;
382         sc->min_frame_size = ETHER_MIN_LEN;
383
384         /* Allocate RX/TX rings' busdma(9) stuffs */
385         error = igb_dma_alloc(sc);
386         if (error)
387                 goto failed;
388
389         /* Allocate the appropriate stats memory */
390         if (sc->vf_ifp) {
391                 sc->stats = kmalloc(sizeof(struct e1000_vf_stats), M_DEVBUF,
392                     M_WAITOK | M_ZERO);
393                 igb_vf_init_stats(sc);
394         } else {
395                 sc->stats = kmalloc(sizeof(struct e1000_hw_stats), M_DEVBUF,
396                     M_WAITOK | M_ZERO);
397         }
398
399         /* Allocate multicast array memory. */
400         sc->mta = kmalloc(ETHER_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES,
401             M_DEVBUF, M_WAITOK);
402
403         /* Some adapter-specific advanced features */
404         if (sc->hw.mac.type >= e1000_i350) {
405 #ifdef notyet
406                 igb_set_sysctl_value(adapter, "dma_coalesce",
407                     "configure dma coalesce",
408                     &adapter->dma_coalesce, igb_dma_coalesce);
409                 igb_set_sysctl_value(adapter, "eee_disabled",
410                     "enable Energy Efficient Ethernet",
411                     &adapter->hw.dev_spec._82575.eee_disable,
412                     igb_eee_disabled);
413 #else
414                 sc->dma_coalesce = igb_dma_coalesce;
415                 sc->hw.dev_spec._82575.eee_disable = igb_eee_disabled;
416 #endif
417                 e1000_set_eee_i350(&sc->hw);
418         }
419
420         /*
421          * Start from a known state, this is important in reading the nvm and
422          * mac from that.
423          */
424         e1000_reset_hw(&sc->hw);
425
426         /* Make sure we have a good EEPROM before we read from it */
427         if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
428                 /*
429                  * Some PCI-E parts fail the first check due to
430                  * the link being in sleep state, call it again,
431                  * if it fails a second time its a real issue.
432                  */
433                 if (e1000_validate_nvm_checksum(&sc->hw) < 0) {
434                         device_printf(dev,
435                             "The EEPROM Checksum Is Not Valid\n");
436                         error = EIO;
437                         goto failed;
438                 }
439         }
440
441         /* Copy the permanent MAC address out of the EEPROM */
442         if (e1000_read_mac_addr(&sc->hw) < 0) {
443                 device_printf(dev, "EEPROM read error while reading MAC"
444                     " address\n");
445                 error = EIO;
446                 goto failed;
447         }
448         if (!igb_is_valid_ether_addr(sc->hw.mac.addr)) {
449                 device_printf(dev, "Invalid MAC address\n");
450                 error = EIO;
451                 goto failed;
452         }
453
454 #ifdef notyet
455         /* 
456         ** Configure Interrupts
457         */
458         if ((adapter->msix > 1) && (igb_enable_msix))
459                 error = igb_allocate_msix(adapter);
460         else /* MSI or Legacy */
461                 error = igb_allocate_legacy(adapter);
462         if (error)
463                 goto err_late;
464 #endif
465
466         /* Setup OS specific network interface */
467         igb_setup_ifp(sc);
468
469         /* Add sysctl tree, must after igb_setup_ifp() */
470         igb_add_sysctl(sc);
471
472         /* Now get a good starting state */
473         igb_reset(sc);
474
475         /* Initialize statistics */
476         igb_update_stats_counters(sc);
477
478         sc->hw.mac.get_link_status = 1;
479         igb_update_link_status(sc);
480
481         /* Indicate SOL/IDER usage */
482         if (e1000_check_reset_block(&sc->hw)) {
483                 device_printf(dev,
484                     "PHY reset is blocked due to SOL/IDER session.\n");
485         }
486
487         /* Determine if we have to control management hardware */
488         sc->has_manage = e1000_enable_mng_pass_thru(&sc->hw);
489
490         /*
491          * Setup Wake-on-Lan
492          */
493         /* APME bit in EEPROM is mapped to WUC.APME */
494         eeprom_data = E1000_READ_REG(&sc->hw, E1000_WUC) & E1000_WUC_APME;
495         if (eeprom_data)
496                 sc->wol = E1000_WUFC_MAG;
497         /* XXX disable WOL */
498         sc->wol = 0; 
499
500 #ifdef notyet
501         /* Register for VLAN events */
502         adapter->vlan_attach = EVENTHANDLER_REGISTER(vlan_config,
503              igb_register_vlan, adapter, EVENTHANDLER_PRI_FIRST);
504         adapter->vlan_detach = EVENTHANDLER_REGISTER(vlan_unconfig,
505              igb_unregister_vlan, adapter, EVENTHANDLER_PRI_FIRST);
506 #endif
507
508 #ifdef notyet
509         igb_add_hw_stats(adapter);
510 #endif
511
512         error = bus_setup_intr(dev, sc->intr_res, INTR_MPSAFE, igb_intr, sc,
513             &sc->intr_tag, ifp->if_serializer);
514         if (error) {
515                 device_printf(dev, "Failed to register interrupt handler");
516                 ether_ifdetach(&sc->arpcom.ac_if);
517                 goto failed;
518         }
519
520         ifp->if_cpuid = rman_get_cpuid(sc->intr_res);
521         KKASSERT(ifp->if_cpuid >= 0 && ifp->if_cpuid < ncpus);
522
523         return 0;
524
525 failed:
526         igb_detach(dev);
527         return error;
528 }
529
530 static int
531 igb_detach(device_t dev)
532 {
533         struct igb_softc *sc = device_get_softc(dev);
534
535         if (device_is_attached(dev)) {
536                 struct ifnet *ifp = &sc->arpcom.ac_if;
537
538                 ifnet_serialize_all(ifp);
539
540                 igb_stop(sc);
541
542                 e1000_phy_hw_reset(&sc->hw);
543
544                 /* Give control back to firmware */
545                 igb_rel_mgmt(sc);
546                 igb_rel_hw_control(sc);
547
548                 if (sc->wol) {
549                         E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
550                         E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
551                         igb_enable_wol(dev);
552                 }
553
554                 bus_teardown_intr(dev, sc->intr_res, sc->intr_tag);
555
556                 ifnet_deserialize_all(ifp);
557
558                 ether_ifdetach(ifp);
559         } else if (sc->mem_res != NULL) {
560                 igb_rel_hw_control(sc);
561         }
562         bus_generic_detach(dev);
563
564         if (sc->intr_res != NULL) {
565                 bus_release_resource(dev, SYS_RES_IRQ, sc->intr_rid,
566                     sc->intr_res);
567         }
568         if (sc->intr_type == PCI_INTR_TYPE_MSI)
569                 pci_release_msi(dev);
570
571         if (sc->mem_res != NULL) {
572                 bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid,
573                     sc->mem_res);
574         }
575
576         igb_dma_free(sc);
577
578         if (sc->mta != NULL)
579                 kfree(sc->mta, M_DEVBUF);
580         if (sc->stats != NULL)
581                 kfree(sc->stats, M_DEVBUF);
582
583         if (sc->sysctl_tree != NULL)
584                 sysctl_ctx_free(&sc->sysctl_ctx);
585
586         return 0;
587 }
588
589 static int
590 igb_shutdown(device_t dev)
591 {
592         return igb_suspend(dev);
593 }
594
595 static int
596 igb_suspend(device_t dev)
597 {
598         struct igb_softc *sc = device_get_softc(dev);
599         struct ifnet *ifp = &sc->arpcom.ac_if;
600
601         ifnet_serialize_all(ifp);
602
603         igb_stop(sc);
604
605         igb_rel_mgmt(sc);
606         igb_rel_hw_control(sc);
607
608         if (sc->wol) {
609                 E1000_WRITE_REG(&sc->hw, E1000_WUC, E1000_WUC_PME_EN);
610                 E1000_WRITE_REG(&sc->hw, E1000_WUFC, sc->wol);
611                 igb_enable_wol(dev);
612         }
613
614         ifnet_deserialize_all(ifp);
615
616         return bus_generic_suspend(dev);
617 }
618
619 static int
620 igb_resume(device_t dev)
621 {
622         struct igb_softc *sc = device_get_softc(dev);
623         struct ifnet *ifp = &sc->arpcom.ac_if;
624
625         ifnet_serialize_all(ifp);
626
627         igb_init(sc);
628         igb_get_mgmt(sc);
629
630         if_devstart(ifp);
631
632         ifnet_deserialize_all(ifp);
633
634         return bus_generic_resume(dev);
635 }
636
637 static int
638 igb_ioctl(struct ifnet *ifp, u_long command, caddr_t data, struct ucred *cr)
639 {
640         struct igb_softc *sc = ifp->if_softc;
641         struct ifreq *ifr = (struct ifreq *)data;
642         int max_frame_size, mask, reinit;
643         int error = 0;
644
645         ASSERT_IFNET_SERIALIZED_ALL(ifp);
646
647         switch (command) {
648         case SIOCSIFMTU:
649                 max_frame_size = 9234;
650                 if (ifr->ifr_mtu > max_frame_size - ETHER_HDR_LEN -
651                     ETHER_CRC_LEN) {
652                         error = EINVAL;
653                         break;
654                 }
655
656                 ifp->if_mtu = ifr->ifr_mtu;
657                 sc->max_frame_size = ifp->if_mtu + ETHER_HDR_LEN +
658                     ETHER_CRC_LEN;
659
660                 if (ifp->if_flags & IFF_RUNNING)
661                         igb_init(sc);
662                 break;
663
664         case SIOCSIFFLAGS:
665                 if (ifp->if_flags & IFF_UP) {
666                         if (ifp->if_flags & IFF_RUNNING) {
667                                 if ((ifp->if_flags ^ sc->if_flags) &
668                                     (IFF_PROMISC | IFF_ALLMULTI)) {
669                                         igb_disable_promisc(sc);
670                                         igb_set_promisc(sc);
671                                 }
672                         } else {
673                                 igb_init(sc);
674                         }
675                 } else if (ifp->if_flags & IFF_RUNNING) {
676                         igb_stop(sc);
677                 }
678                 sc->if_flags = ifp->if_flags;
679                 break;
680
681         case SIOCADDMULTI:
682         case SIOCDELMULTI:
683                 if (ifp->if_flags & IFF_RUNNING) {
684                         igb_disable_intr(sc);
685                         igb_set_multi(sc);
686 #ifdef DEVICE_POLLING
687                         if (!(ifp->if_flags & IFF_POLLING))
688 #endif
689                                 igb_enable_intr(sc);
690                 }
691                 break;
692
693         case SIOCSIFMEDIA:
694                 /*
695                  * As the speed/duplex settings are being
696                  * changed, we need toreset the PHY.
697                  */
698                 sc->hw.phy.reset_disable = FALSE;
699
700                 /* Check SOL/IDER usage */
701                 if (e1000_check_reset_block(&sc->hw)) {
702                         if_printf(ifp, "Media change is "
703                             "blocked due to SOL/IDER session.\n");
704                         break;
705                 }
706                 /* FALL THROUGH */
707
708         case SIOCGIFMEDIA:
709                 error = ifmedia_ioctl(ifp, ifr, &sc->media, command);
710                 break;
711
712         case SIOCSIFCAP:
713                 reinit = 0;
714                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
715                 if (mask & IFCAP_HWCSUM) {
716                         ifp->if_capenable ^= (mask & IFCAP_HWCSUM);
717                         reinit = 1;
718                 }
719                 if (mask & IFCAP_VLAN_HWTAGGING) {
720                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
721                         reinit = 1;
722                 }
723                 if (reinit && (ifp->if_flags & IFF_RUNNING))
724                         igb_init(sc);
725                 break;
726
727         default:
728                 error = ether_ioctl(ifp, command, data);
729                 break;
730         }
731         return error;
732 }
733
734 static void
735 igb_init(void *xsc)
736 {
737         struct igb_softc *sc = xsc;
738         struct ifnet *ifp = &sc->arpcom.ac_if;
739         int i;
740
741         ASSERT_IFNET_SERIALIZED_ALL(ifp);
742
743         igb_stop(sc);
744
745         /* Get the latest mac address, User can use a LAA */
746         bcopy(IF_LLADDR(ifp), sc->hw.mac.addr, ETHER_ADDR_LEN);
747
748         /* Put the address into the Receive Address Array */
749         e1000_rar_set(&sc->hw, sc->hw.mac.addr, 0);
750
751         igb_reset(sc);
752         igb_update_link_status(sc);
753
754         E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
755
756         /* Set hardware offload abilities */
757         if (ifp->if_capenable & IFCAP_TXCSUM)
758                 ifp->if_hwassist = IGB_CSUM_FEATURES;
759         else
760                 ifp->if_hwassist = 0;
761
762         /* Configure for OS presence */
763         igb_get_mgmt(sc);
764
765         /* Prepare transmit descriptors and buffers */
766         for (i = 0; i < sc->num_queues; ++i)
767                 igb_init_tx_ring(&sc->tx_rings[i]);
768         igb_init_tx_unit(sc);
769
770         /* Setup Multicast table */
771         igb_set_multi(sc);
772
773 #if 0
774         /*
775          * Figure out the desired mbuf pool
776          * for doing jumbo/packetsplit
777          */
778         if (adapter->max_frame_size <= 2048)
779                 adapter->rx_mbuf_sz = MCLBYTES;
780         else if (adapter->max_frame_size <= 4096)
781                 adapter->rx_mbuf_sz = MJUMPAGESIZE;
782         else
783                 adapter->rx_mbuf_sz = MJUM9BYTES;
784 #else
785         sc->rx_mbuf_sz = MCLBYTES;
786 #endif
787
788         /* Prepare receive descriptors and buffers */
789         for (i = 0; i < sc->num_queues; ++i) {
790                 int error;
791
792                 error = igb_init_rx_ring(&sc->rx_rings[i]);
793                 if (error) {
794                         if_printf(ifp, "Could not setup receive structures\n");
795                         igb_stop(sc);
796                         return;
797                 }
798         }
799         igb_init_rx_unit(sc);
800
801         /* Enable VLAN support */
802         if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
803                 igb_set_vlan(sc);
804
805         /* Don't lose promiscuous settings */
806         igb_set_promisc(sc);
807
808         /* Configure interrupt moderation */
809         igb_set_itr(sc);
810
811         ifp->if_flags |= IFF_RUNNING;
812         ifp->if_flags &= ~IFF_OACTIVE;
813
814         callout_reset(&sc->timer, hz, igb_timer, sc);
815         e1000_clear_hw_cntrs_base_generic(&sc->hw);
816
817 #if 0
818         if (adapter->msix > 1) /* Set up queue routing */
819                 igb_configure_queues(adapter);
820 #endif
821
822         /* this clears any pending interrupts */
823         E1000_READ_REG(&sc->hw, E1000_ICR);
824 #ifdef DEVICE_POLLING
825         /*
826          * Only enable interrupts if we are not polling, make sure
827          * they are off otherwise.
828          */
829         if (ifp->if_flags & IFF_POLLING)
830                 igb_disable_intr(sc);
831         else
832 #endif /* DEVICE_POLLING */
833         {
834                 igb_enable_intr(sc);
835                 E1000_WRITE_REG(&sc->hw, E1000_ICS, E1000_ICS_LSC);
836         }
837
838         /* Set Energy Efficient Ethernet */
839         e1000_set_eee_i350(&sc->hw);
840
841         /* Don't reset the phy next time init gets called */
842         sc->hw.phy.reset_disable = TRUE;
843 }
844
845 static void
846 igb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
847 {
848         struct igb_softc *sc = ifp->if_softc;
849         u_char fiber_type = IFM_1000_SX;
850
851         ASSERT_IFNET_SERIALIZED_ALL(ifp);
852
853         igb_update_link_status(sc);
854
855         ifmr->ifm_status = IFM_AVALID;
856         ifmr->ifm_active = IFM_ETHER;
857
858         if (!sc->link_active)
859                 return;
860
861         ifmr->ifm_status |= IFM_ACTIVE;
862
863         if (sc->hw.phy.media_type == e1000_media_type_fiber ||
864             sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
865                 ifmr->ifm_active |= fiber_type | IFM_FDX;
866         } else {
867                 switch (sc->link_speed) {
868                 case 10:
869                         ifmr->ifm_active |= IFM_10_T;
870                         break;
871
872                 case 100:
873                         ifmr->ifm_active |= IFM_100_TX;
874                         break;
875
876                 case 1000:
877                         ifmr->ifm_active |= IFM_1000_T;
878                         break;
879                 }
880                 if (sc->link_duplex == FULL_DUPLEX)
881                         ifmr->ifm_active |= IFM_FDX;
882                 else
883                         ifmr->ifm_active |= IFM_HDX;
884         }
885 }
886
887 static int
888 igb_media_change(struct ifnet *ifp)
889 {
890         struct igb_softc *sc = ifp->if_softc;
891         struct ifmedia *ifm = &sc->media;
892
893         ASSERT_IFNET_SERIALIZED_ALL(ifp);
894
895         if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
896                 return EINVAL;
897
898         switch (IFM_SUBTYPE(ifm->ifm_media)) {
899         case IFM_AUTO:
900                 sc->hw.mac.autoneg = DO_AUTO_NEG;
901                 sc->hw.phy.autoneg_advertised = AUTONEG_ADV_DEFAULT;
902                 break;
903
904         case IFM_1000_LX:
905         case IFM_1000_SX:
906         case IFM_1000_T:
907                 sc->hw.mac.autoneg = DO_AUTO_NEG;
908                 sc->hw.phy.autoneg_advertised = ADVERTISE_1000_FULL;
909                 break;
910
911         case IFM_100_TX:
912                 sc->hw.mac.autoneg = FALSE;
913                 sc->hw.phy.autoneg_advertised = 0;
914                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
915                         sc->hw.mac.forced_speed_duplex = ADVERTISE_100_FULL;
916                 else
917                         sc->hw.mac.forced_speed_duplex = ADVERTISE_100_HALF;
918                 break;
919
920         case IFM_10_T:
921                 sc->hw.mac.autoneg = FALSE;
922                 sc->hw.phy.autoneg_advertised = 0;
923                 if ((ifm->ifm_media & IFM_GMASK) == IFM_FDX)
924                         sc->hw.mac.forced_speed_duplex = ADVERTISE_10_FULL;
925                 else
926                         sc->hw.mac.forced_speed_duplex = ADVERTISE_10_HALF;
927                 break;
928
929         default:
930                 if_printf(ifp, "Unsupported media type\n");
931                 break;
932         }
933
934         igb_init(sc);
935
936         return 0;
937 }
938
939 static void
940 igb_set_promisc(struct igb_softc *sc)
941 {
942         struct ifnet *ifp = &sc->arpcom.ac_if;
943         struct e1000_hw *hw = &sc->hw;
944         uint32_t reg;
945
946         if (sc->vf_ifp) {
947                 e1000_promisc_set_vf(hw, e1000_promisc_enabled);
948                 return;
949         }
950
951         reg = E1000_READ_REG(hw, E1000_RCTL);
952         if (ifp->if_flags & IFF_PROMISC) {
953                 reg |= (E1000_RCTL_UPE | E1000_RCTL_MPE);
954                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
955         } else if (ifp->if_flags & IFF_ALLMULTI) {
956                 reg |= E1000_RCTL_MPE;
957                 reg &= ~E1000_RCTL_UPE;
958                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
959         }
960 }
961
962 static void
963 igb_disable_promisc(struct igb_softc *sc)
964 {
965         struct e1000_hw *hw = &sc->hw;
966         uint32_t reg;
967
968         if (sc->vf_ifp) {
969                 e1000_promisc_set_vf(hw, e1000_promisc_disabled);
970                 return;
971         }
972         reg = E1000_READ_REG(hw, E1000_RCTL);
973         reg &= ~E1000_RCTL_UPE;
974         reg &= ~E1000_RCTL_MPE;
975         E1000_WRITE_REG(hw, E1000_RCTL, reg);
976 }
977
978 static void
979 igb_set_multi(struct igb_softc *sc)
980 {
981         struct ifnet *ifp = &sc->arpcom.ac_if;
982         struct ifmultiaddr *ifma;
983         uint32_t reg_rctl = 0;
984         uint8_t *mta;
985         int mcnt = 0;
986
987         mta = sc->mta;
988         bzero(mta, ETH_ADDR_LEN * MAX_NUM_MULTICAST_ADDRESSES);
989
990         TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
991                 if (ifma->ifma_addr->sa_family != AF_LINK)
992                         continue;
993
994                 if (mcnt == MAX_NUM_MULTICAST_ADDRESSES)
995                         break;
996
997                 bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
998                     &mta[mcnt * ETH_ADDR_LEN], ETH_ADDR_LEN);
999                 mcnt++;
1000         }
1001
1002         if (mcnt >= MAX_NUM_MULTICAST_ADDRESSES) {
1003                 reg_rctl = E1000_READ_REG(&sc->hw, E1000_RCTL);
1004                 reg_rctl |= E1000_RCTL_MPE;
1005                 E1000_WRITE_REG(&sc->hw, E1000_RCTL, reg_rctl);
1006         } else {
1007                 e1000_update_mc_addr_list(&sc->hw, mta, mcnt);
1008         }
1009 }
1010
1011 static void
1012 igb_timer(void *xsc)
1013 {
1014         struct igb_softc *sc = xsc;
1015         struct ifnet *ifp = &sc->arpcom.ac_if;
1016
1017         ifnet_serialize_all(ifp);
1018
1019         igb_update_link_status(sc);
1020         igb_update_stats_counters(sc);
1021
1022         callout_reset(&sc->timer, hz, igb_timer, sc);
1023
1024         ifnet_deserialize_all(ifp);
1025 }
1026
1027 static void
1028 igb_update_link_status(struct igb_softc *sc)
1029 {
1030         struct ifnet *ifp = &sc->arpcom.ac_if;
1031         struct e1000_hw *hw = &sc->hw;
1032         uint32_t link_check, thstat, ctrl;
1033
1034         link_check = thstat = ctrl = 0;
1035
1036         /* Get the cached link value or read for real */
1037         switch (hw->phy.media_type) {
1038         case e1000_media_type_copper:
1039                 if (hw->mac.get_link_status) {
1040                         /* Do the work to read phy */
1041                         e1000_check_for_link(hw);
1042                         link_check = !hw->mac.get_link_status;
1043                 } else {
1044                         link_check = TRUE;
1045                 }
1046                 break;
1047
1048         case e1000_media_type_fiber:
1049                 e1000_check_for_link(hw);
1050                 link_check = E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU;
1051                 break;
1052
1053         case e1000_media_type_internal_serdes:
1054                 e1000_check_for_link(hw);
1055                 link_check = hw->mac.serdes_has_link;
1056                 break;
1057
1058         /* VF device is type_unknown */
1059         case e1000_media_type_unknown:
1060                 e1000_check_for_link(hw);
1061                 link_check = !hw->mac.get_link_status;
1062                 /* Fall thru */
1063         default:
1064                 break;
1065         }
1066
1067         /* Check for thermal downshift or shutdown */
1068         if (hw->mac.type == e1000_i350) {
1069                 thstat = E1000_READ_REG(hw, E1000_THSTAT);
1070                 ctrl = E1000_READ_REG(hw, E1000_CTRL_EXT);
1071         }
1072
1073         /* Now we check if a transition has happened */
1074         if (link_check && sc->link_active == 0) {
1075                 e1000_get_speed_and_duplex(hw, 
1076                     &sc->link_speed, &sc->link_duplex);
1077                 if (bootverbose) {
1078                         if_printf(ifp, "Link is up %d Mbps %s\n",
1079                             sc->link_speed,
1080                             sc->link_duplex == FULL_DUPLEX ?
1081                             "Full Duplex" : "Half Duplex");
1082                 }
1083                 sc->link_active = 1;
1084
1085                 ifp->if_baudrate = sc->link_speed * 1000000;
1086                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1087                     (thstat & E1000_THSTAT_LINK_THROTTLE))
1088                         if_printf(ifp, "Link: thermal downshift\n");
1089                 /* This can sleep */
1090                 ifp->if_link_state = LINK_STATE_UP;
1091                 if_link_state_change(ifp);
1092         } else if (!link_check && sc->link_active == 1) {
1093                 ifp->if_baudrate = sc->link_speed = 0;
1094                 sc->link_duplex = 0;
1095                 if (bootverbose)
1096                         if_printf(ifp, "Link is Down\n");
1097                 if ((ctrl & E1000_CTRL_EXT_LINK_MODE_GMII) &&
1098                     (thstat & E1000_THSTAT_PWR_DOWN))
1099                         if_printf(ifp, "Link: thermal shutdown\n");
1100                 sc->link_active = 0;
1101                 /* This can sleep */
1102                 ifp->if_link_state = LINK_STATE_DOWN;
1103                 if_link_state_change(ifp);
1104         }
1105 }
1106
1107 static void
1108 igb_stop(struct igb_softc *sc)
1109 {
1110         struct ifnet *ifp = &sc->arpcom.ac_if;
1111         int i;
1112
1113         ASSERT_IFNET_SERIALIZED_ALL(ifp);
1114
1115         igb_disable_intr(sc);
1116
1117         callout_stop(&sc->timer);
1118
1119         ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE);
1120         ifp->if_timer = 0;
1121
1122         e1000_reset_hw(&sc->hw);
1123         E1000_WRITE_REG(&sc->hw, E1000_WUC, 0);
1124
1125         e1000_led_off(&sc->hw);
1126         e1000_cleanup_led(&sc->hw);
1127
1128         for (i = 0; i < sc->num_queues; ++i)
1129                 igb_free_tx_ring(&sc->tx_rings[i]);
1130         for (i = 0; i < sc->num_queues; ++i)
1131                 igb_free_rx_ring(&sc->rx_rings[i]);
1132 }
1133
1134 static void
1135 igb_reset(struct igb_softc *sc)
1136 {
1137         struct ifnet *ifp = &sc->arpcom.ac_if;
1138         struct e1000_hw *hw = &sc->hw;
1139         struct e1000_fc_info *fc = &hw->fc;
1140         uint32_t pba = 0;
1141         uint16_t hwm;
1142
1143         /* Let the firmware know the OS is in control */
1144         igb_get_hw_control(sc);
1145
1146         /*
1147          * Packet Buffer Allocation (PBA)
1148          * Writing PBA sets the receive portion of the buffer
1149          * the remainder is used for the transmit buffer.
1150          */
1151         switch (hw->mac.type) {
1152         case e1000_82575:
1153                 pba = E1000_PBA_32K;
1154                 break;
1155
1156         case e1000_82576:
1157         case e1000_vfadapt:
1158                 pba = E1000_READ_REG(hw, E1000_RXPBS);
1159                 pba &= E1000_RXPBS_SIZE_MASK_82576;
1160                 break;
1161
1162         case e1000_82580:
1163         case e1000_i350:
1164         case e1000_vfadapt_i350:
1165                 pba = E1000_READ_REG(hw, E1000_RXPBS);
1166                 pba = e1000_rxpbs_adjust_82580(pba);
1167                 break;
1168                 /* XXX pba = E1000_PBA_35K; */
1169
1170         default:
1171                 break;
1172         }
1173
1174         /* Special needs in case of Jumbo frames */
1175         if (hw->mac.type == e1000_82575 && ifp->if_mtu > ETHERMTU) {
1176                 uint32_t tx_space, min_tx, min_rx;
1177
1178                 pba = E1000_READ_REG(hw, E1000_PBA);
1179                 tx_space = pba >> 16;
1180                 pba &= 0xffff;
1181
1182                 min_tx = (sc->max_frame_size +
1183                     sizeof(struct e1000_tx_desc) - ETHER_CRC_LEN) * 2;
1184                 min_tx = roundup2(min_tx, 1024);
1185                 min_tx >>= 10;
1186                 min_rx = sc->max_frame_size;
1187                 min_rx = roundup2(min_rx, 1024);
1188                 min_rx >>= 10;
1189                 if (tx_space < min_tx && (min_tx - tx_space) < pba) {
1190                         pba = pba - (min_tx - tx_space);
1191                         /*
1192                          * if short on rx space, rx wins
1193                          * and must trump tx adjustment
1194                          */
1195                         if (pba < min_rx)
1196                                 pba = min_rx;
1197                 }
1198                 E1000_WRITE_REG(hw, E1000_PBA, pba);
1199         }
1200
1201         /*
1202          * These parameters control the automatic generation (Tx) and
1203          * response (Rx) to Ethernet PAUSE frames.
1204          * - High water mark should allow for at least two frames to be
1205          *   received after sending an XOFF.
1206          * - Low water mark works best when it is very near the high water mark.
1207          *   This allows the receiver to restart by sending XON when it has
1208          *   drained a bit.
1209          */
1210         hwm = min(((pba << 10) * 9 / 10),
1211             ((pba << 10) - 2 * sc->max_frame_size));
1212
1213         if (hw->mac.type < e1000_82576) {
1214                 fc->high_water = hwm & 0xFFF8; /* 8-byte granularity */
1215                 fc->low_water = fc->high_water - 8;
1216         } else {
1217                 fc->high_water = hwm & 0xFFF0; /* 16-byte granularity */
1218                 fc->low_water = fc->high_water - 16;
1219         }
1220         fc->pause_time = IGB_FC_PAUSE_TIME;
1221         fc->send_xon = TRUE;
1222
1223         /* Issue a global reset */
1224         e1000_reset_hw(hw);
1225         E1000_WRITE_REG(hw, E1000_WUC, 0);
1226
1227         if (e1000_init_hw(hw) < 0)
1228                 if_printf(ifp, "Hardware Initialization Failed\n");
1229
1230         /* Setup DMA Coalescing */
1231         if (hw->mac.type == e1000_i350 && sc->dma_coalesce) {
1232                 uint32_t reg;
1233
1234                 hwm = (pba - 4) << 10;
1235                 reg = ((pba - 6) << E1000_DMACR_DMACTHR_SHIFT)
1236                     & E1000_DMACR_DMACTHR_MASK;
1237
1238                 /* transition to L0x or L1 if available..*/
1239                 reg |= (E1000_DMACR_DMAC_EN | E1000_DMACR_DMAC_LX_MASK);
1240
1241                 /* timer = +-1000 usec in 32usec intervals */
1242                 reg |= (1000 >> 5);
1243                 E1000_WRITE_REG(hw, E1000_DMACR, reg);
1244
1245                 /* No lower threshold */
1246                 E1000_WRITE_REG(hw, E1000_DMCRTRH, 0);
1247
1248                 /* set hwm to PBA -  2 * max frame size */
1249                 E1000_WRITE_REG(hw, E1000_FCRTC, hwm);
1250
1251                 /* Set the interval before transition */
1252                 reg = E1000_READ_REG(hw, E1000_DMCTLX);
1253                 reg |= 0x800000FF; /* 255 usec */
1254                 E1000_WRITE_REG(hw, E1000_DMCTLX, reg);
1255
1256                 /* free space in tx packet buffer to wake from DMA coal */
1257                 E1000_WRITE_REG(hw, E1000_DMCTXTH,
1258                     (20480 - (2 * sc->max_frame_size)) >> 6);
1259
1260                 /* make low power state decision controlled by DMA coal */
1261                 reg = E1000_READ_REG(hw, E1000_PCIEMISC);
1262                 E1000_WRITE_REG(hw, E1000_PCIEMISC,
1263                     reg | E1000_PCIEMISC_LX_DECISION);
1264                 if_printf(ifp, "DMA Coalescing enabled\n");
1265         }
1266
1267         E1000_WRITE_REG(&sc->hw, E1000_VET, ETHERTYPE_VLAN);
1268         e1000_get_phy_info(hw);
1269         e1000_check_for_link(hw);
1270 }
1271
1272 static void
1273 igb_setup_ifp(struct igb_softc *sc)
1274 {
1275         struct ifnet *ifp = &sc->arpcom.ac_if;
1276
1277         if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev));
1278         ifp->if_softc = sc;
1279         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1280         ifp->if_init =  igb_init;
1281         ifp->if_ioctl = igb_ioctl;
1282         ifp->if_start = igb_start;
1283 #ifdef DEVICE_POLLING
1284         ifp->if_poll = igb_poll;
1285 #endif
1286         ifp->if_watchdog = igb_watchdog;
1287
1288         ifq_set_maxlen(&ifp->if_snd, sc->num_tx_desc - 1);
1289         ifq_set_ready(&ifp->if_snd);
1290
1291         ether_ifattach(ifp, sc->hw.mac.addr, NULL);
1292
1293         ifp->if_capabilities =
1294             IFCAP_HWCSUM | IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU;
1295         ifp->if_capenable = ifp->if_capabilities;
1296         ifp->if_hwassist = IGB_CSUM_FEATURES;
1297
1298         /*
1299          * Tell the upper layer(s) we support long frames
1300          */
1301         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
1302
1303         /*
1304          * Specify the media types supported by this adapter and register
1305          * callbacks to update media and link information
1306          */
1307         ifmedia_init(&sc->media, IFM_IMASK, igb_media_change, igb_media_status);
1308         if (sc->hw.phy.media_type == e1000_media_type_fiber ||
1309             sc->hw.phy.media_type == e1000_media_type_internal_serdes) {
1310                 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX | IFM_FDX,
1311                     0, NULL);
1312                 ifmedia_add(&sc->media, IFM_ETHER | IFM_1000_SX, 0, NULL);
1313         } else {
1314                 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T, 0, NULL);
1315                 ifmedia_add(&sc->media, IFM_ETHER | IFM_10_T | IFM_FDX,
1316                     0, NULL);
1317                 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX, 0, NULL);
1318                 ifmedia_add(&sc->media, IFM_ETHER | IFM_100_TX | IFM_FDX,
1319                     0, NULL);
1320                 if (sc->hw.phy.type != e1000_phy_ife) {
1321                         ifmedia_add(&sc->media,
1322                             IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1323                         ifmedia_add(&sc->media,
1324                             IFM_ETHER | IFM_1000_T, 0, NULL);
1325                 }
1326         }
1327         ifmedia_add(&sc->media, IFM_ETHER | IFM_AUTO, 0, NULL);
1328         ifmedia_set(&sc->media, IFM_ETHER | IFM_AUTO);
1329 }
1330
1331 static void
1332 igb_add_sysctl(struct igb_softc *sc)
1333 {
1334         sysctl_ctx_init(&sc->sysctl_ctx);
1335         sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
1336             SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
1337             device_get_nameunit(sc->dev), CTLFLAG_RD, 0, "");
1338         if (sc->sysctl_tree == NULL) {
1339                 device_printf(sc->dev, "can't add sysctl node\n");
1340                 return;
1341         }
1342
1343         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1344             OID_AUTO, "rxd", CTLFLAG_RD, &sc->num_rx_desc, 0, NULL);
1345         SYSCTL_ADD_INT(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1346             OID_AUTO, "txd", CTLFLAG_RD, &sc->num_tx_desc, 0, NULL);
1347
1348         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1349             OID_AUTO, "intr_rate", CTLTYPE_INT | CTLFLAG_RW,
1350             sc, 0, igb_sysctl_intr_rate, "I", "interrupt rate");
1351
1352         SYSCTL_ADD_PROC(&sc->sysctl_ctx, SYSCTL_CHILDREN(sc->sysctl_tree),
1353             OID_AUTO, "tx_intr_nsegs", CTLTYPE_INT | CTLFLAG_RW,
1354             sc, 0, igb_sysctl_tx_intr_nsegs, "I",
1355             "# segments per TX interrupt");
1356 }
1357
1358 static int
1359 igb_dma_alloc(struct igb_softc *sc)
1360 {
1361         int error, i;
1362
1363         /* First allocate the top level queue structs */
1364         sc->queues = kmalloc(sizeof(struct igb_queue) * sc->num_queues,
1365             M_DEVBUF, M_WAITOK | M_ZERO);
1366
1367         /*
1368          * Create top level busdma tag
1369          */
1370         error = bus_dma_tag_create(NULL, 1, 0,
1371             BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL,
1372             BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0,
1373             &sc->parent_tag);
1374         if (error) {
1375                 device_printf(sc->dev, "could not create top level DMA tag\n");
1376                 return error;
1377         }
1378
1379         /*
1380          * Allocate TX descriptor rings and buffers
1381          */
1382         sc->tx_rings = kmalloc(sizeof(struct igb_tx_ring) * sc->num_queues,
1383             M_DEVBUF, M_WAITOK | M_ZERO);
1384         for (i = 0; i < sc->num_queues; ++i) {
1385                 struct igb_tx_ring *txr = &sc->tx_rings[i];
1386
1387                 /* Set up some basics */
1388                 txr->sc = sc;
1389                 txr->me = i;
1390
1391                 error = igb_create_tx_ring(txr);
1392                 if (error)
1393                         return error;
1394         }
1395
1396         /*
1397          * Allocate RX descriptor rings and buffers
1398          */ 
1399         sc->rx_rings = kmalloc(sizeof(struct igb_rx_ring) * sc->num_queues,
1400             M_DEVBUF, M_WAITOK | M_ZERO);
1401         for (i = 0; i < sc->num_queues; ++i) {
1402                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
1403
1404                 /* Set up some basics */
1405                 rxr->sc = sc;
1406                 rxr->me = i;
1407
1408                 error = igb_create_rx_ring(rxr);
1409                 if (error)
1410                         return error;
1411         }
1412
1413         /*
1414          * Finally set up the queue holding structs
1415          */
1416         for (i = 0; i < sc->num_queues; i++) {
1417                 struct igb_queue *que = &sc->queues[i];
1418
1419                 que->sc = sc;
1420                 que->txr = &sc->tx_rings[i];
1421                 que->rxr = &sc->rx_rings[i];
1422         }
1423         return 0;
1424 }
1425
1426 static void
1427 igb_dma_free(struct igb_softc *sc)
1428 {
1429         int i;
1430
1431         if (sc->queues != NULL)
1432                 kfree(sc->queues, M_DEVBUF);
1433
1434         if (sc->tx_rings != NULL) {
1435                 for (i = 0; i < sc->num_queues; ++i)
1436                         igb_destroy_tx_ring(&sc->tx_rings[i], sc->num_tx_desc);
1437                 kfree(sc->tx_rings, M_DEVBUF);
1438         }
1439
1440         if (sc->rx_rings != NULL) {
1441                 for (i = 0; i < sc->num_queues; ++i)
1442                         igb_destroy_rx_ring(&sc->rx_rings[i], sc->num_rx_desc);
1443                 kfree(sc->rx_rings, M_DEVBUF);
1444         }
1445 }
1446
1447 static int
1448 igb_create_tx_ring(struct igb_tx_ring *txr)
1449 {
1450         int tsize, error, i;
1451
1452         /*
1453          * Validate number of transmit descriptors. It must not exceed
1454          * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
1455          */
1456         if (((igb_txd * sizeof(struct e1000_tx_desc)) % IGB_DBA_ALIGN) != 0 ||
1457             (igb_txd > IGB_MAX_TXD) || (igb_txd < IGB_MIN_TXD)) {
1458                 device_printf(txr->sc->dev,
1459                     "Using %d TX descriptors instead of %d!\n",
1460                     IGB_DEFAULT_TXD, igb_txd);
1461                 txr->sc->num_tx_desc = IGB_DEFAULT_TXD;
1462         } else {
1463                 txr->sc->num_tx_desc = igb_txd;
1464         }
1465
1466         /*
1467          * Allocate TX descriptor ring
1468          */
1469         tsize = roundup2(txr->sc->num_tx_desc * sizeof(union e1000_adv_tx_desc),
1470             IGB_DBA_ALIGN);
1471         txr->txdma.dma_vaddr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1472             IGB_DBA_ALIGN, tsize, BUS_DMA_WAITOK,
1473             &txr->txdma.dma_tag, &txr->txdma.dma_map, &txr->txdma.dma_paddr);
1474         if (txr->txdma.dma_vaddr == NULL) {
1475                 device_printf(txr->sc->dev,
1476                     "Unable to allocate TX Descriptor memory\n");
1477                 return ENOMEM;
1478         }
1479         txr->tx_base = txr->txdma.dma_vaddr;
1480         bzero(txr->tx_base, tsize);
1481
1482         txr->tx_buf = kmalloc(sizeof(struct igb_tx_buf) * txr->sc->num_tx_desc,
1483             M_DEVBUF, M_WAITOK | M_ZERO);
1484
1485         /*
1486          * Allocate TX head write-back buffer
1487          */
1488         txr->tx_hdr = bus_dmamem_coherent_any(txr->sc->parent_tag,
1489             __VM_CACHELINE_SIZE, __VM_CACHELINE_SIZE, BUS_DMA_WAITOK,
1490             &txr->tx_hdr_dtag, &txr->tx_hdr_dmap, &txr->tx_hdr_paddr);
1491         if (txr->tx_hdr == NULL) {
1492                 device_printf(txr->sc->dev,
1493                     "Unable to allocate TX head write-back buffer\n");
1494                 return ENOMEM;
1495         }
1496
1497         /*
1498          * Create DMA tag for TX buffers
1499          */
1500         error = bus_dma_tag_create(txr->sc->parent_tag,
1501             1, 0,               /* alignment, bounds */
1502             BUS_SPACE_MAXADDR,  /* lowaddr */
1503             BUS_SPACE_MAXADDR,  /* highaddr */
1504             NULL, NULL,         /* filter, filterarg */
1505             IGB_TSO_SIZE,       /* maxsize */
1506             IGB_MAX_SCATTER,    /* nsegments */
1507             PAGE_SIZE,          /* maxsegsize */
1508             BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW |
1509             BUS_DMA_ONEBPAGE,   /* flags */
1510             &txr->tx_tag);
1511         if (error) {
1512                 device_printf(txr->sc->dev, "Unable to allocate TX DMA tag\n");
1513                 kfree(txr->tx_buf, M_DEVBUF);
1514                 txr->tx_buf = NULL;
1515                 return error;
1516         }
1517
1518         /*
1519          * Create DMA maps for TX buffers
1520          */
1521         for (i = 0; i < txr->sc->num_tx_desc; ++i) {
1522                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1523
1524                 error = bus_dmamap_create(txr->tx_tag,
1525                     BUS_DMA_WAITOK | BUS_DMA_ONEBPAGE, &txbuf->map);
1526                 if (error) {
1527                         device_printf(txr->sc->dev,
1528                             "Unable to create TX DMA map\n");
1529                         igb_destroy_tx_ring(txr, i);
1530                         return error;
1531                 }
1532         }
1533
1534         /*
1535          * Initialize various watermark
1536          */
1537         txr->spare_desc = IGB_TX_SPARE;
1538         txr->intr_nsegs = txr->sc->num_tx_desc / 16;
1539         txr->oact_hi_desc = txr->sc->num_tx_desc / 2;
1540         txr->oact_lo_desc = txr->sc->num_tx_desc / 8;
1541         if (txr->oact_lo_desc > IGB_TX_OACTIVE_MAX)
1542                 txr->oact_lo_desc = IGB_TX_OACTIVE_MAX;
1543         if (txr->oact_lo_desc < txr->spare_desc + IGB_TX_RESERVED)
1544                 txr->oact_lo_desc = txr->spare_desc + IGB_TX_RESERVED;
1545
1546         return 0;
1547 }
1548
1549 static void
1550 igb_free_tx_ring(struct igb_tx_ring *txr)
1551 {
1552         int i;
1553
1554         for (i = 0; i < txr->sc->num_tx_desc; ++i) {
1555                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1556
1557                 if (txbuf->m_head != NULL) {
1558                         bus_dmamap_unload(txr->tx_tag, txbuf->map);
1559                         m_freem(txbuf->m_head);
1560                         txbuf->m_head = NULL;
1561                 }
1562         }
1563 }
1564
1565 static void
1566 igb_destroy_tx_ring(struct igb_tx_ring *txr, int ndesc)
1567 {
1568         int i;
1569
1570         if (txr->txdma.dma_vaddr != NULL) {
1571                 bus_dmamap_unload(txr->txdma.dma_tag, txr->txdma.dma_map);
1572                 bus_dmamem_free(txr->txdma.dma_tag, txr->txdma.dma_vaddr,
1573                     txr->txdma.dma_map);
1574                 bus_dma_tag_destroy(txr->txdma.dma_tag);
1575                 txr->txdma.dma_vaddr = NULL;
1576         }
1577
1578         if (txr->tx_hdr != NULL) {
1579                 bus_dmamap_unload(txr->tx_hdr_dtag, txr->tx_hdr_dmap);
1580                 bus_dmamem_free(txr->tx_hdr_dtag, txr->tx_hdr,
1581                     txr->tx_hdr_dmap);
1582                 bus_dma_tag_destroy(txr->tx_hdr_dtag);
1583                 txr->tx_hdr = NULL;
1584         }
1585
1586         if (txr->tx_buf == NULL)
1587                 return;
1588
1589         for (i = 0; i < ndesc; ++i) {
1590                 struct igb_tx_buf *txbuf = &txr->tx_buf[i];
1591
1592                 KKASSERT(txbuf->m_head == NULL);
1593                 bus_dmamap_destroy(txr->tx_tag, txbuf->map);
1594         }
1595         bus_dma_tag_destroy(txr->tx_tag);
1596
1597         kfree(txr->tx_buf, M_DEVBUF);
1598         txr->tx_buf = NULL;
1599 }
1600
1601 static void
1602 igb_init_tx_ring(struct igb_tx_ring *txr)
1603 {
1604         /* Clear the old descriptor contents */
1605         bzero(txr->tx_base,
1606             sizeof(union e1000_adv_tx_desc) * txr->sc->num_tx_desc);
1607
1608         /* Clear TX head write-back buffer */
1609         *(txr->tx_hdr) = 0;
1610
1611         /* Reset indices */
1612         txr->next_avail_desc = 0;
1613         txr->next_to_clean = 0;
1614         txr->tx_nsegs = 0;
1615
1616         /* Set number of descriptors available */
1617         txr->tx_avail = txr->sc->num_tx_desc;
1618 }
1619
1620 static void
1621 igb_init_tx_unit(struct igb_softc *sc)
1622 {
1623         struct e1000_hw *hw = &sc->hw;
1624         uint32_t tctl;
1625         int i;
1626
1627         /* Setup the Tx Descriptor Rings */
1628         for (i = 0; i < sc->num_queues; ++i) {
1629                 struct igb_tx_ring *txr = &sc->tx_rings[i];
1630                 uint64_t bus_addr = txr->txdma.dma_paddr;
1631                 uint32_t txdctl = 0;
1632                 uint32_t dca_txctrl;
1633
1634                 E1000_WRITE_REG(hw, E1000_TDLEN(i),
1635                     sc->num_tx_desc * sizeof(struct e1000_tx_desc));
1636                 E1000_WRITE_REG(hw, E1000_TDBAH(i),
1637                     (uint32_t)(bus_addr >> 32));
1638                 E1000_WRITE_REG(hw, E1000_TDBAL(i),
1639                     (uint32_t)bus_addr);
1640
1641                 /* Setup the HW Tx Head and Tail descriptor pointers */
1642                 E1000_WRITE_REG(hw, E1000_TDT(i), 0);
1643                 E1000_WRITE_REG(hw, E1000_TDH(i), 0);
1644
1645                 txdctl |= IGB_TX_PTHRESH;
1646                 txdctl |= IGB_TX_HTHRESH << 8;
1647                 txdctl |= IGB_TX_WTHRESH << 16;
1648                 txdctl |= E1000_TXDCTL_QUEUE_ENABLE;
1649                 E1000_WRITE_REG(hw, E1000_TXDCTL(i), txdctl);
1650
1651                 dca_txctrl = E1000_READ_REG(hw, E1000_DCA_TXCTRL(i));
1652                 dca_txctrl &= ~E1000_DCA_TXCTRL_TX_WB_RO_EN;
1653                 E1000_WRITE_REG(hw, E1000_DCA_TXCTRL(i), dca_txctrl);
1654
1655                 E1000_WRITE_REG(hw, E1000_TDWBAH(i),
1656                     (uint32_t)(txr->tx_hdr_paddr >> 32));
1657                 E1000_WRITE_REG(hw, E1000_TDWBAL(i),
1658                     ((uint32_t)txr->tx_hdr_paddr) | E1000_TX_HEAD_WB_ENABLE);
1659         }
1660
1661         if (sc->vf_ifp)
1662                 return;
1663
1664         e1000_config_collision_dist(hw);
1665
1666         /* Program the Transmit Control Register */
1667         tctl = E1000_READ_REG(hw, E1000_TCTL);
1668         tctl &= ~E1000_TCTL_CT;
1669         tctl |= (E1000_TCTL_PSP | E1000_TCTL_RTLC | E1000_TCTL_EN |
1670             (E1000_COLLISION_THRESHOLD << E1000_CT_SHIFT));
1671
1672         /* This write will effectively turn on the transmit unit. */
1673         E1000_WRITE_REG(hw, E1000_TCTL, tctl);
1674 }
1675
1676 static boolean_t
1677 igb_txctx(struct igb_tx_ring *txr, struct mbuf *mp)
1678 {
1679         struct e1000_adv_tx_context_desc *TXD;
1680         struct igb_tx_buf *txbuf;
1681         uint32_t vlan_macip_lens, type_tucmd_mlhl, mss_l4len_idx;
1682         struct ether_vlan_header *eh;
1683         struct ip *ip = NULL;
1684         int ehdrlen, ctxd, ip_hlen = 0;
1685         uint16_t etype, vlantag = 0;
1686         boolean_t offload = TRUE;
1687
1688         if ((mp->m_pkthdr.csum_flags & IGB_CSUM_FEATURES) == 0)
1689                 offload = FALSE;
1690
1691         vlan_macip_lens = type_tucmd_mlhl = mss_l4len_idx = 0;
1692         ctxd = txr->next_avail_desc;
1693         txbuf = &txr->tx_buf[ctxd];
1694         TXD = (struct e1000_adv_tx_context_desc *)&txr->tx_base[ctxd];
1695
1696         /*
1697          * In advanced descriptors the vlan tag must 
1698          * be placed into the context descriptor, thus
1699          * we need to be here just for that setup.
1700          */
1701         if (mp->m_flags & M_VLANTAG) {
1702                 vlantag = htole16(mp->m_pkthdr.ether_vlantag);
1703                 vlan_macip_lens |= (vlantag << E1000_ADVTXD_VLAN_SHIFT);
1704         } else if (!offload) {
1705                 return FALSE;
1706         }
1707
1708         /*
1709          * Determine where frame payload starts.
1710          * Jump over vlan headers if already present,
1711          * helpful for QinQ too.
1712          */
1713         KASSERT(mp->m_len >= ETHER_HDR_LEN,
1714             ("igb_txctx_pullup is not called (eh)?\n"));
1715         eh = mtod(mp, struct ether_vlan_header *);
1716         if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
1717                 KASSERT(mp->m_len >= ETHER_HDR_LEN + EVL_ENCAPLEN,
1718                     ("igb_txctx_pullup is not called (evh)?\n"));
1719                 etype = ntohs(eh->evl_proto);
1720                 ehdrlen = ETHER_HDR_LEN + EVL_ENCAPLEN;
1721         } else {
1722                 etype = ntohs(eh->evl_encap_proto);
1723                 ehdrlen = ETHER_HDR_LEN;
1724         }
1725
1726         /* Set the ether header length */
1727         vlan_macip_lens |= ehdrlen << E1000_ADVTXD_MACLEN_SHIFT;
1728
1729         switch (etype) {
1730         case ETHERTYPE_IP:
1731                 KASSERT(mp->m_len >= ehdrlen + IGB_IPVHL_SIZE,
1732                     ("igb_txctx_pullup is not called (eh+ip_vhl)?\n"));
1733
1734                 /* NOTE: We could only safely access ip.ip_vhl part */
1735                 ip = (struct ip *)(mp->m_data + ehdrlen);
1736                 ip_hlen = ip->ip_hl << 2;
1737
1738                 if (mp->m_pkthdr.csum_flags & CSUM_IP)
1739                         type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV4;
1740                 break;
1741
1742 #ifdef notyet
1743         case ETHERTYPE_IPV6:
1744                 ip6 = (struct ip6_hdr *)(mp->m_data + ehdrlen);
1745                 ip_hlen = sizeof(struct ip6_hdr);
1746                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_IPV6;
1747                 break;
1748 #endif
1749
1750         default:
1751                 offload = FALSE;
1752                 break;
1753         }
1754
1755         vlan_macip_lens |= ip_hlen;
1756         type_tucmd_mlhl |= E1000_ADVTXD_DCMD_DEXT | E1000_ADVTXD_DTYP_CTXT;
1757
1758         if (mp->m_pkthdr.csum_flags & CSUM_TCP)
1759                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_TCP;
1760         else if (mp->m_pkthdr.csum_flags & CSUM_UDP)
1761                 type_tucmd_mlhl |= E1000_ADVTXD_TUCMD_L4T_UDP;
1762
1763         /* 82575 needs the queue index added */
1764         if (txr->sc->hw.mac.type == e1000_82575)
1765                 mss_l4len_idx = txr->me << 4;
1766
1767         /* Now copy bits into descriptor */
1768         TXD->vlan_macip_lens = htole32(vlan_macip_lens);
1769         TXD->type_tucmd_mlhl = htole32(type_tucmd_mlhl);
1770         TXD->seqnum_seed = htole32(0);
1771         TXD->mss_l4len_idx = htole32(mss_l4len_idx);
1772
1773         txbuf->m_head = NULL;
1774
1775         /* We've consumed the first desc, adjust counters */
1776         if (++ctxd == txr->sc->num_tx_desc)
1777                 ctxd = 0;
1778         txr->next_avail_desc = ctxd;
1779         --txr->tx_avail;
1780
1781         return offload;
1782 }
1783
1784 static void
1785 igb_txeof(struct igb_tx_ring *txr)
1786 {
1787         struct ifnet *ifp = &txr->sc->arpcom.ac_if;
1788         int first, hdr, avail;
1789
1790         if (txr->tx_avail == txr->sc->num_tx_desc)
1791                 return;
1792
1793         first = txr->next_to_clean;
1794         hdr = *(txr->tx_hdr);
1795
1796         if (first == hdr)
1797                 return;
1798
1799         avail = txr->tx_avail;
1800         while (first != hdr) {
1801                 struct igb_tx_buf *txbuf = &txr->tx_buf[first];
1802
1803                 ++avail;
1804                 if (txbuf->m_head) {
1805                         bus_dmamap_unload(txr->tx_tag, txbuf->map);
1806                         m_freem(txbuf->m_head);
1807                         txbuf->m_head = NULL;
1808                         ++ifp->if_opackets;
1809                 }
1810                 if (++first == txr->sc->num_tx_desc)
1811                         first = 0;
1812         }
1813         txr->next_to_clean = first;
1814         txr->tx_avail = avail;
1815
1816         /*
1817          * If we have a minimum free, clear IFF_OACTIVE
1818          * to tell the stack that it is OK to send packets.
1819          */
1820         if (IGB_IS_NOT_OACTIVE(txr)) {
1821                 ifp->if_flags &= ~IFF_OACTIVE;
1822
1823                 /*
1824                  * We have enough TX descriptors, turn off
1825                  * the watchdog.  We allow small amount of
1826                  * packets (roughly intr_nsegs) pending on
1827                  * the transmit ring.
1828                  */
1829                 ifp->if_timer = 0;
1830         }
1831 }
1832
1833 static int
1834 igb_create_rx_ring(struct igb_rx_ring *rxr)
1835 {
1836         int rsize, i, error;
1837
1838         /*
1839          * Validate number of receive descriptors. It must not exceed
1840          * hardware maximum, and must be multiple of IGB_DBA_ALIGN.
1841          */
1842         if (((igb_rxd * sizeof(struct e1000_rx_desc)) % IGB_DBA_ALIGN) != 0 ||
1843             (igb_rxd > IGB_MAX_RXD) || (igb_rxd < IGB_MIN_RXD)) {
1844                 device_printf(rxr->sc->dev,
1845                     "Using %d RX descriptors instead of %d!\n",
1846                     IGB_DEFAULT_RXD, igb_rxd);
1847                 rxr->sc->num_rx_desc = IGB_DEFAULT_RXD;
1848         } else {
1849                 rxr->sc->num_rx_desc = igb_rxd;
1850         }
1851
1852         /*
1853          * Allocate RX descriptor ring
1854          */
1855         rsize = roundup2(rxr->sc->num_rx_desc * sizeof(union e1000_adv_rx_desc),
1856             IGB_DBA_ALIGN);
1857         rxr->rxdma.dma_vaddr = bus_dmamem_coherent_any(rxr->sc->parent_tag,
1858             IGB_DBA_ALIGN, rsize, BUS_DMA_WAITOK,
1859             &rxr->rxdma.dma_tag, &rxr->rxdma.dma_map,
1860             &rxr->rxdma.dma_paddr);
1861         if (rxr->rxdma.dma_vaddr == NULL) {
1862                 device_printf(rxr->sc->dev,
1863                     "Unable to allocate RxDescriptor memory\n");
1864                 return ENOMEM;
1865         }
1866         rxr->rx_base = rxr->rxdma.dma_vaddr;
1867         bzero(rxr->rx_base, rsize);
1868
1869         rxr->rx_buf = kmalloc(sizeof(struct igb_rx_buf) * rxr->sc->num_rx_desc,
1870             M_DEVBUF, M_WAITOK | M_ZERO);
1871
1872         /*
1873          * Create DMA tag for RX buffers
1874          */
1875         error = bus_dma_tag_create(rxr->sc->parent_tag,
1876             1, 0,               /* alignment, bounds */
1877             BUS_SPACE_MAXADDR,  /* lowaddr */
1878             BUS_SPACE_MAXADDR,  /* highaddr */
1879             NULL, NULL,         /* filter, filterarg */
1880             MCLBYTES,           /* maxsize */
1881             1,                  /* nsegments */
1882             MCLBYTES,           /* maxsegsize */
1883             BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, /* flags */
1884             &rxr->rx_tag);
1885         if (error) {
1886                 device_printf(rxr->sc->dev,
1887                     "Unable to create RX payload DMA tag\n");
1888                 kfree(rxr->rx_buf, M_DEVBUF);
1889                 rxr->rx_buf = NULL;
1890                 return error;
1891         }
1892
1893         /*
1894          * Create spare DMA map for RX buffers
1895          */
1896         error = bus_dmamap_create(rxr->rx_tag, BUS_DMA_WAITOK,
1897             &rxr->rx_sparemap);
1898         if (error) {
1899                 device_printf(rxr->sc->dev,
1900                     "Unable to create spare RX DMA maps\n");
1901                 bus_dma_tag_destroy(rxr->rx_tag);
1902                 kfree(rxr->rx_buf, M_DEVBUF);
1903                 rxr->rx_buf = NULL;
1904                 return error;
1905         }
1906
1907         /*
1908          * Create DMA maps for RX buffers
1909          */
1910         for (i = 0; i < rxr->sc->num_rx_desc; i++) {
1911                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
1912
1913                 error = bus_dmamap_create(rxr->rx_tag,
1914                     BUS_DMA_WAITOK, &rxbuf->map);
1915                 if (error) {
1916                         device_printf(rxr->sc->dev,
1917                             "Unable to create RX DMA maps\n");
1918                         igb_destroy_rx_ring(rxr, i);
1919                         return error;
1920                 }
1921         }
1922         return 0;
1923 }
1924
1925 static void
1926 igb_free_rx_ring(struct igb_rx_ring *rxr)
1927 {
1928         int i;
1929
1930         for (i = 0; i < rxr->sc->num_rx_desc; ++i) {
1931                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
1932
1933                 if (rxbuf->m_head != NULL) {
1934                         bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
1935                         m_freem(rxbuf->m_head);
1936                         rxbuf->m_head = NULL;
1937                 }
1938         }
1939
1940         if (rxr->fmp != NULL)
1941                 m_freem(rxr->fmp);
1942         rxr->fmp = NULL;
1943         rxr->lmp = NULL;
1944 }
1945
1946 static void
1947 igb_destroy_rx_ring(struct igb_rx_ring *rxr, int ndesc)
1948 {
1949         int i;
1950
1951         if (rxr->rxdma.dma_vaddr != NULL) {
1952                 bus_dmamap_unload(rxr->rxdma.dma_tag, rxr->rxdma.dma_map);
1953                 bus_dmamem_free(rxr->rxdma.dma_tag, rxr->rxdma.dma_vaddr,
1954                     rxr->rxdma.dma_map);
1955                 bus_dma_tag_destroy(rxr->rxdma.dma_tag);
1956                 rxr->rxdma.dma_vaddr = NULL;
1957         }
1958
1959         if (rxr->rx_buf == NULL)
1960                 return;
1961
1962         for (i = 0; i < ndesc; ++i) {
1963                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
1964
1965                 KKASSERT(rxbuf->m_head == NULL);
1966                 bus_dmamap_destroy(rxr->rx_tag, rxbuf->map);
1967         }
1968         bus_dmamap_destroy(rxr->rx_tag, rxr->rx_sparemap);
1969         bus_dma_tag_destroy(rxr->rx_tag);
1970
1971         kfree(rxr->rx_buf, M_DEVBUF);
1972         rxr->rx_buf = NULL;
1973 }
1974
1975 static void
1976 igb_setup_rxdesc(union e1000_adv_rx_desc *rxd, const struct igb_rx_buf *rxbuf)
1977 {
1978         rxd->read.pkt_addr = htole64(rxbuf->paddr);
1979         rxd->wb.upper.status_error = 0;
1980 }
1981
1982 static int
1983 igb_newbuf(struct igb_rx_ring *rxr, int i, boolean_t wait)
1984 {
1985         struct mbuf *m;
1986         bus_dma_segment_t seg;
1987         bus_dmamap_t map;
1988         struct igb_rx_buf *rxbuf;
1989         int error, nseg;
1990
1991         m = m_getcl(wait ? MB_WAIT : MB_DONTWAIT, MT_DATA, M_PKTHDR);
1992         if (m == NULL) {
1993                 if (wait) {
1994                         if_printf(&rxr->sc->arpcom.ac_if,
1995                             "Unable to allocate RX mbuf\n");
1996                 }
1997                 return ENOBUFS;
1998         }
1999         m->m_len = m->m_pkthdr.len = MCLBYTES;
2000
2001         if (rxr->sc->max_frame_size <= MCLBYTES - ETHER_ALIGN)
2002                 m_adj(m, ETHER_ALIGN);
2003
2004         error = bus_dmamap_load_mbuf_segment(rxr->rx_tag,
2005             rxr->rx_sparemap, m, &seg, 1, &nseg, BUS_DMA_NOWAIT);
2006         if (error) {
2007                 m_freem(m);
2008                 if (wait) {
2009                         if_printf(&rxr->sc->arpcom.ac_if,
2010                             "Unable to load RX mbuf\n");
2011                 }
2012                 return error;
2013         }
2014
2015         rxbuf = &rxr->rx_buf[i];
2016         if (rxbuf->m_head != NULL)
2017                 bus_dmamap_unload(rxr->rx_tag, rxbuf->map);
2018
2019         map = rxbuf->map;
2020         rxbuf->map = rxr->rx_sparemap;
2021         rxr->rx_sparemap = map;
2022
2023         rxbuf->m_head = m;
2024         rxbuf->paddr = seg.ds_addr;
2025
2026         igb_setup_rxdesc(&rxr->rx_base[i], rxbuf);
2027         return 0;
2028 }
2029
2030 static int
2031 igb_init_rx_ring(struct igb_rx_ring *rxr)
2032 {
2033         int i;
2034
2035         /* Clear the ring contents */
2036         bzero(rxr->rx_base,
2037             rxr->sc->num_rx_desc * sizeof(union e1000_adv_rx_desc));
2038
2039         /* Now replenish the ring mbufs */
2040         for (i = 0; i < rxr->sc->num_rx_desc; ++i) {
2041                 int error;
2042
2043                 error = igb_newbuf(rxr, i, TRUE);
2044                 if (error)
2045                         return error;
2046         }
2047
2048         /* Setup our descriptor indices */
2049         rxr->next_to_check = 0;
2050
2051         rxr->fmp = NULL;
2052         rxr->lmp = NULL;
2053         rxr->discard = FALSE;
2054
2055         return 0;
2056 }
2057
2058 static void
2059 igb_init_rx_unit(struct igb_softc *sc)
2060 {
2061         struct ifnet *ifp = &sc->arpcom.ac_if;
2062         struct e1000_hw *hw = &sc->hw;
2063         uint32_t rctl, rxcsum, srrctl = 0;
2064         int i;
2065
2066         /*
2067          * Make sure receives are disabled while setting
2068          * up the descriptor ring
2069          */
2070         rctl = E1000_READ_REG(hw, E1000_RCTL);
2071         E1000_WRITE_REG(hw, E1000_RCTL, rctl & ~E1000_RCTL_EN);
2072
2073 #if 0
2074         /*
2075         ** Set up for header split
2076         */
2077         if (igb_header_split) {
2078                 /* Use a standard mbuf for the header */
2079                 srrctl |= IGB_HDR_BUF << E1000_SRRCTL_BSIZEHDRSIZE_SHIFT;
2080                 srrctl |= E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS;
2081         } else
2082 #endif
2083                 srrctl |= E1000_SRRCTL_DESCTYPE_ADV_ONEBUF;
2084
2085         /*
2086         ** Set up for jumbo frames
2087         */
2088         if (ifp->if_mtu > ETHERMTU) {
2089                 rctl |= E1000_RCTL_LPE;
2090 #if 0
2091                 if (adapter->rx_mbuf_sz == MJUMPAGESIZE) {
2092                         srrctl |= 4096 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2093                         rctl |= E1000_RCTL_SZ_4096 | E1000_RCTL_BSEX;
2094                 } else if (adapter->rx_mbuf_sz > MJUMPAGESIZE) {
2095                         srrctl |= 8192 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2096                         rctl |= E1000_RCTL_SZ_8192 | E1000_RCTL_BSEX;
2097                 }
2098                 /* Set maximum packet len */
2099                 psize = adapter->max_frame_size;
2100                 /* are we on a vlan? */
2101                 if (adapter->ifp->if_vlantrunk != NULL)
2102                         psize += VLAN_TAG_SIZE;
2103                 E1000_WRITE_REG(&adapter->hw, E1000_RLPML, psize);
2104 #else
2105                 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2106                 rctl |= E1000_RCTL_SZ_2048;
2107 #endif
2108         } else {
2109                 rctl &= ~E1000_RCTL_LPE;
2110                 srrctl |= 2048 >> E1000_SRRCTL_BSIZEPKT_SHIFT;
2111                 rctl |= E1000_RCTL_SZ_2048;
2112         }
2113
2114         /* Setup the Base and Length of the Rx Descriptor Rings */
2115         for (i = 0; i < sc->num_queues; ++i) {
2116                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2117                 uint64_t bus_addr = rxr->rxdma.dma_paddr;
2118                 uint32_t rxdctl;
2119
2120                 E1000_WRITE_REG(hw, E1000_RDLEN(i),
2121                     sc->num_rx_desc * sizeof(struct e1000_rx_desc));
2122                 E1000_WRITE_REG(hw, E1000_RDBAH(i),
2123                     (uint32_t)(bus_addr >> 32));
2124                 E1000_WRITE_REG(hw, E1000_RDBAL(i),
2125                     (uint32_t)bus_addr);
2126                 E1000_WRITE_REG(hw, E1000_SRRCTL(i), srrctl);
2127                 /* Enable this Queue */
2128                 rxdctl = E1000_READ_REG(hw, E1000_RXDCTL(i));
2129                 rxdctl |= E1000_RXDCTL_QUEUE_ENABLE;
2130                 rxdctl &= 0xFFF00000;
2131                 rxdctl |= IGB_RX_PTHRESH;
2132                 rxdctl |= IGB_RX_HTHRESH << 8;
2133                 rxdctl |= IGB_RX_WTHRESH << 16;
2134                 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl);
2135         }
2136
2137         /*
2138          * Setup for RX MultiQueue
2139          */
2140         rxcsum = E1000_READ_REG(hw, E1000_RXCSUM);
2141 #if 0
2142         if (adapter->num_queues >1) {
2143                 u32 random[10], mrqc, shift = 0;
2144                 union igb_reta {
2145                         u32 dword;
2146                         u8  bytes[4];
2147                 } reta;
2148
2149                 arc4rand(&random, sizeof(random), 0);
2150                 if (adapter->hw.mac.type == e1000_82575)
2151                         shift = 6;
2152                 /* Warning FM follows */
2153                 for (int i = 0; i < 128; i++) {
2154                         reta.bytes[i & 3] =
2155                             (i % adapter->num_queues) << shift;
2156                         if ((i & 3) == 3)
2157                                 E1000_WRITE_REG(hw,
2158                                     E1000_RETA(i >> 2), reta.dword);
2159                 }
2160                 /* Now fill in hash table */
2161                 mrqc = E1000_MRQC_ENABLE_RSS_4Q;
2162                 for (int i = 0; i < 10; i++)
2163                         E1000_WRITE_REG_ARRAY(hw,
2164                             E1000_RSSRK(0), i, random[i]);
2165
2166                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV4 |
2167                     E1000_MRQC_RSS_FIELD_IPV4_TCP);
2168                 mrqc |= (E1000_MRQC_RSS_FIELD_IPV6 |
2169                     E1000_MRQC_RSS_FIELD_IPV6_TCP);
2170                 mrqc |=( E1000_MRQC_RSS_FIELD_IPV4_UDP |
2171                     E1000_MRQC_RSS_FIELD_IPV6_UDP);
2172                 mrqc |=( E1000_MRQC_RSS_FIELD_IPV6_UDP_EX |
2173                     E1000_MRQC_RSS_FIELD_IPV6_TCP_EX);
2174
2175                 E1000_WRITE_REG(hw, E1000_MRQC, mrqc);
2176
2177                 /*
2178                 ** NOTE: Receive Full-Packet Checksum Offload 
2179                 ** is mutually exclusive with Multiqueue. However
2180                 ** this is not the same as TCP/IP checksums which
2181                 ** still work.
2182                 */
2183                 rxcsum |= E1000_RXCSUM_PCSD;
2184         } else
2185 #endif
2186         {
2187                 /* Non RSS setup */
2188                 if (ifp->if_capenable & IFCAP_RXCSUM)
2189                         rxcsum |= E1000_RXCSUM_IPPCSE;
2190                 else
2191                         rxcsum &= ~E1000_RXCSUM_TUOFL;
2192         }
2193         E1000_WRITE_REG(hw, E1000_RXCSUM, rxcsum);
2194
2195         /* Setup the Receive Control Register */
2196         rctl &= ~(3 << E1000_RCTL_MO_SHIFT);
2197         rctl |= E1000_RCTL_EN | E1000_RCTL_BAM | E1000_RCTL_LBM_NO |
2198             E1000_RCTL_RDMTS_HALF |
2199             (hw->mac.mc_filter_type << E1000_RCTL_MO_SHIFT);
2200         /* Strip CRC bytes. */
2201         rctl |= E1000_RCTL_SECRC;
2202         /* Make sure VLAN Filters are off */
2203         rctl &= ~E1000_RCTL_VFE;
2204         /* Don't store bad packets */
2205         rctl &= ~E1000_RCTL_SBP;
2206
2207         /* Enable Receives */
2208         E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2209
2210         /*
2211          * Setup the HW Rx Head and Tail Descriptor Pointers
2212          *   - needs to be after enable
2213          */
2214         for (i = 0; i < sc->num_queues; ++i) {
2215                 struct igb_rx_ring *rxr = &sc->rx_rings[i];
2216
2217                 E1000_WRITE_REG(hw, E1000_RDH(i), rxr->next_to_check);
2218                 E1000_WRITE_REG(hw, E1000_RDT(i), rxr->sc->num_rx_desc - 1);
2219         }
2220 }
2221
2222 static void
2223 igb_rxeof(struct igb_rx_ring *rxr, int count)
2224 {
2225         struct ifnet *ifp = &rxr->sc->arpcom.ac_if;
2226         union e1000_adv_rx_desc *cur;
2227         uint32_t staterr;
2228         int i;
2229
2230         i = rxr->next_to_check;
2231         cur = &rxr->rx_base[i];
2232         staterr = le32toh(cur->wb.upper.status_error);
2233
2234         if ((staterr & E1000_RXD_STAT_DD) == 0)
2235                 return;
2236
2237         while ((staterr & E1000_RXD_STAT_DD) && count != 0) {
2238                 struct igb_rx_buf *rxbuf = &rxr->rx_buf[i];
2239                 struct mbuf *m = NULL;
2240                 boolean_t eop;
2241
2242                 eop = (staterr & E1000_RXD_STAT_EOP) ? TRUE : FALSE;
2243                 if (eop)
2244                         --count;
2245
2246                 if ((staterr & E1000_RXDEXT_ERR_FRAME_ERR_MASK) == 0 &&
2247                     !rxr->discard) {
2248                         struct mbuf *mp = rxbuf->m_head;
2249                         uint16_t vlan;
2250                         int len;
2251
2252                         len = le16toh(cur->wb.upper.length);
2253                         if (rxr->sc->hw.mac.type == e1000_i350 &&
2254                             (staterr & E1000_RXDEXT_STATERR_LB))
2255                                 vlan = be16toh(cur->wb.upper.vlan);
2256                         else
2257                                 vlan = le16toh(cur->wb.upper.vlan);
2258
2259                         bus_dmamap_sync(rxr->rx_tag, rxbuf->map,
2260                             BUS_DMASYNC_POSTREAD);
2261
2262                         if (igb_newbuf(rxr, i, FALSE) != 0) {
2263                                 ifp->if_iqdrops++;
2264                                 goto discard;
2265                         }
2266
2267                         mp->m_len = len;
2268                         if (rxr->fmp == NULL) {
2269                                 mp->m_pkthdr.len = len;
2270                                 rxr->fmp = mp;
2271                                 rxr->lmp = mp;
2272                         } else {
2273                                 rxr->lmp->m_next = mp;
2274                                 rxr->lmp = rxr->lmp->m_next;
2275                                 rxr->fmp->m_pkthdr.len += len;
2276                         }
2277
2278                         if (eop) {
2279                                 m = rxr->fmp;
2280                                 rxr->fmp = NULL;
2281                                 rxr->lmp = NULL;
2282
2283                                 m->m_pkthdr.rcvif = ifp;
2284                                 ifp->if_ipackets++;
2285
2286                                 if (ifp->if_capenable & IFCAP_RXCSUM)
2287                                         igb_rxcsum(staterr, m);
2288
2289                                 if (staterr & E1000_RXD_STAT_VP) {
2290                                         m->m_pkthdr.ether_vlantag = vlan;
2291                                         m->m_flags |= M_VLANTAG;
2292                                 }
2293
2294 #if 0
2295                                 if (ifp->if_capenable & IFCAP_RSS) {
2296                                         pi = emx_rssinfo(m, &pi0, mrq,
2297                                                          rss_hash, staterr);
2298                                 }
2299 #endif
2300                         }
2301                 } else {
2302                         ifp->if_ierrors++;
2303 discard:
2304                         igb_setup_rxdesc(cur, rxbuf);
2305                         if (!eop)
2306                                 rxr->discard = TRUE;
2307                         else
2308                                 rxr->discard = FALSE;
2309                         if (rxr->fmp != NULL) {
2310                                 m_freem(rxr->fmp);
2311                                 rxr->fmp = NULL;
2312                                 rxr->lmp = NULL;
2313                         }
2314                         m = NULL;
2315                 }
2316
2317                 if (m != NULL)
2318                         ether_input_pkt(ifp, m, NULL);
2319
2320                 /* Advance our pointers to the next descriptor. */
2321                 if (++i == rxr->sc->num_rx_desc)
2322                         i = 0;
2323
2324                 cur = &rxr->rx_base[i];
2325                 staterr = le32toh(cur->wb.upper.status_error);
2326         }
2327         rxr->next_to_check = i;
2328
2329         if (--i < 0)
2330                 i = rxr->sc->num_rx_desc - 1;
2331         E1000_WRITE_REG(&rxr->sc->hw, E1000_RDT(rxr->me), i);
2332 }
2333
2334
2335 static void
2336 igb_set_vlan(struct igb_softc *sc)
2337 {
2338         struct e1000_hw *hw = &sc->hw;
2339         uint32_t reg;
2340 #if 0
2341         struct ifnet *ifp = sc->arpcom.ac_if;
2342 #endif
2343
2344         if (sc->vf_ifp) {
2345                 e1000_rlpml_set_vf(hw, sc->max_frame_size + VLAN_TAG_SIZE);
2346                 return;
2347         }
2348
2349         reg = E1000_READ_REG(hw, E1000_CTRL);
2350         reg |= E1000_CTRL_VME;
2351         E1000_WRITE_REG(hw, E1000_CTRL, reg);
2352
2353 #if 0
2354         /* Enable the Filter Table */
2355         if (ifp->if_capenable & IFCAP_VLAN_HWFILTER) {
2356                 reg = E1000_READ_REG(hw, E1000_RCTL);
2357                 reg &= ~E1000_RCTL_CFIEN;
2358                 reg |= E1000_RCTL_VFE;
2359                 E1000_WRITE_REG(hw, E1000_RCTL, reg);
2360         }
2361 #endif
2362
2363         /* Update the frame size */
2364         E1000_WRITE_REG(&sc->hw, E1000_RLPML,
2365             sc->max_frame_size + VLAN_TAG_SIZE);
2366
2367 #if 0
2368         /* Don't bother with table if no vlans */
2369         if ((adapter->num_vlans == 0) ||
2370             ((ifp->if_capenable & IFCAP_VLAN_HWFILTER) == 0))
2371                 return;
2372         /*
2373         ** A soft reset zero's out the VFTA, so
2374         ** we need to repopulate it now.
2375         */
2376         for (int i = 0; i < IGB_VFTA_SIZE; i++)
2377                 if (adapter->shadow_vfta[i] != 0) {
2378                         if (adapter->vf_ifp)
2379                                 e1000_vfta_set_vf(hw,
2380                                     adapter->shadow_vfta[i], TRUE);
2381                         else
2382                                 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA,
2383                                  i, adapter->shadow_vfta[i]);
2384                 }
2385 #endif
2386 }
2387
2388 static void
2389 igb_enable_intr(struct igb_softc *sc)
2390 {
2391         lwkt_serialize_handler_enable(sc->arpcom.ac_if.if_serializer);
2392
2393         /* With RSS set up what to auto clear */
2394         if (sc->msix_mem) {
2395                 uint32_t mask = (sc->que_mask | sc->link_mask);
2396
2397                 E1000_WRITE_REG(&sc->hw, E1000_EIAC, mask);
2398                 E1000_WRITE_REG(&sc->hw, E1000_EIAM, mask);
2399                 E1000_WRITE_REG(&sc->hw, E1000_EIMS, mask);
2400                 E1000_WRITE_REG(&sc->hw, E1000_IMS, E1000_IMS_LSC);
2401         } else {
2402                 E1000_WRITE_REG(&sc->hw, E1000_IMS, IMS_ENABLE_MASK);
2403         }
2404         E1000_WRITE_FLUSH(&sc->hw);
2405 }
2406
2407 static void
2408 igb_disable_intr(struct igb_softc *sc)
2409 {
2410         if (sc->msix_mem != NULL) {
2411                 E1000_WRITE_REG(&sc->hw, E1000_EIMC, 0xffffffff);
2412                 E1000_WRITE_REG(&sc->hw, E1000_EIAC, 0);
2413         } 
2414         E1000_WRITE_REG(&sc->hw, E1000_IMC, 0xffffffff);
2415         E1000_WRITE_FLUSH(&sc->hw);
2416
2417         lwkt_serialize_handler_disable(sc->arpcom.ac_if.if_serializer);
2418 }
2419
2420 /*
2421  * Bit of a misnomer, what this really means is
2422  * to enable OS management of the system... aka
2423  * to disable special hardware management features 
2424  */
2425 static void
2426 igb_get_mgmt(struct igb_softc *sc)
2427 {
2428         if (sc->has_manage) {
2429                 int manc2h = E1000_READ_REG(&sc->hw, E1000_MANC2H);
2430                 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2431
2432                 /* disable hardware interception of ARP */
2433                 manc &= ~E1000_MANC_ARP_EN;
2434
2435                 /* enable receiving management packets to the host */
2436                 manc |= E1000_MANC_EN_MNG2HOST;
2437                 manc2h |= 1 << 5; /* Mng Port 623 */
2438                 manc2h |= 1 << 6; /* Mng Port 664 */
2439                 E1000_WRITE_REG(&sc->hw, E1000_MANC2H, manc2h);
2440                 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2441         }
2442 }
2443
2444 /*
2445  * Give control back to hardware management controller
2446  * if there is one.
2447  */
2448 static void
2449 igb_rel_mgmt(struct igb_softc *sc)
2450 {
2451         if (sc->has_manage) {
2452                 int manc = E1000_READ_REG(&sc->hw, E1000_MANC);
2453
2454                 /* Re-enable hardware interception of ARP */
2455                 manc |= E1000_MANC_ARP_EN;
2456                 manc &= ~E1000_MANC_EN_MNG2HOST;
2457
2458                 E1000_WRITE_REG(&sc->hw, E1000_MANC, manc);
2459         }
2460 }
2461
2462 /*
2463  * Sets CTRL_EXT:DRV_LOAD bit.
2464  *
2465  * For ASF and Pass Through versions of f/w this means that
2466  * the driver is loaded. 
2467  */
2468 static void
2469 igb_get_hw_control(struct igb_softc *sc)
2470 {
2471         uint32_t ctrl_ext;
2472
2473         if (sc->vf_ifp)
2474                 return;
2475
2476         /* Let firmware know the driver has taken over */
2477         ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2478         E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2479             ctrl_ext | E1000_CTRL_EXT_DRV_LOAD);
2480 }
2481
2482 /*
2483  * Resets CTRL_EXT:DRV_LOAD bit.
2484  *
2485  * For ASF and Pass Through versions of f/w this means that the
2486  * driver is no longer loaded.
2487  */
2488 static void
2489 igb_rel_hw_control(struct igb_softc *sc)
2490 {
2491         uint32_t ctrl_ext;
2492
2493         if (sc->vf_ifp)
2494                 return;
2495
2496         /* Let firmware taken over control of h/w */
2497         ctrl_ext = E1000_READ_REG(&sc->hw, E1000_CTRL_EXT);
2498         E1000_WRITE_REG(&sc->hw, E1000_CTRL_EXT,
2499             ctrl_ext & ~E1000_CTRL_EXT_DRV_LOAD);
2500 }
2501
2502 static int
2503 igb_is_valid_ether_addr(const uint8_t *addr)
2504 {
2505         uint8_t zero_addr[ETHER_ADDR_LEN] = { 0, 0, 0, 0, 0, 0 };
2506
2507         if ((addr[0] & 1) || !bcmp(addr, zero_addr, ETHER_ADDR_LEN))
2508                 return FALSE;
2509         return TRUE;
2510 }
2511
2512 /*
2513  * Enable PCI Wake On Lan capability
2514  */
2515 static void
2516 igb_enable_wol(device_t dev)
2517 {
2518         uint16_t cap, status;
2519         uint8_t id;
2520
2521         /* First find the capabilities pointer*/
2522         cap = pci_read_config(dev, PCIR_CAP_PTR, 2);
2523
2524         /* Read the PM Capabilities */
2525         id = pci_read_config(dev, cap, 1);
2526         if (id != PCIY_PMG)     /* Something wrong */
2527                 return;
2528
2529         /*
2530          * OK, we have the power capabilities,
2531          * so now get the status register
2532          */
2533         cap += PCIR_POWER_STATUS;
2534         status = pci_read_config(dev, cap, 2);
2535         status |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
2536         pci_write_config(dev, cap, status, 2);
2537 }
2538
2539 static void
2540 igb_update_stats_counters(struct igb_softc *sc)
2541 {
2542         struct e1000_hw *hw = &sc->hw;
2543         struct e1000_hw_stats *stats;
2544         struct ifnet *ifp = &sc->arpcom.ac_if;
2545
2546         /* 
2547          * The virtual function adapter has only a
2548          * small controlled set of stats, do only 
2549          * those and return.
2550          */
2551         if (sc->vf_ifp) {
2552                 igb_update_vf_stats_counters(sc);
2553                 return;
2554         }
2555         stats = sc->stats;
2556
2557         if (sc->hw.phy.media_type == e1000_media_type_copper ||
2558             (E1000_READ_REG(hw, E1000_STATUS) & E1000_STATUS_LU)) {
2559                 stats->symerrs +=
2560                     E1000_READ_REG(hw,E1000_SYMERRS);
2561                 stats->sec += E1000_READ_REG(hw, E1000_SEC);
2562         }
2563
2564         stats->crcerrs += E1000_READ_REG(hw, E1000_CRCERRS);
2565         stats->mpc += E1000_READ_REG(hw, E1000_MPC);
2566         stats->scc += E1000_READ_REG(hw, E1000_SCC);
2567         stats->ecol += E1000_READ_REG(hw, E1000_ECOL);
2568
2569         stats->mcc += E1000_READ_REG(hw, E1000_MCC);
2570         stats->latecol += E1000_READ_REG(hw, E1000_LATECOL);
2571         stats->colc += E1000_READ_REG(hw, E1000_COLC);
2572         stats->dc += E1000_READ_REG(hw, E1000_DC);
2573         stats->rlec += E1000_READ_REG(hw, E1000_RLEC);
2574         stats->xonrxc += E1000_READ_REG(hw, E1000_XONRXC);
2575         stats->xontxc += E1000_READ_REG(hw, E1000_XONTXC);
2576
2577         /*
2578          * For watchdog management we need to know if we have been
2579          * paused during the last interval, so capture that here.
2580          */ 
2581         sc->pause_frames = E1000_READ_REG(hw, E1000_XOFFRXC);
2582         stats->xoffrxc += sc->pause_frames;
2583         stats->xofftxc += E1000_READ_REG(hw, E1000_XOFFTXC);
2584         stats->fcruc += E1000_READ_REG(hw, E1000_FCRUC);
2585         stats->prc64 += E1000_READ_REG(hw, E1000_PRC64);
2586         stats->prc127 += E1000_READ_REG(hw, E1000_PRC127);
2587         stats->prc255 += E1000_READ_REG(hw, E1000_PRC255);
2588         stats->prc511 += E1000_READ_REG(hw, E1000_PRC511);
2589         stats->prc1023 += E1000_READ_REG(hw, E1000_PRC1023);
2590         stats->prc1522 += E1000_READ_REG(hw, E1000_PRC1522);
2591         stats->gprc += E1000_READ_REG(hw, E1000_GPRC);
2592         stats->bprc += E1000_READ_REG(hw, E1000_BPRC);
2593         stats->mprc += E1000_READ_REG(hw, E1000_MPRC);
2594         stats->gptc += E1000_READ_REG(hw, E1000_GPTC);
2595
2596         /* For the 64-bit byte counters the low dword must be read first. */
2597         /* Both registers clear on the read of the high dword */
2598
2599         stats->gorc += E1000_READ_REG(hw, E1000_GORCL) +
2600             ((uint64_t)E1000_READ_REG(hw, E1000_GORCH) << 32);
2601         stats->gotc += E1000_READ_REG(hw, E1000_GOTCL) +
2602             ((uint64_t)E1000_READ_REG(hw, E1000_GOTCH) << 32);
2603
2604         stats->rnbc += E1000_READ_REG(hw, E1000_RNBC);
2605         stats->ruc += E1000_READ_REG(hw, E1000_RUC);
2606         stats->rfc += E1000_READ_REG(hw, E1000_RFC);
2607         stats->roc += E1000_READ_REG(hw, E1000_ROC);
2608         stats->rjc += E1000_READ_REG(hw, E1000_RJC);
2609
2610         stats->tor += E1000_READ_REG(hw, E1000_TORH);
2611         stats->tot += E1000_READ_REG(hw, E1000_TOTH);
2612
2613         stats->tpr += E1000_READ_REG(hw, E1000_TPR);
2614         stats->tpt += E1000_READ_REG(hw, E1000_TPT);
2615         stats->ptc64 += E1000_READ_REG(hw, E1000_PTC64);
2616         stats->ptc127 += E1000_READ_REG(hw, E1000_PTC127);
2617         stats->ptc255 += E1000_READ_REG(hw, E1000_PTC255);
2618         stats->ptc511 += E1000_READ_REG(hw, E1000_PTC511);
2619         stats->ptc1023 += E1000_READ_REG(hw, E1000_PTC1023);
2620         stats->ptc1522 += E1000_READ_REG(hw, E1000_PTC1522);
2621         stats->mptc += E1000_READ_REG(hw, E1000_MPTC);
2622         stats->bptc += E1000_READ_REG(hw, E1000_BPTC);
2623
2624         /* Interrupt Counts */
2625
2626         stats->iac += E1000_READ_REG(hw, E1000_IAC);
2627         stats->icrxptc += E1000_READ_REG(hw, E1000_ICRXPTC);
2628         stats->icrxatc += E1000_READ_REG(hw, E1000_ICRXATC);
2629         stats->ictxptc += E1000_READ_REG(hw, E1000_ICTXPTC);
2630         stats->ictxatc += E1000_READ_REG(hw, E1000_ICTXATC);
2631         stats->ictxqec += E1000_READ_REG(hw, E1000_ICTXQEC);
2632         stats->ictxqmtc += E1000_READ_REG(hw, E1000_ICTXQMTC);
2633         stats->icrxdmtc += E1000_READ_REG(hw, E1000_ICRXDMTC);
2634         stats->icrxoc += E1000_READ_REG(hw, E1000_ICRXOC);
2635
2636         /* Host to Card Statistics */
2637
2638         stats->cbtmpc += E1000_READ_REG(hw, E1000_CBTMPC);
2639         stats->htdpmc += E1000_READ_REG(hw, E1000_HTDPMC);
2640         stats->cbrdpc += E1000_READ_REG(hw, E1000_CBRDPC);
2641         stats->cbrmpc += E1000_READ_REG(hw, E1000_CBRMPC);
2642         stats->rpthc += E1000_READ_REG(hw, E1000_RPTHC);
2643         stats->hgptc += E1000_READ_REG(hw, E1000_HGPTC);
2644         stats->htcbdpc += E1000_READ_REG(hw, E1000_HTCBDPC);
2645         stats->hgorc += (E1000_READ_REG(hw, E1000_HGORCL) +
2646             ((uint64_t)E1000_READ_REG(hw, E1000_HGORCH) << 32));
2647         stats->hgotc += (E1000_READ_REG(hw, E1000_HGOTCL) +
2648             ((uint64_t)E1000_READ_REG(hw, E1000_HGOTCH) << 32));
2649         stats->lenerrs += E1000_READ_REG(hw, E1000_LENERRS);
2650         stats->scvpc += E1000_READ_REG(hw, E1000_SCVPC);
2651         stats->hrmpc += E1000_READ_REG(hw, E1000_HRMPC);
2652
2653         stats->algnerrc += E1000_READ_REG(hw, E1000_ALGNERRC);
2654         stats->rxerrc += E1000_READ_REG(hw, E1000_RXERRC);
2655         stats->tncrs += E1000_READ_REG(hw, E1000_TNCRS);
2656         stats->cexterr += E1000_READ_REG(hw, E1000_CEXTERR);
2657         stats->tsctc += E1000_READ_REG(hw, E1000_TSCTC);
2658         stats->tsctfc += E1000_READ_REG(hw, E1000_TSCTFC);
2659
2660         ifp->if_collisions = stats->colc;
2661
2662         /* Rx Errors */
2663         ifp->if_ierrors = stats->rxerrc + stats->crcerrs + stats->algnerrc +
2664             stats->ruc + stats->roc + stats->mpc + stats->cexterr;
2665
2666         /* Tx Errors */
2667         ifp->if_oerrors = stats->ecol + stats->latecol + sc->watchdog_events;
2668
2669         /* Driver specific counters */
2670         sc->device_control = E1000_READ_REG(hw, E1000_CTRL);
2671         sc->rx_control = E1000_READ_REG(hw, E1000_RCTL);
2672         sc->int_mask = E1000_READ_REG(hw, E1000_IMS);
2673         sc->eint_mask = E1000_READ_REG(hw, E1000_EIMS);
2674         sc->packet_buf_alloc_tx =
2675             ((E1000_READ_REG(hw, E1000_PBA) & 0xffff0000) >> 16);
2676         sc->packet_buf_alloc_rx =
2677             (E1000_READ_REG(hw, E1000_PBA) & 0xffff);
2678 }
2679
2680 static void
2681 igb_vf_init_stats(struct igb_softc *sc)
2682 {
2683         struct e1000_hw *hw = &sc->hw;
2684         struct e1000_vf_stats *stats;
2685
2686         stats = sc->stats;
2687         stats->last_gprc = E1000_READ_REG(hw, E1000_VFGPRC);
2688         stats->last_gorc = E1000_READ_REG(hw, E1000_VFGORC);
2689         stats->last_gptc = E1000_READ_REG(hw, E1000_VFGPTC);
2690         stats->last_gotc = E1000_READ_REG(hw, E1000_VFGOTC);
2691         stats->last_mprc = E1000_READ_REG(hw, E1000_VFMPRC);
2692 }
2693  
2694 static void
2695 igb_update_vf_stats_counters(struct igb_softc *sc)
2696 {
2697         struct e1000_hw *hw = &sc->hw;
2698         struct e1000_vf_stats *stats;
2699
2700         if (sc->link_speed == 0)
2701                 return;
2702
2703         stats = sc->stats;
2704         UPDATE_VF_REG(E1000_VFGPRC, stats->last_gprc, stats->gprc);
2705         UPDATE_VF_REG(E1000_VFGORC, stats->last_gorc, stats->gorc);
2706         UPDATE_VF_REG(E1000_VFGPTC, stats->last_gptc, stats->gptc);
2707         UPDATE_VF_REG(E1000_VFGOTC, stats->last_gotc, stats->gotc);
2708         UPDATE_VF_REG(E1000_VFMPRC, stats->last_mprc, stats->mprc);
2709 }
2710
2711 #ifdef DEVICE_POLLING
2712
2713 static void
2714 igb_poll(struct ifnet *ifp, enum poll_cmd cmd, int count)
2715 {
2716         struct igb_softc *sc = ifp->if_softc;
2717         uint32_t reg_icr;
2718
2719         ASSERT_SERIALIZED(ifp->if_serializer);
2720
2721         switch (cmd) {
2722         case POLL_REGISTER:
2723                 igb_disable_intr(sc);
2724                 break;
2725
2726         case POLL_DEREGISTER:
2727                 igb_enable_intr(sc);
2728                 break;
2729
2730         case POLL_AND_CHECK_STATUS:
2731                 reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
2732                 if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
2733                         sc->hw.mac.get_link_status = 1;
2734                         igb_update_link_status(sc);
2735                 }
2736                 /* FALL THROUGH */
2737         case POLL_ONLY:
2738                 if (ifp->if_flags & IFF_RUNNING) {
2739                         igb_rxeof(sc->queues[0].rxr, count);
2740
2741                         igb_txeof(sc->queues[0].txr);
2742                         if (!ifq_is_empty(&ifp->if_snd))
2743                                 if_devstart(ifp);
2744                 }
2745                 break;
2746         }
2747 }
2748
2749 #endif /* DEVICE_POLLING */
2750
2751 static void
2752 igb_intr(void *xsc)
2753 {
2754         struct igb_softc *sc = xsc;
2755         struct ifnet *ifp = &sc->arpcom.ac_if;
2756         uint32_t reg_icr;
2757
2758         ASSERT_IFNET_SERIALIZED_ALL(ifp);
2759
2760         reg_icr = E1000_READ_REG(&sc->hw, E1000_ICR);
2761
2762         /* Hot eject?  */
2763         if (reg_icr == 0xffffffff)
2764                 return;
2765
2766         /* Definitely not our interrupt.  */
2767         if (reg_icr == 0x0)
2768                 return;
2769
2770         if ((reg_icr & E1000_ICR_INT_ASSERTED) == 0)
2771                 return;
2772
2773         if (ifp->if_flags & IFF_RUNNING) {
2774                 igb_rxeof(sc->queues[0].rxr, -1);
2775
2776                 igb_txeof(sc->queues[0].txr);
2777                 if (!ifq_is_empty(&ifp->if_snd))
2778                         if_devstart(ifp);
2779         }
2780
2781         /* Link status change */
2782         if (reg_icr & (E1000_ICR_RXSEQ | E1000_ICR_LSC)) {
2783                 sc->hw.mac.get_link_status = 1;
2784                 igb_update_link_status(sc);
2785         }
2786
2787         if (reg_icr & E1000_ICR_RXO)
2788                 sc->rx_overruns++;
2789 }
2790
2791 static int
2792 igb_txctx_pullup(struct igb_tx_ring *txr, struct mbuf **m0)
2793 {
2794         struct mbuf *m = *m0;
2795         struct ether_header *eh;
2796         int len;
2797
2798         txr->ctx_try_pullup++;
2799
2800         len = ETHER_HDR_LEN + IGB_IPVHL_SIZE;
2801
2802         if (__predict_false(!M_WRITABLE(m))) {
2803                 if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
2804                         txr->ctx_drop1++;
2805                         m_freem(m);
2806                         *m0 = NULL;
2807                         return ENOBUFS;
2808                 }
2809                 eh = mtod(m, struct ether_header *);
2810
2811                 if (eh->ether_type == htons(ETHERTYPE_VLAN))
2812                         len += EVL_ENCAPLEN;
2813
2814                 if (m->m_len < len) {
2815                         txr->ctx_drop2++;
2816                         m_freem(m);
2817                         *m0 = NULL;
2818                         return ENOBUFS;
2819                 }
2820                 return 0;
2821         }
2822
2823         if (__predict_false(m->m_len < ETHER_HDR_LEN)) {
2824                 txr->ctx_pullup1++;
2825                 m = m_pullup(m, ETHER_HDR_LEN);
2826                 if (m == NULL) {
2827                         txr->ctx_pullup1_failed++;
2828                         *m0 = NULL;
2829                         return ENOBUFS;
2830                 }
2831                 *m0 = m;
2832         }
2833         eh = mtod(m, struct ether_header *);
2834
2835         if (eh->ether_type == htons(ETHERTYPE_VLAN))
2836                 len += EVL_ENCAPLEN;
2837
2838         if (m->m_len < len) {
2839                 txr->ctx_pullup2++;
2840                 m = m_pullup(m, len);
2841                 if (m == NULL) {
2842                         txr->ctx_pullup2_failed++;
2843                         *m0 = NULL;
2844                         return ENOBUFS;
2845                 }
2846                 *m0 = m;
2847         }
2848         return 0;
2849 }
2850
2851 static int
2852 igb_encap(struct igb_tx_ring *txr, struct mbuf **m_headp)
2853 {
2854         bus_dma_segment_t segs[IGB_MAX_SCATTER];
2855         bus_dmamap_t map;
2856         struct igb_tx_buf *tx_buf, *tx_buf_mapped;
2857         union e1000_adv_tx_desc *txd = NULL;
2858         struct mbuf *m_head = *m_headp;
2859         uint32_t olinfo_status = 0, cmd_type_len = 0, cmd_rs = 0;
2860         int maxsegs, nsegs, i, j, error, last = 0;
2861         uint32_t hdrlen = 0;
2862
2863         if (m_head->m_len < IGB_TXCSUM_MINHL &&
2864             ((m_head->m_pkthdr.csum_flags & IGB_CSUM_FEATURES) ||
2865              (m_head->m_flags & M_VLANTAG))) {
2866                 /*
2867                  * Make sure that ethernet header and ip.ip_hl are in
2868                  * contiguous memory, since if TXCSUM or VLANTAG is
2869                  * enabled, later TX context descriptor's setup need
2870                  * to access ip.ip_hl.
2871                  */
2872                 error = igb_txctx_pullup(txr, m_headp);
2873                 if (error) {
2874                         KKASSERT(*m_headp == NULL);
2875                         return error;
2876                 }
2877                 m_head = *m_headp;
2878         }
2879
2880         /* Set basic descriptor constants */
2881         cmd_type_len |= E1000_ADVTXD_DTYP_DATA;
2882         cmd_type_len |= E1000_ADVTXD_DCMD_IFCS | E1000_ADVTXD_DCMD_DEXT;
2883         if (m_head->m_flags & M_VLANTAG)
2884                 cmd_type_len |= E1000_ADVTXD_DCMD_VLE;
2885
2886         /*
2887          * Map the packet for DMA.
2888          */
2889         tx_buf = &txr->tx_buf[txr->next_avail_desc];
2890         tx_buf_mapped = tx_buf;
2891         map = tx_buf->map;
2892
2893         maxsegs = txr->tx_avail - IGB_TX_RESERVED;
2894         KASSERT(maxsegs >= txr->spare_desc, ("not enough spare TX desc\n"));
2895         if (maxsegs > IGB_MAX_SCATTER)
2896                 maxsegs = IGB_MAX_SCATTER;
2897
2898         error = bus_dmamap_load_mbuf_defrag(txr->tx_tag, map, m_headp,
2899             segs, maxsegs, &nsegs, BUS_DMA_NOWAIT);
2900         if (error) {
2901                 if (error == ENOBUFS)
2902                         txr->sc->mbuf_defrag_failed++;
2903                 else
2904                         txr->sc->no_tx_dma_setup++;
2905
2906                 m_freem(*m_headp);
2907                 *m_headp = NULL;
2908                 return error;
2909         }
2910         bus_dmamap_sync(txr->tx_tag, map, BUS_DMASYNC_PREWRITE);
2911
2912         m_head = *m_headp;
2913
2914 #if 0
2915         /*
2916          * Set up the context descriptor:
2917          * used when any hardware offload is done.
2918          * This includes CSUM, VLAN, and TSO. It
2919          * will use the first descriptor.
2920          */
2921         if (m_head->m_pkthdr.csum_flags & CSUM_TSO) {
2922                 if (igb_tso_setup(txr, m_head, &hdrlen)) {
2923                         cmd_type_len |= E1000_ADVTXD_DCMD_TSE;
2924                         olinfo_status |= E1000_TXD_POPTS_IXSM << 8;
2925                         olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2926                 } else
2927                         return (ENXIO); 
2928         } else if (igb_tx_ctx_setup(txr, m_head))
2929                 olinfo_status |= E1000_TXD_POPTS_TXSM << 8;
2930 #else
2931         if (igb_txctx(txr, m_head)) {
2932                 olinfo_status |= (E1000_TXD_POPTS_IXSM << 8);
2933                 if (m_head->m_pkthdr.csum_flags & (CSUM_UDP | CSUM_TCP))
2934                         olinfo_status |= (E1000_TXD_POPTS_TXSM << 8);
2935                 txr->tx_nsegs++;
2936         }
2937 #endif
2938
2939         txr->tx_nsegs += nsegs;
2940         if (txr->tx_nsegs >= txr->intr_nsegs) {
2941                 /*
2942                  * Report Status (RS) is turned on every intr_nsegs
2943                  * descriptors (roughly).
2944                  */
2945                 txr->tx_nsegs = 0;
2946                 cmd_rs = E1000_ADVTXD_DCMD_RS;
2947         }
2948
2949         /* Calculate payload length */
2950         olinfo_status |= ((m_head->m_pkthdr.len - hdrlen)
2951             << E1000_ADVTXD_PAYLEN_SHIFT);
2952
2953         /* 82575 needs the queue index added */
2954         if (txr->sc->hw.mac.type == e1000_82575)
2955                 olinfo_status |= txr->me << 4;
2956
2957         /* Set up our transmit descriptors */
2958         i = txr->next_avail_desc;
2959         for (j = 0; j < nsegs; j++) {
2960                 bus_size_t seg_len;
2961                 bus_addr_t seg_addr;
2962
2963                 tx_buf = &txr->tx_buf[i];
2964                 txd = (union e1000_adv_tx_desc *)&txr->tx_base[i];
2965                 seg_addr = segs[j].ds_addr;
2966                 seg_len = segs[j].ds_len;
2967
2968                 txd->read.buffer_addr = htole64(seg_addr);
2969                 txd->read.cmd_type_len = htole32(cmd_type_len | seg_len);
2970                 txd->read.olinfo_status = htole32(olinfo_status);
2971                 last = i;
2972                 if (++i == txr->sc->num_tx_desc)
2973                         i = 0;
2974                 tx_buf->m_head = NULL;
2975         }
2976
2977         KASSERT(txr->tx_avail > nsegs, ("invalid avail TX desc\n"));
2978         txr->next_avail_desc = i;
2979         txr->tx_avail -= nsegs;
2980
2981         tx_buf->m_head = m_head;
2982         tx_buf_mapped->map = tx_buf->map;
2983         tx_buf->map = map;
2984
2985         /*
2986          * Last Descriptor of Packet needs End Of Packet (EOP)
2987          */
2988         txd->read.cmd_type_len |= htole32(E1000_ADVTXD_DCMD_EOP | cmd_rs);
2989
2990         /*
2991          * Advance the Transmit Descriptor Tail (TDT), this tells the E1000
2992          * that this frame is available to transmit.
2993          */
2994         E1000_WRITE_REG(&txr->sc->hw, E1000_TDT(txr->me), i);
2995         ++txr->tx_packets;
2996
2997         return 0;
2998 }
2999
3000 static void
3001 igb_start(struct ifnet *ifp)
3002 {
3003         struct igb_softc *sc = ifp->if_softc;
3004         struct igb_tx_ring *txr = sc->queues[0].txr;
3005         struct mbuf *m_head;
3006
3007         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3008
3009         if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING)
3010                 return;
3011
3012         if (!sc->link_active) {
3013                 ifq_purge(&ifp->if_snd);
3014                 return;
3015         }
3016
3017         if (!IGB_IS_NOT_OACTIVE(txr))
3018                 igb_txeof(txr);
3019
3020         while (!ifq_is_empty(&ifp->if_snd)) {
3021                 if (IGB_IS_OACTIVE(txr)) {
3022                         ifp->if_flags |= IFF_OACTIVE;
3023                         /* Set watchdog on */
3024                         ifp->if_timer = 5;
3025                         break;
3026                 }
3027
3028                 m_head = ifq_dequeue(&ifp->if_snd, NULL);
3029                 if (m_head == NULL)
3030                         break;
3031
3032                 if (igb_encap(txr, &m_head)) {
3033                         ifp->if_oerrors++;
3034                         continue;
3035                 }
3036
3037                 /* Send a copy of the frame to the BPF listener */
3038                 ETHER_BPF_MTAP(ifp, m_head);
3039         }
3040 }
3041
3042 static void
3043 igb_watchdog(struct ifnet *ifp)
3044 {
3045         struct igb_softc *sc = ifp->if_softc;
3046         struct igb_tx_ring *txr = sc->queues[0].txr;
3047
3048         ASSERT_IFNET_SERIALIZED_ALL(ifp);
3049
3050         /* 
3051          * If flow control has paused us since last checking
3052          * it invalidates the watchdog timing, so dont run it.
3053          */
3054         if (sc->pause_frames) {
3055                 sc->pause_frames = 0;
3056                 ifp->if_timer = 5;
3057                 return;
3058         }
3059
3060         if_printf(ifp, "Watchdog timeout -- resetting\n");
3061         if_printf(ifp, "Queue(%d) tdh = %d, hw tdt = %d\n", txr->me,
3062             E1000_READ_REG(&sc->hw, E1000_TDH(txr->me)),
3063             E1000_READ_REG(&sc->hw, E1000_TDT(txr->me)));
3064         if_printf(ifp, "TX(%d) desc avail = %d, "
3065             "Next TX to Clean = %d\n",
3066             txr->me, txr->tx_avail, txr->next_to_clean);
3067
3068         ifp->if_oerrors++;
3069         sc->watchdog_events++;
3070
3071         igb_init(sc);
3072         if (!ifq_is_empty(&ifp->if_snd))
3073                 if_devstart(ifp);
3074 }
3075
3076 static void
3077 igb_set_itr(struct igb_softc *sc)
3078 {
3079         uint32_t itr = 0;
3080
3081         if (sc->intr_rate > 0) {
3082                 if (sc->hw.mac.type == e1000_82575) {
3083                         itr = 1000000000 / 256 / sc->intr_rate;
3084                         /*
3085                          * NOTE:
3086                          * Document is wrong on the 2 bits left shift
3087                          */
3088                 } else {
3089                         itr = 1000000 / sc->intr_rate;
3090                         itr <<= 2;
3091                 }
3092                 itr &= 0x7FFC;
3093         }
3094         if (sc->hw.mac.type == e1000_82575)
3095                 itr |= itr << 16;
3096         else
3097                 itr |= E1000_EITR_CNT_IGNR;
3098         E1000_WRITE_REG(&sc->hw, E1000_EITR(0), itr);
3099 }
3100
3101 static int
3102 igb_sysctl_intr_rate(SYSCTL_HANDLER_ARGS)
3103 {
3104         struct igb_softc *sc = (void *)arg1;
3105         struct ifnet *ifp = &sc->arpcom.ac_if;
3106         int error, intr_rate;
3107
3108         intr_rate = sc->intr_rate;
3109         error = sysctl_handle_int(oidp, &intr_rate, 0, req);
3110         if (error || req->newptr == NULL)
3111                 return error;
3112         if (intr_rate < 0)
3113                 return EINVAL;
3114
3115         ifnet_serialize_all(ifp);
3116
3117         sc->intr_rate = intr_rate;
3118         if (ifp->if_flags & IFF_RUNNING)
3119                 igb_set_itr(sc);
3120
3121         ifnet_deserialize_all(ifp);
3122
3123         if (bootverbose)
3124                 if_printf(ifp, "Interrupt rate set to %d/sec\n", sc->intr_rate);
3125         return 0;
3126 }
3127
3128 static int
3129 igb_sysctl_tx_intr_nsegs(SYSCTL_HANDLER_ARGS)
3130 {
3131         struct igb_softc *sc = (void *)arg1;
3132         struct ifnet *ifp = &sc->arpcom.ac_if;
3133         struct igb_tx_ring *txr = sc->queues[0].txr;
3134         int error, nsegs;
3135
3136         nsegs = txr->intr_nsegs;
3137         error = sysctl_handle_int(oidp, &nsegs, 0, req);
3138         if (error || req->newptr == NULL)
3139                 return error;
3140         if (nsegs <= 0)
3141                 return EINVAL;
3142
3143         ifnet_serialize_all(ifp);
3144
3145         if (nsegs >= sc->num_tx_desc - txr->oact_lo_desc ||
3146             nsegs >= txr->oact_hi_desc - IGB_MAX_SCATTER) {
3147                 error = EINVAL;
3148         } else {
3149                 error = 0;
3150                 txr->intr_nsegs = nsegs;
3151         }
3152
3153         ifnet_deserialize_all(ifp);
3154
3155         return error;
3156 }