2 * Copyright (c) 1996, by Steve Passe
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. The name of the developer may NOT be used to endorse or promote products
11 * derived from this software without specific prior written permission.
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * $FreeBSD: src/sys/i386/i386/mpapic.c,v 1.37.2.7 2003/01/25 02:31:47 peter Exp $
28 #include <sys/param.h>
29 #include <sys/systm.h>
30 #include <sys/kernel.h>
31 #include <machine/globaldata.h>
32 #include <machine/smp.h>
33 #include <machine/cputypes.h>
34 #include <machine/md_var.h>
35 #include <machine/pmap.h>
36 #include <machine_base/apic/mpapic.h>
37 #include <machine/segments.h>
38 #include <sys/thread2.h>
40 #include <machine_base/isa/intr_machdep.h> /* Xspuriousint() */
43 extern pt_entry_t *SMPpt;
45 /* EISA Edge/Level trigger control registers */
46 #define ELCR0 0x4d0 /* eisa irq 0-7 */
47 #define ELCR1 0x4d1 /* eisa irq 8-15 */
49 static void lapic_timer_calibrate(void);
50 static void lapic_timer_set_divisor(int);
51 static void lapic_timer_fixup_handler(void *);
52 static void lapic_timer_restart_handler(void *);
54 void lapic_timer_process(void);
55 void lapic_timer_process_frame(struct intrframe *);
57 static int lapic_timer_enable = 1;
58 TUNABLE_INT("hw.lapic_timer_enable", &lapic_timer_enable);
60 static void lapic_timer_intr_reload(struct cputimer_intr *, sysclock_t);
61 static void lapic_timer_intr_enable(struct cputimer_intr *);
62 static void lapic_timer_intr_restart(struct cputimer_intr *);
63 static void lapic_timer_intr_pmfixup(struct cputimer_intr *);
65 static struct cputimer_intr lapic_cputimer_intr = {
67 .reload = lapic_timer_intr_reload,
68 .enable = lapic_timer_intr_enable,
69 .config = cputimer_intr_default_config,
70 .restart = lapic_timer_intr_restart,
71 .pmfixup = lapic_timer_intr_pmfixup,
72 .initclock = cputimer_intr_default_initclock,
73 .next = SLIST_ENTRY_INITIALIZER,
75 .type = CPUTIMER_INTR_LAPIC,
76 .prio = CPUTIMER_INTR_PRIO_LAPIC,
77 .caps = CPUTIMER_INTR_CAP_NONE
81 * pointers to pmapped apic hardware.
84 volatile ioapic_t **ioapic;
86 static int lapic_timer_divisor_idx = -1;
87 static const uint32_t lapic_timer_divisors[] = {
88 APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16,
89 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128, APIC_TDCR_1
91 #define APIC_TIMER_NDIVISORS (int)(NELEM(lapic_timer_divisors))
95 * Enable APIC, configure interrupts.
98 apic_initialize(boolean_t bsp)
104 * setup LVT1 as ExtINT on the BSP. This is theoretically an
105 * aggregate interrupt input from the 8259. The INTA cycle
106 * will be routed to the external controller (the 8259) which
107 * is expected to supply the vector.
109 * Must be setup edge triggered, active high.
111 * Disable LVT1 on the APs. It doesn't matter what delivery
112 * mode we use because we leave it masked.
114 temp = lapic.lvt_lint0;
115 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
116 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
117 if (mycpu->gd_cpuid == 0)
118 temp |= APIC_LVT_DM_EXTINT;
120 temp |= APIC_LVT_DM_FIXED | APIC_LVT_MASKED;
121 lapic.lvt_lint0 = temp;
124 * setup LVT2 as NMI, masked till later. Edge trigger, active high.
126 temp = lapic.lvt_lint1;
127 temp &= ~(APIC_LVT_MASKED | APIC_LVT_TRIG_MASK |
128 APIC_LVT_POLARITY_MASK | APIC_LVT_DM_MASK);
129 temp |= APIC_LVT_MASKED | APIC_LVT_DM_NMI;
130 lapic.lvt_lint1 = temp;
133 * Mask the apic error interrupt, apic performance counter
136 lapic.lvt_error = lapic.lvt_error | APIC_LVT_MASKED;
137 lapic.lvt_pcint = lapic.lvt_pcint | APIC_LVT_MASKED;
139 /* Set apic timer vector and mask the apic timer interrupt. */
140 timer = lapic.lvt_timer;
141 timer &= ~APIC_LVTT_VECTOR;
142 timer |= XTIMER_OFFSET;
143 timer |= APIC_LVTT_MASKED;
144 lapic.lvt_timer = timer;
147 * Set the Task Priority Register as needed. At the moment allow
148 * interrupts on all cpus (the APs will remain CLId until they are
149 * ready to deal). We could disable all but IPIs by setting
150 * temp |= TPR_IPI for cpu != 0.
153 temp &= ~APIC_TPR_PRIO; /* clear priority field */
154 #ifdef SMP /* APIC-IO */
155 if (!apic_io_enable) {
158 * If we are NOT running the IO APICs, the LAPIC will only be used
159 * for IPIs. Set the TPR to prevent any unintentional interrupts.
162 #ifdef SMP /* APIC-IO */
169 * enable the local APIC
172 temp |= APIC_SVR_ENABLE; /* enable the APIC */
173 temp &= ~APIC_SVR_FOCUS_DISABLE; /* enable lopri focus processor */
176 * Set the spurious interrupt vector. The low 4 bits of the vector
179 if ((XSPURIOUSINT_OFFSET & 0x0F) != 0x0F)
180 panic("bad XSPURIOUSINT_OFFSET: 0x%08x", XSPURIOUSINT_OFFSET);
181 temp &= ~APIC_SVR_VECTOR;
182 temp |= XSPURIOUSINT_OFFSET;
187 * Pump out a few EOIs to clean out interrupts that got through
188 * before we were able to set the TPR.
195 lapic_timer_calibrate();
196 if (lapic_timer_enable) {
197 cputimer_intr_register(&lapic_cputimer_intr);
198 cputimer_intr_select(&lapic_cputimer_intr, 0);
201 lapic_timer_set_divisor(lapic_timer_divisor_idx);
205 apic_dump("apic_initialize()");
210 lapic_timer_set_divisor(int divisor_idx)
212 KKASSERT(divisor_idx >= 0 && divisor_idx < APIC_TIMER_NDIVISORS);
213 lapic.dcr_timer = lapic_timer_divisors[divisor_idx];
217 lapic_timer_oneshot(u_int count)
221 value = lapic.lvt_timer;
222 value &= ~APIC_LVTT_PERIODIC;
223 lapic.lvt_timer = value;
224 lapic.icr_timer = count;
228 lapic_timer_oneshot_quick(u_int count)
230 lapic.icr_timer = count;
234 lapic_timer_calibrate(void)
238 /* Try to calibrate the local APIC timer. */
239 for (lapic_timer_divisor_idx = 0;
240 lapic_timer_divisor_idx < APIC_TIMER_NDIVISORS;
241 lapic_timer_divisor_idx++) {
242 lapic_timer_set_divisor(lapic_timer_divisor_idx);
243 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT);
245 value = APIC_TIMER_MAX_COUNT - lapic.ccr_timer;
246 if (value != APIC_TIMER_MAX_COUNT)
249 if (lapic_timer_divisor_idx >= APIC_TIMER_NDIVISORS)
250 panic("lapic: no proper timer divisor?!\n");
251 lapic_cputimer_intr.freq = value / 2;
253 kprintf("lapic: divisor index %d, frequency %u Hz\n",
254 lapic_timer_divisor_idx, lapic_cputimer_intr.freq);
258 lapic_timer_process_oncpu(struct globaldata *gd, struct intrframe *frame)
262 gd->gd_timer_running = 0;
264 count = sys_cputimer->count();
265 if (TAILQ_FIRST(&gd->gd_systimerq) != NULL)
266 systimer_intr(&count, 0, frame);
270 lapic_timer_process(void)
272 lapic_timer_process_oncpu(mycpu, NULL);
276 lapic_timer_process_frame(struct intrframe *frame)
278 lapic_timer_process_oncpu(mycpu, frame);
282 lapic_timer_intr_reload(struct cputimer_intr *cti, sysclock_t reload)
284 struct globaldata *gd = mycpu;
286 reload = (int64_t)reload * cti->freq / sys_cputimer->freq;
290 if (gd->gd_timer_running) {
291 if (reload < lapic.ccr_timer)
292 lapic_timer_oneshot_quick(reload);
294 gd->gd_timer_running = 1;
295 lapic_timer_oneshot_quick(reload);
300 lapic_timer_intr_enable(struct cputimer_intr *cti __unused)
304 timer = lapic.lvt_timer;
305 timer &= ~(APIC_LVTT_MASKED | APIC_LVTT_PERIODIC);
306 lapic.lvt_timer = timer;
308 lapic_timer_fixup_handler(NULL);
312 lapic_timer_fixup_handler(void *arg)
319 if (cpu_vendor_id == CPU_VENDOR_AMD) {
321 * Detect the presence of C1E capability mostly on latest
322 * dual-cores (or future) k8 family. This feature renders
323 * the local APIC timer dead, so we disable it by reading
324 * the Interrupt Pending Message register and clearing both
325 * C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27).
328 * "BIOS and Kernel Developer's Guide for AMD NPT
329 * Family 0Fh Processors"
330 * #32559 revision 3.00
332 if ((cpu_id & 0x00000f00) == 0x00000f00 &&
333 (cpu_id & 0x0fff0000) >= 0x00040000) {
336 msr = rdmsr(0xc0010055);
337 if (msr & 0x18000000) {
338 struct globaldata *gd = mycpu;
340 kprintf("cpu%d: AMD C1E detected\n",
342 wrmsr(0xc0010055, msr & ~0x18000000ULL);
345 * We are kinda stalled;
348 gd->gd_timer_running = 1;
349 lapic_timer_oneshot_quick(2);
359 lapic_timer_restart_handler(void *dummy __unused)
363 lapic_timer_fixup_handler(&started);
365 struct globaldata *gd = mycpu;
367 gd->gd_timer_running = 1;
368 lapic_timer_oneshot_quick(2);
373 * This function is called only by ACPI-CA code currently:
374 * - AMD C1E fixup. AMD C1E only seems to happen after ACPI
375 * module controls PM. So once ACPI-CA is attached, we try
376 * to apply the fixup to prevent LAPIC timer from hanging.
379 lapic_timer_intr_pmfixup(struct cputimer_intr *cti __unused)
381 lwkt_send_ipiq_mask(smp_active_mask,
382 lapic_timer_fixup_handler, NULL);
386 lapic_timer_intr_restart(struct cputimer_intr *cti __unused)
388 lwkt_send_ipiq_mask(smp_active_mask, lapic_timer_restart_handler, NULL);
393 * dump contents of local APIC registers
398 kprintf("SMP: CPU%d %s:\n", mycpu->gd_cpuid, str);
399 kprintf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n",
400 lapic.lvt_lint0, lapic.lvt_lint1, lapic.tpr, lapic.svr);
404 #ifdef SMP /* APIC-IO */
410 #define IOAPIC_ISA_INTS 16
411 #define REDIRCNT_IOAPIC(A) \
412 ((int)((io_apic_versions[(A)] & IOART_VER_MAXREDIR) >> MAXREDIRSHIFT) + 1)
414 static int trigger (int apic, int pin, u_int32_t * flags);
415 static void polarity (int apic, int pin, u_int32_t * flags, int level);
417 #define DEFAULT_FLAGS \
423 #define DEFAULT_ISA_FLAGS \
432 io_apic_set_id(int apic, int id)
436 ux = io_apic_read(apic, IOAPIC_ID); /* get current contents */
437 if (((ux & APIC_ID_MASK) >> 24) != id) {
438 kprintf("Changing APIC ID for IO APIC #%d"
439 " from %d to %d on chip\n",
440 apic, ((ux & APIC_ID_MASK) >> 24), id);
441 ux &= ~APIC_ID_MASK; /* clear the ID field */
443 io_apic_write(apic, IOAPIC_ID, ux); /* write new value */
444 ux = io_apic_read(apic, IOAPIC_ID); /* re-read && test */
445 if (((ux & APIC_ID_MASK) >> 24) != id)
446 panic("can't control IO APIC #%d ID, reg: 0x%08x",
453 io_apic_get_id(int apic)
455 return (io_apic_read(apic, IOAPIC_ID) & APIC_ID_MASK) >> 24;
464 io_apic_setup_intpin(int apic, int pin)
466 int bus, bustype, irq;
467 u_char select; /* the select register is 8 bits */
468 u_int32_t flags; /* the window register is 32 bits */
469 u_int32_t target; /* the window register is 32 bits */
470 u_int32_t vector; /* the window register is 32 bits */
475 select = pin * 2 + IOAPIC_REDTBL0; /* register */
478 * Always clear an IO APIC pin before [re]programming it. This is
479 * particularly important if the pin is set up for a level interrupt
480 * as the IOART_REM_IRR bit might be set. When we reprogram the
481 * vector any EOI from pending ints on this pin could be lost and
482 * IRR might never get reset.
484 * To fix this problem, clear the vector and make sure it is
485 * programmed as an edge interrupt. This should theoretically
486 * clear IRR so we can later, safely program it as a level
491 flags = io_apic_read(apic, select) & IOART_RESV;
492 flags |= IOART_INTMSET | IOART_TRGREDG | IOART_INTAHI;
493 flags |= IOART_DESTPHY | IOART_DELFIXED;
495 target = io_apic_read(apic, select + 1) & IOART_HI_DEST_RESV;
496 target |= 0; /* fixed mode cpu mask of 0 - don't deliver anywhere */
500 io_apic_write(apic, select, flags | vector);
501 io_apic_write(apic, select + 1, target);
506 * We only deal with vectored interrupts here. ? documentation is
507 * lacking, I'm guessing an interrupt type of 0 is the 'INT' type,
510 * This test also catches unconfigured pins.
512 if (apic_int_type(apic, pin) != 0)
516 * Leave the pin unprogrammed if it does not correspond to
519 irq = apic_irq(apic, pin);
523 /* determine the bus type for this pin */
524 bus = apic_src_bus_id(apic, pin);
527 bustype = apic_bus_type(bus);
529 if ((bustype == ISA) &&
530 (pin < IOAPIC_ISA_INTS) &&
532 (apic_polarity(apic, pin) == 0x1) &&
533 (apic_trigger(apic, pin) == 0x3)) {
535 * A broken BIOS might describe some ISA
536 * interrupts as active-high level-triggered.
537 * Use default ISA flags for those interrupts.
539 flags = DEFAULT_ISA_FLAGS;
542 * Program polarity and trigger mode according to
545 flags = DEFAULT_FLAGS;
546 level = trigger(apic, pin, &flags);
548 int_to_apicintpin[irq].flags |= IOAPIC_IM_FLAG_LEVEL;
549 polarity(apic, pin, &flags, level);
553 ksnprintf(envpath, sizeof(envpath), "hw.irq.%d.dest", irq);
554 kgetenv_int(envpath, &cpuid);
556 /* ncpus may not be available yet */
561 kprintf("IOAPIC #%d intpin %d -> irq %d (CPU%d)\n",
562 apic, pin, irq, cpuid);
566 * Program the appropriate registers. This routing may be
567 * overridden when an interrupt handler for a device is
568 * actually added (see register_int(), which calls through
569 * the MACHINTR ABI to set up an interrupt handler/vector).
571 * The order in which we must program the two registers for
572 * safety is unclear! XXX
576 vector = IDT_OFFSET + irq; /* IDT vec */
577 target = io_apic_read(apic, select + 1) & IOART_HI_DEST_RESV;
578 /* Deliver all interrupts to CPU0 (BSP) */
579 target |= (CPU_TO_ID(cpuid) << IOART_HI_DEST_SHIFT) &
581 flags |= io_apic_read(apic, select) & IOART_RESV;
582 io_apic_write(apic, select, flags | vector);
583 io_apic_write(apic, select + 1, target);
589 io_apic_setup(int apic)
594 maxpin = REDIRCNT_IOAPIC(apic); /* pins in APIC */
595 kprintf("Programming %d pins in IOAPIC #%d\n", maxpin, apic);
597 for (pin = 0; pin < maxpin; ++pin) {
598 io_apic_setup_intpin(apic, pin);
601 if (apic_int_type(apic, pin) >= 0) {
602 kprintf("Warning: IOAPIC #%d pin %d does not exist,"
603 " cannot program!\n", apic, pin);
608 /* return GOOD status */
611 #undef DEFAULT_ISA_FLAGS
615 #define DEFAULT_EXTINT_FLAGS \
624 * XXX this function is only used by 8254 setup
625 * Setup the source of External INTerrupts.
628 ext_int_setup(int apic, int intr)
630 u_char select; /* the select register is 8 bits */
631 u_int32_t flags; /* the window register is 32 bits */
632 u_int32_t target; /* the window register is 32 bits */
633 u_int32_t vector; /* the window register is 32 bits */
637 if (apic_int_type(apic, intr) != 3)
641 ksnprintf(envpath, sizeof(envpath), "hw.irq.%d.dest", intr);
642 kgetenv_int(envpath, &cpuid);
644 /* ncpus may not be available yet */
648 /* Deliver interrupts to CPU0 (BSP) */
649 target = (CPU_TO_ID(cpuid) << IOART_HI_DEST_SHIFT) &
651 select = IOAPIC_REDTBL0 + (2 * intr);
652 vector = IDT_OFFSET + intr;
653 flags = DEFAULT_EXTINT_FLAGS;
655 io_apic_write(apic, select, flags | vector);
656 io_apic_write(apic, select + 1, target);
660 #undef DEFAULT_EXTINT_FLAGS
664 * Set the trigger level for an IO APIC pin.
667 trigger(int apic, int pin, u_int32_t * flags)
672 static int intcontrol = -1;
674 switch (apic_trigger(apic, pin)) {
680 *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG */
684 *flags |= IOART_TRGRLVL;
692 if ((id = apic_src_bus_id(apic, pin)) == -1)
695 switch (apic_bus_type(id)) {
697 *flags &= ~IOART_TRGRLVL; /* *flags |= IOART_TRGREDG; */
701 eirq = apic_src_bus_irq(apic, pin);
703 if (eirq < 0 || eirq > 15) {
704 kprintf("EISA IRQ %d?!?!\n", eirq);
708 if (intcontrol == -1) {
709 intcontrol = inb(ELCR1) << 8;
710 intcontrol |= inb(ELCR0);
711 kprintf("EISA INTCONTROL = %08x\n", intcontrol);
714 /* Use ELCR settings to determine level or edge mode */
715 level = (intcontrol >> eirq) & 1;
718 * Note that on older Neptune chipset based systems, any
719 * pci interrupts often show up here and in the ELCR as well
720 * as level sensitive interrupts attributed to the EISA bus.
724 *flags |= IOART_TRGRLVL;
726 *flags &= ~IOART_TRGRLVL;
731 *flags |= IOART_TRGRLVL;
740 panic("bad APIC IO INT flags");
745 * Set the polarity value for an IO APIC pin.
748 polarity(int apic, int pin, u_int32_t * flags, int level)
752 switch (apic_polarity(apic, pin)) {
758 *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
762 *flags |= IOART_INTALO;
770 if ((id = apic_src_bus_id(apic, pin)) == -1)
773 switch (apic_bus_type(id)) {
775 *flags &= ~IOART_INTALO; /* *flags |= IOART_INTAHI */
779 /* polarity converter always gives active high */
780 *flags &= ~IOART_INTALO;
784 *flags |= IOART_INTALO;
793 panic("bad APIC IO INT flags");
798 * Print contents of unmasked IRQs.
805 kprintf("SMP: enabled INTs: ");
806 for (x = 0; x < APIC_INTMAPSIZE; ++x) {
807 if ((int_to_apicintpin[x].flags & IOAPIC_IM_FLAG_MASKED) == 0)
815 * Inter Processor Interrupt functions.
818 #endif /* SMP APIC-IO */
821 * Send APIC IPI 'vector' to 'destType' via 'deliveryMode'.
823 * destType is 1 of: APIC_DEST_SELF, APIC_DEST_ALLISELF, APIC_DEST_ALLESELF
824 * vector is any valid SYSTEM INT vector
825 * delivery_mode is 1 of: APIC_DELMODE_FIXED, APIC_DELMODE_LOWPRIO
827 * A backlog of requests can create a deadlock between cpus. To avoid this
828 * we have to be able to accept IPIs at the same time we are trying to send
829 * them. The critical section prevents us from attempting to send additional
830 * IPIs reentrantly, but also prevents IPIQ processing so we have to call
831 * lwkt_process_ipiq() manually. It's rather messy and expensive for this
832 * to occur but fortunately it does not happen too often.
835 apic_ipi(int dest_type, int vector, int delivery_mode)
840 if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
841 unsigned int eflags = read_eflags();
843 DEBUG_PUSH_INFO("apic_ipi");
844 while ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
848 write_eflags(eflags);
851 icr_lo = (lapic.icr_lo & APIC_ICRLO_RESV_MASK) | dest_type |
852 delivery_mode | vector;
853 lapic.icr_lo = icr_lo;
859 single_apic_ipi(int cpu, int vector, int delivery_mode)
865 if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
866 unsigned int eflags = read_eflags();
868 DEBUG_PUSH_INFO("single_apic_ipi");
869 while ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
873 write_eflags(eflags);
875 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
876 icr_hi |= (CPU_TO_ID(cpu) << 24);
877 lapic.icr_hi = icr_hi;
880 icr_lo = (lapic.icr_lo & APIC_ICRLO_RESV_MASK)
881 | APIC_DEST_DESTFLD | delivery_mode | vector;
884 lapic.icr_lo = icr_lo;
891 * Returns 0 if the apic is busy, 1 if we were able to queue the request.
893 * NOT WORKING YET! The code as-is may end up not queueing an IPI at all
894 * to the target, and the scheduler does not 'poll' for IPI messages.
897 single_apic_ipi_passive(int cpu, int vector, int delivery_mode)
903 if ((lapic.icr_lo & APIC_DELSTAT_MASK) != 0) {
907 icr_hi = lapic.icr_hi & ~APIC_ID_MASK;
908 icr_hi |= (CPU_TO_ID(cpu) << 24);
909 lapic.icr_hi = icr_hi;
912 icr_lo = (lapic.icr_lo & APIC_RESV2_MASK)
913 | APIC_DEST_DESTFLD | delivery_mode | vector;
916 lapic.icr_lo = icr_lo;
924 * Send APIC IPI 'vector' to 'target's via 'delivery_mode'.
926 * target is a bitmask of destination cpus. Vector is any
927 * valid system INT vector. Delivery mode may be either
928 * APIC_DELMODE_FIXED or APIC_DELMODE_LOWPRIO.
931 selected_apic_ipi(cpumask_t target, int vector, int delivery_mode)
935 int n = BSFCPUMASK(target);
936 target &= ~CPUMASK(n);
937 single_apic_ipi(n, vector, delivery_mode);
943 * Timer code, in development...
944 * - suggested by rgrimes@gndrsh.aac.dev.com
947 get_apic_timer_frequency(void)
949 return(lapic_cputimer_intr.freq);
953 * Load a 'downcount time' in uSeconds.
956 set_apic_timer(int us)
961 * When we reach here, lapic timer's frequency
962 * must have been calculated as well as the
963 * divisor (lapic.dcr_timer is setup during the
964 * divisor calculation).
966 KKASSERT(lapic_cputimer_intr.freq != 0 &&
967 lapic_timer_divisor_idx >= 0);
969 count = ((us * (int64_t)lapic_cputimer_intr.freq) + 999999) / 1000000;
970 lapic_timer_oneshot(count);
975 * Read remaining time in timer.
978 read_apic_timer(void)
981 /** XXX FIXME: we need to return the actual remaining time,
982 * for now we just return the remaining count.
985 return lapic.ccr_timer;
991 * Spin-style delay, set delay time in uS, spin till it drains.
996 set_apic_timer(count);
997 while (read_apic_timer())
1002 lapic_map(vm_offset_t lapic_addr)
1004 /* Local apic is mapped on last page */
1005 SMPpt[NPTEPG - 1] = (pt_entry_t)(PG_V | PG_RW | PG_N |
1006 pmap_get_pgeflag() | (lapic_addr & PG_FRAME));
1008 kprintf("lapic: at %p\n", (void *)lapic_addr);
1011 static TAILQ_HEAD(, lapic_enumerator) lapic_enumerators =
1012 TAILQ_HEAD_INITIALIZER(lapic_enumerators);
1017 struct lapic_enumerator *e;
1020 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) {
1021 error = e->lapic_probe(e);
1026 panic("can't config lapic\n");
1028 e->lapic_enumerate(e);
1032 lapic_enumerator_register(struct lapic_enumerator *ne)
1034 struct lapic_enumerator *e;
1036 TAILQ_FOREACH(e, &lapic_enumerators, lapic_link) {
1037 if (e->lapic_prio < ne->lapic_prio) {
1038 TAILQ_INSERT_BEFORE(e, ne, lapic_link);
1042 TAILQ_INSERT_TAIL(&lapic_enumerators, ne, lapic_link);