2 * Copyright (c) 2008 The DragonFly Project. All rights reserved.
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5 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
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12 * the documentation and/or other materials provided with the
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16 * from this software without specific, prior written permission.
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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21 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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31 * from: vector.s, 386BSD 0.1 unknown origin
32 * $FreeBSD: src/sys/i386/isa/icu_vector.s,v 1.14.2.2 2000/07/18 21:12:42 dfr Exp $
33 * $DragonFly: src/sys/platform/pc64/icu/icu_vector.s,v 1.1 2008/08/29 17:07:16 dillon Exp $
36 * WARNING! SMP builds can use the ICU now so this code must be MP safe.
39 #include "opt_auto_eoi.h"
41 #include <machine/asmacros.h>
42 #include <machine/lock.h>
43 #include <machine/psl.h>
44 #include <machine/trap.h>
46 #include <machine_base/icu/icu.h>
47 #include <bus/isa/i386/isa.h>
54 #define ICU_IMR_OFFSET 1 /* IO_ICU{1,2} + 1 */
56 #define ICU_EOI 0x20 /* XXX - define elsewhere */
58 #define IRQ_LBIT(irq_num) (1 << (irq_num))
59 #define IRQ_BIT(irq_num) (1 << ((irq_num) % 8))
60 #define IRQ_BYTE(irq_num) ((irq_num) >> 3)
63 #define ENABLE_ICU1 /* use auto-EOI to reduce i/o */
67 movb $ICU_EOI,%al ; /* as soon as possible send EOI ... */ \
68 OUTB_ICU1 ; /* ... to clear in service bit */ \
77 * The data sheet says no auto-EOI on slave, but it sometimes works.
79 #define ENABLE_ICU1_AND_2 ENABLE_ICU1
81 #define ENABLE_ICU1_AND_2 \
82 movb $ICU_EOI,%al ; /* as above */ \
83 outb %al,$IO_ICU2 ; /* but do second icu first ... */ \
84 OUTB_ICU1 ; /* ... then first icu (if !AUTO_EOI_1) */ \
91 #define ICU_PUSH_FRAME \
92 PUSH_FRAME ; /* 15 regs + space for 5 extras */ \
93 movl $0,TF_XFLAGS(%rsp) ; \
94 movl $0,TF_TRAPNO(%rsp) ; \
95 movl $0,TF_ADDR(%rsp) ; \
96 movl $0,TF_FLAGS(%rsp) ; \
97 movl $0,TF_ERR(%rsp) ; \
100 #define MASK_IRQ(icu, irq_num) \
102 movb icu_imen + IRQ_BYTE(irq_num),%al ; \
103 orb $IRQ_BIT(irq_num),%al ; \
104 movb %al,icu_imen + IRQ_BYTE(irq_num) ; \
105 outb %al,$icu+ICU_IMR_OFFSET ; \
108 #define UNMASK_IRQ(icu, irq_num) \
112 movb icu_imen + IRQ_BYTE(irq_num),%al ; \
113 andb $~IRQ_BIT(irq_num),%al ; \
114 movb %al,icu_imen + IRQ_BYTE(irq_num) ; \
115 outb %al,$icu+ICU_IMR_OFFSET ; \
120 * Fast interrupt call handlers run in the following sequence:
122 * - Push the trap frame required by doreti.
123 * - Mask the interrupt and reenable its source.
124 * - If we cannot take the interrupt set its fpending bit and
126 * - If we can take the interrupt clear its fpending bit,
127 * call the handler, then unmask the interrupt and doreti.
129 * YYY can cache gd base pointer instead of using hidden %fs
133 #define FAST_INTR(irq_num, vec_name, icu, enable_icus) \
138 FAKE_MCOUNT(15*4(%esp)) ; \
139 MASK_IRQ(icu, irq_num) ; \
141 movq PCPU(curthread),%rbx ; \
142 testl $-1,TD_NEST_COUNT(%rbx) ; \
144 cmpl $TDPRI_CRIT,TD_PRI(%rbx) ; \
147 /* set pending bit and return, leave interrupt masked */ \
148 orl $IRQ_LBIT(irq_num),PCPU(fpending) ; \
149 orl $RQF_INTPEND, PCPU(reqflags) ; \
152 /* clear pending bit, run handler */ \
153 andl $~IRQ_LBIT(irq_num),PCPU(fpending) ; \
155 movq %rsp,%rdi ; /* rdi = call argument */ \
156 addl $TDPRI_CRIT,TD_PRI(%ebx) ; \
157 call ithread_fast_handler ; /* returns 0 to unmask int */ \
158 subl $TDPRI_CRIT,TD_PRI(%ebx) ; \
159 addq $8,%rsp ; /* intr frame -> trap frame */ \
160 UNMASK_IRQ(icu, irq_num) ; \
166 * Unmask a slow interrupt. This function is used by interrupt threads
167 * after they have descheduled themselves to reenable interrupts and
168 * possibly cause a reschedule to occur.
171 #define INTR_UNMASK(irq_num, vec_name, icu) \
175 pushq %rbp ; /* frame for ddb backtrace */ \
178 UNMASK_IRQ(icu, irq_num) ; \
183 FAST_INTR(0,icu_fastintr0, IO_ICU1, ENABLE_ICU1)
184 FAST_INTR(1,icu_fastintr1, IO_ICU1, ENABLE_ICU1)
185 FAST_INTR(2,icu_fastintr2, IO_ICU1, ENABLE_ICU1)
186 FAST_INTR(3,icu_fastintr3, IO_ICU1, ENABLE_ICU1)
187 FAST_INTR(4,icu_fastintr4, IO_ICU1, ENABLE_ICU1)
188 FAST_INTR(5,icu_fastintr5, IO_ICU1, ENABLE_ICU1)
189 FAST_INTR(6,icu_fastintr6, IO_ICU1, ENABLE_ICU1)
190 FAST_INTR(7,icu_fastintr7, IO_ICU1, ENABLE_ICU1)
191 FAST_INTR(8,icu_fastintr8, IO_ICU2, ENABLE_ICU1_AND_2)
192 FAST_INTR(9,icu_fastintr9, IO_ICU2, ENABLE_ICU1_AND_2)
193 FAST_INTR(10,icu_fastintr10, IO_ICU2, ENABLE_ICU1_AND_2)
194 FAST_INTR(11,icu_fastintr11, IO_ICU2, ENABLE_ICU1_AND_2)
195 FAST_INTR(12,icu_fastintr12, IO_ICU2, ENABLE_ICU1_AND_2)
196 FAST_INTR(13,icu_fastintr13, IO_ICU2, ENABLE_ICU1_AND_2)
197 FAST_INTR(14,icu_fastintr14, IO_ICU2, ENABLE_ICU1_AND_2)
198 FAST_INTR(15,icu_fastintr15, IO_ICU2, ENABLE_ICU1_AND_2)