2 * $NetBSD: uhcireg.h,v 1.15 2002/02/11 11:41:30 augustss Exp $
3 * $FreeBSD: src/sys/dev/usb/uhcireg.h,v 1.21 2003/07/04 01:50:38 jmg Exp $
4 * $DragonFly: src/sys/bus/usb/uhcireg.h,v 1.4 2003/12/30 01:01:44 dillon Exp $
8 * Copyright (c) 1998 The NetBSD Foundation, Inc.
11 * This code is derived from software contributed to The NetBSD Foundation
12 * by Lennart Augustsson (lennart@augustsson.net) at
13 * Carlstedt Research & Technology.
15 * Redistribution and use in source and binary forms, with or without
16 * modification, are permitted provided that the following conditions
18 * 1. Redistributions of source code must retain the above copyright
19 * notice, this list of conditions and the following disclaimer.
20 * 2. Redistributions in binary form must reproduce the above copyright
21 * notice, this list of conditions and the following disclaimer in the
22 * documentation and/or other materials provided with the distribution.
23 * 3. All advertising materials mentioning features or use of this software
24 * must display the following acknowledgement:
25 * This product includes software developed by the NetBSD
26 * Foundation, Inc. and its contributors.
27 * 4. Neither the name of The NetBSD Foundation nor the names of its
28 * contributors may be used to endorse or promote products derived
29 * from this software without specific prior written permission.
31 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
32 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
33 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
34 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
35 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
36 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
37 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
38 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
39 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
40 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
41 * POSSIBILITY OF SUCH DAMAGE.
44 #ifndef _DEV_PCI_UHCIREG_H_
45 #define _DEV_PCI_UHCIREG_H_
47 /*** PCI config registers ***/
49 #define PCI_USBREV 0x60 /* USB protocol revision */
50 #define PCI_USBREV_MASK 0xff
51 #define PCI_USBREV_PRE_1_0 0x00
52 #define PCI_USBREV_1_0 0x10
53 #define PCI_USBREV_1_1 0x11
55 #define PCI_LEGSUP 0xc0 /* Legacy Support register */
56 #define PCI_LEGSUP_USBPIRQDEN 0x2000 /* USB PIRQ D Enable */
58 #define PCI_CBIO 0x20 /* configuration base IO */
60 #define PCI_INTERFACE_UHCI 0x00
62 /*** UHCI registers ***/
65 #define UHCI_CMD_RS 0x0001
66 #define UHCI_CMD_HCRESET 0x0002
67 #define UHCI_CMD_GRESET 0x0004
68 #define UHCI_CMD_EGSM 0x0008
69 #define UHCI_CMD_FGR 0x0010
70 #define UHCI_CMD_SWDBG 0x0020
71 #define UHCI_CMD_CF 0x0040
72 #define UHCI_CMD_MAXP 0x0080
75 #define UHCI_STS_USBINT 0x0001
76 #define UHCI_STS_USBEI 0x0002
77 #define UHCI_STS_RD 0x0004
78 #define UHCI_STS_HSE 0x0008
79 #define UHCI_STS_HCPE 0x0010
80 #define UHCI_STS_HCH 0x0020
81 #define UHCI_STS_ALLINTRS 0x003f
83 #define UHCI_INTR 0x04
84 #define UHCI_INTR_TOCRCIE 0x0001
85 #define UHCI_INTR_RIE 0x0002
86 #define UHCI_INTR_IOCE 0x0004
87 #define UHCI_INTR_SPIE 0x0008
89 #define UHCI_FRNUM 0x06
90 #define UHCI_FRNUM_MASK 0x03ff
92 #define UHCI_FLBASEADDR 0x08
95 #define UHCI_SOF_MASK 0x7f
97 #define UHCI_PORTSC1 0x010
98 #define UHCI_PORTSC2 0x012
99 #define UHCI_PORTSC_CCS 0x0001
100 #define UHCI_PORTSC_CSC 0x0002
101 #define UHCI_PORTSC_PE 0x0004
102 #define UHCI_PORTSC_POEDC 0x0008
103 #define UHCI_PORTSC_LS 0x0030
104 #define UHCI_PORTSC_LS_SHIFT 4
105 #define UHCI_PORTSC_RD 0x0040
106 #define UHCI_PORTSC_LSDA 0x0100
107 #define UHCI_PORTSC_PR 0x0200
108 #define UHCI_PORTSC_OCI 0x0400
109 #define UHCI_PORTSC_OCIC 0x0800
110 #define UHCI_PORTSC_SUSP 0x1000
113 ((x) & (UHCI_PORTSC_SUSP | UHCI_PORTSC_PR | UHCI_PORTSC_RD | UHCI_PORTSC_PE))
115 #define UHCI_FRAMELIST_COUNT 1024
116 #define UHCI_FRAMELIST_ALIGN 4096
118 #define UHCI_TD_ALIGN 16
119 #define UHCI_QH_ALIGN 16
121 typedef u_int32_t uhci_physaddr_t;
122 #define UHCI_PTR_T 0x00000001
123 #define UHCI_PTR_TD 0x00000000
124 #define UHCI_PTR_QH 0x00000002
125 #define UHCI_PTR_VF 0x00000004
128 * Wait this long after a QH has been removed. This gives that HC a
129 * chance to stop looking at it before it's recycled.
131 #define UHCI_QH_REMOVE_DELAY 5
134 * The Queue Heads and Transfer Descriptors are accessed
135 * by both the CPU and the USB controller which run
136 * concurrently. This means that they have to be accessed
137 * with great care. As long as the data structures are
138 * not linked into the controller's frame list they cannot
139 * be accessed by it and anything goes. As soon as a
140 * TD is accessible by the controller it "owns" the td_status
141 * field; it will not be written by the CPU. Similarly
142 * the controller "owns" the qh_elink field.
146 uhci_physaddr_t td_link;
148 #define UHCI_TD_GET_ACTLEN(s) (((s) + 1) & 0x3ff)
149 #define UHCI_TD_ZERO_ACTLEN(t) ((t) | 0x3ff)
150 #define UHCI_TD_BITSTUFF 0x00020000
151 #define UHCI_TD_CRCTO 0x00040000
152 #define UHCI_TD_NAK 0x00080000
153 #define UHCI_TD_BABBLE 0x00100000
154 #define UHCI_TD_DBUFFER 0x00200000
155 #define UHCI_TD_STALLED 0x00400000
156 #define UHCI_TD_ACTIVE 0x00800000
157 #define UHCI_TD_IOC 0x01000000
158 #define UHCI_TD_IOS 0x02000000
159 #define UHCI_TD_LS 0x04000000
160 #define UHCI_TD_GET_ERRCNT(s) (((s) >> 27) & 3)
161 #define UHCI_TD_SET_ERRCNT(n) ((n) << 27)
162 #define UHCI_TD_SPD 0x20000000
164 #define UHCI_TD_PID_IN 0x00000069
165 #define UHCI_TD_PID_OUT 0x000000e1
166 #define UHCI_TD_PID_SETUP 0x0000002d
167 #define UHCI_TD_GET_PID(s) ((s) & 0xff)
168 #define UHCI_TD_SET_DEVADDR(a) ((a) << 8)
169 #define UHCI_TD_GET_DEVADDR(s) (((s) >> 8) & 0x7f)
170 #define UHCI_TD_SET_ENDPT(e) (((e)&0xf) << 15)
171 #define UHCI_TD_GET_ENDPT(s) (((s) >> 15) & 0xf)
172 #define UHCI_TD_SET_DT(t) ((t) << 19)
173 #define UHCI_TD_GET_DT(s) (((s) >> 19) & 1)
174 #define UHCI_TD_SET_MAXLEN(l) (((l)-1) << 21)
175 #define UHCI_TD_GET_MAXLEN(s) ((((s) >> 21) + 1) & 0x7ff)
176 #define UHCI_TD_MAXLEN_MASK 0xffe00000
180 #define UHCI_TD_ERROR (UHCI_TD_BITSTUFF|UHCI_TD_CRCTO|UHCI_TD_BABBLE|UHCI_TD_DBUFFER|UHCI_TD_STALLED)
182 #define UHCI_TD_SETUP(len, endp, dev) (UHCI_TD_SET_MAXLEN(len) | \
183 UHCI_TD_SET_ENDPT(endp) | UHCI_TD_SET_DEVADDR(dev) | UHCI_TD_PID_SETUP)
184 #define UHCI_TD_OUT(len, endp, dev, dt) (UHCI_TD_SET_MAXLEN(len) | \
185 UHCI_TD_SET_ENDPT(endp) | UHCI_TD_SET_DEVADDR(dev) | \
186 UHCI_TD_PID_OUT | UHCI_TD_SET_DT(dt))
187 #define UHCI_TD_IN(len, endp, dev, dt) (UHCI_TD_SET_MAXLEN(len) | \
188 UHCI_TD_SET_ENDPT(endp) | UHCI_TD_SET_DEVADDR(dev) | UHCI_TD_PID_IN | \
192 uhci_physaddr_t qh_hlink;
193 uhci_physaddr_t qh_elink;
196 #endif /* _DEV_PCI_UHCIREG_H_ */