sys/dev/netif/ig_hal/e1000_hw.h

   1 /******************************************************************************
   2
   3   Copyright (c) 2001-2014, Intel Corporation
   4   All rights reserved.
   5
   6   Redistribution and use in source and binary forms, with or without
   7   modification, are permitted provided that the following conditions are met:
   8
   9    1. Redistributions of source code must retain the above copyright notice,
  10       this list of conditions and the following disclaimer.
  11
  12    2. Redistributions in binary form must reproduce the above copyright
  13       notice, this list of conditions and the following disclaimer in the
  14       documentation and/or other materials provided with the distribution.
  15
  16    3. Neither the name of the Intel Corporation nor the names of its
  17       contributors may be used to endorse or promote products derived from
  18       this software without specific prior written permission.
  19
  20   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23   ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30   POSSIBILITY OF SUCH DAMAGE.
  31
  32 ******************************************************************************/
  33 /*$FreeBSD:$*/
  34
  35 #ifndef _E1000_HW_H_
  36 #define _E1000_HW_H_
  37
  38 #include "e1000_osdep.h"
  39 #include "e1000_regs.h"
  40 #include "e1000_defines.h"
  41
  42 struct e1000_hw;
  43
  44 #ifndef NO_82542_SUPPORT
  45 #define E1000_DEV_ID_82542                      0x1000
  46 #endif
  47 #define E1000_DEV_ID_82543GC_FIBER              0x1001
  48 #define E1000_DEV_ID_82543GC_COPPER             0x1004
  49 #define E1000_DEV_ID_82544EI_COPPER             0x1008
  50 #define E1000_DEV_ID_82544EI_FIBER              0x1009
  51 #define E1000_DEV_ID_82544GC_COPPER             0x100C
  52 #define E1000_DEV_ID_82544GC_LOM                0x100D
  53 #define E1000_DEV_ID_82540EM                    0x100E
  54 #define E1000_DEV_ID_82540EM_LOM                0x1015
  55 #define E1000_DEV_ID_82540EP_LOM                0x1016
  56 #define E1000_DEV_ID_82540EP                    0x1017
  57 #define E1000_DEV_ID_82540EP_LP                 0x101E
  58 #define E1000_DEV_ID_82545EM_COPPER             0x100F
  59 #define E1000_DEV_ID_82545EM_FIBER              0x1011
  60 #define E1000_DEV_ID_82545GM_COPPER             0x1026
  61 #define E1000_DEV_ID_82545GM_FIBER              0x1027
  62 #define E1000_DEV_ID_82545GM_SERDES             0x1028
  63 #define E1000_DEV_ID_82546EB_COPPER             0x1010
  64 #define E1000_DEV_ID_82546EB_FIBER              0x1012
  65 #define E1000_DEV_ID_82546EB_QUAD_COPPER        0x101D
  66 #define E1000_DEV_ID_82546GB_COPPER             0x1079
  67 #define E1000_DEV_ID_82546GB_FIBER              0x107A
  68 #define E1000_DEV_ID_82546GB_SERDES             0x107B
  69 #define E1000_DEV_ID_82546GB_PCIE               0x108A
  70 #define E1000_DEV_ID_82546GB_QUAD_COPPER        0x1099
  71 #define E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3   0x10B5
  72 #define E1000_DEV_ID_82541EI                    0x1013
  73 #define E1000_DEV_ID_82541EI_MOBILE             0x1018
  74 #define E1000_DEV_ID_82541ER_LOM                0x1014
  75 #define E1000_DEV_ID_82541ER                    0x1078
  76 #define E1000_DEV_ID_82541GI                    0x1076
  77 #define E1000_DEV_ID_82541GI_LF                 0x107C
  78 #define E1000_DEV_ID_82541GI_MOBILE             0x1077
  79 #define E1000_DEV_ID_82547EI                    0x1019
  80 #define E1000_DEV_ID_82547EI_MOBILE             0x101A
  81 #define E1000_DEV_ID_82547GI                    0x1075
  82 #define E1000_DEV_ID_82571EB_COPPER             0x105E
  83 #define E1000_DEV_ID_82571EB_FIBER              0x105F
  84 #define E1000_DEV_ID_82571EB_SERDES             0x1060
  85 #define E1000_DEV_ID_82571EB_SERDES_DUAL        0x10D9
  86 #define E1000_DEV_ID_82571EB_SERDES_QUAD        0x10DA
  87 #define E1000_DEV_ID_82571EB_QUAD_COPPER        0x10A4
  88 #define E1000_DEV_ID_82571PT_QUAD_COPPER        0x10D5
  89 #define E1000_DEV_ID_82571EB_QUAD_FIBER         0x10A5
  90 #define E1000_DEV_ID_82571EB_QUAD_COPPER_LP     0x10BC
  91 #define E1000_DEV_ID_82571EB_QUAD_COPPER_BP     0x10A0
  92 #define E1000_DEV_ID_82572EI_COPPER             0x107D
  93 #define E1000_DEV_ID_82572EI_FIBER              0x107E
  94 #define E1000_DEV_ID_82572EI_SERDES             0x107F
  95 #define E1000_DEV_ID_82572EI                    0x10B9
  96 #define E1000_DEV_ID_82573E                     0x108B
  97 #define E1000_DEV_ID_82573E_IAMT                0x108C
  98 #define E1000_DEV_ID_82573L                     0x109A
  99 #define E1000_DEV_ID_82574L                     0x10D3
 100 #define E1000_DEV_ID_82574LA                    0x10F6
 101 #define E1000_DEV_ID_82583V                     0x150C
 102 #define E1000_DEV_ID_80003ES2LAN_COPPER_DPT     0x1096
 103 #define E1000_DEV_ID_80003ES2LAN_SERDES_DPT     0x1098
 104 #define E1000_DEV_ID_80003ES2LAN_COPPER_SPT     0x10BA
 105 #define E1000_DEV_ID_80003ES2LAN_SERDES_SPT     0x10BB
 106 #define E1000_DEV_ID_ICH8_82567V_3              0x1501
 107 #define E1000_DEV_ID_ICH8_IGP_M_AMT             0x1049
 108 #define E1000_DEV_ID_ICH8_IGP_AMT               0x104A
 109 #define E1000_DEV_ID_ICH8_IGP_C                 0x104B
 110 #define E1000_DEV_ID_ICH8_IFE                   0x104C
 111 #define E1000_DEV_ID_ICH8_IFE_GT                0x10C4
 112 #define E1000_DEV_ID_ICH8_IFE_G                 0x10C5
 113 #define E1000_DEV_ID_ICH8_IGP_M                 0x104D
 114 #define E1000_DEV_ID_ICH9_IGP_M                 0x10BF
 115 #define E1000_DEV_ID_ICH9_IGP_M_AMT             0x10F5
 116 #define E1000_DEV_ID_ICH9_IGP_M_V               0x10CB
 117 #define E1000_DEV_ID_ICH9_IGP_AMT               0x10BD
 118 #define E1000_DEV_ID_ICH9_BM                    0x10E5
 119 #define E1000_DEV_ID_ICH9_IGP_C                 0x294C
 120 #define E1000_DEV_ID_ICH9_IFE                   0x10C0
 121 #define E1000_DEV_ID_ICH9_IFE_GT                0x10C3
 122 #define E1000_DEV_ID_ICH9_IFE_G                 0x10C2
 123 #define E1000_DEV_ID_ICH10_R_BM_LM              0x10CC
 124 #define E1000_DEV_ID_ICH10_R_BM_LF              0x10CD
 125 #define E1000_DEV_ID_ICH10_R_BM_V               0x10CE
 126 #define E1000_DEV_ID_ICH10_D_BM_LM              0x10DE
 127 #define E1000_DEV_ID_ICH10_D_BM_LF              0x10DF
 128 #define E1000_DEV_ID_ICH10_D_BM_V               0x1525
 129
 130 #define E1000_DEV_ID_PCH_M_HV_LM                0x10EA
 131 #define E1000_DEV_ID_PCH_M_HV_LC                0x10EB
 132 #define E1000_DEV_ID_PCH_D_HV_DM                0x10EF
 133 #define E1000_DEV_ID_PCH_D_HV_DC                0x10F0
 134 #define E1000_DEV_ID_PCH2_LV_LM                 0x1502
 135 #define E1000_DEV_ID_PCH2_LV_V                  0x1503
 136
 137 #define E1000_DEV_ID_PCH_LPT_I217_LM            0x153A
 138 #define E1000_DEV_ID_PCH_LPT_I217_V             0x153B
 139 #define E1000_DEV_ID_PCH_LPTLP_I218_LM          0x155A
 140 #define E1000_DEV_ID_PCH_LPTLP_I218_V           0x1559
 141 #define E1000_DEV_ID_PCH_I218_LM2               0x15A0
 142 #define E1000_DEV_ID_PCH_I218_V2                0x15A1
 143 #define E1000_DEV_ID_PCH_I218_LM3               0x15A2 /* Wildcat Point PCH */
 144 #define E1000_DEV_ID_PCH_I218_V3                0x15A3 /* Wildcat Point PCH */
 145
 146 #define E1000_DEV_ID_82576                      0x10C9
 147 #define E1000_DEV_ID_82576_FIBER                0x10E6
 148 #define E1000_DEV_ID_82576_SERDES               0x10E7
 149 #define E1000_DEV_ID_82576_QUAD_COPPER          0x10E8
 150 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2      0x1526
 151 #define E1000_DEV_ID_82576_NS                   0x150A
 152 #define E1000_DEV_ID_82576_NS_SERDES            0x1518
 153 #define E1000_DEV_ID_82576_SERDES_QUAD          0x150D
 154 #define E1000_DEV_ID_82576_VF                   0x10CA
 155 #define E1000_DEV_ID_82576_VF_HV                0x152D
 156 #define E1000_DEV_ID_I350_VF                    0x1520
 157 #define E1000_DEV_ID_I350_VF_HV                 0x152F
 158 #define E1000_DEV_ID_82575EB_COPPER             0x10A7
 159 #define E1000_DEV_ID_82575EB_FIBER_SERDES       0x10A9
 160 #define E1000_DEV_ID_82575GB_QUAD_COPPER        0x10D6
 161 #define E1000_DEV_ID_82580_COPPER               0x150E
 162 #define E1000_DEV_ID_82580_FIBER                0x150F
 163 #define E1000_DEV_ID_82580_SERDES               0x1510
 164 #define E1000_DEV_ID_82580_SGMII                0x1511
 165 #define E1000_DEV_ID_82580_COPPER_DUAL          0x1516
 166 #define E1000_DEV_ID_82580_QUAD_FIBER           0x1527
 167 #define E1000_DEV_ID_I350_COPPER                0x1521
 168 #define E1000_DEV_ID_I350_FIBER                 0x1522
 169 #define E1000_DEV_ID_I350_SERDES                0x1523
 170 #define E1000_DEV_ID_I350_SGMII                 0x1524
 171 #define E1000_DEV_ID_I350_DA4                   0x1546
 172 #define E1000_DEV_ID_I210_COPPER                0x1533
 173 #define E1000_DEV_ID_I210_COPPER_OEM1           0x1534
 174 #define E1000_DEV_ID_I210_COPPER_IT             0x1535
 175 #define E1000_DEV_ID_I210_FIBER                 0x1536
 176 #define E1000_DEV_ID_I210_SERDES                0x1537
 177 #define E1000_DEV_ID_I210_SGMII                 0x1538
 178 #define E1000_DEV_ID_I210_COPPER_FLASHLESS      0x157B
 179 #define E1000_DEV_ID_I210_SERDES_FLASHLESS      0x157C
 180 #define E1000_DEV_ID_I211_COPPER                0x1539
 181 #define E1000_DEV_ID_I354_BACKPLANE_1GBPS       0x1F40
 182 #define E1000_DEV_ID_I354_SGMII                 0x1F41
 183 #define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS     0x1F45
 184 #define E1000_DEV_ID_DH89XXCC_SGMII             0x0438
 185 #define E1000_DEV_ID_DH89XXCC_SERDES            0x043A
 186 #define E1000_DEV_ID_DH89XXCC_BACKPLANE         0x043C
 187 #define E1000_DEV_ID_DH89XXCC_SFP               0x0440
 188
 189 #define E1000_REVISION_0        0
 190 #define E1000_REVISION_1        1
 191 #define E1000_REVISION_2        2
 192 #define E1000_REVISION_3        3
 193 #define E1000_REVISION_4        4
 194
 195 #define E1000_FUNC_0            0
 196 #define E1000_FUNC_1            1
 197 #define E1000_FUNC_2            2
 198 #define E1000_FUNC_3            3
 199
 200 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0       0
 201 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1       3
 202 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2       6
 203 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3       9
 204
 205 enum e1000_mac_type {
 206         e1000_undefined = 0,
 207 #ifndef NO_82542_SUPPORT
 208         e1000_82542,
 209 #endif
 210         e1000_82543,
 211         e1000_82544,
 212         e1000_82540,
 213         e1000_82545,
 214         e1000_82545_rev_3,
 215         e1000_82546,
 216         e1000_82546_rev_3,
 217         e1000_82541,
 218         e1000_82541_rev_2,
 219         e1000_82547,
 220         e1000_82547_rev_2,
 221         e1000_82571,
 222         e1000_82572,
 223         e1000_82573,
 224         e1000_82574,
 225         e1000_82583,
 226         e1000_80003es2lan,
 227         e1000_ich8lan,
 228         e1000_ich9lan,
 229         e1000_ich10lan,
 230         e1000_pchlan,
 231         e1000_pch2lan,
 232         e1000_pch_lpt,
 233         e1000_82575,
 234         e1000_82576,
 235         e1000_82580,
 236         e1000_i350,
 237         e1000_i354,
 238         e1000_i210,
 239         e1000_i211,
 240         e1000_vfadapt,
 241         e1000_vfadapt_i350,
 242         e1000_num_macs  /* List is 1-based, so subtract 1 for TRUE count. */
 243 };
 244
 245 enum e1000_media_type {
 246         e1000_media_type_unknown = 0,
 247         e1000_media_type_copper = 1,
 248         e1000_media_type_fiber = 2,
 249         e1000_media_type_internal_serdes = 3,
 250         e1000_num_media_types
 251 };
 252
 253 enum e1000_nvm_type {
 254         e1000_nvm_unknown = 0,
 255         e1000_nvm_none,
 256         e1000_nvm_eeprom_spi,
 257         e1000_nvm_eeprom_microwire,
 258         e1000_nvm_flash_hw,
 259         e1000_nvm_invm,
 260         e1000_nvm_flash_sw
 261 };
 262
 263 enum e1000_nvm_override {
 264         e1000_nvm_override_none = 0,
 265         e1000_nvm_override_spi_small,
 266         e1000_nvm_override_spi_large,
 267         e1000_nvm_override_microwire_small,
 268         e1000_nvm_override_microwire_large
 269 };
 270
 271 enum e1000_phy_type {
 272         e1000_phy_unknown = 0,
 273         e1000_phy_none,
 274         e1000_phy_m88,
 275         e1000_phy_igp,
 276         e1000_phy_igp_2,
 277         e1000_phy_gg82563,
 278         e1000_phy_igp_3,
 279         e1000_phy_ife,
 280         e1000_phy_bm,
 281         e1000_phy_82578,
 282         e1000_phy_82577,
 283         e1000_phy_82579,
 284         e1000_phy_i217,
 285         e1000_phy_82580,
 286         e1000_phy_vf,
 287         e1000_phy_i210,
 288 };
 289
 290 enum e1000_bus_type {
 291         e1000_bus_type_unknown = 0,
 292         e1000_bus_type_pci,
 293         e1000_bus_type_pcix,
 294         e1000_bus_type_pci_express,
 295         e1000_bus_type_reserved
 296 };
 297
 298 enum e1000_bus_speed {
 299         e1000_bus_speed_unknown = 0,
 300         e1000_bus_speed_33,
 301         e1000_bus_speed_66,
 302         e1000_bus_speed_100,
 303         e1000_bus_speed_120,
 304         e1000_bus_speed_133,
 305         e1000_bus_speed_2500,
 306         e1000_bus_speed_5000,
 307         e1000_bus_speed_reserved
 308 };
 309
 310 enum e1000_bus_width {
 311         e1000_bus_width_unknown = 0,
 312         e1000_bus_width_pcie_x1,
 313         e1000_bus_width_pcie_x2,
 314         e1000_bus_width_pcie_x4 = 4,
 315         e1000_bus_width_pcie_x8 = 8,
 316         e1000_bus_width_32,
 317         e1000_bus_width_64,
 318         e1000_bus_width_reserved
 319 };
 320
 321 enum e1000_1000t_rx_status {
 322         e1000_1000t_rx_status_not_ok = 0,
 323         e1000_1000t_rx_status_ok,
 324         e1000_1000t_rx_status_undefined = 0xFF
 325 };
 326
 327 enum e1000_rev_polarity {
 328         e1000_rev_polarity_normal = 0,
 329         e1000_rev_polarity_reversed,
 330         e1000_rev_polarity_undefined = 0xFF
 331 };
 332
 333 enum e1000_fc_mode {
 334         e1000_fc_none = 0,
 335         e1000_fc_rx_pause,
 336         e1000_fc_tx_pause,
 337         e1000_fc_full,
 338         e1000_fc_default = 0xFF
 339 };
 340
 341 enum e1000_ffe_config {
 342         e1000_ffe_config_enabled = 0,
 343         e1000_ffe_config_active,
 344         e1000_ffe_config_blocked
 345 };
 346
 347 enum e1000_dsp_config {
 348         e1000_dsp_config_disabled = 0,
 349         e1000_dsp_config_enabled,
 350         e1000_dsp_config_activated,
 351         e1000_dsp_config_undefined = 0xFF
 352 };
 353
 354 enum e1000_ms_type {
 355         e1000_ms_hw_default = 0,
 356         e1000_ms_force_master,
 357         e1000_ms_force_slave,
 358         e1000_ms_auto
 359 };
 360
 361 enum e1000_smart_speed {
 362         e1000_smart_speed_default = 0,
 363         e1000_smart_speed_on,
 364         e1000_smart_speed_off
 365 };
 366
 367 enum e1000_serdes_link_state {
 368         e1000_serdes_link_down = 0,
 369         e1000_serdes_link_autoneg_progress,
 370         e1000_serdes_link_autoneg_complete,
 371         e1000_serdes_link_forced_up
 372 };
 373
 374 #define __le16 u16
 375 #define __le32 u32
 376 #define __le64 u64
 377 /* Receive Descriptor */
 378 struct e1000_rx_desc {
 379         __le64 buffer_addr; /* Address of the descriptor's data buffer */
 380         __le16 length;      /* Length of data DMAed into data buffer */
 381         __le16 csum; /* Packet checksum */
 382         u8  status;  /* Descriptor status */
 383         u8  errors;  /* Descriptor Errors */
 384         __le16 special;
 385 };
 386
 387 /* Receive Descriptor - Extended */
 388 union e1000_rx_desc_extended {
 389         struct {
 390                 __le64 buffer_addr;
 391                 __le64 reserved;
 392         } read;
 393         struct {
 394                 struct {
 395                         __le32 mrq; /* Multiple Rx Queues */
 396                         union {
 397                                 __le32 rss; /* RSS Hash */
 398                                 struct {
 399                                         __le16 ip_id;  /* IP id */
 400                                         __le16 csum;   /* Packet Checksum */
 401                                 } csum_ip;
 402                         } hi_dword;
 403                 } lower;
 404                 struct {
 405                         __le32 status_error;  /* ext status/error */
 406                         __le16 length;
 407                         __le16 vlan; /* VLAN tag */
 408                 } upper;
 409         } wb;  /* writeback */
 410 };
 411
 412 #define MAX_PS_BUFFERS 4
 413
 414 /* Number of packet split data buffers (not including the header buffer) */
 415 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
 416
 417 /* Receive Descriptor - Packet Split */
 418 union e1000_rx_desc_packet_split {
 419         struct {
 420                 /* one buffer for protocol header(s), three data buffers */
 421                 __le64 buffer_addr[MAX_PS_BUFFERS];
 422         } read;
 423         struct {
 424                 struct {
 425                         __le32 mrq;  /* Multiple Rx Queues */
 426                         union {
 427                                 __le32 rss; /* RSS Hash */
 428                                 struct {
 429                                         __le16 ip_id;    /* IP id */
 430                                         __le16 csum;     /* Packet Checksum */
 431                                 } csum_ip;
 432                         } hi_dword;
 433                 } lower;
 434                 struct {
 435                         __le32 status_error;  /* ext status/error */
 436                         __le16 length0;  /* length of buffer 0 */
 437                         __le16 vlan;  /* VLAN tag */
 438                 } middle;
 439                 struct {
 440                         __le16 header_status;
 441                         /* length of buffers 1-3 */
 442                         __le16 length[PS_PAGE_BUFFERS];
 443                 } upper;
 444                 __le64 reserved;
 445         } wb; /* writeback */
 446 };
 447
 448 /* Transmit Descriptor */
 449 struct e1000_tx_desc {
 450         __le64 buffer_addr;   /* Address of the descriptor's data buffer */
 451         union {
 452                 __le32 data;
 453                 struct {
 454                         __le16 length;  /* Data buffer length */
 455                         u8 cso;  /* Checksum offset */
 456                         u8 cmd;  /* Descriptor control */
 457                 } flags;
 458         } lower;
 459         union {
 460                 __le32 data;
 461                 struct {
 462                         u8 status; /* Descriptor status */
 463                         u8 css;  /* Checksum start */
 464                         __le16 special;
 465                 } fields;
 466         } upper;
 467 };
 468
 469 /* Offload Context Descriptor */
 470 struct e1000_context_desc {
 471         union {
 472                 __le32 ip_config;
 473                 struct {
 474                         u8 ipcss;  /* IP checksum start */
 475                         u8 ipcso;  /* IP checksum offset */
 476                         __le16 ipcse;  /* IP checksum end */
 477                 } ip_fields;
 478         } lower_setup;
 479         union {
 480                 __le32 tcp_config;
 481                 struct {
 482                         u8 tucss;  /* TCP checksum start */
 483                         u8 tucso;  /* TCP checksum offset */
 484                         __le16 tucse;  /* TCP checksum end */
 485                 } tcp_fields;
 486         } upper_setup;
 487         __le32 cmd_and_length;
 488         union {
 489                 __le32 data;
 490                 struct {
 491                         u8 status;  /* Descriptor status */
 492                         u8 hdr_len;  /* Header length */
 493                         __le16 mss;  /* Maximum segment size */
 494                 } fields;
 495         } tcp_seg_setup;
 496 };
 497
 498 /* Offload data descriptor */
 499 struct e1000_data_desc {
 500         __le64 buffer_addr;  /* Address of the descriptor's buffer address */
 501         union {
 502                 __le32 data;
 503                 struct {
 504                         __le16 length;  /* Data buffer length */
 505                         u8 typ_len_ext;
 506                         u8 cmd;
 507                 } flags;
 508         } lower;
 509         union {
 510                 __le32 data;
 511                 struct {
 512                         u8 status;  /* Descriptor status */
 513                         u8 popts;  /* Packet Options */
 514                         __le16 special;
 515                 } fields;
 516         } upper;
 517 };
 518
 519 /* Statistics counters collected by the MAC */
 520 struct e1000_hw_stats {
 521         u64 crcerrs;
 522         u64 algnerrc;
 523         u64 symerrs;
 524         u64 rxerrc;
 525         u64 mpc;
 526         u64 scc;
 527         u64 ecol;
 528         u64 mcc;
 529         u64 latecol;
 530         u64 colc;
 531         u64 dc;
 532         u64 tncrs;
 533         u64 sec;
 534         u64 cexterr;
 535         u64 rlec;
 536         u64 xonrxc;
 537         u64 xontxc;
 538         u64 xoffrxc;
 539         u64 xofftxc;
 540         u64 fcruc;
 541         u64 prc64;
 542         u64 prc127;
 543         u64 prc255;
 544         u64 prc511;
 545         u64 prc1023;
 546         u64 prc1522;
 547         u64 gprc;
 548         u64 bprc;
 549         u64 mprc;
 550         u64 gptc;
 551         u64 gorc;
 552         u64 gotc;
 553         u64 rnbc;
 554         u64 ruc;
 555         u64 rfc;
 556         u64 roc;
 557         u64 rjc;
 558         u64 mgprc;
 559         u64 mgpdc;
 560         u64 mgptc;
 561         u64 tor;
 562         u64 tot;
 563         u64 tpr;
 564         u64 tpt;
 565         u64 ptc64;
 566         u64 ptc127;
 567         u64 ptc255;
 568         u64 ptc511;
 569         u64 ptc1023;
 570         u64 ptc1522;
 571         u64 mptc;
 572         u64 bptc;
 573         u64 tsctc;
 574         u64 tsctfc;
 575         u64 iac;
 576         u64 icrxptc;
 577         u64 icrxatc;
 578         u64 ictxptc;
 579         u64 ictxatc;
 580         u64 ictxqec;
 581         u64 ictxqmtc;
 582         u64 icrxdmtc;
 583         u64 icrxoc;
 584         u64 cbtmpc;
 585         u64 htdpmc;
 586         u64 cbrdpc;
 587         u64 cbrmpc;
 588         u64 rpthc;
 589         u64 hgptc;
 590         u64 htcbdpc;
 591         u64 hgorc;
 592         u64 hgotc;
 593         u64 lenerrs;
 594         u64 scvpc;
 595         u64 hrmpc;
 596         u64 doosync;
 597         u64 o2bgptc;
 598         u64 o2bspc;
 599         u64 b2ospc;
 600         u64 b2ogprc;
 601 };
 602
 603 struct e1000_vf_stats {
 604         u64 base_gprc;
 605         u64 base_gptc;
 606         u64 base_gorc;
 607         u64 base_gotc;
 608         u64 base_mprc;
 609         u64 base_gotlbc;
 610         u64 base_gptlbc;
 611         u64 base_gorlbc;
 612         u64 base_gprlbc;
 613
 614         u32 last_gprc;
 615         u32 last_gptc;
 616         u32 last_gorc;
 617         u32 last_gotc;
 618         u32 last_mprc;
 619         u32 last_gotlbc;
 620         u32 last_gptlbc;
 621         u32 last_gorlbc;
 622         u32 last_gprlbc;
 623
 624         u64 gprc;
 625         u64 gptc;
 626         u64 gorc;
 627         u64 gotc;
 628         u64 mprc;
 629         u64 gotlbc;
 630         u64 gptlbc;
 631         u64 gorlbc;
 632         u64 gprlbc;
 633 };
 634
 635 struct e1000_phy_stats {
 636         u32 idle_errors;
 637         u32 receive_errors;
 638 };
 639
 640 struct e1000_host_mng_dhcp_cookie {
 641         u32 signature;
 642         u8  status;
 643         u8  reserved0;
 644         u16 vlan_id;
 645         u32 reserved1;
 646         u16 reserved2;
 647         u8  reserved3;
 648         u8  checksum;
 649 };
 650
 651 /* Host Interface "Rev 1" */
 652 struct e1000_host_command_header {
 653         u8 command_id;
 654         u8 command_length;
 655         u8 command_options;
 656         u8 checksum;
 657 };
 658
 659 #define E1000_HI_MAX_DATA_LENGTH        252
 660 struct e1000_host_command_info {
 661         struct e1000_host_command_header command_header;
 662         u8 command_data[E1000_HI_MAX_DATA_LENGTH];
 663 };
 664
 665 /* Host Interface "Rev 2" */
 666 struct e1000_host_mng_command_header {
 667         u8  command_id;
 668         u8  checksum;
 669         u16 reserved1;
 670         u16 reserved2;
 671         u16 command_length;
 672 };
 673
 674 #define E1000_HI_MAX_MNG_DATA_LENGTH    0x6F8
 675 struct e1000_host_mng_command_info {
 676         struct e1000_host_mng_command_header command_header;
 677         u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
 678 };
 679
 680 #include "e1000_mac.h"
 681 #include "e1000_phy.h"
 682 #include "e1000_nvm.h"
 683 #include "e1000_manage.h"
 684 #include "e1000_mbx.h"
 685
 686 /* Function pointers for the MAC. */
 687 struct e1000_mac_operations {
 688         s32  (*init_params)(struct e1000_hw *);
 689         s32  (*id_led_init)(struct e1000_hw *);
 690         s32  (*blink_led)(struct e1000_hw *);
 691         bool (*check_mng_mode)(struct e1000_hw *);
 692         s32  (*check_for_link)(struct e1000_hw *);
 693         s32  (*cleanup_led)(struct e1000_hw *);
 694         void (*clear_hw_cntrs)(struct e1000_hw *);
 695         void (*clear_vfta)(struct e1000_hw *);
 696         s32  (*get_bus_info)(struct e1000_hw *);
 697         void (*set_lan_id)(struct e1000_hw *);
 698         s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
 699         s32  (*led_on)(struct e1000_hw *);
 700         s32  (*led_off)(struct e1000_hw *);
 701         void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
 702         s32  (*reset_hw)(struct e1000_hw *);
 703         s32  (*init_hw)(struct e1000_hw *);
 704         void (*shutdown_serdes)(struct e1000_hw *);
 705         void (*power_up_serdes)(struct e1000_hw *);
 706         s32  (*setup_link)(struct e1000_hw *);
 707         s32  (*setup_physical_interface)(struct e1000_hw *);
 708         s32  (*setup_led)(struct e1000_hw *);
 709         void (*write_vfta)(struct e1000_hw *, u32, u32);
 710         void (*config_collision_dist)(struct e1000_hw *);
 711         int  (*rar_set)(struct e1000_hw *, u8*, u32);
 712         s32  (*read_mac_addr)(struct e1000_hw *);
 713         s32  (*validate_mdi_setting)(struct e1000_hw *);
 714         s32  (*acquire_swfw_sync)(struct e1000_hw *, u16);
 715         void (*release_swfw_sync)(struct e1000_hw *, u16);
 716         s32  (*set_obff_timer)(struct e1000_hw *, u32);
 717 };
 718
 719 /* When to use various PHY register access functions:
 720  *
 721  *                 Func   Caller
 722  *   Function      Does   Does    When to use
 723  *   ~~~~~~~~~~~~  ~~~~~  ~~~~~~  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 724  *   X_reg         L,P,A  n/a     for simple PHY reg accesses
 725  *   X_reg_locked  P,A    L       for multiple accesses of different regs
 726  *                                on different pages
 727  *   X_reg_page    A      L,P     for multiple accesses of different regs
 728  *                                on the same page
 729  *
 730  * Where X=[read|write], L=locking, P=sets page, A=register access
 731  *
 732  */
 733 struct e1000_phy_operations {
 734         s32  (*init_params)(struct e1000_hw *);
 735         s32  (*acquire)(struct e1000_hw *);
 736         s32  (*cfg_on_link_up)(struct e1000_hw *);
 737         s32  (*check_polarity)(struct e1000_hw *);
 738         s32  (*check_reset_block)(struct e1000_hw *);
 739         s32  (*commit)(struct e1000_hw *);
 740         s32  (*force_speed_duplex)(struct e1000_hw *);
 741         s32  (*get_cfg_done)(struct e1000_hw *hw);
 742         s32  (*get_cable_length)(struct e1000_hw *);
 743         s32  (*get_info)(struct e1000_hw *);
 744         s32  (*set_page)(struct e1000_hw *, u16);
 745         s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
 746         s32  (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
 747         s32  (*read_reg_page)(struct e1000_hw *, u32, u16 *);
 748         void (*release)(struct e1000_hw *);
 749         s32  (*reset)(struct e1000_hw *);
 750         s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
 751         s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
 752         s32  (*write_reg)(struct e1000_hw *, u32, u16);
 753         s32  (*write_reg_locked)(struct e1000_hw *, u32, u16);
 754         s32  (*write_reg_page)(struct e1000_hw *, u32, u16);
 755         void (*power_up)(struct e1000_hw *);
 756         void (*power_down)(struct e1000_hw *);
 757         s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *);
 758         s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8);
 759 };
 760
 761 /* Function pointers for the NVM. */
 762 struct e1000_nvm_operations {
 763         s32  (*init_params)(struct e1000_hw *);
 764         s32  (*acquire)(struct e1000_hw *);
 765         s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
 766         void (*release)(struct e1000_hw *);
 767         void (*reload)(struct e1000_hw *);
 768         s32  (*update)(struct e1000_hw *);
 769         s32  (*valid_led_default)(struct e1000_hw *, u16 *);
 770         s32  (*validate)(struct e1000_hw *);
 771         s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
 772 };
 773
 774 struct e1000_mac_info {
 775         struct e1000_mac_operations ops;
 776         u8 addr[ETH_ADDR_LEN];
 777         u8 perm_addr[ETH_ADDR_LEN];
 778
 779         enum e1000_mac_type type;
 780
 781         u32 collision_delta;
 782         u32 ledctl_default;
 783         u32 ledctl_mode1;
 784         u32 ledctl_mode2;
 785         u32 mc_filter_type;
 786         u32 tx_packet_delta;
 787         u32 txcw;
 788
 789         u16 current_ifs_val;
 790         u16 ifs_max_val;
 791         u16 ifs_min_val;
 792         u16 ifs_ratio;
 793         u16 ifs_step_size;
 794         u16 mta_reg_count;
 795         u16 uta_reg_count;
 796
 797         /* Maximum size of the MTA register table in all supported adapters */
 798 #define MAX_MTA_REG 128
 799         u32 mta_shadow[MAX_MTA_REG];
 800         u16 rar_entry_count;
 801
 802         u8  forced_speed_duplex;
 803
 804         bool adaptive_ifs;
 805         bool has_fwsm;
 806         bool arc_subsystem_valid;
 807         bool asf_firmware_present;
 808         bool autoneg;
 809         bool autoneg_failed;
 810         bool get_link_status;
 811         bool in_ifs_mode;
 812 #ifndef NO_82542_SUPPORT
 813         bool report_tx_early;
 814 #endif
 815         enum e1000_serdes_link_state serdes_link_state;
 816         bool serdes_has_link;
 817         bool tx_pkt_filtering;
 818         u32 max_frame_size;
 819 };
 820
 821 struct e1000_phy_info {
 822         struct e1000_phy_operations ops;
 823         enum e1000_phy_type type;
 824
 825         enum e1000_1000t_rx_status local_rx;
 826         enum e1000_1000t_rx_status remote_rx;
 827         enum e1000_ms_type ms_type;
 828         enum e1000_ms_type original_ms_type;
 829         enum e1000_rev_polarity cable_polarity;
 830         enum e1000_smart_speed smart_speed;
 831
 832         u32 addr;
 833         u32 id;
 834         u32 reset_delay_us; /* in usec */
 835         u32 revision;
 836
 837         enum e1000_media_type media_type;
 838
 839         u16 autoneg_advertised;
 840         u16 autoneg_mask;
 841         u16 cable_length;
 842         u16 max_cable_length;
 843         u16 min_cable_length;
 844
 845         u8 mdix;
 846
 847         bool disable_polarity_correction;
 848         bool is_mdix;
 849         bool polarity_correction;
 850         bool speed_downgraded;
 851         bool autoneg_wait_to_complete;
 852 };
 853
 854 struct e1000_nvm_info {
 855         struct e1000_nvm_operations ops;
 856         enum e1000_nvm_type type;
 857         enum e1000_nvm_override override;
 858
 859         u32 flash_bank_size;
 860         u32 flash_base_addr;
 861
 862         u16 word_size;
 863         u16 delay_usec;
 864         u16 address_bits;
 865         u16 opcode_bits;
 866         u16 page_size;
 867 };
 868
 869 struct e1000_bus_info {
 870         enum e1000_bus_type type;
 871         enum e1000_bus_speed speed;
 872         enum e1000_bus_width width;
 873
 874         u16 func;
 875         u16 pci_cmd_word;
 876 };
 877
 878 struct e1000_fc_info {
 879         u32 high_water;  /* Flow control high-water mark */
 880         u32 low_water;  /* Flow control low-water mark */
 881         u16 pause_time;  /* Flow control pause timer */
 882         u16 refresh_time;  /* Flow control refresh timer */
 883         bool send_xon;  /* Flow control send XON */
 884         bool strict_ieee;  /* Strict IEEE mode */
 885         enum e1000_fc_mode current_mode;  /* FC mode in effect */
 886         enum e1000_fc_mode requested_mode;  /* FC mode requested by caller */
 887 };
 888
 889 struct e1000_dev_spec_82541 {
 890         enum e1000_dsp_config dsp_config;
 891         enum e1000_ffe_config ffe_config;
 892         u16 spd_default;
 893         bool phy_init_script;
 894 };
 895
 896 #ifndef NO_82542_SUPPORT
 897 struct e1000_dev_spec_82542 {
 898         bool dma_fairness;
 899 };
 900
 901 #endif /* NO_82542_SUPPORT */
 902 struct e1000_dev_spec_82543 {
 903         u32  tbi_compatibility;
 904         bool dma_fairness;
 905         bool init_phy_disabled;
 906 };
 907
 908 struct e1000_dev_spec_82571 {
 909         bool laa_is_present;
 910         u32 smb_counter;
 911 };
 912
 913 struct e1000_dev_spec_80003es2lan {
 914         bool  mdic_wa_enable;
 915 };
 916
 917 struct e1000_shadow_ram {
 918         u16  value;
 919         bool modified;
 920 };
 921
 922 struct e1000_mbx_operations {
 923         s32 (*init_params)(struct e1000_hw *hw);
 924         s32 (*read)(struct e1000_hw *, u32 *, u16,  u16);
 925         s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
 926         s32 (*read_posted)(struct e1000_hw *, u32 *, u16,  u16);
 927         s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
 928         s32 (*check_for_msg)(struct e1000_hw *, u16);
 929         s32 (*check_for_ack)(struct e1000_hw *, u16);
 930         s32 (*check_for_rst)(struct e1000_hw *, u16);
 931 };
 932
 933 struct e1000_mbx_stats {
 934         u32 msgs_tx;
 935         u32 msgs_rx;
 936
 937         u32 acks;
 938         u32 reqs;
 939         u32 rsts;
 940 };
 941
 942 struct e1000_mbx_info {
 943         struct e1000_mbx_operations ops;
 944         struct e1000_mbx_stats stats;
 945         u32 timeout;
 946         u32 usec_delay;
 947         u16 size;
 948 };
 949
 950 struct e1000_dev_spec_82575 {
 951         bool sgmii_active;
 952         bool global_device_reset;
 953         bool eee_disable;
 954         bool module_plugged;
 955         bool clear_semaphore_once;
 956         u32 mtu;
 957         struct sfp_e1000_flags eth_flags;
 958         u8 media_port;
 959         bool media_changed;
 960 };
 961
 962 #define E1000_SHADOW_RAM_WORDS  2048
 963
 964 /* I218 PHY Ultra Low Power (ULP) states */
 965 enum e1000_ulp_state {
 966         e1000_ulp_state_unknown,
 967         e1000_ulp_state_off,
 968         e1000_ulp_state_on,
 969 };
 970
 971 struct e1000_dev_spec_ich8lan {
 972         bool kmrn_lock_loss_workaround_enabled;
 973         struct e1000_shadow_ram shadow_ram[E1000_SHADOW_RAM_WORDS];
 974         bool nvm_k1_enabled;
 975         bool eee_disable;
 976         u16 eee_lp_ability;
 977         enum e1000_ulp_state ulp_state;
 978 };
 979
 980 struct e1000_dev_spec_vf {
 981         u32 vf_number;
 982         u32 v2p_mailbox;
 983 };
 984
 985 struct e1000_hw {
 986         void *back;
 987
 988         u8 *hw_addr;
 989         u8 *flash_address;
 990         unsigned long io_base;
 991
 992         struct e1000_mac_info  mac;
 993         struct e1000_fc_info   fc;
 994         struct e1000_phy_info  phy;
 995         struct e1000_nvm_info  nvm;
 996         struct e1000_bus_info  bus;
 997         struct e1000_mbx_info mbx;
 998         struct e1000_host_mng_dhcp_cookie mng_cookie;
 999
1000         union {
1001                 struct e1000_dev_spec_82541 _82541;
1002 #ifndef NO_82542_SUPPORT
1003                 struct e1000_dev_spec_82542 _82542;
1004 #endif
1005                 struct e1000_dev_spec_82543 _82543;
1006                 struct e1000_dev_spec_82571 _82571;
1007                 struct e1000_dev_spec_80003es2lan _80003es2lan;
1008                 struct e1000_dev_spec_ich8lan ich8lan;
1009                 struct e1000_dev_spec_82575 _82575;
1010                 struct e1000_dev_spec_vf vf;
1011         } dev_spec;
1012
1013         u16 device_id;
1014         u16 subsystem_vendor_id;
1015         u16 subsystem_device_id;
1016         u16 vendor_id;
1017
1018         u8  revision_id;
1019 };
1020
1021 #include "e1000_82541.h"
1022 #include "e1000_82543.h"
1023 #include "e1000_82571.h"
1024 #include "e1000_80003es2lan.h"
1025 #include "e1000_ich8lan.h"
1026 #include "e1000_82575.h"
1027 #include "e1000_i210.h"
1028
1029 /* These functions must be implemented by drivers */
1030 #ifndef NO_82542_SUPPORT
1031 void e1000_pci_clear_mwi(struct e1000_hw *hw);
1032 void e1000_pci_set_mwi(struct e1000_hw *hw);
1033 #endif
1034 s32  e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
1035 s32  e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
1036 void e1000_read_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
1037 void e1000_write_pci_cfg(struct e1000_hw *hw, u32 reg, u16 *value);
1038
1039 #endif