2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 * $FreeBSD: head/sys/dev/drm2/radeon/radeon_device.c 255573 2013-09-14 17:24:41Z dumbbell $
32 #include <drm/drm_crtc_helper.h>
33 #include <uapi_drm/radeon_drm.h>
34 #include "radeon_reg.h"
38 static const char radeon_family_name[][16] = {
98 * radeon_surface_init - Clear GPU surface registers.
100 * @rdev: radeon_device pointer
102 * Clear GPU surface registers (r1xx-r5xx).
104 void radeon_surface_init(struct radeon_device *rdev)
106 /* FIXME: check this out */
107 if (rdev->family < CHIP_R600) {
110 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
111 if (rdev->surface_regs[i].bo)
112 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
114 radeon_clear_surface_reg(rdev, i);
116 /* enable surfaces */
117 WREG32(RADEON_SURFACE_CNTL, 0);
122 * GPU scratch registers helpers function.
125 * radeon_scratch_init - Init scratch register driver information.
127 * @rdev: radeon_device pointer
129 * Init CP scratch register driver information (r1xx-r5xx)
131 void radeon_scratch_init(struct radeon_device *rdev)
135 /* FIXME: check this out */
136 if (rdev->family < CHIP_R300) {
137 rdev->scratch.num_reg = 5;
139 rdev->scratch.num_reg = 7;
141 rdev->scratch.reg_base = RADEON_SCRATCH_REG0;
142 for (i = 0; i < rdev->scratch.num_reg; i++) {
143 rdev->scratch.free[i] = true;
144 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
149 * radeon_scratch_get - Allocate a scratch register
151 * @rdev: radeon_device pointer
152 * @reg: scratch register mmio offset
154 * Allocate a CP scratch register for use by the driver (all asics).
155 * Returns 0 on success or -EINVAL on failure.
157 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
161 for (i = 0; i < rdev->scratch.num_reg; i++) {
162 if (rdev->scratch.free[i]) {
163 rdev->scratch.free[i] = false;
164 *reg = rdev->scratch.reg[i];
172 * radeon_scratch_free - Free a scratch register
174 * @rdev: radeon_device pointer
175 * @reg: scratch register mmio offset
177 * Free a CP scratch register allocated for use by the driver (all asics)
179 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
183 for (i = 0; i < rdev->scratch.num_reg; i++) {
184 if (rdev->scratch.reg[i] == reg) {
185 rdev->scratch.free[i] = true;
193 * Writeback is the the method by which the the GPU updates special pages
194 * in memory with the status of certain GPU events (fences, ring pointers,
199 * radeon_wb_disable - Disable Writeback
201 * @rdev: radeon_device pointer
203 * Disables Writeback (all asics). Used for suspend.
205 void radeon_wb_disable(struct radeon_device *rdev)
209 if (rdev->wb.wb_obj) {
210 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
211 if (unlikely(r != 0))
213 radeon_bo_kunmap(rdev->wb.wb_obj);
214 radeon_bo_unpin(rdev->wb.wb_obj);
215 radeon_bo_unreserve(rdev->wb.wb_obj);
217 rdev->wb.enabled = false;
221 * radeon_wb_fini - Disable Writeback and free memory
223 * @rdev: radeon_device pointer
225 * Disables Writeback and frees the Writeback memory (all asics).
226 * Used at driver shutdown.
228 void radeon_wb_fini(struct radeon_device *rdev)
230 radeon_wb_disable(rdev);
231 if (rdev->wb.wb_obj) {
232 radeon_bo_unref(&rdev->wb.wb_obj);
234 rdev->wb.wb_obj = NULL;
239 * radeon_wb_init- Init Writeback driver info and allocate memory
241 * @rdev: radeon_device pointer
243 * Disables Writeback and frees the Writeback memory (all asics).
244 * Used at driver startup.
245 * Returns 0 on success or an -error on failure.
247 int radeon_wb_init(struct radeon_device *rdev)
252 if (rdev->wb.wb_obj == NULL) {
253 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
254 RADEON_GEM_DOMAIN_GTT, NULL, &rdev->wb.wb_obj);
256 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
260 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
261 if (unlikely(r != 0)) {
262 radeon_wb_fini(rdev);
265 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
268 radeon_bo_unreserve(rdev->wb.wb_obj);
269 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
270 radeon_wb_fini(rdev);
273 wb_ptr = &rdev->wb.wb;
274 r = radeon_bo_kmap(rdev->wb.wb_obj, wb_ptr);
275 radeon_bo_unreserve(rdev->wb.wb_obj);
277 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
278 radeon_wb_fini(rdev);
282 /* clear wb memory */
283 memset(*(void **)wb_ptr, 0, RADEON_GPU_PAGE_SIZE);
284 /* disable event_write fences */
285 rdev->wb.use_event = false;
286 /* disabled via module param */
287 if (radeon_no_wb == 1) {
288 rdev->wb.enabled = false;
290 if (rdev->flags & RADEON_IS_AGP) {
291 /* often unreliable on AGP */
292 rdev->wb.enabled = false;
293 } else if (rdev->family < CHIP_R300) {
294 /* often unreliable on pre-r300 */
295 rdev->wb.enabled = false;
297 rdev->wb.enabled = true;
298 /* event_write fences are only available on r600+ */
299 if (rdev->family >= CHIP_R600) {
300 rdev->wb.use_event = true;
304 /* always use writeback/events on NI, APUs */
305 if (rdev->family >= CHIP_PALM) {
306 rdev->wb.enabled = true;
307 rdev->wb.use_event = true;
310 dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis");
316 * radeon_vram_location - try to find VRAM location
317 * @rdev: radeon device structure holding all necessary informations
318 * @mc: memory controller structure holding memory informations
319 * @base: base address at which to put VRAM
321 * Function will place try to place VRAM at base address provided
322 * as parameter (which is so far either PCI aperture address or
323 * for IGP TOM base address).
325 * If there is not enough space to fit the unvisible VRAM in the 32bits
326 * address space then we limit the VRAM size to the aperture.
328 * If we are using AGP and if the AGP aperture doesn't allow us to have
329 * room for all the VRAM than we restrict the VRAM to the PCI aperture
330 * size and print a warning.
332 * This function will never fails, worst case are limiting VRAM.
334 * Note: GTT start, end, size should be initialized before calling this
335 * function on AGP platform.
337 * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size,
338 * this shouldn't be a problem as we are using the PCI aperture as a reference.
339 * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but
342 * Note: we use mc_vram_size as on some board we need to program the mc to
343 * cover the whole aperture even if VRAM size is inferior to aperture size
344 * Novell bug 204882 + along with lots of ubuntu ones
346 * Note: when limiting vram it's safe to overwritte real_vram_size because
347 * we are not in case where real_vram_size is inferior to mc_vram_size (ie
348 * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu
351 * Note: IGP TOM addr should be the same as the aperture addr, we don't
352 * explicitly check for that thought.
354 * FIXME: when reducing VRAM size align new size on power of 2.
356 void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
358 uint64_t limit = (uint64_t)radeon_vram_limit << 20;
360 mc->vram_start = base;
361 if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) {
362 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
363 mc->real_vram_size = mc->aper_size;
364 mc->mc_vram_size = mc->aper_size;
366 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
367 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) {
368 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
369 mc->real_vram_size = mc->aper_size;
370 mc->mc_vram_size = mc->aper_size;
372 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
373 if (limit && limit < mc->real_vram_size)
374 mc->real_vram_size = limit;
375 dev_info(rdev->dev, "VRAM: %juM 0x%016jX - 0x%016jX (%juM used)\n",
376 (uintmax_t)mc->mc_vram_size >> 20, (uintmax_t)mc->vram_start,
377 (uintmax_t)mc->vram_end, (uintmax_t)mc->real_vram_size >> 20);
381 * radeon_gtt_location - try to find GTT location
382 * @rdev: radeon device structure holding all necessary informations
383 * @mc: memory controller structure holding memory informations
385 * Function will place try to place GTT before or after VRAM.
387 * If GTT size is bigger than space left then we ajust GTT size.
388 * Thus function will never fails.
390 * FIXME: when reducing GTT size align new size on power of 2.
392 void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
394 u64 size_af, size_bf;
396 size_af = ((0xFFFFFFFF - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
397 size_bf = mc->vram_start & ~mc->gtt_base_align;
398 if (size_bf > size_af) {
399 if (mc->gtt_size > size_bf) {
400 dev_warn(rdev->dev, "limiting GTT\n");
401 mc->gtt_size = size_bf;
403 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
405 if (mc->gtt_size > size_af) {
406 dev_warn(rdev->dev, "limiting GTT\n");
407 mc->gtt_size = size_af;
409 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
411 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
412 dev_info(rdev->dev, "GTT: %juM 0x%016jX - 0x%016jX\n",
413 (uintmax_t)mc->gtt_size >> 20, (uintmax_t)mc->gtt_start, (uintmax_t)mc->gtt_end);
417 * GPU helpers function.
420 * radeon_card_posted - check if the hw has already been initialized
422 * @rdev: radeon_device pointer
424 * Check if the asic has been initialized (all asics).
425 * Used at driver startup.
426 * Returns true if initialized or false if not.
428 bool radeon_card_posted(struct radeon_device *rdev)
433 if (efi_enabled(EFI_BOOT) &&
434 rdev->dev->pci_subvendor == PCI_VENDOR_ID_APPLE)
436 #endif /* DUMBBELL_WIP */
438 /* first check CRTCs */
439 if (ASIC_IS_DCE41(rdev)) {
440 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
441 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
442 if (reg & EVERGREEN_CRTC_MASTER_EN)
444 } else if (ASIC_IS_DCE4(rdev)) {
445 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
446 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
447 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
448 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
449 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
450 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
451 if (reg & EVERGREEN_CRTC_MASTER_EN)
453 } else if (ASIC_IS_AVIVO(rdev)) {
454 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
455 RREG32(AVIVO_D2CRTC_CONTROL);
456 if (reg & AVIVO_CRTC_EN) {
460 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
461 RREG32(RADEON_CRTC2_GEN_CNTL);
462 if (reg & RADEON_CRTC_EN) {
467 /* then check MEM_SIZE, in case the crtcs are off */
468 if (rdev->family >= CHIP_R600)
469 reg = RREG32(R600_CONFIG_MEMSIZE);
471 reg = RREG32(RADEON_CONFIG_MEMSIZE);
481 * radeon_update_bandwidth_info - update display bandwidth params
483 * @rdev: radeon_device pointer
485 * Used when sclk/mclk are switched or display modes are set.
486 * params are used to calculate display watermarks (all asics)
488 void radeon_update_bandwidth_info(struct radeon_device *rdev)
491 u32 sclk = rdev->pm.current_sclk;
492 u32 mclk = rdev->pm.current_mclk;
494 /* sclk/mclk in Mhz */
495 a.full = dfixed_const(100);
496 rdev->pm.sclk.full = dfixed_const(sclk);
497 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
498 rdev->pm.mclk.full = dfixed_const(mclk);
499 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
501 if (rdev->flags & RADEON_IS_IGP) {
502 a.full = dfixed_const(16);
503 /* core_bandwidth = sclk(Mhz) * 16 */
504 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
509 * radeon_boot_test_post_card - check and possibly initialize the hw
511 * @rdev: radeon_device pointer
513 * Check if the asic is initialized and if not, attempt to initialize
515 * Returns true if initialized or false if not.
517 bool radeon_boot_test_post_card(struct radeon_device *rdev)
519 if (radeon_card_posted(rdev))
523 DRM_INFO("GPU not posted. posting now...\n");
524 if (rdev->is_atom_bios)
525 atom_asic_init(rdev->mode_info.atom_context);
527 radeon_combios_asic_init(rdev->ddev);
530 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
536 * radeon_dummy_page_init - init dummy page used by the driver
538 * @rdev: radeon_device pointer
540 * Allocate the dummy page used by the driver (all asics).
541 * This dummy page is used by the driver as a filler for gart entries
542 * when pages are taken out of the GART
543 * Returns 0 on sucess, -ENOMEM on failure.
545 int radeon_dummy_page_init(struct radeon_device *rdev)
547 if (rdev->dummy_page.dmah)
549 rdev->dummy_page.dmah = drm_pci_alloc(rdev->ddev,
550 PAGE_SIZE, PAGE_SIZE, ~0);
551 if (rdev->dummy_page.dmah == NULL)
553 rdev->dummy_page.addr =
554 (dma_addr_t)(uintptr_t)rdev->dummy_page.dmah->vaddr;
559 * radeon_dummy_page_fini - free dummy page used by the driver
561 * @rdev: radeon_device pointer
563 * Frees the dummy page used by the driver (all asics).
565 void radeon_dummy_page_fini(struct radeon_device *rdev)
567 if (rdev->dummy_page.dmah == NULL)
569 drm_pci_free(rdev->ddev, rdev->dummy_page.dmah);
570 rdev->dummy_page.dmah = NULL;
571 rdev->dummy_page.addr = 0;
575 /* ATOM accessor methods */
577 * ATOM is an interpreted byte code stored in tables in the vbios. The
578 * driver registers callbacks to access registers and the interpreter
579 * in the driver parses the tables and executes then to program specific
580 * actions (set display modes, asic init, etc.). See radeon_atombios.c,
581 * atombios.h, and atom.c
585 * cail_pll_read - read PLL register
587 * @info: atom card_info pointer
588 * @reg: PLL register offset
590 * Provides a PLL register accessor for the atom interpreter (r4xx+).
591 * Returns the value of the PLL register.
593 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
595 struct radeon_device *rdev = info->dev->dev_private;
598 r = rdev->pll_rreg(rdev, reg);
603 * cail_pll_write - write PLL register
605 * @info: atom card_info pointer
606 * @reg: PLL register offset
607 * @val: value to write to the pll register
609 * Provides a PLL register accessor for the atom interpreter (r4xx+).
611 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
613 struct radeon_device *rdev = info->dev->dev_private;
615 rdev->pll_wreg(rdev, reg, val);
619 * cail_mc_read - read MC (Memory Controller) register
621 * @info: atom card_info pointer
622 * @reg: MC register offset
624 * Provides an MC register accessor for the atom interpreter (r4xx+).
625 * Returns the value of the MC register.
627 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
629 struct radeon_device *rdev = info->dev->dev_private;
632 r = rdev->mc_rreg(rdev, reg);
637 * cail_mc_write - write MC (Memory Controller) register
639 * @info: atom card_info pointer
640 * @reg: MC register offset
641 * @val: value to write to the pll register
643 * Provides a MC register accessor for the atom interpreter (r4xx+).
645 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
647 struct radeon_device *rdev = info->dev->dev_private;
649 rdev->mc_wreg(rdev, reg, val);
653 * cail_reg_write - write MMIO register
655 * @info: atom card_info pointer
656 * @reg: MMIO register offset
657 * @val: value to write to the pll register
659 * Provides a MMIO register accessor for the atom interpreter (r4xx+).
661 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
663 struct radeon_device *rdev = info->dev->dev_private;
669 * cail_reg_read - read MMIO register
671 * @info: atom card_info pointer
672 * @reg: MMIO register offset
674 * Provides an MMIO register accessor for the atom interpreter (r4xx+).
675 * Returns the value of the MMIO register.
677 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
679 struct radeon_device *rdev = info->dev->dev_private;
687 * cail_ioreg_write - write IO register
689 * @info: atom card_info pointer
690 * @reg: IO register offset
691 * @val: value to write to the pll register
693 * Provides a IO register accessor for the atom interpreter (r4xx+).
695 static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
697 struct radeon_device *rdev = info->dev->dev_private;
699 WREG32_IO(reg*4, val);
703 * cail_ioreg_read - read IO register
705 * @info: atom card_info pointer
706 * @reg: IO register offset
708 * Provides an IO register accessor for the atom interpreter (r4xx+).
709 * Returns the value of the IO register.
711 static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
713 struct radeon_device *rdev = info->dev->dev_private;
716 r = RREG32_IO(reg*4);
721 * radeon_atombios_init - init the driver info and callbacks for atombios
723 * @rdev: radeon_device pointer
725 * Initializes the driver info and register access callbacks for the
726 * ATOM interpreter (r4xx+).
727 * Returns 0 on sucess, -ENOMEM on failure.
728 * Called at driver startup.
730 int radeon_atombios_init(struct radeon_device *rdev)
732 struct card_info *atom_card_info =
733 kmalloc(sizeof(struct card_info), DRM_MEM_DRIVER,
739 rdev->mode_info.atom_card_info = atom_card_info;
740 atom_card_info->dev = rdev->ddev;
741 atom_card_info->reg_read = cail_reg_read;
742 atom_card_info->reg_write = cail_reg_write;
743 /* needed for iio ops */
745 atom_card_info->ioreg_read = cail_ioreg_read;
746 atom_card_info->ioreg_write = cail_ioreg_write;
748 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
749 atom_card_info->ioreg_read = cail_reg_read;
750 atom_card_info->ioreg_write = cail_reg_write;
752 atom_card_info->mc_read = cail_mc_read;
753 atom_card_info->mc_write = cail_mc_write;
754 atom_card_info->pll_read = cail_pll_read;
755 atom_card_info->pll_write = cail_pll_write;
757 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
758 lockinit(&rdev->mode_info.atom_context->mutex, "rmiacmtx", 0,
760 radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
761 atom_allocate_fb_scratch(rdev->mode_info.atom_context);
766 * radeon_atombios_fini - free the driver info and callbacks for atombios
768 * @rdev: radeon_device pointer
770 * Frees the driver info and register access callbacks for the ATOM
771 * interpreter (r4xx+).
772 * Called at driver shutdown.
774 void radeon_atombios_fini(struct radeon_device *rdev)
776 if (rdev->mode_info.atom_context) {
777 drm_free(rdev->mode_info.atom_context->scratch,
779 atom_destroy(rdev->mode_info.atom_context);
781 drm_free(rdev->mode_info.atom_card_info, DRM_MEM_DRIVER);
786 * COMBIOS is the bios format prior to ATOM. It provides
787 * command tables similar to ATOM, but doesn't have a unified
788 * parser. See radeon_combios.c
792 * radeon_combios_init - init the driver info for combios
794 * @rdev: radeon_device pointer
796 * Initializes the driver info for combios (r1xx-r3xx).
797 * Returns 0 on sucess.
798 * Called at driver startup.
800 int radeon_combios_init(struct radeon_device *rdev)
802 radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
807 * radeon_combios_fini - free the driver info for combios
809 * @rdev: radeon_device pointer
811 * Frees the driver info for combios (r1xx-r3xx).
812 * Called at driver shutdown.
814 void radeon_combios_fini(struct radeon_device *rdev)
819 /* if we get transitioned to only one device, take VGA back */
821 * radeon_vga_set_decode - enable/disable vga decode
823 * @cookie: radeon_device pointer
824 * @state: enable/disable vga decode
826 * Enable/disable vga decode (all asics).
827 * Returns VGA resource flags.
829 static unsigned int radeon_vga_set_decode(void *cookie, bool state)
831 struct radeon_device *rdev = cookie;
832 radeon_vga_set_state(rdev, state);
834 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
835 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
837 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
839 #endif /* DUMBBELL_WIP */
842 * radeon_check_pot_argument - check that argument is a power of two
844 * @arg: value to check
846 * Validates that a certain argument is a power of two (all asics).
847 * Returns true if argument is valid.
849 static bool radeon_check_pot_argument(int arg)
851 return (arg & (arg - 1)) == 0;
855 * radeon_check_arguments - validate module params
857 * @rdev: radeon_device pointer
859 * Validates certain module parameters and updates
860 * the associated values used by the driver (all asics).
862 static void radeon_check_arguments(struct radeon_device *rdev)
864 /* vramlimit must be a power of two */
865 if (!radeon_check_pot_argument(radeon_vram_limit)) {
866 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
868 radeon_vram_limit = 0;
871 /* gtt size must be power of two and greater or equal to 32M */
872 if (radeon_gart_size < 32) {
873 dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n",
875 radeon_gart_size = 512;
877 } else if (!radeon_check_pot_argument(radeon_gart_size)) {
878 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
880 radeon_gart_size = 512;
882 rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20;
884 /* AGP mode can only be -1, 1, 2, 4, 8 */
885 switch (radeon_agpmode) {
894 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
895 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
902 * radeon_switcheroo_quirk_long_wakeup - return true if longer d3 delay is
903 * needed for waking up.
905 * @pdev: pci dev pointer
908 static bool radeon_switcheroo_quirk_long_wakeup(struct pci_dev *pdev)
911 /* 6600m in a macbook pro */
912 if (pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
913 pdev->subsystem_device == 0x00e2) {
914 printk(KERN_INFO "radeon: quirking longer d3 wakeup delay\n");
920 #endif /* DUMBBELL_WIP */
923 * radeon_switcheroo_set_state - set switcheroo state
925 * @pdev: pci dev pointer
926 * @state: vga switcheroo state
928 * Callback for the switcheroo driver. Suspends or resumes the
929 * the asics before or after it is powered up using ACPI methods.
932 static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
934 struct drm_device *dev = pci_get_drvdata(pdev);
935 pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
936 if (state == VGA_SWITCHEROO_ON) {
937 unsigned d3_delay = dev->pdev->d3_delay;
939 printk(KERN_INFO "radeon: switched on\n");
940 /* don't suspend or resume card normally */
941 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
943 if (d3_delay < 20 && radeon_switcheroo_quirk_long_wakeup(pdev))
944 dev->pdev->d3_delay = 20;
946 radeon_resume_kms(dev);
948 dev->pdev->d3_delay = d3_delay;
950 dev->switch_power_state = DRM_SWITCH_POWER_ON;
951 drm_kms_helper_poll_enable(dev);
953 printk(KERN_INFO "radeon: switched off\n");
954 drm_kms_helper_poll_disable(dev);
955 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
956 radeon_suspend_kms(dev, pmm);
957 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
960 #endif /* DUMBBELL_WIP */
963 * radeon_switcheroo_can_switch - see if switcheroo state can change
965 * @pdev: pci dev pointer
967 * Callback for the switcheroo driver. Check of the switcheroo
968 * state can be changed.
969 * Returns true if the state can be changed, false if not.
972 static bool radeon_switcheroo_can_switch(struct pci_dev *pdev)
974 struct drm_device *dev = pci_get_drvdata(pdev);
977 spin_lock(&dev->count_lock);
978 can_switch = (dev->open_count == 0);
979 spin_unlock(&dev->count_lock);
983 static const struct vga_switcheroo_client_ops radeon_switcheroo_ops = {
984 .set_gpu_state = radeon_switcheroo_set_state,
986 .can_switch = radeon_switcheroo_can_switch,
988 #endif /* DUMBBELL_WIP */
991 * radeon_device_init - initialize the driver
993 * @rdev: radeon_device pointer
994 * @pdev: drm dev pointer
995 * @flags: driver flags
997 * Initializes the driver info and hw (all asics).
998 * Returns 0 for success or an error on failure.
999 * Called at driver startup.
1001 int radeon_device_init(struct radeon_device *rdev,
1002 struct drm_device *ddev,
1008 rdev->shutdown = false;
1009 rdev->dev = ddev->dev;
1011 rdev->flags = flags;
1012 rdev->family = flags & RADEON_FAMILY_MASK;
1013 rdev->is_atom_bios = false;
1014 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
1015 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
1016 rdev->accel_working = false;
1017 rdev->fictitious_range_registered = false;
1018 /* set up ring ids */
1019 for (i = 0; i < RADEON_NUM_RINGS; i++) {
1020 rdev->ring[i].idx = i;
1023 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n",
1024 radeon_family_name[rdev->family], ddev->pci_vendor, ddev->pci_device,
1025 ddev->pci_subvendor, ddev->pci_subdevice);
1027 /* mutex initialization are all done here so we
1028 * can recall function without having locking issues */
1029 lockinit(&rdev->ring_lock, "drm__radeon_device__ring_lock", 0,
1031 lockinit(&rdev->dc_hw_i2c_mutex,
1032 "drm__radeon_device__dc_hw_i2c_mutex", 0, LK_CANRECURSE);
1033 atomic_set(&rdev->ih.lock, 0);
1034 spin_init(&rdev->gem.mutex, "radeon_gemmtx");
1035 lockinit(&rdev->pm.mutex, "drm__radeon_device__pm__mutex", 0,
1037 spin_init(&rdev->gpu_clock_mutex, "radeon_clockmtx");
1038 lockinit(&rdev->pm.mclk_lock, "drm__radeon_device__pm__mclk_lock", 0,
1040 lockinit(&rdev->exclusive_lock, "drm__radeon_device__exclusive_lock",
1042 DRM_INIT_WAITQUEUE(&rdev->irq.vblank_queue);
1043 r = radeon_gem_init(rdev);
1046 /* initialize vm here */
1047 lockinit(&rdev->vm_manager.lock,
1048 "drm__radeon_device__vm_manager__lock", 0, LK_CANRECURSE);
1049 /* Adjust VM size here.
1050 * Currently set to 4GB ((1 << 20) 4k pages).
1051 * Max GPUVM size for cayman and SI is 40 bits.
1053 rdev->vm_manager.max_pfn = 1 << 20;
1054 INIT_LIST_HEAD(&rdev->vm_manager.lru_vm);
1056 /* Set asic functions */
1057 r = radeon_asic_init(rdev);
1060 radeon_check_arguments(rdev);
1062 /* all of the newer IGP chips have an internal gart
1063 * However some rs4xx report as AGP, so remove that here.
1065 if ((rdev->family >= CHIP_RS400) &&
1066 (rdev->flags & RADEON_IS_IGP)) {
1067 rdev->flags &= ~RADEON_IS_AGP;
1070 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
1071 radeon_agp_disable(rdev);
1074 /* set DMA mask + need_dma32 flags.
1075 * PCIE - can handle 40-bits.
1076 * IGP - can handle 40-bits
1077 * AGP - generally dma32 is safest
1078 * PCI - dma32 for legacy pci gart, 40 bits on newer asics
1080 rdev->need_dma32 = false;
1081 if (rdev->flags & RADEON_IS_AGP)
1082 rdev->need_dma32 = true;
1083 if ((rdev->flags & RADEON_IS_PCI) &&
1084 (rdev->family <= CHIP_RS740))
1085 rdev->need_dma32 = true;
1087 dma_bits = rdev->need_dma32 ? 32 : 40;
1089 r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
1091 rdev->need_dma32 = true;
1093 printk(KERN_WARNING "radeon: No suitable DMA available.\n");
1095 r = pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
1097 pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(32));
1098 printk(KERN_WARNING "radeon: No coherent DMA available.\n");
1100 #endif /* DUMBBELL_WIP */
1102 /* Registers mapping */
1103 /* TODO: block userspace mapping of io register */
1104 spin_init(&rdev->mmio_idx_lock, "radeon_mpio");
1105 rdev->rmmio_rid = PCIR_BAR(2);
1106 rdev->rmmio = bus_alloc_resource_any(rdev->dev, SYS_RES_MEMORY,
1107 &rdev->rmmio_rid, RF_ACTIVE | RF_SHAREABLE);
1108 if (rdev->rmmio == NULL) {
1111 rdev->rmmio_base = rman_get_start(rdev->rmmio);
1112 rdev->rmmio_size = rman_get_size(rdev->rmmio);
1113 DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
1114 DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
1116 /* io port mapping */
1117 for (i = 0; i < DRM_MAX_PCI_RESOURCE; i++) {
1120 data = pci_read_config(rdev->dev, PCIR_BAR(i), 4);
1121 if (PCI_BAR_IO(data)) {
1122 rdev->rio_rid = PCIR_BAR(i);
1123 rdev->rio_mem = bus_alloc_resource_any(rdev->dev,
1124 SYS_RES_IOPORT, &rdev->rio_rid,
1125 RF_ACTIVE | RF_SHAREABLE);
1129 if (rdev->rio_mem == NULL)
1130 DRM_ERROR("Unable to find PCI I/O BAR\n");
1132 rdev->tq = taskqueue_create("radeonkms", M_WAITOK,
1133 taskqueue_thread_enqueue, &rdev->tq);
1134 taskqueue_start_threads(&rdev->tq, 1, 0, -1, "radeon taskq");
1137 /* if we have > 1 VGA cards, then disable the radeon VGA resources */
1138 /* this will fail for cards that aren't VGA class devices, just
1140 vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
1141 vga_switcheroo_register_client(rdev->pdev, &radeon_switcheroo_ops);
1142 #endif /* DUMBBELL_WIP */
1144 r = radeon_init(rdev);
1148 r = radeon_ib_ring_tests(rdev);
1150 DRM_ERROR("ib ring test failed (%d).\n", r);
1152 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
1153 /* Acceleration not working on AGP card try again
1154 * with fallback to PCI or PCIE GART
1156 radeon_asic_reset(rdev);
1158 radeon_agp_disable(rdev);
1159 r = radeon_init(rdev);
1164 DRM_INFO("%s: Taking over the fictitious range 0x%jx-0x%jx\n",
1165 __func__, (uintmax_t)rdev->mc.aper_base,
1166 (uintmax_t)rdev->mc.aper_base + rdev->mc.visible_vram_size);
1167 r = vm_phys_fictitious_reg_range(
1169 rdev->mc.aper_base + rdev->mc.visible_vram_size,
1170 VM_MEMATTR_WRITE_COMBINING);
1172 DRM_ERROR("Failed to register fictitious range "
1173 "0x%jx-0x%jx (%d).\n", (uintmax_t)rdev->mc.aper_base,
1174 (uintmax_t)rdev->mc.aper_base + rdev->mc.visible_vram_size, r);
1177 rdev->fictitious_range_registered = true;
1179 if ((radeon_testing & 1)) {
1180 radeon_test_moves(rdev);
1182 if ((radeon_testing & 2)) {
1183 radeon_test_syncing(rdev);
1185 if (radeon_benchmarking) {
1186 radeon_benchmark(rdev, radeon_benchmarking);
1192 static void radeon_debugfs_remove_files(struct radeon_device *rdev);
1193 #endif /* DUMBBELL_WIP */
1196 * radeon_device_fini - tear down the driver
1198 * @rdev: radeon_device pointer
1200 * Tear down the driver info (all asics).
1201 * Called at driver shutdown.
1203 void radeon_device_fini(struct radeon_device *rdev)
1205 DRM_INFO("radeon: finishing device.\n");
1206 rdev->shutdown = true;
1207 /* evict vram memory */
1208 radeon_bo_evict_vram(rdev);
1210 if (rdev->fictitious_range_registered) {
1211 vm_phys_fictitious_unreg_range(
1213 rdev->mc.aper_base + rdev->mc.visible_vram_size);
1218 vga_switcheroo_unregister_client(rdev->pdev);
1219 vga_client_register(rdev->pdev, NULL, NULL, NULL);
1220 #endif /* DUMBBELL_WIP */
1222 if (rdev->tq != NULL) {
1223 taskqueue_free(rdev->tq);
1228 bus_release_resource(rdev->dev, SYS_RES_IOPORT, rdev->rio_rid,
1230 rdev->rio_mem = NULL;
1231 bus_release_resource(rdev->dev, SYS_RES_MEMORY, rdev->rmmio_rid,
1235 radeon_debugfs_remove_files(rdev);
1236 #endif /* DUMBBELL_WIP */
1244 * radeon_suspend_kms - initiate device suspend
1246 * @pdev: drm dev pointer
1247 * @state: suspend state
1249 * Puts the hw in the suspend state (all asics).
1250 * Returns 0 for success or an error on failure.
1251 * Called at driver suspend.
1253 int radeon_suspend_kms(struct drm_device *dev)
1255 struct radeon_device *rdev;
1256 struct drm_crtc *crtc;
1257 struct drm_connector *connector;
1259 bool force_completion = false;
1261 if (dev == NULL || dev->dev_private == NULL) {
1265 if (state.event == PM_EVENT_PRETHAW) {
1268 #endif /* DUMBBELL_WIP */
1269 rdev = dev->dev_private;
1271 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1274 drm_kms_helper_poll_disable(dev);
1276 /* turn off display hw */
1277 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1278 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
1281 /* unpin the front buffers */
1282 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1283 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb);
1284 struct radeon_bo *robj;
1286 if (rfb == NULL || rfb->obj == NULL) {
1289 robj = gem_to_radeon_bo(rfb->obj);
1290 /* don't unpin kernel fb objects */
1291 if (!radeon_fbdev_robj_is_fb(rdev, robj)) {
1292 r = radeon_bo_reserve(robj, false);
1294 radeon_bo_unpin(robj);
1295 radeon_bo_unreserve(robj);
1299 /* evict vram memory */
1300 radeon_bo_evict_vram(rdev);
1302 lockmgr(&rdev->ring_lock, LK_EXCLUSIVE);
1303 /* wait for gpu to finish processing current batch */
1304 for (i = 0; i < RADEON_NUM_RINGS; i++) {
1305 r = radeon_fence_wait_empty_locked(rdev, i);
1307 /* delay GPU reset to resume */
1308 force_completion = true;
1311 if (force_completion) {
1312 radeon_fence_driver_force_completion(rdev);
1314 lockmgr(&rdev->ring_lock, LK_RELEASE);
1316 radeon_save_bios_scratch_regs(rdev);
1318 radeon_pm_suspend(rdev);
1319 radeon_suspend(rdev);
1320 radeon_hpd_fini(rdev);
1321 /* evict remaining vram memory */
1322 radeon_bo_evict_vram(rdev);
1324 radeon_agp_suspend(rdev);
1326 pci_save_state(device_get_parent(rdev->dev));
1328 if (state.event == PM_EVENT_SUSPEND) {
1329 /* Shut down the device */
1330 pci_disable_device(dev->pdev);
1331 #endif /* DUMBBELL_WIP */
1332 pci_set_powerstate(dev->dev, PCI_POWERSTATE_D3);
1336 #endif /* DUMBBELL_WIP */
1337 radeon_fbdev_set_suspend(rdev, 1);
1340 #endif /* DUMBBELL_WIP */
1345 * radeon_resume_kms - initiate device resume
1347 * @pdev: drm dev pointer
1349 * Bring the hw back to operating state (all asics).
1350 * Returns 0 for success or an error on failure.
1351 * Called at driver resume.
1353 int radeon_resume_kms(struct drm_device *dev)
1355 struct drm_connector *connector;
1356 struct radeon_device *rdev = dev->dev_private;
1359 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1364 #endif /* DUMBBELL_WIP */
1365 pci_set_powerstate(dev->dev, PCI_POWERSTATE_D0);
1366 pci_restore_state(device_get_parent(rdev->dev));
1368 if (pci_enable_device(dev->pdev)) {
1372 #endif /* DUMBBELL_WIP */
1373 /* resume AGP if in use */
1374 radeon_agp_resume(rdev);
1375 radeon_resume(rdev);
1377 r = radeon_ib_ring_tests(rdev);
1379 DRM_ERROR("ib ring test failed (%d).\n", r);
1381 radeon_pm_resume(rdev);
1382 radeon_restore_bios_scratch_regs(rdev);
1384 radeon_fbdev_set_suspend(rdev, 0);
1387 #endif /* DUMBBELL_WIP */
1389 /* init dig PHYs, disp eng pll */
1390 if (rdev->is_atom_bios) {
1391 radeon_atom_encoder_init(rdev);
1392 radeon_atom_disp_eng_pll_init(rdev);
1393 /* turn on the BL */
1394 if (rdev->mode_info.bl_encoder) {
1395 u8 bl_level = radeon_get_backlight_level(rdev,
1396 rdev->mode_info.bl_encoder);
1397 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder,
1401 /* reset hpd state */
1402 radeon_hpd_init(rdev);
1403 /* blat the mode back in */
1404 drm_helper_resume_force_mode(dev);
1405 /* turn on display hw */
1406 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1407 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
1410 drm_kms_helper_poll_enable(dev);
1415 * radeon_gpu_reset - reset the asic
1417 * @rdev: radeon device pointer
1419 * Attempt the reset the GPU if it has hung (all asics).
1420 * Returns 0 for success or an error on failure.
1422 int radeon_gpu_reset(struct radeon_device *rdev)
1424 unsigned ring_sizes[RADEON_NUM_RINGS];
1425 uint32_t *ring_data[RADEON_NUM_RINGS];
1432 lockmgr(&rdev->exclusive_lock, LK_EXCLUSIVE);
1433 radeon_save_bios_scratch_regs(rdev);
1435 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
1436 radeon_suspend(rdev);
1438 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1439 ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i],
1441 if (ring_sizes[i]) {
1443 dev_info(rdev->dev, "Saved %d dwords of commands "
1444 "on ring %d.\n", ring_sizes[i], i);
1449 r = radeon_asic_reset(rdev);
1451 dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n");
1452 radeon_resume(rdev);
1455 radeon_restore_bios_scratch_regs(rdev);
1458 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1459 radeon_ring_restore(rdev, &rdev->ring[i],
1460 ring_sizes[i], ring_data[i]);
1462 ring_data[i] = NULL;
1465 r = radeon_ib_ring_tests(rdev);
1467 dev_err(rdev->dev, "ib ring test failed (%d).\n", r);
1470 radeon_suspend(rdev);
1475 radeon_fence_driver_force_completion(rdev);
1476 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1477 drm_free(ring_data[i], DRM_MEM_DRIVER);
1481 drm_helper_resume_force_mode(rdev->ddev);
1483 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
1485 /* bad news, how to tell it to userspace ? */
1486 dev_info(rdev->dev, "GPU reset failed\n");
1489 lockmgr(&rdev->exclusive_lock, LK_RELEASE);
1498 int radeon_debugfs_add_files(struct radeon_device *rdev,
1499 struct drm_info_list *files,
1504 for (i = 0; i < rdev->debugfs_count; i++) {
1505 if (rdev->debugfs[i].files == files) {
1506 /* Already registered */
1511 i = rdev->debugfs_count + 1;
1512 if (i > RADEON_DEBUGFS_MAX_COMPONENTS) {
1513 DRM_ERROR("Reached maximum number of debugfs components.\n");
1514 DRM_ERROR("Report so we increase "
1515 "RADEON_DEBUGFS_MAX_COMPONENTS.\n");
1518 rdev->debugfs[rdev->debugfs_count].files = files;
1519 rdev->debugfs[rdev->debugfs_count].num_files = nfiles;
1520 rdev->debugfs_count = i;
1521 #if defined(CONFIG_DEBUG_FS)
1522 drm_debugfs_create_files(files, nfiles,
1523 rdev->ddev->control->debugfs_root,
1524 rdev->ddev->control);
1525 drm_debugfs_create_files(files, nfiles,
1526 rdev->ddev->primary->debugfs_root,
1527 rdev->ddev->primary);
1532 static void radeon_debugfs_remove_files(struct radeon_device *rdev)
1534 #if defined(CONFIG_DEBUG_FS)
1537 for (i = 0; i < rdev->debugfs_count; i++) {
1538 drm_debugfs_remove_files(rdev->debugfs[i].files,
1539 rdev->debugfs[i].num_files,
1540 rdev->ddev->control);
1541 drm_debugfs_remove_files(rdev->debugfs[i].files,
1542 rdev->debugfs[i].num_files,
1543 rdev->ddev->primary);
1548 #if defined(CONFIG_DEBUG_FS)
1549 int radeon_debugfs_init(struct drm_minor *minor)
1554 void radeon_debugfs_cleanup(struct drm_minor *minor)
1557 #endif /* DUMBBELL_WIP */